Industrial Ethernet system on chip and control method

Abstract

The present invention provides a system on chip and a control method for an industrial Ethernet, and relates to the fields of industrial control and electronic information technology. The system on chip includes a main control processor for configuring a processing environment for motion data, and sending the motion data to a motion analysis IP core; the motion analysis IP core is connected to a main station through the main control processor for receiving motion data to be executed from the main station, and analyzing the motion data to obtain motion control data; and a communication control main station IP core is connected to the motion analysis IP core for writing the motion control data into a memory module, and the motion control data in the memory module is packaged and periodically sent to a slave device. The system on chip and the control method provided by the present invention can solve the problems of long control cycle time and large jitter due to the software and hardware performance of a small main control processor, accelerate data processing, and shorten the control cycle.

Description

Technical Field

[0001] The present invention relates to the field of industrial control and electronic information technology, and in particular to an industrial Ethernet system on chip and a control method. Background Art

[0002] The EtherCAT (Ethernet Control Automation Technology) protocol has the characteristics of high real-time performance, high bandwidth utilization and easy integration, and is widely used in the industrial automation industry. EtherCAT is a master-slave network architecture. The master station uses a standard Ethernet card and the slave station uses a dedicated ESC chip. The slave station uses hardware to achieve low latency communication and high synchronization between devices, while the master station is implemented through software based on a high-performance CPU. In order to meet the needs of the control cycle, the real-time performance of the operating system is required to be high enough.

[0003] The CPU (processor) of the current master station usually uses high-performance chips of ARM architecture or X86 architecture, which will increase product costs and make the development of high-performance chips more complicated. The software uses a real-time operating system or a non-real-time operating system and a real-time patch to achieve high real-time performance. However, since the real-time performance of the operating system is affected by many factors, the software cannot guarantee strong real-time control. This will cause uncontrollable jitter when processing periodic data, thus affecting the real-time performance of the master station. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an industrial Ethernet system-on-chip and a control method, which are used to solve the problems of insufficient performance of small CPUs and insufficient real-time performance of operating systems in industrial Ethernet (EtherCAT) control in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides an industrial Ethernet system on chip, including: a main control processor, which is used to configure a processing environment for motion data and send the motion data to a motion analysis IP (intellectual property) core; the motion analysis IP core is connected to a master station through the main control processor to receive the motion data to be executed sent by the master station, and analyze the motion data to obtain motion control data; and a communication control master station IP core is connected to the motion analysis IP core to write the motion control data into a memory module, and the motion control data in the memory module is packaged and periodically sent to a slave station device.

[0006] In one embodiment of the present invention, the motion analysis IP core is configured to analyze multiple groups of axis motions, each group of axis motions including at least one and at most six interpolation axes.

[0007] In one embodiment of the present invention, the motion analysis IP core is configured to obtain motion data inputted through G code and register mode for analysis, and perform cycle and axis parameter configuration to obtain motion control data of each axis.

[0008] In one embodiment of the present invention, the motion analysis IP core is configured to: obtain the G code in the memory module, parse the corresponding action configuration information and G code instructions, and decompose to obtain independent action data of each axis, then configure the cycle and axis information, slice the motion, and send it to the communication control master station IP core.

[0009] In one embodiment of the present invention, the motion analysis IP core includes: a register module, which is used to receive the motion configuration information of each axis configured by the main control processor and send it to the motion analysis module; an instruction pre-fetch module, which is used to obtain the G code from the memory module, configure the starting position and slicing period of the G code instruction through the main control processor, and send it to the motion analysis module; the motion analysis module is used to parse the motion configuration information and the G code instruction respectively to obtain specific axis movements; the motion decomposition module is used to decompose the specific axis movement to obtain independent motion data of each axis; and the motion slicing module is used to perform motion slicing and compose messages according to the period and axis information configured by the register module, and send them to the communication control master station IP core.

[0010] In one embodiment of the present invention, the communication control master station IP core includes: a receiving control module, which is used to receive Ethernet messages for scanning, filter to obtain new messages based on valid descriptor chain information of slave station devices, and map them to the memory module; a clock module, which is used to send clock synchronization messages as clock references through hardware, and synchronize all slave station devices to the same time of the clock reference; and a sending control module, including multiple message transmitters, which are used to receive new messages in the memory module; the sending control module is configured to: read the corresponding motion control data to be sent from the memory module according to the sending signal received by the message transmitter corresponding to the motion control data, and assemble and send them according to the clock reference.

[0011] In one embodiment of the present invention, the descriptor chain information includes: configuration information, the first address of the message, the cycle time of the message and the first address of the descriptor.

[0012] In one embodiment of the present invention, the messages sent by the message transmitter include periodic messages and non-periodic messages, wherein the sending priority of the periodic messages is higher than that of the non-periodic messages; and the constituent messages of the motion control data are periodic messages.

[0013] In one embodiment of the present invention, the sending control module is configured to: retrieve descriptor chain information from multiple message senders, and read corresponding data to be sent from the memory module according to the descriptor chain information, and group the messages composed of clock reference and motion control data respectively and send multiple messages simultaneously in the same cycle.

[0014] The present invention also provides a control method for the system on chip applied to the aforementioned industrial Ethernet, comprising the following steps:

[0015] The main control processor configures the processing environment for motion data and sends the motion data to the motion analysis IP core;

[0016] The motion analysis IP core is connected to the main station through the main control processor, and the motion data to be executed sent by the main station is received through the motion analysis IP core, and the motion data is analyzed to obtain motion control data;

[0017] The communication control master IP core is connected to the motion analysis IP core, and the motion control data is written into the memory module through the communication control master IP core. The motion control data in the memory module is packaged and periodically sent to the slave device.

[0018] Beneficial effects of the present invention: The present invention proposes an industrial Ethernet system-on-chip and control method, which reduces the requirements for the main control processor, and only requires 100MHz to 200MHz to achieve a 1ms control cycle (32 slave devices), and the cycle jitter is within 100ns, which greatly reduces the hardware cost of the main control processor 1. At the same time, motion slicing, cycle control and message parsing are realized through hardware algorithms, and the real-time requirements of the software system are greatly reduced, and there is no need to carry out additional development of the system real-time, which reduces the development difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. 1 is a schematic diagram of the structure of a system on a chip in a preferred embodiment of the present invention.

[0020] Figure 2 It is a schematic diagram of the structure of the motion analysis IP core in a preferred embodiment of the present invention.

[0021] Figure 3 It is a schematic diagram of the structure of the communication control IP core in a preferred embodiment of the present invention.

[0022] Figure 4 The figure is a schematic diagram of the period when periodic messages are sent in a preferred embodiment of the present invention.

[0023] Figure 5 The figure is a schematic diagram of shielding the transmission of periodic messages in a preferred embodiment of the present invention.

[0024] Figure 6 The figure is a schematic diagram of transmission control of a transmission control module in a preferred embodiment of the present invention.

[0025] Figure 7 It is a schematic diagram of the periodic sending process of motion slice data in a preferred embodiment of the present invention.

[0026] Figure 8 It is a schematic diagram of message reception and mapping in a preferred embodiment of the present invention.

[0027] Fig. 9 The figure is a flow chart of the control method of the system on chip of the present invention.

[0028] Component number description

[0029] Main control processor 1, motion analysis IP core 2; communication control master station IP core 3; memory module 4; slave station device 20; master station 10; register module 21; instruction prefetch module 22; motion analysis module 23; motion decomposition module 24; motion slicing module 25; receiving control module 31; clock module 32; sending control module 33. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] See also Figure 1The present invention provides a system on chip for industrial Ethernet, which can solve the problem of long control cycle time and large jitter due to the software and hardware performance of small main control processors. The system on chip may include a main control processor 1, a parallel bus (AMBA), a motion analysis IP core 2, a communication control master station IP (intellectual property) core 3, a memory module (RAM) 4, a master station 10 and a slave station device 20. The product can be applied to PLC, motion controller and industrial controller, etc. Among them, PLC is a programmable logic controller, a controller commonly used in industrial environments, including input, output, storage, main control and other parts, and can realize logic control, motion control and other functions through configuration programming. The motion controller is an industrial controller, which is mainly used for the control of mechanical axes. Through function interfaces or configuration programming, it can realize the precise position, speed, acceleration and other control of mechanical motion, and also supports point input and output. The IP core is an intellectual property core, which refers to a reusable module in the form of a logic unit and chip design provided by one party in the design of integrated circuits. A master-slave mode network architecture of EtherCAT (Ethernet Control Automation Technology) may be used between the master station 10 and the slave station device 20. EtherCAT is an industrial real-time Ethernet bus, which is divided into a master station and a slave station.

[0032] See also Figure 1 In one embodiment of the present invention, the main control processor 1, the motion analysis IP core 2 and the communication control master station IP core 3 are interconnected through a parallel bus (AMBA). The communication control master station IP core 3 is connected to the slave device through the port physical layer. Among them, the main control processor 1 assists in carrying the industrial control system and the master station, and processes the control data. The motion analysis IP core 2 is responsible for realizing the decomposition of the motion and outputting the motion control data to the communication control master station IP core 3. The communication control master station IP core 3 is responsible for the periodic or non-periodic transmission of the data and the real-time analysis of the received industrial Ethernet packets. Through the mutual cooperation between the motion analysis IP core 2 and the communication control master station IP core 3, the automatic control of motion decomposition, data packaging and periodic transmission is realized, the bus performance is improved, the control cycle is shorter, and the period jitter is smaller.

[0033] See also Figure 1 , AMBA is a matrix interconnect bus. The system has two motion control channels, which can run simultaneously. 1. The master processor 1 can directly control the slave device 20 through the communication control master IP core 3 through AMBA. That is, the master processor 1 can directly send out periodic / non-periodic data packets through the descriptor chain. Please refer to Figure 6The descriptor chain part of the function, the master processor 1 can put the data in the memory module (RAM) 4 first, and then configure the communication control master IP core to work. Second, the master processor 1 will also give the motion control data (in the memory module RAM (G code) or through the write register mode) to the motion analysis IP core 2, and the motion analysis IP core 2 will control the communication control master IP core 3 to send the message cycle and control the slave device 20. For details, please refer to Figure 6 Motion slicing feature in .

[0034] See also Figure 1 In one embodiment of the present invention, the present invention provides an industrial Ethernet system on chip, including: a main control processor 1, a motion analysis IP core 2, a communication control master station IP core 3, a memory module 4, a master station 10 and a slave station device 20.

[0035] Among them, the main control processor 1 is used to configure the processing environment for motion data and send the motion data to the motion analysis IP core 2. In this embodiment, the main control processor 1 is responsible for carrying the industrial control system and the main station 10 to process the motion data, that is, to send the motion data to the motion analysis IP core 2 for further processing. The main control processor 1 can be a small CPU with an architecture such as ARM (Advanced RISC Machine) or RISCV (fifth generation open source instruction set architecture). The operating frequency of the small CPU can be between 100MHz and 200MHz. The main control processor 2 is mainly used to execute the industrial control program core to control the operation of the slave station device. Similarly, the main control processor 2 is the same as a conventional MCU (microcontroller), and also includes general peripheral modules such as GPIO (General-purpose input / output, general input / output) module, communication module and PLL (PhaseLocked Loop, phase-locked loop), and each module is connected through an AMBA high-speed bus. Moreover, the main control processor 1 can also initialize the communication control master station IP core 3, that is, by configuring the messages to be sent, and using these messages to control the initialization configuration and control of each slave station device 20.

[0036] The motion analysis IP core 2 is connected to the master station 10 through the master control processor 1 to receive the motion data to be executed from the master station 10, and analyze the motion data to obtain motion control data. In this embodiment, the motion analysis IP core 2 is responsible for decomposing the motion data, parsing the motion data into motion control data, and outputting the motion control data to the communication control master station IP core 3. The master station 10 is a software protocol stack running on the master control processor 1, which is used to control the corresponding slave station device 20.

[0037] The communication control master station IP core 3 is connected to the motion analysis IP core 2 for communication, so as to write the motion control data into the memory module 4, and to group the motion control data in the memory module 4 and send it to the slave device 20 periodically. In the present embodiment, the communication control master station IP core 3 is connected to the slave device 20 via a network port, and the slave devices 20 are connected via at least one network cable. The communication control master station IP core 3 is responsible for the periodic or non-periodic transmission of data and real-time analysis of the received industrial Ethernet packet, and writes the motion data control to the memory module 4 after the motion analysis IP core 2 is completed. And when the sending signal of the main control processor 1 is obtained, the motion control data stored in the memory module 4 is grouped and sent to the slave device 20 periodically. Specifically, the communication control master station IP core 3 can perform clock synchronization, periodic and non-periodic message transmission, message reception and mapping according to the configuration.

[0038] In one embodiment of the present invention, the motion analysis IP core 2 is configured to analyze multiple groups of axis motions, each group of axis motions includes at least one and at most six interpolation axes. In this embodiment, the motion analysis IP core 2 supports the analysis of multiple groups of axis motions, supports at most six interpolation axes in one group of axis motions, and at least one interpolation axis in one group of axis motions. In other words, it can support 1 to 6 independent axes for simultaneous or linkage control, so that the workpiece can make a corresponding degree of complexity, such as curved motion.

[0039] Specifically, the motion analysis IP core 2 is configured to obtain motion data inputted through G code and register mode for analysis, and configure the cycle and axis parameters to obtain motion control data of each axis. When the motion analysis IP core 2 performs analysis, the motion data input can be realized through G code or register mode. Further, according to the configured cycle and axis parameters, the motion control data corresponding to each axis is outputted.

[0040] Preferably, the motion analysis IP core 2 is configured to: obtain the G code instruction in the memory module 4, analyze the corresponding action configuration information and G code instruction, and decompose to obtain the independent action data of each axis, and then configure the cycle and axis information, and send the motion slice to the communication control master station IP core 3. In this embodiment, the main control processor 1 configures the motion analysis IP core 2 working information and motion action through the AMBA bus. And it will also obtain the G code from the memory module 4 through the AMBA bus, and then further analyze the action configuration information and G code instruction of the G code, and decompose the specific axis action to obtain the independent action data of each axis. Then according to the configured cycle and axis information, the motion is sliced ​​and sent to the communication control master station IP core 3. Then, the independent action data, cycle and axis information are configured as motion control data and sent to the memory module 4 for storage through the communication control master station IP core 3. And when the communication control master station IP core 3 receives the sending signal, it controls the motion control data group stored in the memory module 4 to be sent to the slave station device 20.

[0041] See also Figure 2 In one embodiment of the present invention, the motion analysis IP core 2 includes a register module 21, an instruction pre-fetch module 22, a motion analysis module 23, a motion decomposition module 24 and a motion slicing module 25. Among them, the register module 21 is used to receive the motion configuration information of each axis configured by the main control processor 1, and send it to the motion analysis module 23. The instruction pre-fetch module 22 is used to obtain the G code from the memory module 4, configure the starting position and slicing cycle of the G code instruction through the main control processor 1, and send it to the motion analysis module 23. The motion analysis module 23 is used to parse the action configuration information and the G code instruction respectively to obtain specific axis actions. The motion decomposition module 24 is used to decompose the specific axis action to obtain independent action data of each axis. The motion slicing module 25 is used to perform motion slicing and compose messages according to the cycle and axis information configured by the register module 21, and send them to the communication control master station IP core 3. Among them, the main control processor 1 is connected to the motion analysis module 23 through the register module 21. The memory module 4 is connected to the motion analysis module 23 through the instruction pre-fetch module 22. The motion analysis module 23 is connected to the communication control master station IP core 3 in turn through the motion decomposition module 24 and the motion slicing module 25. The main control processor 1 is also connected to the interrupt / status module to determine whether the periodic message sent to the main control processor 1 is sent within the cycle, and generates an alarm interrupt signal if it is not sent. If it is a non-periodic message, the interrupt / status module will calculate whether the non-periodic message is sent in the current cycle. The non-periodic message supports setting a timeout. If the non-periodic message fails to be sent when the timeout is reached, an alarm interrupt will also be generated.

[0042] In this embodiment, the register module 21 supports the AMBA interface to communicate with the main control processor 2, so as to configure the working information and motion actions to the motion analysis IP core 2 through the main control processor 1. The instruction pre-fetch module 22 obtains the G code from the memory module 4 through the AMBA bus, and transmits it to the motion analysis module 23 for the action configuration information and G code instructions of the register module 21. And the specific axis action is handed over to the motion decomposition module to decompose and obtain the independent action data of each axis. Finally, according to the cycle and axis information configured by the register module 21, after the motion is sliced ​​by the motion slicing module 25, each configuration information is composed into a message and sent to the communication control master station IP core 3, and then the communication control master station IP core 3 controls the further sending of the message to each slave station device 20.

[0043] Specifically, the register module 21 supports two working modes: register and G code. In the register mode, the register module 21 of the motion analysis IP core 2 is configured by the main control processor 1 to realize the control of different motions of each axis, such as supporting motion modes such as straight lines, arcs, and ellipses. In the G code mode, the main control processor 1 needs to configure the starting position and slicing cycle of the G code, and after startup, the motion analysis IP core 2 will compose the motion control data of the slice into a message, and then further send it through the communication control master station IP core 3.

[0044] In one embodiment of the present invention, the communication control master station IP core 3 can provide a high real-time, low-jitter communication interface based on the EtherCAT (Ethernet Control Automation Technology, an open framework, Ethernet-based fieldbus system) protocol to solve the problems of insufficient software and hardware performance of the small master processor and large control cycle jitter.

[0045] See also Figure 3 In one embodiment of the present invention, the communication control master station IP core 3 includes a receiving control module 31, a clock module 32 and a sending control module 33. Among them, the receiving control module 31 is used to receive Ethernet messages for scanning, filter to obtain new messages based on the valid descriptor chain information of the slave device 20, and map them to the memory module 4. The clock module 32 is used to send clock synchronization messages as clock references through hardware, and synchronize all slave devices 20 to the same time of the clock reference. The sending control module 33 includes multiple message transmitters, and is used to receive new messages in the memory module 4. The sending control module 33 is configured to: read the corresponding motion control data to be sent from the memory module 4 according to the sending signal received by the message transmitter corresponding to the motion control data, and assemble and send them according to the clock reference.

[0046] In the present embodiment, the communication control master station IP core 3 also includes an AMBA communication module, the main control processor 1 is connected to the receiving control module 31 through the AMBA communication module, the receiving control module 31 is connected to the sending control module 33 through the clock module 32, and the sending control module 33 is connected to the memory module 4 through the AMBA communication module. Among them, the main control processor 1 is connected to the motion analysis module 23 through the register module 21. The memory module 4 is connected to the motion analysis module 23 through the instruction pre-fetch module 22. The motion analysis module 23 is connected to the communication control master station IP core 3 through the motion decomposition module 24 and the motion slicing module 25 in turn. The main control processor 1 is also connected to the interrupt / status module to determine whether the periodic message sent to the main control processor 1 is sent within the cycle, and an alarm interrupt signal is generated when the sending is not completed. If it is a non-periodic message, the interrupt / status module will calculate whether the non-periodic message is sent in the current cycle. The non-periodic message supports setting a timeout. If the timeout is reached and the non-periodic message is not sent, an alarm interrupt will also be generated.

[0047] The receiving control module 31 is used to receive, parse and map message data. The receiving control module 31 includes a receiving descriptor chain scanning function to receive Ethernet messages according to the descriptors on the descriptor chain. It supports filtering the received Ethernet messages, and can discard the entire message or only discard some sub-messages in the message to form a new message for uploading.

[0048] Specifically, the receiving control module 31 provides a variety of message data mapping mechanisms, which can directly map the valid slave data corresponding to the slave device 20 in the message to the memory module 4 through the AMBA bus after filtering the required message data through a flag bit or a command filter. For the mapped messages or unnecessary messages, they can be filtered through the receiving message filter, and such messages will be directly discarded without occupying the receiving descriptor.

[0049] The clock module 32 provides a 64-bit high-precision clock. The clock synchronization message can be sent through hardware as a clock reference to synchronize all slave devices 20 to this clock. The clock synchronization message can also be parsed to synchronize this clock to the clock reference of the slave device 20, so that the clocks between the master station 10 and the slave device 20 are highly synchronized. The master control processor 1 can obtain the time of the bus reference clock in real time, which can be used for synchronization of EtherCAT bus slave devices, or synchronization of other application functions or heterogeneous communication buses.

[0050] The sending control module 33 includes multiple message transmitters, supports configuring multiple periodic descriptor linked lists with different periods to send periodic messages, and also supports configuring a non-periodic message linked list. When processing motion control data, the sending control module 33 reads the corresponding motion control data to be sent from the memory module 4 according to the sending signal received by the message transmitter corresponding to the motion control data, and assembles and sends the data according to the clock reference.

[0051] In one embodiment of the present invention, the descriptor chain information includes: configuration information, the first address of the message, the cycle time of the message and the first address of the descriptor.

[0052] Table 1: Transmit descriptor 1 contains the configuration information of the message.

[0053] Bit Logo describe Initial Value access 31 OWN When set to 1, this bit indicates that the descriptor is owned by the master IP core. When this bit is reset to 0, this bit indicates that the descriptor is owned by the CPU. The master IP core clears this bit when it completes frame reception or the buffer associated with this descriptor is full. 0 R W 30:25 reserved reserve 0 R W 24:22 PSN Periodic message sending shielding times 0 R W 21 LS End message, set to 1, indicating that the current message is the last message descriptor of the message group. 0 R W 20 FS The first message, when set to 1, indicates that the current message is the first message descriptor of the message group, and the subsequent message cycles are invalid, and the cycle of this descriptor is used. 0 R W 19 DT Descriptor message type, when set to 1, it means the message is a periodic message, and 0 means the message is a non-periodic message 0 R W 18:15 TDP Send description priority, 0 is the highest priority 0 14 IC Completion interrupt, when set to 1, a transmission completion interrupt will be generated when the message is sent. 0 R W 13 DC CRC disabled, when set to 1, will not add a 32-bit CRC check value at the end of the message 12 TER The circular send descriptor ends. When bit 1 is set, it means that the send descriptor list reaches the last descriptor and returns to the base address of the descriptor list. 0 R W 11 TCH Next descriptor enable, when set to 1, indicates that the next descriptor address is valid. 0 R W 10:0 TBS Length of the sent message 0 R W

[0054] Table 2: Transmit descriptor 2 contains the first address of the message.

[0055] Bit Logo describe Initial Value access 31-0 buffer address Data address of the message 0 R W

[0056] Table 3: Transmit Descriptor 3 contains the cycle time of the message.

[0057] Bit Logo describe Initial Value access 31-0 period The period of a periodic message or the timeout of an aperiodic frame, in units of clock 1 / system frequency. 500 R W

[0058] Table 4: Send descriptor 4 contains the first address of the next descriptor.

[0059] Bit Logo describe Initial Value access 31-0 next descriptor address The first address of the next descriptor 0 R W

[0060] Specifically, the descriptors can be connected in a chain or ring. When the message pointed to by the current descriptor is sent, if there are subsequent descriptors, it will jump to the next descriptor to send the message. The descriptors in the linked list will only start timing after the message of the previous descriptor is sent and the cycle time ends. Therefore, periodic messages and non-periodic messages should not form a linked list, otherwise the sending cycle of the periodic messages following the non-periodic messages will be affected.

[0061] See also Figure 4 In one embodiment of the present invention, the message sent by the message sender includes a periodic message and a non-periodic message. The sending priority of the periodic message is higher than the sending priority of the non-periodic message; and the component message of the motion control data is a periodic message.

[0062] In this embodiment, there are two ways to use periodic messages. One is to describe the same message sending cycle in the chain, indicating data at different times of the same periodic message. The other is that the FS (first message) position of the first descriptor is 1, and all subsequent messages until the LS (end message) position of the descriptor is 1 need to be sent within the cycle time of the first descriptor, that is, a descriptor chain represents multiple messages that need to be sent in one cycle. For example: Cycle 1 includes linked list 1 descriptor 1; linked list 2 descriptor 1, ..., linked list 2 descriptor N. Cycle 2 also includes: linked list 1 descriptor 1; linked list 2 descriptor 1, ..., linked list 2 descriptor N.

[0063] See also Figure 5 In one embodiment of the present invention, the periodic message sending in the descriptor chain can be shielded by PSN (periodic message sending shielding times), that is, the first PSN cycles exist but no message will be sent, and the periodic message will be sent in PSN+1 cycle. In this way, flexible sending of multiple periodic messages can be achieved through a descriptor chain. Non-periodic message sending is sent in sequence through the descriptor chain. When the non-periodic sending in the descriptor linked list times out, the subsequent non-periodic messages in the descriptor chain will stop sending. For example: cycle 1 includes an empty cycle of descriptor 1 in linked list 1. ... Cycle n includes an empty cycle of descriptor 1 in linked list 1. Cycle n+1 includes descriptor 1 in linked list 1.

[0064] See also Figure 6 In one embodiment of the present invention, the sending control module 33 configures multiple message transmitters to support multiple periodic descriptor linked lists of different periods to send periodic messages and send non-periodic message linked lists. The periodic message descriptor supports the configuration of sending priority, and the non-periodic message descriptor will be sent in the order of numbering, and the periodic message sending priority is higher than the non-periodic message. The sending arbitrator will send the periodic message with the highest current priority. If the periodic message cannot be sent within the period, an alarm interrupt will be generated. The module will calculate whether the non-periodic message can be sent in the current period (whether it will affect the sending of the periodic message). The non-periodic message sending supports setting a timeout. If the non-periodic message fails to be sent when the timeout is reached, an alarm interrupt will also be generated. In addition, the sending control module 33 is also configured with an additional message transmitter for sending the motion slice data of the motion analysis IP core 2, and only supports the sending of periodic messages, which is equal to the priority of the periodic message of the descriptor chain. For example, by processing descriptor chain 1 to descriptor N together with the slice movement, by setting the cycle and SOF (Start of Frame) timestamp, and then assembling the message after sending arbitration, the message data is formed and sent to each slave station device 20 through the port physical layer.

[0065] In one embodiment of the present invention, the sending control module 33 is configured to: retrieve descriptor chain information from multiple message senders, and read corresponding data to be sent from the memory module 4 according to the descriptor chain information, and group the messages composed of the clock reference and motion control data into packages and send multiple messages simultaneously in the same cycle.

[0066] In one embodiment of the present invention, the main control processor 1 initializes the communication control master station IP core 3 during initialization configuration, and controls the communication control master station IP core 3 to periodically send messages. The main control processor 1 only needs to update the sending descriptor and the data to be sent in the memory module 4 in a larger control cycle. The sending control module 23 retrieves the descriptor chain information in the message transmitter, reads the data to be sent from the memory according to the information in the descriptor, and assembles and sends the data.

[0067] See also Figure 7 In one embodiment of the present invention, the slice motion control method of the motion parsing IP core 2 can be used simultaneously with the above-mentioned descriptor method. After the slice motion is started, the slice data will be sent in the next cycle. Each cycle contains the motion data of a slice. After all the data is sent, a motion completion interrupt will be generated. If the cycle width supports it, multiple messages can be included in one cycle to improve the flexibility of the EtherCAT bus. For example: cycle n includes linked list 1 descriptor 1 and slice motion 1. Cycle n+1 includes linked list 1 descriptor 1, linked list 2 descriptor 1..., linked list 2 descriptor N and slice motion 2.

[0068] See also Figure 8 A preferred embodiment is provided for the reception and processing of periodic and non-periodic messages. In the process of receiving the message through the port physical layer, after the format conversion of the received message data, the message data will be checked and filtered according to the configured processing mode, and the data will be written to the memory module 4 (RAM) synchronously according to the receiving descriptor. In the message mapping process, the entire message needs to be stored in the receiving cache first, and then the data is mapped according to the mapping table after the message is checked and filtered. Generally, if the message data is mapped to the RAM through hardware, the message will be filtered out during the reception process to reduce the processing load of the main control processor (CPU) 1. Periodic messages can use this method to map data to the RAM, and the CPU only needs to obtain the data in the RAM when needed or idle.

[0069] It can be seen that in the above scheme, the problem of long control cycle time and large jitter caused by the software and hardware performance of the small master processor can be solved. The communication control master station IP core 3 has an independent working clock inside, which can be synchronized with the slave device 20 through synchronization messages. It supports the sending of periodic messages described by descriptor chains, and the hardware automatically completes the cycle control according to the descriptor, reducing the demand for the master processor 1. The master processor 1 can perform data operations in a larger cycle composed of multiple control cycles. Two description methods of periodic messages are supported, one of which has the same message sending cycle in the description chain, indicating data at different times of the same periodic message. The other is that the FS position of the first descriptor is 1, and the subsequent LS position of the descriptor is 1. All messages in between need to be sent and completed within the cycle time of the first descriptor, that is, one descriptor chain represents multiple messages that need to be sent in one cycle. Support multiple descriptor chains configured as different sending cycles, and support multi-cycle control. Support the message corresponding to the descriptor in the descriptor chain to be configurable to mask the cycle, and flexible sending of multiple periodic messages can be achieved through a descriptor chain. Supports the use of motion analysis IP core to perform motion decomposition through hardware, reducing the performance requirements of the CPU. By using the motion analysis IP core 2 and the communication control master IP core 3 to collaborate, the automatic control of motion decomposition, data packaging and periodic transmission is realized, the bus performance is improved, the control cycle is shorter, and the cycle jitter is smaller. Supports the process of message reception, and the data will be checked and filtered according to the configured mode, and the message data will be directly mapped to RAM according to the mapping table.

[0070] In one embodiment of the present invention, the industrial Ethernet system-on-chip provided by the present invention has very low requirements for the master processor 1, and only 100MHz to 200MHz is required to achieve a 1ms control cycle (32 slave devices), and the cycle jitter is within 100ns, which greatly reduces the hardware cost of the master processor 1. At the same time, motion slicing, cycle control and message parsing are realized through hardware algorithms, and the real-time requirements of the software system are greatly reduced, and there is no need to perform additional development on the real-time performance of the system, thereby reducing the difficulty of development.

[0071] like Fig. 9 As shown, the present invention also provides a control method for the system on chip applied to the aforementioned industrial Ethernet, comprising the following steps:

[0072] Step S1, configuring a processing environment for motion data through the main control processor 1, and sending the motion data to the motion analysis IP core 2;

[0073] Step S2, the motion analysis IP core 2 is connected to the main station 10 through the main control processor 1, and the motion analysis IP core 2 receives the motion data to be executed sent by the main station 10, and analyzes the motion data to obtain motion control data;

[0074] Step S3, connect the communication control master station IP core 3 to the motion analysis IP core 2, write the motion control data into the memory module 4 through the communication control master station IP core 3, and package the motion control data in the memory module 4 and send it to the slave device 20 periodically.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A system on chip for industrial Ethernet, characterized in that: include: The main control processor is used to configure the processing environment for motion data and send the motion data to the motion analysis IP core; The motion analysis IP core is connected to the main station through the main control processor, and is used to receive the motion data to be executed sent by the main station, and analyze the motion data to obtain motion control data; as well as The communication control master station IP core is connected to the motion analysis IP core for writing the motion control data into the memory module, and packaging and periodically sending the motion control data in the memory module to the slave station device; The motion analysis IP core includes: A register module, used for receiving the motion configuration information of each axis configured by the main control processor, and sending it to the motion analysis module; An instruction pre-fetching module is used to obtain the G code from the memory module, configure the starting position and slicing cycle of the G code instruction through the main control processor, and send it to the motion analysis module; The motion analysis module is used to analyze the motion configuration information and G code instructions respectively to obtain specific axis motions; A motion decomposition module is used to decompose the specific axis motion to obtain independent motion data of each axis; and A motion slicing module, used to perform motion slicing and compose messages according to the cycle and axis information configured by the register module, and send the messages to the communication control master station IP core; The communication control master station IP core includes: A receiving control module, used for receiving Ethernet messages for scanning, filtering to obtain new messages based on valid descriptor chain information of slave devices, and mapping them into the memory module; A clock module, used to send a clock synchronization message as a clock reference through hardware, and synchronize all slave station devices to the same time of the clock reference; and A sending control module, comprising a plurality of message transmitters, for receiving the new message in the memory module; the sending control module is configured to: read the corresponding motion control data to be sent from the memory module according to the sending signal received by the message transmitter corresponding to the motion control data, and perform packetization and sending according to the clock reference; The transmission control module is configured to: retrieve descriptor chain information from multiple message transmitters, read corresponding data to be transmitted from the memory module according to the descriptor chain information, and respectively group the packets according to the clock reference and the constituent messages of the motion control data and transmit multiple messages simultaneously in the same cycle; After starting the slice motion, the slice data will be sent in the next cycle. Each cycle contains the motion control data of one slice. After all the motion control data are sent, a motion completion interrupt will be generated. With the support of the cycle width, multiple messages are included in one cycle.

2. The industrial Ethernet system on chip according to claim 1, characterized in that: The motion analysis IP core is configured to analyze multiple groups of axis motions, each group of axis motions including at least one and at most six interpolation axes.

3. The industrial Ethernet system on chip according to claim 1, characterized in that: The motion analysis IP core is configured to obtain the motion data inputted through G code and register mode for analysis, and perform cycle and axis parameter configuration to obtain motion control data of each axis.

4. The industrial Ethernet system on chip according to claim 3, characterized in that: The motion analysis IP core is configured to: obtain the G code in the memory module, parse the corresponding action configuration information and G code instructions, and decompose to obtain independent action data of each axis, then configure the cycle and axis information, slice the motion, and send it to the communication control master station IP core.

5. The industrial Ethernet system on chip according to claim 1, characterized in that: The descriptor chain information includes: configuration information, the first address of the message, the cycle time of the message and the first address of the descriptor.

6. The industrial Ethernet system on chip according to claim 1, characterized in that: The messages sent by the message transmitter include periodic messages and non-periodic messages, wherein the sending priority of the periodic messages is higher than the sending priority of the non-periodic messages; and the constituent messages of the motion control data are periodic messages.

7. A control method for an industrial Ethernet system on chip applied to any one of claims 1-6, characterized in that: The steps include: The main control processor configures the processing environment for motion data and sends the motion data to the motion analysis IP core; The motion analysis IP core is connected to the main station through the main control processor, and the motion data to be executed sent by the main station is received through the motion analysis IP core, and the motion data is analyzed to obtain motion control data; The communication control master station IP core is connected to the motion analysis IP core for communication, and the motion control data is written into the memory module through the communication control master station IP core, and the motion control data in the memory module is packaged and periodically sent to the slave station device.

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