Methods, apparatus, processors, network devices and systems for improving transmission rates

Abstract

This application provides a method, apparatus, processor, network device, and system for improving transmission rate. The method includes: obtaining first data at a first rate; adding additional data to the first data at a certain proportion to obtain second data; and transmitting the second data at a second rate greater than the first rate. By adding additional data to the first data at a certain proportion, the transmission rate is increased, thereby breaking the limitations imposed by the backplane on device expansion and upgrades. This not only avoids frequency gaps but also adapts to future performance requirements.

Description

[0001] This application is a divisional application. The original application has the application number 201910731452.X and the original application date is August 8, 2019. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and specifically to a method, apparatus, processor, network device, and system for improving transmission rate. Background Technology

[0003] Communication equipment is expensive, and upgrades often employ a smooth evolution approach, first upgrading modules and line cards to achieve higher performance and newer features. Consequently, the backplane becomes one of the biggest bottlenecks limiting communication equipment upgrades; its performance often determines the upgradeability and lifespan of the equipment. However, as hardware, the backplane sometimes struggles to meet future performance requirements. Summary of the Invention

[0004] This application provides methods, apparatus, processors, network devices, and systems for improving transmission rates.

[0005] On the one hand, a method for improving transmission rate is provided, comprising: obtaining first data at a first rate; adding additional data to the first data in a certain proportion to obtain second data; and sending the second data at a second rate greater than the first rate. By adding additional data to the first data in a certain proportion, the transmission rate is improved, thereby breaking the limitations of the backplane on device expansion and upgrades, avoiding frequency gaps, and adapting to future performance requirements.

[0006] In one exemplary embodiment, the second rate is not an integer multiple of the first rate.

[0007] In one exemplary embodiment, transmitting the second data at a second rate includes: transmitting the second data at a second rate using a physical channel, wherein the data transmission rate of the physical channel is determined based on bit multiplexing of an expanded virtual channel, and the number of expanded virtual channels is determined based on the number of virtual channels transmitting the first data and the number of physical channels corresponding to the data transmission interface transmitting data at the second rate. For cases where the second rate is not an integer multiple of the first rate, the number of virtual channels is adjusted to support the number of physical channels at that second rate.

[0008] In one exemplary embodiment, the additional data is located in the first portion of the second data. In this manner, the additional data can be added to the first data as a whole; for example, the first portion of the second data could be positioned before or after the alignment mark AM character.

[0009] In one exemplary embodiment, a first portion of the additional data is located within a first portion of the second data, and a second portion of the additional data is located within a second portion of the second data, with a portion of the first data included between the first and second portions of the additional data. In this manner, the additional data is added to the first data in segments. Exemplarily, the first data may be divided into multiple portions, and the additional data is added to different portions of the first data in segments.

[0010] In one exemplary embodiment, the first data includes the AM character, and the step of adding additional data to the first data at a certain proportion includes: using the AM character in the first data as a boundary, inserting additional data into the first data at a certain proportion. Since the AM character provides an existing marker for data recognition, additional data can be inserted using the AM character as a reference point, thereby facilitating subsequent recognition of the inserted data.

[0011] In one exemplary embodiment, adding additional data to the first data at a certain proportion to obtain the second data includes: when the first data is data from the Media Access Control (MAC) layer, inserting first additional data into the MAC layer data at a first proportion to obtain the second data; or, when the first data is data transmitted on a Virtual Lane (VL) after distribution by the Forward Error Correction (FEC) sublayer, inserting second additional data into the data transmitted on the VL after distribution by the FEC sublayer at a second proportion to obtain the second data; or, when the first data is data after VL remapping but before entering the physical link, inserting third additional data into the data after VL remapping but before entering the physical link at a third proportion to obtain the second data; or, when the first data is data transmitted on the physical link, inserting fourth additional data into the data transmitted on the physical link at a fourth proportion to obtain the second data; or, when the first data is original data, inserting fifth additional data into the original data at a fifth proportion to obtain the second data. A physical link can have multiple physical lanes, allowing for flexible insertion of additional data at multiple locations.

[0012] In one exemplary embodiment, adding additional data to the first data at a certain proportion to obtain the second data includes: encoding the first data using forward error correction (FEC) codes based on the second rate to obtain the second data. Because the rate increase leads to increased insertion losses from backplane wiring and connectors relative to the backplane design specifications, and also increases crosstalk between signals, the signal-to-noise ratio (SNR) is significantly reduced. Avoiding frequency holes requires link speed-up, which introduces overhead. This overhead can be utilized to compensate for the SNR loss by adding additional forward error correction (FEC).

[0013] In one exemplary embodiment, the step of encoding the first data with a forward error correction (FEC) code based on the second rate to obtain the second data includes: when the first data is data transmitted on a virtual channel (VL) after FEC sublayer distribution and encoded using a first FEC code pattern, performing secondary encoding on the data transmitted on the VL after FEC sublayer distribution and encoded using the first FEC code pattern using a second FEC code pattern that matches the rate ratio to obtain the second data, wherein the rate ratio is the ratio of the second rate to the first rate; or, when the first data is data after VL remapping and before entering the physical link and encoded using a first FEC code pattern, performing secondary encoding on the data after VL remapping and before entering the physical link and encoded using the first FEC code pattern using a second FEC code pattern that matches the rate ratio to obtain the second data; Alternatively, when the first data is data transmitted on the physical link and encoded using the first FEC code pattern, the data transmitted on the physical link and encoded using the first FEC code pattern is encoded using the second FEC code pattern that matches the rate ratio to obtain the second data; or, when the first data is data encoded using the first FEC code pattern, the data encoded using the first FEC code pattern is decoded to obtain the original data, and the original data is encoded using the third FEC code pattern that matches the second rate to obtain the second data, wherein the overhead of the third FEC code pattern is greater than the overhead of the first FEC code pattern; or, when the first data is the original data, the original data is encoded using the third FEC code pattern that matches the second rate to obtain the second data, wherein the overhead of the third FEC code pattern is greater than the overhead of the first FEC code pattern.

[0014] On one hand, an apparatus for improving transmission rate is provided, the apparatus comprising: an acquisition module for acquiring first data at a first rate; a processing module for adding additional data to the first data at a certain proportion to obtain second data; and a sending module for sending the second data at a second rate greater than the first rate.

[0015] In one exemplary embodiment, the second rate is not an integer multiple of the first rate.

[0016] In one exemplary embodiment, the sending module is configured to send the second data at a second rate using a physical channel, wherein the data transmission rate of the physical channel is determined based on bit multiplexing of the expanded virtual channel, and the number of the expanded virtual channels is determined based on the number of virtual channels transmitting the first data and the number of physical channels corresponding to the data transmission interface transmitting data at the second rate.

[0017] In one exemplary embodiment, the additional data is located in the first portion of the second data.

[0018] In one exemplary embodiment, a first portion of the additional data is located within a first portion of the second data, and a second portion of the additional data is located within a second portion of the second data, with a portion of the first data included between the first portion and the second portion of the additional data.

[0019] In one exemplary embodiment, the first data includes alignment marker AM characters, and the processing module is configured to insert additional data into the first data at a certain proportion, using the AM characters in the first data as boundaries.

[0020] In one exemplary embodiment, the processing module is configured to: when the first data is data from the Media Access Control (MAC) layer, insert first additional data into the data at a first ratio to obtain second data; or when the first data is data transmitted on a Virtual Channel (VL) after distribution by the Forward Error Correction (FEC) sublayer, insert second additional data into the data transmitted on the VL after distribution by the FEC sublayer to obtain second data; or when the first data is data after VL remapping but before entering the physical link, insert third additional data into the data after VL remapping but before entering the physical link to obtain second data; or when the first data is data transmitted on the physical link, insert fourth additional data into the data transmitted on the physical link at a fourth ratio to obtain second data; or when the first data is original data, insert fifth additional data into the original data at a fifth ratio to obtain second data.

[0021] In one exemplary embodiment, the processing module is configured to encode the first data using forward error correction (FEC) codes based on the second rate to obtain the second data.

[0022] In one exemplary embodiment, the processing module is configured to: when the first data is data transmitted on a Virtual Channel (VL) after FEC sublayer distribution and encoded using a first FEC code pattern, perform secondary encoding on the data transmitted on the VL after FEC sublayer distribution and encoded using the first FEC code pattern using a second FEC code pattern matching the rate ratio to obtain second data, wherein the rate ratio is the ratio of the second rate to the first rate; or, when the first data is data after VL remapping and before entering the physical link and encoded using the first FEC code pattern, perform secondary encoding on the data after VL remapping and before entering the physical link and encoded using the first FEC code pattern using a second FEC code pattern matching the rate ratio to obtain second data; or, when the first data is data uploaded to the physical link... When transmitting data encoded using the first FEC code pattern, the data transmitted on the physical link and encoded using the first FEC code pattern is further encoded using the second FEC code pattern that matches the rate ratio to obtain the second data; or, when the first data is data encoded using the first FEC code pattern, the data encoded using the first FEC code pattern is decoded to obtain the original data, and the original data is encoded using the third FEC code pattern that matches the second rate to obtain the second data, wherein the overhead of the third FEC code pattern is greater than the overhead of the first FEC code pattern; or, when the first data is the original data, the original data is encoded using the third FEC code pattern that matches the second rate to obtain the second data, wherein the overhead of the third FEC code pattern is greater than the overhead of the first FEC code pattern.

[0023] A processor is also provided, which can be used to perform any of the methods described above.

[0024] A network device is also provided, the network device including the processor described above.

[0025] In one exemplary embodiment, the network device includes a line card, which includes the processor described above.

[0026] In one exemplary embodiment, the network device further includes a backplane.

[0027] In one exemplary embodiment, the network device further includes a CDR circuit located between the line card and the backplane, the line card communicating with the backplane via the CDR circuit.

[0028] A network system is also provided, the network system including one or more network devices, the network devices being any of the network devices described above.

[0029] A device for improving transmission rate is also provided, the device comprising: a memory and a processor, the memory storing at least one instruction or program, the at least one instruction or program being loaded and executed by the processor to implement any of the methods for improving transmission rate described above.

[0030] A computer-readable storage medium is also provided, wherein at least one instruction or program is stored therein, the instruction or program being loaded and executed by a processor to implement the method for improving transmission rate as described above.

[0031] Another communication device is provided, comprising a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other via internal interconnection. The memory stores instructions or programs, and the processor executes the instructions or programs stored in the memory to control the transceiver to receive and transmit signals. When the processor executes the instructions or programs stored in the memory, it causes the processor to perform the methods described in any of the possible implementations above. In one embodiment, the processor, memory, and transceiver can communicate via a bus.

[0032] As an exemplary embodiment, the processor may be one or more, and the memory may be one or more.

[0033] As an exemplary embodiment, the memory may be integrated with the processor, or the memory may be disposed separately from the processor.

[0034] In specific implementation, the memory can be a non-transitory memory, such as read-only memory (ROM), which can be integrated with the processor on the same chip or set on different chips. The embodiments of this application do not limit the type of memory or the way the memory and processor are set.

[0035] A computer program (product) is provided, the computer program (product) comprising: computer program code, which, when executed by a computer, causes the computer to perform the methods described in the above aspects.

[0036] A chip is provided, including a processor for calling and running instructions or programs stored in a memory, causing a communication device on which the chip is mounted to perform the methods described above.

[0037] Another chip is provided, comprising: an input interface, an output interface, a processor, and a memory, wherein the input interface, the output interface, the processor, and the memory are connected via an internal connection path, and the processor is used to execute code in the memory, wherein when the code is executed, the processor is used to perform the methods described above. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a network system provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the network device provided in the embodiments of this application;

[0040] Figure 3 This is a schematic diagram of the network device provided in the embodiments of this application;

[0041] Figure 4A This is a schematic diagram of the logical architecture of the Ethernet interface provided in an embodiment of this application;

[0042] Figure 4B This is a flowchart of a method for improving transmission rate provided in an embodiment of this application;

[0043] Figure 5A This is a schematic diagram of an encoding provided in an embodiment of this application;

[0044] Figure 5B This is another encoding diagram provided in an embodiment of this application;

[0045] Figure 5C This is a schematic diagram of a method for improving data transmission rate provided in an embodiment of this application;

[0046] Figure 6 These are schematic diagrams illustrating various scenarios for inserting additional data pads as provided in the embodiments of this application;

[0047] Figure 7 This is a schematic diagram of a scenario where stuffing MAC frames(s) is added to the MAC layer, as provided in an embodiment of this application.

[0048] Figure 8A This is a schematic diagram of the method for expanding VL by corresponding AM0 to AM7 through 8 VLs provided in the embodiments of this application;

[0049] Figure 8B This is a schematic diagram of a method for reusing 8 VLs to expand VLs using 24 VLs, as provided in an embodiment of this application.

[0050] Figure 9 This is a schematic diagram of the device structure for improving transmission rate provided in the embodiments of this application;

[0051] Figure 10 This is a schematic diagram of the device structure for improving transmission rate provided in the embodiments of this application. Detailed Implementation

[0052] To enable those skilled in the art to better understand the present application, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings and implementation methods.

[0053] like Figure 1 The diagram illustrates a network scenario according to an embodiment of this application. In this scenario, one or more user devices 11, 12, 13, etc., access the network via multiple network devices 11, 12, and reach a remote network device 31 via one or more intermediate network devices 20 in the network, and finally communicate with one or more remote user devices 41, 42, 43 via network device 31. Figure 1 The network can be a local area network (LAN) or a carrier network. Figure 1 Network devices, such as routing or switching devices, can act as forwarding or gateway devices in a network. Network devices can be communication devices or other electronic devices.

[0054] like Figure 2 As shown, the network device includes a line card, a main processing unit (MPU), and a backplane. The line card and the MPU are interconnected via the backplane. Figure 3 As shown, line cards and MPUs can be interconnected with the backplane via connectors. A line card, also known as a line processing unit (LPU), is used for forwarding packets and can be categorized by forwarding capability as 10G (gigabit), 20G, 40G, 50G, 100G, 120G, 240G, etc. The MPU is responsible for the centralized control and management of network devices; for example, the MPU can perform routing calculations, device management and maintenance functions, data configuration functions, and data storage functions. Network devices may also include physical interface cards (PICs), which can be plugged into the interface board of the line cards and are responsible for converting photoelectric signals into data frames and performing "validity" checks on the data frames. In some embodiments, the network device also includes a switch fabric, also known as a switch fabric unit (SFU), which is responsible for data exchange between the various LPUs. The switch fabric can be interconnected with the main control board and line cards via the backplane.

[0055] A backplane comprises multiple channels. The number of channels on each backplane varies depending on the speed and specifications, but the number of channels on a single backplane is fixed. Each channel on the backplane can be used to transmit data. Since there is an upper limit to the data transmission rate supported by a channel on any given circuit board, when network equipment needs to be upgraded, the backplane on the existing network equipment cannot be cross-generationally compatible with the speed of the new serializer / deserializer (SerDes) in the processor. The processor can be a network processor (NP) or a central processing unit (CPU). This processor is used in port chips or switching chips. Specifically, the port chip or switching chip can be an application-specific integrated circuit (ASIC) or a clock & data recovery (CDR), while the SerDes can be circuitry within an ASIC or CDR. In practice, the backplane capacity limit = number of channels × maximum data transmission rate per channel.

[0056] Taking the current 400GbE port rate as an example, the SerDes rate on each physical channel of the electrical interface, according to the IEEE 802.3 standard, can be:

[0057] -26.5625 gigabits per second (Gbps) (16-channel 400GAUI-16)

[0058] -53.125Gbps (8-channel 400GA UI-8),

[0059] -106.25Gbps (4-channel 400GAUI-4, standard under development).

[0060] In addition to the rates mentioned above, SerDes typically supports other rates that are integer multiples of 156.25 MHz. For example, 112.5 Gbps 4-level pulse amplitude modulation (PAM, PAM4) (56.25 gigabaud, GBd).

[0061] There is currently no standard for next-generation Ethernet interface speeds. The following discussion assumes 800GbE using an 8x electrical interface, but is not limited to this speed. To achieve a smooth upgrade, the key is for the current backplane to support next-generation Ethernet speeds, increasing the overall capacity by improving the port speeds on the line cards. For example... Figure 3As shown, the backplane connects to the line card via connectors. Achieving 8×100G speeds using the same backplane and connectors as in the 8×50G era would be difficult to achieve given the performance specifications of the printed circuit board (PCB) and connectors. If the backplane continues to use 50G single-channel technology, the overall capacity remains the same, without improvement, and future standards may not even support 50G single-channel speeds. Therefore, other single-channel speeds need to be considered. However, because SerDes designs often have frequency limitations, operating only within certain ranges, it's necessary to confirm whether the desired speed is supported by SerDes. If a frequency gap exists that SerDes doesn't support (frequency holes), it needs to be avoided. Increasing the single-channel speed, compared to the backplane design specifications, will increase insertion losses from backplane wiring and connectors, and crosstalk between signals will also increase, leading to a significant decrease in the signal-to-noise ratio (SNR). Avoiding frequency holes requires increasing link speed, which also brings certain overhead. Therefore, this overhead can be used to compensate for SNR loss by adding additional forward error correction (FEC).

[0062] In SerDes design, the phase-locked loop (PLL) is the core circuit that determines its operating frequency. The PLL's operating frequency is typically not continuously adjustable, but rather a multiple of a fundamental frequency. While flexible PLL designs can support both integer and fractional frequency multiples, the operating frequency is still not continuously adjustable. This inherently means that SerDes cannot support all frequencies, but only certain fixed frequency points. We call the frequency range that the PLL does not support a "frequency hole."

[0063] Furthermore, because SerDes designs are often optimized for the frequencies required for operation, they may choose not to support or provide performance degradation at non-operational frequencies. For example, 53.125Gbps and 106.25Gbps are commonly used SerDes rates, but the area around 80Gbps may be an uncommon rate. Therefore, the design may be simplified to avoid the frequency band around 80Gbps, resulting in a larger frequency gap. For instance, a certain SerDes may choose not to support rates between 75G and 85Gbps to simplify the design and reduce costs.

[0064] In this application embodiment, the following three high link rate methods are provided:

[0065] a) Select an FEC with appropriate overhead based on the overhead space available for the target rate;

[0066] b) Insert additional data, either all at once or in segments, using the alignment marker (AM) character as the boundary; the data format is not limited.

[0067] c) Insert additional data through the medium access control (MAC) layer. This additional data can be special, identifiable code blocks.

[0068] This application also provides a method for expanding the number of PCS lanes to accommodate non-standard rate physical interfaces.

[0069] like Figure 2 The diagram shows a network device according to an embodiment of this application. A backplane connects the main control board and the line card. The main control board includes ASIC1, and the line card includes ASIC2. In some embodiments, the main control board also includes a clock and data recovery (CDR) circuit CDR1 that communicates with ASIC1. In some embodiments, the line card also includes a clock and data recovery circuit CDR2 that communicates with ASIC2. In some embodiments, the CDR circuit may appear on the main control board or the line card, but it may not be necessary if the ASIC capability is sufficient. This embodiment is related to some or all of ASIC1, CDR1, CDR2, and ASIC2. ASIC1 in the main control board can communicate with the backplane, and ASIC2 in the line card can communicate with the backplane. Figure 3 As shown, the main control board and line card can be connected to the backplane via connectors, thereby communicating with the backplane.

[0070] like Figure 4A As shown, Figure 1 or Figure 2 or Figure 3 The logical layer architecture corresponding to the Ethernet interface on the network device. Based on different implementation locations in the system according to embodiments of this application, this... Figure 4AThere will be slight differences. PCS / FEC refers to the PCS layer and FEC sublayer functions defined in the IEEE 802.3 standard. This functionality is typically integrated into an ASIC. The physical coding sublayer (PCS) encodes, transcodes, scrambles, inserts AM and FEC codes into the data from the MAC layer, and distributes the processed data to multiple virtual lanes (VLs) or physical lanes (PLs) according to a certain pattern. The pattern for distributing the processed data to multiple VLs or PLs is not limited in this application; for example, it can be determined based on the scenario or data encoding requirements. For instance, taking a 200GE / 400GE Ethernet interface as an example, any two consecutive FEC symbols come from different codewords; that is, two consecutive FEC symbols of one codeword are distributed to different VLs or PLs. However, for a 100GE Ethernet interface, FEC symbols are sent to each VL or PL in a round-robin fashion.

[0071] like Figure 4A As shown, the processed data is transmitted to the Physical Medium Attachment Sublayer (PMA) via n Virtual Links (VLs). The PMA then transmits the data from multiple VLs to p channels. For example, bit-muxing can be performed before PMA transmission. For instance, the data processed by the PCS / FEC is distributed across p channels on the Attachment Unit Interface (AUI), where p channels can be VLs. The data on the p channels is remapped to m physical channels (PLs) on the backplane, where m and p are positive integers and m > p > 0. After backplane processing, the data leaves the backplane via the m physical channels, is regrouped, and then reaches another PCS / FEC via p channels, where p channels can be VLs. For example, the other PCS / FEC can support a different number of VLs; this embodiment does not limit this.

[0072] Taking the existing 400GbE standard as an example, the data processed by the PCS layer is distributed to 16 VLs, and the equivalent bit rate on each VL is 26.5625Gbps. The number of physical lanes (PLs) is determined by the specific application. For example, if the single-channel 50G PAM4 technology (also commonly referred to as 56G PAM4 in the industry, with an actual rate of 53.125Gbps) is adopted in the backplane design, the number of PLs is 8. Assuming the total number of channels in the backplane design here is M, the design capacity of this backplane is 50G×M. If you want to upgrade the device and replace the single board that supports a higher electrical interface rate, for example, a single board that supports the single-channel 100G PAM4 technology (also known as 112G PAM4 in the industry, with an actual rate of 106.25Gbps), the capacity of the whole machine can be increased by increasing the rate of each channel. However, whether it is the wiring on the PCB or the connector between the single board and the backplane, its performance is restricted by many aspects such as materials and design, and it is difficult to cope with the new higher rate. Therefore, it is necessary to find a suitable electrical interface transmission rate B2 that is higher than the original electrical interface rate B0 but lower than the new electrical interface rate B1. Among them, B0 < B2 < B1.

[0073] Assume that under the new electrical interface rate, the number of physical lanes corresponding to an Ethernet interface of a certain rate standard is N1. The rate of this Ethernet interface is equal to N1×B1. (For example, for a 400GbE interface, if B1 = 100Gbps, then N1 = 4) The number of electrical interface channels corresponding to B2 is N2, then: B2×N2 = B1×N1. Since B2 < B1, so N2 > N1.

[0074] In the existing Ethernet standards, the number of physical lanes P that a certain Ethernet interface rate can support depends on the number of virtual lanes N. For example, 16 virtual lanes can correspond to generating 16 or 8 or 4 etc. numbers of physical lanes, which can be achieved through simple bit multiplexing. If the rate of the electrical interface is doubled, the corresponding number of physical lanes can be reduced to 1 / 2 of the original. However, if the multiple of the electrical interface rate increase is not an integer multiple, it is necessary to adjust the number of virtual lanes N to support the number of physical lanes P2 at this rate B2. Still taking 400GbE as an example, between 8×50G and 4×100G, there may be a combination of 5×80G (B2 = 80G, N2 = 5). For future 800GbE, there may be a combination of 8×100G. If the backplane cannot support the 100G electrical interface, there may be rates such as 10×80G or 12×66.67G etc. Even, as long as it can be ensured that N2×B2 >= N1×B1, there will be enough ability to transmit the total data rate of N1×B1 through N2 electrical interfaces with a rate lower than the standard rate.

[0075] In the above embodiments, an example of supporting 800GbE with 10×80G was given. If SerDes does not support this electrical interface rate, it is difficult to adopt this configuration. To avoid this gap, the data transmission rate on the electrical interface can be increased. Reducing the electrical interface rate requires more physical channels on the backplane, and this number is fixed. To fully utilize the channels on the backplane, N2 is often calculated as the maximum utilization value based on the backplane's transmission capacity. If the electrical interface rate is reduced, the N2 value needs to be increased, thus reducing the total number of Ethernet interfaces that the backplane can support. Increasing the bit rate of data transmission on the electrical interface, but with a fixed payload, requires inserting additional data into the original data stream. Increasing the data transmission rate on the electrical interface means greater insertion loss in the backplane channels and greater crosstalk between signals, thus reducing link performance and potentially causing excessively high bit error rates and other problems.

[0076] To address this issue, this application provides a method for improving transmission rate. This method increases the transmission rate by adding additional data to the first data in a certain proportion. This breaks the limitations imposed by the backplane on device expansion and upgrades, not only avoiding frequency gaps but also adapting to future performance requirements. See also... Figure 4B The method includes:

[0077] 401, Obtain the first data at the first rate.

[0078] The first data can be FEC-encoded data or raw data. This application does not limit the type of the first data.

[0079] For example, combining Figure 2 Taking the network device shown as an example, in the logical layer architecture corresponding to the Ethernet interface on the network device, the PCS / FEC processes the data from the MAC layer through encoding, transcoding, scrambling, and inserting AM and FEC encoding to obtain the first data. Then, the processed data, i.e., the first data, is distributed to multiple VLs or PLs according to a certain rule. The transmission rate of this first data can be a first rate. In this embodiment, the first data can be obtained on multiple VLs or PLs transmitting the first data after the PCS / FEC. Alternatively, the data after VL remapping but before entering the physical link can be used as the first data obtained at the first rate. A physical link can have multiple physical lanes. For example, the first data can also be obtained on the physical link, or the original data can be obtained before the ASIC performs FEC encoding, and this original data serves as the first data. Alternatively, the first data can also be obtained at the CDR communicating with the ASIC.

[0080] 402. Add extra data to the first data in a certain proportion to obtain the second data.

[0081] For example, when additional data is added to the first data in a certain proportion, the additional data can be located in the first part of the second data. In this way, the additional data can be added to the first data as a whole. This embodiment does not limit the specific position of the first part of the second data; it can be determined based on the content of the first data or based on the scenario. For example, the first part of the second data can be located before or after the "AM" character.

[0082] Alternatively, the first portion of the additional data is located within the first portion of the second data, and the second portion of the additional data is located within the second portion of the second data, with a portion of the first data included between the first and second portions of the additional data. In this manner, the additional data is added to the first data in segments. For example, the first data can be divided into multiple portions, and different portions of the additional data are added between different portions of the first data.

[0083] Regardless of the insertion method used, the method provided in this application embodiment can insert additional data in multiple locations, offering flexibility. The following three methods for adding additional data will be illustrated with examples.

[0084] Method 1: In one embodiment of this application, the addition of additional data is exemplified by integrating FEC by utilizing the additional overhead brought about by increasing the rate.

[0085] In this first method, the first data can be encoded using forward error correction (FEC) codes based on the second rate to obtain the second data. For example... Figure 5CAs shown, ASIC1 communicates with ASIC2 via a backplane. ASIC1 includes a MAC, PCS, and a distribution module. ASIC1 may also include some positioning adjustment circuitry. A CDR1 may also be included between ASIC1 and the backplane. ASIC2 includes alignment / deskew circuitry, regrouping circuitry, distribution circuitry, PCS, and MAC. For example, rate adjustment can also be performed at the locations of the alignment / deskew circuit ⑨, demultiplexing circuit ⑩, and regrouping distribution circuit 11. A CDR2 may also be included between ASIC2 and the backplane. Data is processed by the MAC layer of ASIC1 and then reaches the PCS of ASIC1. The PCS includes an FEC sublayer. Data is processed by the FEC sublayer and then reaches the distribution circuitry, which distributes it to N VLs. Data from the N VLs undergoes several possible positioning adjustments, such as... Figure 5C After the operation of functional circuits ④, ⑤, and ⑥, the data reaches the backplane. Here, ④ is the encoding function circuit, ⑤ is the bit multiplexing circuit, and ⑥ is the encoding function circuit. Alternatively, it may reach the backplane after being processed by CDR1 in ⑦. After backplane processing, the data reaches the Alignment / Deskew circuit (i.e., ⑨) of ASIC2. After processing by the Alignment / Deskew circuit, it reaches ⑩ and the regroup and distribution circuits located in ⑾. After further processing, it reaches the standard processing circuit located in ⑿, and finally reaches the PCS and MAC layers of ASIC2.

[0086] Continuing with the example of transmitting the first data at a rate of 80Gbps on a single physical channel and transmitting the second data at a rate of 85Gbps on the same channel, the rate ratio of the second rate to the first rate is 85 / 80 = 17 / 16. Therefore, the ratio of extra data to the first data is 1 / 16, and the ratio of extra data to the second data is 1 / 17. The ratio of encoded data to bit data in an FEC code pattern that matches the rate ratio is the rate ratio. For example, when the rate ratio is 17 / 16, the FEC code pattern that matches the rate ratio is an FEC where the ratio of encoded data to bit data is 17 / 16. For example... Figure 5A As shown, RS(34,32), BCH(340,320), etc., where BCH(340,320) is a type of BCH forward error correction coding (Bose–Chaudhuri–Hocquenghem code, BCH code). Or as... Figure 5BIf there is a certain proportional error between the overhead of FEC and the overhead of the speed increase, an FEC+pad approach can be used for speedup. For example, Hamming (127, 120) can be used, with a 50-bit pad inserted after every 100 Hamming blocks. These 50 bits of pad are used as additional data. Figure 5C As shown, this scheme can be implemented in multiple locations. For example, based on the second rate, the first data can be encoded using FEC codes to obtain the second data, including but not limited to the following methods:

[0087] A. Implemented on the VL after the FEC sublayer distribution (icon ④).

[0088] In method A, the FEC sublayer distributes data to multiple VLs, and the VL data can then directly access one or more second-level FEC encoders, maintaining the same number of VLs after encoding.

[0089] For example, when the first data is data transmitted on the VL after FEC sublayer distribution and encoded using the first FEC code pattern, the data transmitted on the VL after FEC sublayer distribution and encoded using the first FEC code pattern is further encoded using the second FEC code pattern that matches the rate ratio to obtain the second data. Here, the rate ratio is the ratio of the second rate to the first rate.

[0090] B. Implemented after VL remapping and before entering the physical link (see icon ⑥).

[0091] In mode B, VL has already generated the corresponding number of physical channels through bit multiplexing. At this time, the data streams on different physical channels can be encoded using the second-level FEC encoding in the ASIC.

[0092] For example, the first data is the data after VL remapping and before entering the physical link, and encoded using the first FEC code pattern. The second data is obtained by using the second FEC code pattern that matches the rate ratio to perform secondary encoding on the data after VL remapping and before entering the physical link, and encoded using the first FEC code pattern.

[0093] C. Obtain the data stream on the physical link and then encode it (see icon ⑦).

[0094] In the C mode, when data on the physical link passes through CDR1, it undergoes a second-level FEC encoding.

[0095] For example, when the first data is data transmitted on the physical link and encoded using the first FEC code pattern, the data transmitted on the physical link and encoded using the first FEC code pattern is encoded using the second FEC code pattern that matches the rate ratio to obtain the second data.

[0096] D. ASIC directly uses single-level or multi-level FEC for encoding, which has higher overhead (see icon ②).

[0097] In the D mode, the ASIC is directly encoded according to the new, higher-gain FEC.

[0098] For example, the first data is the original data. The original data is encoded using a third FEC code pattern that matches the second rate to obtain the second data. The overhead of the third FEC code pattern is greater than that of the first FEC code pattern.

[0099] E.CDR1 terminates the original FEC and uses a single-level or multi-level FEC with higher overhead for encoding (see icon ⑦).

[0100] In E mode, CDR1 reassembles, decodes, and corrects errors on the data on the link, and then performs new FEC encoding.

[0101] For example, the first data is data encoded using the first FEC code pattern. The data encoded using the first FEC code pattern is decoded to obtain the original data. The original data is then encoded using the third FEC code pattern that matches the second rate to obtain the second data. The overhead of the third FEC code pattern is greater than that of the first FEC code pattern.

[0102] In methods D and E, regardless of whether it's the third or first FEC code type, the overhead of the FEC code type is the data difference, which is the difference between the encoded data and the original data. The encoded data is the data obtained by encoding the original data using the FEC code type. For example, if the encoded data obtained by encoding the original data using the first FEC code type is encoded data 1, then the overhead of the first FEC code type is the difference between encoded data 1 and the original data. Similarly, if the encoded data obtained by encoding the original data using the third FEC code type is encoded data 3, then the overhead of the third FEC code type is the difference between encoded data 3 and the original data. The new FEC, or the third FEC code, can be a code of the same type as the first FEC code, FEC1, but with higher overhead (for example, FEC1 uses RS(544,514), while the new FEC uses Reed-Solomon forward error correction code (RS-FEC), such as RS(576,514)). Alternatively, the new FEC can be a completely different type of FEC from the first FEC code, but with stronger error correction capabilities.

[0103] Method 2: In another embodiment of this application, inserting additional data at the MAC layer is taken as an example. This method is suitable for scenarios where the link condition is relatively healthy and the SNR still meets the requirements after increasing the rate. For example, when the first data is MAC layer data, first additional data is inserted into the MAC layer data at a first ratio to obtain second data. The first ratio can be determined based on the data volume of the second data and the first data, and is not limited in this embodiment of the application.

[0104] like Figure 7 As shown, stuffing MAC frames can be added between normal MAC frames. These stuffing frames can be idle frames or other specially defined data frames that can be recognized and discarded by the peer's MAC layer. The stuffing frames here are similar to the extra data pads mentioned above. In this method, the MAC layer at the receiving end can recognize the original data and locate the extra data pads by examining code blocks or characters within the original data.

[0105] Method 3: In another embodiment of this application, if the first data includes the character AM, then additional data is inserted into the first data at a certain proportion, using AM as the boundary.

[0106] For example, using the AM character as a reference, additional data can be inserted into the data all at once or in segments to increase the data transmission rate. Since FEC encoding can improve SNR, and when the link condition is relatively healthy and the SNR still meets the requirements after increasing the rate, it is not necessary to use FEC encoding to improve the SNR; instead, invalid data can be inserted to achieve the purpose of increasing the data transmission rate. Of course, even if the SNR still meets the requirements after the link condition is relatively healthy and the rate is increased, FEC encoding can still be used, meaning the inserted additional data can be FEC codes. This application does not limit which type of additional data to insert. However, since the original data here is a data stream that has been processed by the PCS layer and no longer has a message format, the receiving end needs to be able to identify and delete the inserted additional data in order to recover the original data according to the PCS layer processing flow. Since the AM character provides an existing marker for data identification, some additional data can be inserted using the AM character as a reference point, thereby facilitating subsequent identification of the inserted data. This data can be added to the VL along with the AM character. Figure 5C It can be inserted at position ④, or it can be inserted after bit multiplexing. Figure 5C Implemented at point ⑥. For example, when the first data is... Figure 5CWhen transmitting data on the VL after the FEC sublayer distribution at point ④, second additional data is inserted into the data transmitted on the VL after the FEC sublayer distribution at a second ratio, with the AM character as the boundary, to obtain the second data. For example, when the first data is... Figure 5C When the data at point ⑥ has undergone VL remapping but is before entering the physical link, a third additional data is inserted into the data after VL remapping but before entering the physical link, with the AM character as the boundary, to obtain the second data. It should be noted that the second and third ratios can be determined based on the data volume of the first and second data, and this application does not limit them in this way.

[0107] Regardless of where the extra data is inserted, the methods for inserting extra data with the AM character as the boundary include, but are not limited to, the following: Figure 6 The types shown are as follows: Figure 6 Each insertion method in the code is as follows:

[0108] (1) Divide the data in the middle into equal parts using the two AM characters as boundaries, and insert pads between the equal parts of the data.

[0109] (2) Divide the data in the middle into equal parts using the two AM characters as boundaries, and insert pad before the data in the middle.

[0110] (3) Divide the data in the middle into equal parts using the two AM characters as boundaries, and insert pad after the data.

[0111] (4) Divide the data in the middle into equal parts using the two AM characters as boundaries, and insert pads before and after the data.

[0112] (5) Insert pad after the AM character all at once.

[0113] (6) Insert pad once before the AM character.

[0114] For the selection of additional data (pads), it is recommended to use the PRBS31 sequence to select segments sequentially to ensure data randomness and avoid spectral spikes. The length of the additional data pads can be chosen according to the implementation method. There are also various ways to insert the additional data pads, such as inserting them before or after the AM character, as long as the ratio of the inserted additional data pads to the data (including the AM character) meets the requirements. Alternatively, in the implementation, a sufficient number of additional data pads can be inserted at once, rather than inserted in segments.

[0115] Besides the three methods mentioned above, there are other ways to insert data. For example, in... Figure 5C Insert additional data at position ⑦ as shown. For example, when the first data is... Figure 5C When transmitting data on the physical link at point ⑦, a fourth additional data is inserted into the data transmitted on the physical link at a fourth ratio to obtain the second data. For example, when the first data is the original data, a fifth additional data is inserted into the original data at a fifth ratio to obtain the second data. The fourth and fifth ratios can be determined based on the data volume of the first data and the data volume of the second data, and this application does not limit them in this regard.

[0116] 403, send the second data at the second rate, which is greater than the first rate.

[0117] For example, the second rate can be an integer multiple of the first rate, or it may not be an integer multiple of the first rate. Regarding the case where the second rate is not an integer multiple of the first rate, if the virtual channel rate is too high after speed-up, even multiplexing at the minimum rate in the virtual channel will exceed the rate the physical channel can handle. The method provided in this application expands the virtual channel and uses bit multiplexing to determine the second rate of the physical channel. For the case where the second rate is not an integer multiple of the first rate, another embodiment of this application provides a method for expanding the virtual channel (VL).

[0118] For the existing standard N1 (i.e., the number of virtual channels for transmitting the first data) VLs, it can be divided by P1, where P1 is the number of physical channels defined by the standard; N2 (the number of non-standard VLs that need to be extended, i.e., the number of virtual channels after expansion) can be divided by P2, where P2 is the number of physical channels corresponding to a single Ethernet port when the backplane cannot support the B1 rate and uses the B2 rate to transmit data (i.e., the number of physical channels corresponding to the data transmission interface when it uses the second rate to transmit data).

[0119] In one embodiment of this application, N2 is set to be equal to the least common multiple of N1 and P2. In this way, N2 can be divided by P2, and N2 can easily reuse the VL structure of N1.

[0120] For example, if N1 = 8 and P2 = 12, N2 = 24 can be made. Thus, 24 VLs can be implemented as 12 PLs through simple 2:1 bit multiplexing. Furthermore, since N2 = 3 * N1, the polling cycle can be changed from 8 to 24 during FEC data distribution. To ensure successful identification of these VLs at the receiver, existing AM patterns can be reused.

[0121] like Figure 8A As shown, there are 8 VLs, corresponding to AM0 to AM7; as Figure 8BAs shown, this is expanded to 24 VLs, with 8 VLs reused, repeated three times. Because it's a backplane connection, and the backplane is implemented internally by the manufacturer, it's possible to determine which PL corresponds to which interface. Furthermore, since the correspondence between PL and VL is known, the relationship between interfaces and VLs can be derived in the case of a backplane connection. Therefore, it's unnecessary to re-find the AM character and use AM to distinguish channels. Of course, different AM characters can also be selected; AM0 to 23 are all different. This is another method for expanding VLs.

[0122] In the case of expanding the virtual channel, sending the second data at the second rate includes: using the physical channel to send the second data at the second rate. As described above, the data transmission rate of the physical channel is determined based on bit multiplexing of the expanded virtual channel, and the number of expanded virtual channels is determined based on the number of virtual channels transmitting the first data and the number of physical channels corresponding to the data transmission interface when transmitting data at the second rate.

[0123] For example, when determining the number of expanded virtual channels based on the number of virtual channels for transmitting the first data and the number of physical channels corresponding to the data transmission interface transmitting data at the second rate, the number can be determined based on the least common multiple of the number of virtual channels for transmitting the first data and the number of physical channels corresponding to the data transmission interface transmitting data at the second rate.

[0124] The method provided in this application improves the transmission rate by adding additional data to the first data in a certain proportion. This breaks the limitations of the backplane on device expansion and upgrade during device expansion and upgrade, not only avoiding frequency holes, but also adapting to future performance requirements.

[0125] Furthermore, due to the increased speed, the insertion loss from backplane wiring and connectors increases relative to the backplane design specifications, and crosstalk between signals also increases, resulting in a significant decrease in SNR. Avoiding frequency holes requires increasing link speed, which also introduces some overhead. Therefore, the overhead brought about by the increased speed is used to compensate for the SNR loss by adding additional FEC (Frequency Equivalent Control).

[0126] This application provides an apparatus for improving transmission rate, see [link to relevant documentation]. Figure 9 The device includes:

[0127] Acquisition module 901 is used to acquire first data at a first rate;

[0128] Processing module 902 is used to add additional data to the first data in a certain proportion to obtain the second data;

[0129] The transmitting module 903 is used to transmit second data at a second rate, which is greater than the first rate.

[0130] In one exemplary embodiment, the second rate is not an integer multiple of the first rate.

[0131] In one exemplary embodiment, the sending module 903 is configured to send second data at a second rate using a physical channel. The data transmission rate of the physical channel is determined based on bit multiplexing of the expanded virtual channel. The number of expanded virtual channels is determined based on the number of virtual channels transmitting the first data and the number of physical channels corresponding to the data transmission interface transmitting data at the second rate.

[0132] In one exemplary embodiment, the additional data is located in the first part of the second data.

[0133] In one exemplary embodiment, a first portion of the additional data is located within a first portion of the second data, a second portion of the additional data is located within a second portion of the second data, and a portion of the first data is included between the first portion of the additional data and the second portion of the additional data.

[0134] In one exemplary embodiment, the first data includes an alignment marker AM character, and the processing module is configured to insert additional data into the first data at a certain proportion, using the AM character in the first data as a boundary.

[0135] In one exemplary embodiment, the processing module 902 is configured to: when the first data is MAC layer data, insert first additional data into the MAC layer data at a first ratio to obtain second data; or when the first data is data transmitted on a Virtual Channel (VL) after FEC sublayer distribution, insert second additional data into the data transmitted on the VL after FEC sublayer distribution at a second ratio to obtain second data; or when the first data is data after VL remapping but before entering the physical link, insert third additional data into the data after VL remapping but before entering the physical link at a third ratio to obtain second data; or when the first data is data transmitted on the physical link, insert fourth additional data into the data transmitted on the physical link at a fourth ratio to obtain second data; or when the first data is original data, insert fifth additional data into the original data at a fifth ratio to obtain second data.

[0136] In one exemplary embodiment, the processing module 902 is used to encode the first data using FEC codes based on the overhead of the second rate or the overhead of the first rate to obtain the second data.

[0137] In one exemplary embodiment, the processing module 902 is configured to: when the first data is data transmitted on a virtual channel (VL) after FEC sublayer distribution and encoded using a first FEC code pattern, perform secondary encoding on the data transmitted on the VL after FEC sublayer distribution and encoded using the first FEC code pattern using a second FEC code pattern that matches the rate ratio to obtain second data, wherein the rate ratio is the ratio of the second rate to the first rate; or, when the first data is data after VL remapping and before entering the physical link and encoded using the first FEC code pattern, perform secondary encoding on the data after VL remapping and before entering the physical link and encoded using the first FEC code pattern using a second FEC code pattern that matches the rate ratio to obtain second data; or, when the first data is data transmitted on a virtual channel (VL) after FEC sublayer distribution ... using the first FEC code pattern. When data transmitted on the physical link and encoded using the first FEC code pattern, the data transmitted on the physical link and encoded using the first FEC code pattern is further encoded using the second FEC code pattern that matches the rate ratio to obtain the second data; or, when the first data is data encoded using the first FEC code pattern, the data encoded using the first FEC code pattern is decoded to obtain the original data, and the original data is encoded using the third FEC code pattern that matches the second rate to obtain the second data, wherein the overhead of the third FEC code pattern is greater than the overhead of the first FEC code pattern; or, when the first data is the original data, the original data is encoded using the third FEC code pattern that matches the second rate to obtain the second data, wherein the overhead of the third FEC code pattern is greater than the overhead of the first FEC code pattern.

[0138] This application provides a processor that can be used to execute any of the methods described above for improving transmission rates.

[0139] This application provides a network device, such as... Figure 2 or Figure 3 As shown, the network device includes the aforementioned processor.

[0140] In one exemplary embodiment, the network device includes a line card, which includes the processor described above.

[0141] In one exemplary embodiment, the network device also includes a backplane.

[0142] In one exemplary embodiment, the network device further includes a CDR located between the line card and the backplane, the line card communicating with the backplane via the CDR.

[0143] This application provides a network system that includes one or more network devices, which are any of the network devices described above.

[0144] See Figure 10 This application also provides a device 1000 for improving transmission rates. Figure 10The device 1000 shown for improving transmission rate is used to perform the operations involved in the method for improving transmission rate described above. The device 1000 for improving transmission rate includes a memory 1001, a processor 1002, and an interface 1003, which are connected via a bus 1004.

[0145] The memory 1001 stores at least one instruction, which is loaded and executed by the processor 1002 to implement any of the methods described above for improving the transmission rate.

[0146] Interface 1003 is used to communicate with other devices in the network. Interface 1003 can be implemented wirelessly or via a wired connection. For example, interface 1003 can be a network interface card (NIC). For instance, device 1000, which improves transmission speed, can communicate with other network devices through interface 1003.

[0147] It should be understood that, Figure 10 This illustration only shows a simplified design of the device 1000 for improving transmission speed. In practical applications, the device 1000 for improving transmission speed can include any number of interfaces, processors, or memory. Furthermore, the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. It is worth noting that the processor can be a processor supporting the Advanced Reduced Instruction Set Computing (RISC) machine (ARM) architecture.

[0148] Furthermore, in an alternative embodiment, the memory described above may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store device type information.

[0149] The memory can be volatile or non-volatile, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. Many forms of RAM are available by way of example, but not limitation. Examples include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0150] A computer-readable storage medium is also provided, which stores at least one instruction that is loaded and executed by a processor to implement the method for improving the transmission rate as described above.

[0151] This application provides a computer program that, when executed by a computer, causes a processor or computer to perform the various operations and / or processes corresponding to those described in the method embodiments.

[0152] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive).

[0153] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the methods in the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM), random access memory (RAM), magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a media gateway) to execute the methods described in various embodiments or some parts of the embodiments of the present invention.

[0154] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The device and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0155] The above description is merely an optional implementation of this application and is not intended to limit the scope of protection of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

[0156] Explanation of terms involved in this application

[0157] FEC: Forward Error Correction

[0158] RS-FEC: Reed-Solomon FEC, Reed-Solomon forward error correction code

[0159] BCH code: Bose–Chaudhuri–Hocquenghem, BCH forward error correction code

[0160] PCS: Physical Coding Sublayer

[0161] PMA: Physical Medium Attachment Sublayer

[0162] PMD: Physical Media Dependent Layer

[0163] PHY: Physical layer

[0164] AM: Alignment Marker

[0165] VL: Virtual Lane, equivalent to PCS Lane

[0166] PL: Physical Lane

[0167] SerDes: Serializer / Deserializer, a serializer / deserializer.

[0168] PLL: Phase-Locked Loop

[0169] CDR: Clock & Data Recovery

[0170] Gbps: Gigabit per second

[0171] GBd:GBaud,Giga-baud,Giga-baud

[0172] PAM: Pulse Amplitude Modulation

[0173] PAM4: 4-level PAM, also written as PAM-4; OSI model: Open Systems Interconnection model; PCB: Printed Circuit Board.

[0174] A Physical Link can have multiple Physical Lanes.

Claims

1. A method for improving transmission rate, characterized in that, include: First data is obtained at a first rate, and the first data is data obtained after encoding using a first forward error correction (FEC) code pattern. The first data is encoded according to the second FEC code pattern, and additional data is added at a certain ratio to obtain the second data, wherein the additional data is FEC encoded data; The second data is transmitted at a second rate, which is greater than the first rate.

2. The method according to claim 1, characterized in that, The process of encoding the first data according to the second FEC code pattern and adding additional data at a certain ratio to obtain the second data includes: The first data is encoded according to the second FEC code pattern to obtain encoded data; The additional data is added to the encoded data in a certain proportion to obtain the second data.

3. The method according to claim 1, characterized in that, The encoding of the first data according to the second FEC code pattern includes: The first data is distributed to multiple virtual channels, and the data on the distributed virtual channels is encoded according to the second FEC code pattern.

4. The method according to claim 3, characterized in that, The addition of extra data at a certain proportion includes: Additional data is added to the data encoded by the second FEC code pattern on each of the multiple virtual channels at a certain ratio.

5. The method according to claim 3 or 4, characterized in that, The step of distributing the first data to multiple virtual channels includes: distributing the first data to multiple virtual channels in a round-robin manner.

6. The method according to any one of claims 1-4, characterized in that, The additional data can be identified by the receiving end so that the receiving end can delete the additional data.

7. The method according to any one of claims 1-4, characterized in that, The second rate is not an integer multiple of the first rate.

8. The method according to any one of claims 1-4, characterized in that, The first portion of the additional data is located within the first portion of the second data, and the second portion of the additional data is located within the second portion of the second data, with a portion of the first data included between the first portion and the second portion of the additional data.

9. An apparatus for improving transmission rate, characterized in that, The device includes: An acquisition module is used to acquire first data at a first rate, wherein the first data is data obtained after encoding using a first forward error correction (FEC) code pattern; The processing module is used to encode the first data according to the second FEC code pattern and add additional data at a certain ratio to obtain the second data, wherein the additional data is FEC encoded data; A sending module is configured to send the second data at a second rate, the second rate being greater than the first rate.

10. The apparatus according to claim 9, characterized in that, The processing module is used to encode the first data according to the second FEC code pattern, and add the additional data at a certain ratio to obtain the second data, specifically including: The processing module is used to encode the first data according to the second FEC code pattern to obtain encoded data; The processing module is also used to add the additional data to the encoded data in a certain proportion to obtain the second data.

11. The apparatus according to claim 9, characterized in that, The processing module is used to encode the first data according to the second FEC code pattern, specifically including: The processing module is used to distribute the first data to multiple virtual channels and encode the data on the distributed virtual channels according to the second FEC code pattern.

12. The apparatus according to claim 11, characterized in that, The processing module is used to add the additional data at a certain ratio, specifically including: The processing module is used to add additional data to the data encoded by the second FEC code pattern on each of the multiple virtual channels at a certain ratio.

13. The apparatus according to claim 11 or 12, characterized in that, The processing module is used to distribute the first data to multiple virtual channels, specifically including: The processing module is used to distribute the first data to multiple virtual channels in a polling manner.

14. The apparatus according to any one of claims 9-12, characterized in that, The additional data can be identified by the receiving end so that the receiving end can delete the additional data.

15. The apparatus according to any one of claims 9-12, characterized in that, The second rate is not an integer multiple of the first rate.

16. The apparatus according to any one of claims 9-12, characterized in that, The first portion of the additional data is located within the first portion of the second data, and the second portion of the additional data is located within the second portion of the second data, with a portion of the first data included between the first portion and the second portion of the additional data.

17. A chip for improving transmission rate, characterized in that, The chip includes at least one circuit for performing the method described in any one of claims 1-8.

18. The chip according to claim 17, characterized in that, The chip includes a clock and a data recovery circuit (CDR).

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