Collection chamber module and flow cytometry data acquisition system

Abstract

The present invention relates to the technical field of data acquisition, and specifically discloses an acquisition chamber module and a flow cell data acquisition system, wherein the acquisition chamber module comprises a plurality of sub-boards, each of which comprises a first FPGA and a plurality of analog-to-digital converters; a motherboard connected to the plurality of sub-boards, the motherboard comprising a second FPGA, a third FPGA, a data processing module and a memory module; the data processing module is connected to the second FPGA and the memory module, and is used for transferring spectral data in a valid signal cached by the second FPGA to the memory module; the third FPGA is connected to the second FPGA and the image data acquisition module, and is used for generating a delayed trigger signal according to the valid signal to trigger the image data acquisition module to run; the acquisition chamber module can timely parse out the valid signal to synchronously extract the spectral data and generate the delayed trigger signal, and timely drive the image data acquisition module to run to acquire image data matching the spectral data.

Description

Technical Field

[0001] The present application relates to the technical field of data acquisition, and in particular to an acquisition chamber module and a flow cytometry data acquisition system. Background Art

[0002] As a cutting-edge technology for cell analysis, flow cytometry has achieved efficient and accurate determination of multiple characteristics of suspended cells through means such as laser-induced fluorescence, greatly promoting the in-depth study of cell biology. However, traditional methods are limited by the selectivity of fluorescent dyes and the lack of spatial structural information, which has led to the emergence of emerging technologies such as spectral flow cytometry and image flow cytometry. Spectral flow cytometry improves data resolution and information volume by capturing the complete spectrum of single cells, while image flow cytometry combines microscopy technology to intuitively display cell structure. Both are designed to make up for the shortcomings of traditional flow cytometry.

[0003] The related technology provides a flow cytometer data acquisition system for synchronously acquiring spectral data and image data. However, the system is difficult to achieve accurate synchronous alignment of the two types of data under high-speed and high-throughput conditions. The system lacks independent acquisition of the two types of data and a timely and effective trigger mechanism, making it impossible to ensure accurate association between the two types of data corresponding to each flow cell.

[0004] There is currently no effective technical solution to the above problems. Summary of the invention

[0005] The purpose of the present application is to provide a collection chamber module and a flow cell data collection system to collect spectral data in a timely manner and trigger an image data collection module to collect image data accordingly, so that the upper function can perform high-precision sorting of flow cells.

[0006] In a first aspect, the present application provides a collection chamber module, which is applied to a flow cytometry data collection system, wherein the flow cytometry data collection system includes a spectral data collection module, an image data collection module and a host computer, and the collection chamber module includes:

[0007] A plurality of daughter boards, each of which comprises a first FPGA and a plurality of analog-to-digital converters;

[0008] A motherboard connected to the plurality of daughterboards, the motherboard comprising a second FPGA, a third FPGA, a data processing module and a memory module;

[0009] The multiple analog-to-digital converters are connected to the first FPGA and the spectral data acquisition module, and are used to convert the analog signals provided by the spectral data acquisition module into digital signals;

[0010] The first FPGA is connected to the second FPGA, and is used to obtain a valid signal according to the digital signal, and transmit the valid signal to the second FPGA for caching;

[0011] The data processing module is connected to the second FPGA and the memory module, and is used to transfer the spectral data in the valid signal cached by the second FPGA to the memory module;

[0012] The data processing module is also connected to the host computer, and is used to sort and upload a preset amount of spectral data in the memory module to the host computer;

[0013] The third FPGA is connected to the second FPGA and the image data acquisition module, and is used to generate a delayed trigger signal according to the effective signal to trigger the image data acquisition module to run.

[0014] The collection chamber module of the present application is used in a flow cytometer data acquisition system, and can adapt to the high-speed, high-throughput characteristics of flow cells to receive the analog signal generated by the spectral data acquisition module, and promptly parse out the effective signal from the analog signal to synchronously extract the spectral data and generate a delayed trigger signal to trigger the operation of the image data acquisition module, and use the delayed trigger signal to promptly drive the image data acquisition module to operate to collect image data that matches the spectral data, so as to facilitate the host computer to perform high-precision sorting of flow cells.

[0015] The acquisition warehouse module, wherein the data processing module is an ARM processor, and the ARM processor transfers the spectral data in the valid signal cached by the second FPGA to the memory module based on the DMA channel configured by the AXI bus.

[0016] In this example, the ARM processor configures a DMA channel to connect the memory module and the second FPGA, so that the spectral data in the valid signal cached in the second FPGA can be directly copied to the memory module based on the DMA transmission technology, thereby realizing high-speed extraction and transmission of spectral data.

[0017] In the acquisition chamber module, the process of the data processing module collating the spectral data in the memory module includes the following steps: compensation, gating and sorting.

[0018] In this example, the above-mentioned sorting method can effectively improve the integrity and effectiveness of the spectral data acquired by the host computer.

[0019] The acquisition bin module, wherein the first FPGA performs threshold reduction processing and amplification processing on the digital signal to obtain the valid signal.

[0020] The acquisition bin module, wherein the process of the second FPGA caching the valid signal comprises:

[0021] Acquire the valid signal based on the first FPGA transmission;

[0022] Performing parallel-to-serial conversion on the valid signal to obtain a serial valid signal;

[0023] The serial valid signal is trimmed and aligned to obtain a valid signal that complies with the 64-bit format of the AXI bus, and is cached based on the FIFO.

[0024] The acquisition chamber module, wherein the effective signal includes a forward effective signal and a lateral effective signal, the lateral effective signal includes the spectral data, and the third FPGA generates the delayed trigger signal based on the forward effective signal.

[0025] In a second aspect, the present application further provides a flow cytometry data acquisition system, comprising: a spectral data acquisition module, an image data acquisition module, a host computer, and an acquisition chamber module as provided in the first aspect;

[0026] The host computer is also connected to the spectral data acquisition module and the image data acquisition module, and is used to drive the spectral data acquisition module to collect data to generate the analog signal, and is also used to obtain the image data collected by the image data acquisition module, and synchronize and store the image data with the spectral data sorted and uploaded by the data processing module.

[0027] The flow cytometry data acquisition system of the present application is configured with an acquisition bin module, which can adapt to the high-speed, high-throughput characteristics of flow cells to receive the analog signal generated by the spectral data acquisition module, and promptly parse out the effective signal from the analog signal to synchronously extract the spectral data and generate a delayed trigger signal to trigger the operation of the image data acquisition module, and use the delayed trigger signal to promptly drive the image data acquisition module to operate to acquire image data that matches the spectral data, so as to facilitate the host computer to perform high-precision sorting of flow cells.

[0028] The flow cytometry data acquisition system, wherein the image data acquisition module includes a high-speed camera and an AOM driver, and the trigger dead time of the high-speed camera satisfies:

[0029] T 死区 ≥1 / f, where T 死区 is the trigger dead time, and f is the frame rate of the high-speed camera;

[0030] The exposure time of the AOM driver satisfies:

[0031] T 曝光≤L / (F*V), where T 曝光 is the exposure time of the AOM driver, L is the pixel size, F is the optical magnification of the image data acquisition module, and V is the flow rate of the flow cell.

[0032] In the flow cytometry data acquisition system, the acquisition chamber module further includes a motherboard adapter board, and the motherboard is connected to the host computer and the image data acquisition module via the motherboard adapter board.

[0033] In the flow cytometry data acquisition system, the motherboard adapter board has an SMA interface, and the SMA interface is connected to the image data acquisition module via a coaxial cable with a characteristic impedance of 50Ω.

[0034] From the above, it can be seen that the present application provides a collection chamber module and a flow cytometry data acquisition system, wherein the collection chamber module can adapt to the high-speed, high-throughput characteristics of flow cells to receive the analog signal generated by the spectral data acquisition module, and promptly parse out the effective signal from the analog signal to synchronously extract the spectral data and generate a delayed trigger signal to trigger the operation of the image data acquisition module, and use the delayed trigger signal to promptly drive the image data acquisition module to operate to collect image data that matches the spectral data, so as to facilitate the host computer to perform high-precision sorting of flow cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of the collection chamber module provided in an embodiment of the present application.

[0036] Figure 2 A schematic diagram of the structure of a flow cytometry data acquisition system provided in an embodiment of the present application.

[0037] Figure numerals: 100, acquisition chamber module; 200, spectral data acquisition module; 300, image data acquisition module; 400, host computer; 110, daughter board; 120, motherboard; 130, motherboard adapter board; 111, analog-to-digital converter; 112, first FPGA; 121, second FPGA; 122, third FPGA; 123, data processing module; 124, memory module; 301, high-speed camera; 302, AOM driver. DETAILED DESCRIPTION

[0038] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0040] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0042] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0043] First, please refer to Figure 1 and Figure 2 Some embodiments of the present application provide a collection chamber module, which is applied to a flow cytometry data collection system. The flow cytometry data collection system includes a spectral data collection module 200, an image data collection module 300 and a host computer 400. The collection chamber module includes:

[0044] A plurality of daughter boards 110, each of which includes a first FPGA 112 and a plurality of analog-to-digital converters 111;

[0045] A motherboard 120 connected to the plurality of daughterboards 110, the motherboard 120 includes a second FPGA 121, a third FPGA 122, a data processing module 123 and a memory module 124;

[0046] A plurality of analog-to-digital converters 111 are connected to the first FPGA 112 and the spectral data acquisition module 200 and are used to convert the analog signal provided by the spectral data acquisition module 200 into a digital signal;

[0047] The first FPGA 112 is connected to the second FPGA 121, and is used to obtain a valid signal according to the digital signal, and transmit the valid signal to the second FPGA 121 for caching;

[0048] The data processing module 123 is connected to the second FPGA 121 and the memory module 124, and is used to transfer the spectrum data in the valid signal cached by the second FPGA 121 to the memory module 124;

[0049] The data processing module 123 is also connected to the host computer 400, and is used to organize and upload the preset amount of spectral data in the memory module 124 to the host computer 400;

[0050] The third FPGA 122 is connected to the second FPGA 121 and the image data acquisition module 300 , and is used to generate a delayed trigger signal according to the effective signal to trigger the image data acquisition module 300 to run.

[0051] Specifically, the flow cytometry data acquisition system is used to collect image data and spectral data of high-speed, high-throughput flow cells to perform accurate quantitative analysis and differentiation of flow cells, and is particularly suitable for sorting flow cells; wherein, the flow cytometry data acquisition system generally uses a fluid pool to transport flow cells at high speed, and the spectral data acquisition module 200 and the image data acquisition module 300 are respectively used to collect spectral information and image information of flow cells flowing through corresponding monitoring positions in the fluid pool, and these information are ultimately converted into digital spectral data and image data and stored in the host computer 400, so as to use the corresponding sorting program in the host computer 400 to sort the flow cells.

[0052] More specifically, the spectral data acquisition module 200 and the image data acquisition module 300 both include a laser excitation component and a data acquisition component, wherein the laser excitation component is used to generate a laser to irradiate the fluid pool so that the data acquisition component can collect corresponding data information; wherein, the irradiation positions of the laser excitation components of the spectral data acquisition module 200 and the image data acquisition module 300 are at a certain distance, so that the flow cell passes through the two irradiation positions successively during the flow process, so that the two data acquisition components can collect spectral information and image information associated with the same flow cell; considering that the data volume of image data is greater than the data volume of spectral data, the acquisition bin module of the embodiment of the present application is mainly used to collect spectral data based on spectral information, and generate a delayed trigger signal to drive the image data acquisition module 300 to run so that the image data acquisition module 300 can collect image information matching the spectral information and convert it into image data and upload it to the host computer 400, that is, the flow cell data acquisition system applied by the acquisition bin module of the embodiment of the present application is a data synchronization system based on spectral data triggering to obtain image data, so the irradiation position of the laser excitation component of the spectral data acquisition module 200 is set to be prior to the irradiation position of the laser excitation component of the image data acquisition module 300.

[0053] More specifically, the collection bin module of the embodiment of the present application mainly has two functions: obtaining valid spectral data based on spectral information, and timely generating a delayed trigger signal for triggering the operation of the image data collection module 300 based on the valid spectral data, so that the host computer 400 can finally obtain spectral data and image data about the flow cell that can be synchronously aligned and perform data analysis; wherein, since the flow cell has a high-throughput characteristic, in order to ensure that the delayed trigger signal is timely, the collection bin module of the embodiment of the present application is provided with a plurality of sub-boards 110, and a plurality of analog-to-digital converters 111 are provided in each sub-board 110 to collect spectral information from the spectral data collection module 200, and the spectral information transmitted to the collection bin module is expressed as an analog signal, and the plurality of analog-to-digital converters 111 in the plurality of sub-boards 110 are used to generate a plurality of analog-to-digital converters 111. The converter 111 can collect these analog signals in parallel and convert them into digital signals that can be used for data analysis, thereby achieving efficient data processing to ensure that the acquisition bin module of the embodiment of the present application can timely generate a delayed trigger signal to acquire image data that matches the corresponding spectral data; wherein, according to usage requirements, multiple sub-boards 110 can be designed to receive analog signals simultaneously, or can be designed to receive analog signals in sequence based on a timing sequence. In the embodiment of the present application, the latter is preferred, that is, based on different sub-boards 110 successively receiving analog signals corresponding to spectral information at different time nodes to independently analyze data signals of different timing sequences and extract valid signals, and then send them to the second FPGA 121 in the motherboard 120 for caching based on the timing sequence. This implementation method can effectively improve the analysis and extraction capabilities of valid signals.

[0054] It should be noted that both the motherboard 120 and the daughterboard 110 are integrated circuit boards and are connected via a data interface, wherein the main function of the daughterboard 110 is to collect and screen analog signals corresponding to spectral information to obtain effective signals (corresponding to the spectral information collected at the irradiation position of the laser excitation component of the flow cell flow through the spectral data acquisition module 200), and the main function of the motherboard 120 is to transfer the spectral data in the effective signal and generate a delayed trigger signal.

[0055] More specifically, the process by which the first FPGA 112 obtains a valid signal based on a digital signal is actually a process of screening out digital signals that do not contain spectral data of flow cells based on preset rules; a second FPGA 121 is provided in the motherboard 120 for caching valid signals, and based on the third FPGA 122 and the data processing module 123, a delayed trigger signal is generated for the valid signal in the second FPGA 121, and spectral data is extracted and transferred. The two processing processes are performed by two control devices, which can ensure the timeliness and accuracy of data processing and avoid mutual interference of data.

[0056] More specifically, the memory module 124 is used to temporarily store the spectral data in the valid signal, and combined with the data processing module 123, it can organize and integrate the spectral data temporarily stored therein, so as to upload the organized spectral data that meets its sorting requirements to the host computer 400; it should be noted that each set of organized spectral data uploaded to the host computer 400 corresponds to a flow cell at a moment, and matches the image data at a moment collected by an image data acquisition module 300.

[0057] It should be noted that the spectral data stored in the memory module 124 includes the corresponding spectral ID, the image data uploaded by the image data acquisition module 300 includes the corresponding image ID, and the host computer 400 matches the image data with the spectral data through the spectral ID and the image ID.

[0058] In some embodiments, the data processing module 123 is connected to the third FPGA 122, and is used to output a spectral ID to the third FPGA 122, so that the third FPGA 122 generates a delayed trigger signal according to the valid signal and the spectral ID, so that the image data acquisition module 300 can generate an image ID according to the delayed trigger signal during the process of acquiring image data, so that the image data and the spectral data are matchable, so as to further simplify the data pairing logic.

[0059] More specifically, the delayed trigger signal can be a trigger signal sent to the image data acquisition module 300 based on a preset delay to trigger the image data acquisition module 300 to run, or it can be a trigger signal directly sent to the image data acquisition module 300 to delay triggering the image data acquisition module 300 to run. Based on the foregoing content, it can be seen that the irradiation positions of the spectral data acquisition module 200 and the image data acquisition module 300 have a certain position difference. In order to ensure that the acquisition objects (flow cells) of the two are the same, it is necessary to design a certain delay to trigger the image data acquisition module 300 to run. The delay value can be set based on the processing efficiency of the acquisition bin module of the embodiment of the present application (the time consumed in the entire process of generating a delayed trigger signal based on an analog signal), the flow rate of the fluid in the fluid pool, and the distance difference between the irradiation positions to ensure that the image data acquired by the host computer 400 matches the spectral data.

[0060] More specifically, the operation process of the motherboard 120 is all based on valid signals, which is equivalent to using the daughterboard 110 to screen the spectral data, so as to collect spectral data based on the valid signal and trigger the image data acquisition module 300 to run, which can ensure data matching and effectively save system resources, and avoid the image data acquisition module 300 from collecting invalid data. In this case, the host computer 400 also only obtains valid and mutually matching spectral data and image data, which can further save data processing resources and storage resources, and facilitate high-precision sorting of flow cells.

[0061] The collection chamber module of the embodiment of the present application is used in a flow cytometer data collection system, and can adapt to the high-speed and high-throughput characteristics of flow cells to receive the analog signal generated by the spectral data collection module 200, and promptly parse out the effective signal from the analog signal to synchronously extract the spectral data and generate a delayed trigger signal to trigger the operation of the image data collection module 300, and use the delayed trigger signal to promptly drive the image data collection module 300 to operate to collect image data that matches the spectral data, so as to facilitate the host computer 400 to perform high-precision sorting of flow cells.

[0062] In some preferred embodiments, the number of daughter boards 110 is preferably five, and the number of analog-to-digital converters 111 in each daughter board 110 is preferably seven.

[0063] In some preferred embodiments, the data processing module 123 is an ARM processor, and the ARM processor transfers the spectral data in the valid signal cached by the second FPGA 121 to the memory module 124 based on the DMA channel configured by the AXI bus.

[0064] Specifically, the ARM processor configures a DMA (Direct Memory Access) channel to connect the memory module 124 and the second FPGA 121, so that the spectral data in the valid signal cached in the second FPGA 121 can be directly copied to the memory module 124 based on the DMA transmission technology, thereby realizing high-speed extraction and transmission of the spectral data.

[0065] More specifically, in this implementation, the DMA configured based on the AXI bus of the ARM processor can effectively improve data transmission performance and reduce data processing load. The AXI (Advanced Extensible Interface) bus can provide high-performance data transmission, support high bandwidth and low latency, and allow complex data burst transmission and out-of-order execution, further improving the efficiency and flexibility of data transmission, and supporting separate address / control and data phases, as well as separate read and write data channels, so that the DMA can independently control the data transmission process without sharing resources with other system components.

[0066] In some preferred embodiments, the process of the data processing module 123 organizing the spectral data in the memory module 124 includes the following steps: compensation, gating, and sorting.

[0067] Specifically, the compensation processing is a crosstalk recovery processing performed on the spectral data, that is, restoring or reducing the signal quality degradation caused by crosstalk during the transmission of the spectral data through specific recovery means; the gate processing is to add preset gate data to the spectral data after the compensation processing; the sorting processing is to sort the spectral data with the gate data added based on the gate data, so as to divide the spectral data into gated data and gated data. After the sorting processing is completed, the processed spectral data is integrated (or directly uploaded without integration) and uploaded to the host computer 400 according to the system usage requirements, wherein the uploading process is that the data processing module 123 sends the data to the software of the host computer 400 based on the TCP protocol of the network port lwIP protocol stack.

[0068] More specifically, the above-mentioned sorting method can effectively improve the integrity and effectiveness of the spectral data acquired by the host computer 400.

[0069] More specifically, in the embodiment of the present application, the data processing module 123 preferably organizes multiple groups of spectral data stored in the memory module 124 at one time to improve data organization efficiency; wherein, after the second FPGA 121 monitors through the data processing module 123 that the unorganized spectral data in the memory module 124 reaches a preset number, it generates an interrupt signal to suspend the caching of the spectral data and the generation of the corresponding delay trigger signal in the third FPGA 122, so that within the interrupt time, the data processing module 123 can be used to organize the preset number of spectral data in the memory module 124, and upload them to the host computer 400, so as to realize batch organization and upload operations of the spectral data, and the interrupt behavior can ensure that the spectral data is uploaded smoothly.

[0070] It should be noted that the spectral data temporarily stored in the memory module 124 has generated a corresponding delayed trigger signal through the third FPGA 122 to trigger the image data acquisition module 300 to acquire image data during the storage process, so the above interruption behavior will not affect the acquisition of the corresponding image data.

[0071] In some preferred embodiments, the third FPGA 122 enables the first FPGA 112 .

[0072] Specifically, the first FPGA112 can only operate when the third FPGA122 operates and generates an enable signal, that is, the first FPGA112 can receive digital signals in real time and obtain valid signals based on the digital signals when the third FPGA122 is in an operating state; in this embodiment, the first FPGA112 is enabled to operate only when the third FPGA122 is in a state where it can normally generate a delay trigger signal, which can avoid the first FPGA112 from working invalidly and ensure that the valid signal extracted by the first FPGA112 can smoothly generate a corresponding delay trigger signal and upload the corresponding spectral data.

[0073] More specifically, in the aforementioned interruption behavior, the third FPGA 122 is also interrupted at the same time, which can suspend the operation of the first FPGA 112 .

[0074] In some preferred implementations, the first FPGA 112 performs threshold pruning and amplification processing on the digital signal to obtain a valid signal.

[0075] Specifically, threshold deletion processing is the act of screening digital signals based on a preset signal threshold. Accordingly, the intensity of digital signals that do not contain flow cytometry-related data is relatively small, so rapid screening of digital signals can be achieved directly based on threshold deletion processing. The screened digital signals can be amplified to obtain effective signals that meet the intensity requirements of system analysis.

[0076] In some preferred implementations, the process of the second FPGA 121 caching a valid signal includes:

[0077] Acquire a valid signal based on the first FPGA 112 transmission;

[0078] Performing parallel-to-serial conversion on the effective signal to obtain a serial effective signal;

[0079] The valid serial signal is trimmed and aligned to obtain a valid signal that conforms to the 64-bit format of the AXI bus, and is cached based on the FIFO.

[0080] Specifically, in this embodiment, based on the foregoing content, it can be known that the first FPGA 112 in the same daughter board 110 obtains digital signals based on multiple analog-to-digital converters 111, so the effective signals obtained are presented as parallel signals. In order to process and obtain effective signals that comply with the 64-bit format of the AXI bus for subsequent DMA transmission based on the AXI bus configuration, the second FPGA 121 needs to perform serial-to-parallel conversion on the effective signals to obtain serial effective signals, and then perform trimming and alignment processing to obtain effective signals that comply with the 64-bit format of the AXI bus. Caching based on the FIFO (first-in-first-out) method can ensure the timing of effective signal transmission, ensure that the subsequent uploaded spectral data matches the delay trigger signal so that the host computer 400 can successfully obtain corresponding spectral data and image data.

[0081] In some preferred embodiments, the effective signal includes a forward effective signal and a lateral effective signal, the lateral effective signal includes spectrum data, and the third FPGA 122 generates a delayed trigger signal based on the forward effective signal.

[0082] Specifically, the spectral data acquisition module 200 includes a lateral spectral data acquisition component and a forward spectral data acquisition component, wherein the lateral spectral data acquisition component is used to collect lateral spectral information generated by lateral emission, including spectral data that can directly correspond to the diffraction characteristics of the fluid, and the corresponding lateral spectral information containing flow cell-related data is used for flow cell sorting processing, and the forward spectral data acquisition component is used to collect forward spectral information generated by the laser passing through the fluid pool and continuing to emit forward, and can conveniently analyze whether the corresponding forward spectral information contains flow cells based on the shielding characteristics of the flow cells; in this embodiment, the analog signal collected by the sub-board 110 includes forward spectral information and lateral spectral information, so that the corresponding digital signal includes a forward digital signal and a lateral digital signal, and the corresponding valid signal includes a forward valid signal and a lateral valid signal; wherein, the process of the first FPGA 112 obtaining a valid signal based on the digital signal is mainly to screen the forward digital signal to extract the forward digital signal and the corresponding lateral digital signal required by the system.

[0083] More specifically, since the lateral spectral information contains spectral data that can directly correspond to the diffraction characteristics of the fluid, the lateral effective signal includes spectral data corresponding to the flow cell. Therefore, the spectral data transferred from the second FPGA 121 to the memory module 124 is the spectral data in the lateral spectral information, and the third FPGA 122 generates a delayed trigger signal based on the forward effective signal, so that the data processed by the third FPGA 122 and the data transferred from the second FPGA 121 are independent and matched, which can ensure that the acquisition bin module of the embodiment of the present application can simultaneously and efficiently complete the tasks of data uploading and delay trigger signal generation.

[0084] Second, please refer to Figure 2 , some embodiments of the present application further provide a flow cytometry data acquisition system, comprising: a spectral data acquisition module 200, an image data acquisition module 300, a host computer 400 and an acquisition chamber module 100 as provided in the first aspect;

[0085] The host computer 400 is also connected to the spectral data acquisition module 200 and the image data acquisition module 300, and is used to drive the spectral data acquisition module 200 to collect to generate analog signals, and is also used to obtain image data collected by the image data acquisition module 300, and synchronize and store the image data with the spectral data uploaded by the data processing module 123.

[0086] Specifically, the host computer 400 is configured with sorting software, which is used to collect the spectral data uploaded by the collection chamber module 100 and the image data uploaded by the image data collection module 300 that match each other to sort the flow cells.

[0087] More specifically, in this embodiment, the host computer 400 is connected to the spectral data acquisition module 200, and can drive the spectral data acquisition module 200 to collect spectral information in real time when the fluid flows in the fluid pool, so that the acquisition chamber module 100 can automatically analyze whether there is spectral data that meets the system requirements based on the spectral information, and trigger the image data acquisition module 300 to run to obtain image data matching the spectral data.

[0088] The flow cytometer data acquisition system of the embodiment of the present application is configured with an acquisition chamber module 100. The acquisition chamber module 100 can adapt to the high-speed and high-throughput characteristics of flow cells to receive the analog signal generated by the spectral data acquisition module 200, and promptly parse out the effective signal from the analog signal to synchronously extract the spectral data and generate a delayed trigger signal to trigger the operation of the image data acquisition module 300, and use the delayed trigger signal to promptly drive the image data acquisition module 300 to operate to acquire image data matching the spectral data, so as to facilitate the host computer 400 to perform high-precision sorting of flow cells.

[0089] In some preferred embodiments, the image data acquisition module 300 includes a high-speed camera 301 and an AOM driver 302, and the trigger dead time of the high-speed camera 301 satisfies:

[0090] T 死区 ≥1 / f, where T 死区 is the trigger dead time, f is the frame rate of the high-speed camera 301;

[0091] The exposure time of the AOM driver 302 satisfies:

[0092] T 曝光 ≤L / (F*V), where T 曝光 is the exposure time of the AOM driver 302, L is the pixel size, F is the optical magnification of the image data acquisition module 300, and V is the flow rate of the flow cell.

[0093] Specifically, the high-speed camera 301 is a data acquisition component of the image data acquisition module 300. In the embodiment of the present application, it is preferably a Phantom S710 visual camera, whose waveform standard is TTL and whose frame rate can reach 27375fps. The corresponding minimum trigger dead zone time minT 死区 =36.5us, considering that the minimum time unit configured for the acquisition bin module 100 is 20ns, this parameter is configured by the software through the protocol frame for the acquisition bin module 100, and the protocol frame should not be too long, so the exposure time of the high-speed camera 301 can be rounded up to 40us according to the minimum trigger dead time.

[0094] More specifically, the laser excitation component includes a laser, an optical component and a corresponding drive control component, wherein the AOM driver 302 is a drive control component of the laser. In the embodiment of the present application, the AOM driver 302 and the AOM acoustic modulator are integrated into one device. In the embodiment of the present application, AODR 1080AF-DINA-1.0 HCR and AOMO 3080-120 are respectively used to comprehensively control the emission pulse of the laser. The AOM driver 302 converts the specified common waveform into the control signal required by the AOM; wherein the AOM driver 302 and the high-speed camera 301 are both connected to the third FPGA 122 of the acquisition chamber module 100, and are triggered to operate based on the delayed trigger signal sent by the third FPGA 122 to generate laser and collect corresponding image data; under the triggering of the delayed trigger signal, the AOM driver 302 cooperates with the AOM acoustic modulator to convert the laser signal into a controllable pulse laser signal to achieve low exposure under high flow rate, so as to ensure that the high-speed camera 301 can collect image data that meets the system requirements, wherein the low exposure process satisfies the above-mentioned T 曝光 The setting conditions are as follows, such as the pixel size is 20um, the optical magnification is 20, and the flow rate is 3m / s, and the maximum exposure time max T of the AOM driver 302 can be obtained. 曝光 =333ns. Considering that the minimum time unit configured for the acquisition bin module 100 is 20ns, the exposure time of the AOM driver 302 can be rounded down to 300ns according to the exposure time of the maximum AOM driver 302.

[0095] More specifically, setting relevant parameters of the high-speed camera 301 and the AOM driver 302 based on the above conditions can ensure that the image data acquisition module 300 can successfully acquire image data matching the spectral data when triggered by the acquisition chamber module 100 .

[0096] More specifically, in some embodiments, the delayed trigger signal includes an external trigger signal and an AOM trigger signal, wherein the external trigger signal and the AOM trigger signal are used to trigger the high-speed camera 301 and the AOM driver 302, respectively. For the same delayed trigger signal, the trigger timing of the high-speed camera 301 precedes the trigger timing of the AOM driver 302, so that the exposure time of the high-speed camera 301 includes the exposure time of the AOM driver 302 to ensure that image data that meets system requirements can be successfully collected. In this embodiment, the duration of the corresponding exposure time is determined by the pulse width of the corresponding trigger signal. For example, the pulse width of the external trigger signal is 1us, the pulse width of the AOM trigger signal is 0.33us, and the phase of the external trigger signal leads the AOM trigger signal by 0.33us, then 0.33us of image data collection is achieved during the continuous exposure of the high-speed camera 301.

[0097] In some preferred embodiments, the acquisition chamber module 100 further includes a motherboard adapter board 130 , and the motherboard 120 is connected to the host computer 400 and the image data acquisition module 300 via the motherboard adapter board 130 .

[0098] Specifically, the motherboard adapter board is used to complete the communication between the motherboard 120 and other modules, such as realizing SPI and CAN bus communications. In the embodiment of the present application, it is mainly used to connect the host computer 400 and the image data acquisition module 300 to ensure that the sorted spectral data can be successfully uploaded to the host computer 400 and to ensure that the delayed trigger signal can be sent to the image data acquisition module 300 in time for image data acquisition.

[0099] In some preferred implementations, the motherboard adapter board 130 has an SMA interface, and the SMA interface is connected to the image data acquisition module 300 via a coaxial cable with a characteristic impedance of 50Ω.

[0100] Specifically, the coaxial cable is preferably an RG-316 cable.

[0101] More specifically, in this embodiment, the motherboard adapter board 130 is preferably based on an RG-316 cable to connect the aforementioned AOM driver 302 and the high-speed camera 301, which can effectively ensure the timeliness of the transmission of the delayed trigger signal to achieve accurate collection of image data.

[0102] In summary, the embodiments of the present application provide a collection chamber module and a flow cytometry data acquisition system, wherein the collection chamber module can adapt to the high-speed, high-throughput characteristics of flow cells to receive the analog signal generated by the spectral data acquisition module 200, and promptly parse out the effective signal from the analog signal to synchronously extract the spectral data and generate a delayed trigger signal to trigger the image data acquisition module 300 to run, and use the delayed trigger signal to promptly drive the image data acquisition module 300 to run to collect image data that matches the spectral data, so as to facilitate the host computer 400 to perform high-precision sorting of flow cells.

[0103] In the description of this specification, the description with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0104] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A collection chamber module, used in a flow cytometry data collection system, characterized in that: The flow cell data acquisition system includes a spectral data acquisition module, an image data acquisition module and a host computer, and the acquisition chamber module includes: A plurality of daughter boards, each of which comprises a first FPGA and a plurality of analog-to-digital converters; A motherboard connected to the plurality of daughterboards, the motherboard comprising a second FPGA, a third FPGA, a data processing module and a memory module; The multiple analog-to-digital converters are connected to the first FPGA and the spectral data acquisition module, and are used to convert the analog signals provided by the spectral data acquisition module into digital signals; The first FPGA is connected to the second FPGA, and is used to obtain a valid signal according to the digital signal, and transmit the valid signal to the second FPGA for caching; The data processing module is connected to the second FPGA and the memory module, and is used to transfer the spectral data in the valid signal cached by the second FPGA to the memory module; The data processing module is also connected to the host computer, and is used to sort and upload a preset amount of spectral data in the memory module to the host computer; The third FPGA is connected to the second FPGA and the image data acquisition module, and is used to generate a delayed trigger signal according to the effective signal to trigger the image data acquisition module to run; The data processing module is an ARM processor, and the ARM processor transfers the spectral data in the valid signal cached by the second FPGA to the memory module based on the DMA channel configured by the AXI bus; The image data acquisition module includes a high-speed camera and an AOM driver, and the trigger dead time of the high-speed camera satisfies: T 死区 ≥1 / f, where T 死区 is the trigger dead time, and f is the frame rate of the high-speed camera; The exposure time of the AOM driver satisfies: T 曝光 ≤L / (F*V), where T 曝光 is the exposure time of the AOM driver, L is the pixel size, F is the optical magnification of the image data acquisition module, and V is the flow rate of the flow cell.

2. The collection chamber module according to claim 1, characterized in that: The process of arranging the spectral data in the memory module by the data processing module includes the following steps: compensation, gating and sorting.

3. The collection chamber module according to claim 1, characterized in that: The first FPGA performs threshold pruning processing and amplification processing on the digital signal to obtain the valid signal.

4. The collection chamber module according to claim 1, characterized in that: The process of the second FPGA caching the valid signal includes: Acquire the valid signal based on the first FPGA transmission; Performing parallel-to-serial conversion on the valid signal to obtain a serial valid signal; The serial valid signal is trimmed and aligned to obtain a valid signal that complies with the 64-bit format of the AXI bus, and is cached based on the FIFO.

5. The collection chamber module according to claim 1, characterized in that: The effective signal includes a forward effective signal and a lateral effective signal, the lateral effective signal includes the spectrum data, and the third FPGA generates the delayed trigger signal based on the forward effective signal.

6. A flow cytometry data acquisition system, characterized in that: include: A spectral data acquisition module, an image data acquisition module, a host computer, and an acquisition chamber module as described in any one of claims 1 to 5; The host computer is also connected to the spectral data acquisition module and the image data acquisition module, and is used to drive the spectral data acquisition module to collect data to generate the analog signal, and is also used to obtain the image data collected by the image data acquisition module, and synchronize and store the image data with the spectral data sorted and uploaded by the data processing module.

7. The flow cytometry data acquisition system according to claim 6, characterized in that: The acquisition bin module also includes a motherboard adapter board, and the motherboard is connected to the host computer and the image data acquisition module through the motherboard adapter board.

8. The flow cytometry data acquisition system according to claim 7, characterized in that: The motherboard adapter board has an SMA interface, and the SMA interface is connected to the image data acquisition module via a coaxial cable with a characteristic impedance of 50Ω.

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