A three-dimensional optoelectronic integrated package structure and a method of forming the same

Abstract

The application relates to a three-dimensional photoelectric integrated packaging structure and a forming method thereof. The forming method comprises the following steps: arranging a light chip and a protection structure in a normal direction on a carrier, wherein a gap exists between the protection structure and the light chip, the edge of the front surface of the light chip is provided with a light port, and the light port is opposite to the protection structure; arranging an electric chip in a reverse direction on the light chip, the electric chip is partially arranged above the protection structure beyond the gap; forming a film layer covering the protection structure, the light chip and the electric chip; forming a plastic sealing layer, the plastic sealing layer integrally seals the protection structure, the light chip and the electric chip, then the plastic sealing layer and the film layer on the electric chip are thinned to expose the electric chip; removing the carrier, and cutting the electric chip along the gap between the protection structure and the light chip to expose the light port; and coupling an optical fiber with the light port of the light chip. The application forms a cavity for light port protection by means of vacuum film pressing, does not occupy the active area of the chip, and can greatly improve the area ratio of the electric chip and the light chip.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a three-dimensional optoelectronic integrated packaging structure and its formation method. Background Technology

[0002] With the development of information technology, increasingly higher requirements are being placed on the transmission rate, latency, and energy efficiency of optical modules. This has led to the widespread application of co-packaged optoelectronic (CPO) structures, which integrate optical and electrical chips within the same package. In CPO structures, through-silicon vias (TSVs) are fabricated on the optical or electrical chip, which is then vertically stacked with matching electrical / optical chips. The resulting three-dimensional optoelectronic integrated package offers advantages such as high interconnect density and low parasitic parameters, representing an important development direction for high-speed optical interconnects.

[0003] Because the silicon interposer board is relatively thin, it warps significantly after mounting, making subsequent C2C assembly difficult. Ideally, the optical chip and electrical chip should be vertically stacked and then molded into a single unit before mounting. However, the optical port of the optical chip is easily contaminated or damaged during the molding process, so a special protective structure is needed at the optical port. Alternatively, die-attach adhesive (DA) can be used to cover the optical port. Fixing the electrical chip and optical port protection structure on the optical chip limits the area of ​​the electrical chip, affecting the overall performance of the optical module. If die-attach adhesive (DA) is used, it is difficult to clean completely, posing a risk of optical port contamination.

[0004] Chinese invention patent CN112034567B discloses a photoelectric chip packaging structure and its packaging method. An electrical chip is placed on an optical chip. Before molding, a protective structure with grooves is attached to the optical chip to protect the optical port area. After mounting, a sealed cavity is formed. After molding, the back of the optical chip is thinned to expose the conductive plug, redistribution is fabricated, and solder balls are arranged. Finally, the chip is diced to expose the optical port. Mounting the protective structure reduces the surface space of the optical chip, limiting the area of ​​the electrical chip. Furthermore, adhesives, such as die-attach adhesive (DA), are typically used for mounting the protective structure, but adhesive overflow can occur, further reducing the usable space on the optical chip and further limiting the area of ​​the electrical chip. In addition, the sealed cavity formed within the protective structure after molding, after the optical chip is thinned and the conductive plug is exposed, presents a risk of silicon explosion due to the pressure difference between the inside and outside of the cavity during the subsequent solder ball arrangement process. Summary of the Invention

[0005] To address at least some of the problems mentioned above in the prior art, the present invention provides a method for forming a three-dimensional optoelectronic integrated packaging structure, comprising:

[0006] An optical chip and a protective structure are mounted on a carrier chip, with a gap between the protective structure and the optical chip. The edge of the front side of the optical chip has an optical port, and the optical port is opposite to the protective structure.

[0007] An electrical chip is flip-chip mounted on the optical chip, with a portion of the electrical chip extending beyond the gap and positioned above the protective structure.

[0008] A thin film layer is formed to cover and protect the structure, optical chip, and electrical chip;

[0009] A molding layer is formed, which integrates the molding layer to protect the optical chip and the electrical chip. Then, the molding layer and thin film layer on the electrical chip are thinned to expose the electrical chip.

[0010] Remove the carrier wafer and cut the electrical chip along the gap between the protective structure and the optical chip to expose the optical port; and

[0011] Couple the optical fiber to the optical port of the optical chip.

[0012] Furthermore, after the thin film layer is formed, the protective structure, optical chip, electrical chip, thin film layer and carrier wafer form a closed space;

[0013] The protruding part of the electrical chip has no transistors or circuits;

[0014] The optical chip has redistribution lines (RDLs) on both the front and back sides, and through-silicon vias (TSVs) in the optical chip, which are electrically connected to the redistribution lines (RDLs).

[0015] Furthermore, it also includes:

[0016] Solder balls are placed on the redistribution surface on the back of the optical chip after the electrical chip is cut; and

[0017] The structure that integrates optical and electrical chips is mounted on a substrate.

[0018] The present invention also provides a method for forming a three-dimensional optoelectronic integrated packaging structure, comprising:

[0019] Electrical chips and protective structures are mounted on a wafer, with gaps between the protective structures and the electrical chips.

[0020] An optical chip is flip-chip mounted on an electrical chip, with a portion of the optical chip extending beyond the gap and positioned above the protective structure. The front side of the optical chip has an optical port, which is 0.08-0.3 mm from the edge of the optical chip and is positioned above the protective structure.

[0021] A thin film layer is formed to cover and protect the structure, electrical chip, and optical chip;

[0022] A molding layer is formed, which integrates the molding layer to protect the optical chip and the electrical chip. The molding layer and thin film layer on the optical chip are thinned to expose the optical chip, and the carrier wafer is removed.

[0023] After cutting and thinning the plastic-encapsulated structure, the cutting line passes through the optical port, exposing the side of the optical waveguide of the optical port; and

[0024] Couple the optical fiber to the optical port of the optical chip.

[0025] The present invention also provides a method for forming a three-dimensional optoelectronic integrated packaging structure, comprising:

[0026] Electrical chips and protective structures are mounted on a wafer, with gaps between the protective structures and the electrical chips.

[0027] An optical chip is flip-chip mounted on an electrical chip, with a portion of the optical chip extending beyond the gap and positioned above the protective structure. The front side of the optical chip has an optical port, which is located above the gap.

[0028] A thin film layer is formed to cover and protect the structure, electrical chip, and optical chip;

[0029] A molding layer is formed, which integrates the molding layer to protect the optical chip and the electrical chip. The molding layer and thin film layer on the optical chip are thinned to expose the optical chip, and the carrier wafer is removed.

[0030] Cutting protective structure; and

[0031] Insert the optical fiber through the gap and couple it with the optical port of the optical chip.

[0032] Furthermore, after cutting, part of the molding layer and thin film layer above the protective structure are retained. The space enclosed by the protective structure, the electrical chip, the optical chip, the molding layer, and the thin film layer can only be entered through the gap between the protective structure and the electrical chip.

[0033] Furthermore, after the thin film layer is formed, the protective structure, optical chip, electrical chip, thin film layer and carrier wafer form a closed space;

[0034] The electrical chip has a redistribution RDL on the front and back sides, and has through-silicon vias (TSVs) that are electrically connected to the redistribution RDLs.

[0035] The present invention also provides a three-dimensional optoelectronic integrated packaging structure, comprising:

[0036] The optical chip has an optical port on its front side;

[0037] An electrical chip, which is electrically connected to the electrical chip;

[0038] Optical fiber, which is coupled to the optical port of the optical chip.

[0039] Furthermore, the front side of the electrical chip faces the front side of the optical chip, the optical port is located at the edge of the optical chip, and the optical fiber is coupled to the optical port of the optical chip from the side.

[0040] The optical chip or the electrical chip has through-silicon vias and redistribution lines (RDLs) on the front and back sides, and the through-silicon vias are electrically connected to the redistribution lines (RDLs).

[0041] Furthermore, it also includes a protective structure, which is arranged side by side with the electrical chip and there is a gap between them.

[0042] Furthermore, the optical chip is flip-chip mounted on the electrical chip, and a portion of the optical chip extends beyond the gap and is located above the protective structure, with the optical port located above the gap;

[0043] The optical fiber extends from the gap and couples with the optical port of the optical chip.

[0044] The present invention has at least the following beneficial effects: (1) The present invention mounts a protective structure on the substrate alongside the chip with through-silicon vias, with a gap between the two. After vacuum pressing, a sealed cavity is formed, and the gap is used for air pressure balance. After debonding, it is connected to the outside atmosphere, eliminating the risk of silicon explosion in the subsequent solder ball placement process; (2) The present invention forms a cavity for optical port protection by vacuum pressing, which does not occupy the active area of ​​the chip, and can greatly improve the area ratio of electrical chips to optical chips. Attached Figure Description

[0045] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0046] Figures 1 to 10 A schematic diagram illustrating the process of forming a three-dimensional optoelectronic integrated packaging structure according to an embodiment of the present invention is shown.

[0047] Figure 11 A schematic diagram of a three-dimensional optoelectronic integrated packaging structure with fiber edge coupling according to an embodiment of the present invention is shown.

[0048] Figures 12 to 21 A schematic diagram illustrating the process of forming a three-dimensional optoelectronic integrated packaging structure according to another embodiment of the present invention is shown.

[0049] Figure 22 A schematic diagram of a three-dimensional optoelectronic integrated packaging structure with fiber edge coupling according to another embodiment of the present invention is shown.

[0050] Figure 23A schematic diagram of a three-dimensional optoelectronic integrated packaging structure with vertical fiber coupling according to an embodiment of the present invention is shown. Detailed Implementation

[0051] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0052] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0053] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0054] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0055] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0056] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0057] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0058] Figures 1 to 10 A schematic diagram illustrating the process of forming a three-dimensional optoelectronic integrated packaging structure according to an embodiment of the present invention is shown.

[0059] When an optical chip is used as an adapter board, the methods for forming a three-dimensional optoelectronic integrated packaging structure include:

[0060] Step 1, as follows Figure 1 As shown, a temporary bonding adhesive layer 102 is coated on the substrate 101.

[0061] Step 2, as follows Figure 2 As shown, a protective structure 103 and an optical chip 104 are mounted on a temporary bonding adhesive layer 102 at a certain spacing. A gap exists between the protective structure 103 and the optical chip 104. The optical chip 104 has been fabricated with through-silicon vias and front / back redistribution lines (RDLs). The optical port 1041 is located at the edge of the front side of the optical chip 104, and the optical port is opposite to the protective structure 103. The optical chip 104 is mounted on a carrier 101 with its front side facing upwards. The protective structure can be a plate-like or block-like structure with the same thickness as the optical chip, such as a dummy die.

[0062] Step 3, as follows Figure 3 As shown, an electrical chip 105 is flip-chip mounted on the optical chip 104, and a filler is formed between the optical chip 104 and the electrical chip 105. A portion of the electrical chip 105 extends beyond the gap and is located above the protective structure 103. The extended portion of the electrical chip has no transistors or circuitry.

[0063] Step 4, as follows Figure 4 and 5 As shown, a thin film layer 106 is formed by vacuum lamination process to cover the protective structure 103, the optical chip 104, and the electrical chip 105. The gap under the electrical chip 105 is blocked and will not be filled by the film. The protective structure 103, the optical chip 104, the electrical chip 105, the thin film layer 106, and the carrier 101 form a closed space to protect the optical port 1041.

[0064] Step 5, as follows Figure 6 and 7 As shown, a molding compound 107 is formed, and the molding compound 107 and thin film layer 106 located on the electrical chip 105 are thinned to expose the electrical chip 105. The molding compound 107 integrally molds and protects the structure 103, the optical chip 104, and the electrical chip 105. The thinning process includes chemical mechanical polishing, etching, or mechanical polishing.

[0065] Step 6, as follows Figure 8 and 9 As shown, the carrier 101 and the temporary bonding adhesive layer 102 are removed, and the electrical chip 105 is cut along the gap between the protective structure 103 and the optical chip 104 to expose the optical port. Then, solder balls are arranged on the redistribution RDL surface on the back of the optical chip 104.

[0066] Step 7, as follows Figure 10 As shown, the structure of the optical chip 104 and the electrical chip 105 packaged together is mounted on the substrate 108, and the optical fiber 109 is coupled to the optical port 1041 of the optical chip 104.

[0067] Figure 11 A schematic diagram of a three-dimensional optoelectronic integrated packaging structure with fiber edge coupling according to an embodiment of the present invention is shown.

[0068] like Figure 11 As shown, the three-dimensional optoelectronic integrated packaging structure formed by the above embodiments includes an optical chip 201, an electrical chip 202, an optical fiber 203, and a substrate 204.

[0069] The optical chip 201 has redistribution RDLs on both its front and back sides. Through-silicon vias (TSVs) are present in the optical chip 201 and are electrically connected to the redistribution RDLs. An optical port 2021 is located at the edge of the front side of the optical chip 201. Solder balls are disposed on the surface of the redistribution RDL on the back side of the optical chip 201.

[0070] The optical chip 201 is mounted upright on the substrate 204, with the front side facing upwards.

[0071] The electrical chip 202 is flip-chip mounted on the optical chip 201, with a primer filling the space between them. The electrical chip 202 and the optical chip 201 are electrically connected.

[0072] Optical fiber 203 is coupled to optical port 2021 of optical chip 201 from the side.

[0073] Figures 12 to 21 A schematic diagram illustrating the process of forming a three-dimensional optoelectronic integrated packaging structure according to another embodiment of the present invention is shown.

[0074] When an electronic chip is used as an adapter board, the methods for forming a three-dimensional optoelectronic integrated packaging structure include:

[0075] Step 1, as follows Figure 12 As shown, a temporary bonding adhesive layer 302 is coated on the substrate 301.

[0076] Step 2, as follows Figure 13 As shown, a protective structure 303 and an electrical chip 304 are mounted on a temporary bonding adhesive layer 302 at a certain spacing. There are gaps between the protective structure 303 and the electrical chip 304. The electrical chip 304 has undergone through-silicon via (TSV) fabrication and front and back redistribution lines (RDLs). The electrical chip 304 is mounted on the carrier 101 with its front side facing upwards. The protective structure can be a plate-like or block-like structure with the same thickness as the electrical chip, such as a dummy die.

[0077] Step 3, as follows Figure 14 and 15 As shown, an optical chip 305 is flip-chip mounted on an electrical chip 304, and a filler is formed between the optical chip 305 and the electrical chip 304. A portion of the optical chip 305 extends beyond the gap and is positioned above the protective structure 303.

[0078] In one embodiment of the present invention, the front side of the optical chip 305 has an optical port 3051, the optical port 3051 is 0.08-0.3mm away from the edge of the optical chip, and the optical port 3051 is located above the protective structure 303. Corresponding to the edge coupling situation, as shown... Figure 14 As shown.

[0079] In another embodiment of the present invention, the front side of the optical chip 305 has an optical port 3051, the optical port 3051 is more than 0.2 mm away from the edge of the optical chip, and the optical port 3051 of the optical chip 305 is located above the gap, corresponding to the vertical coupling situation, such as... Figure 15 As shown.

[0080] Step 4: A thin film layer is formed by vacuum lamination process to cover the protective structure 303, the electrical chip 304, and the optical chip 305. The gap under the optical chip 305 is blocked and will not be filled by the film. The protective structure 303, the electrical chip 304, the optical chip 305, the thin film layer, and the carrier wafer form a closed space to protect the optical port.

[0081] Step 5, as follows Figure 16 and 17 As shown, a molding compound 306 is formed. The molding compound 306 and the thin film layer above the optical chip 305 are thinned to expose the optical chip 305. Then, the carrier 301 and the temporary bonding adhesive layer 302 are removed. The molding compound 306 integrally molds and protects the structure 303, the electrical chip 304, and the optical chip 305. The thinning process includes chemical mechanical polishing, etching, or mechanical polishing.

[0082] Step 6, as follows Figure 16 and 18 As shown, for the structure where the optical port is located above the protective structure 303, the structure after plastic encapsulation and thinning is cut, and the cutting line passes through the optical port, exposing the side of the optical waveguide of the optical port 3051.

[0083] Figure 16 The dicing line passes through the optical port area because the mounted optical chip 305 is a chip that has not been pre-cut to expose the side of the optical port waveguide. To prevent the flow of film material during vacuum lamination from contaminating the optical port area, a certain width of silicon (0.08–0.3 mm without transistors or circuitry) needs to be maintained between the optical port area and the edge of the optical chip during lamination. During dicing after debonding, the dicing line needs to pass through the optical port area to cut out the side of the waveguide for subsequent edge coupling with the optical fiber. In contrast, Figure 8 Since the optical port area is far from the film material, pre-cut optical chips can be used, and the optical port area is not cut during the cutting process.

[0084] In another embodiment of the invention, such as Figure 17 and 19As shown, for the structure where the optical port is located above the gap, the protective structure 303 is cut. The cut structure retains part of the molding layer and thin film layer above the protective structure 303. The space enclosed by the protective structure 303, the electrical chip 304, the optical chip 305 and the molding layer and thin film layer can only be entered through the gap between the protective structure 303 and the electrical chip 304.

[0085] Step 7, as follows Figure 18 and 19 As shown, solder balls are arranged on the surface of the redistribution RDL on the back of the electrical chip 304.

[0086] Step 8, as follows Figure 20 and 21 As shown, the structure that encapsulates the optical chip 305 and the electrical chip 304 together is mounted on the substrate 307, and the optical fiber 308 is coupled to the optical port of the optical chip 305. For side coupling, the optical fiber connects to the optical port from the side. For vertical coupling, the optical fiber extends from the gap between the protective structure 303 and the electrical chip 304 and connects to the optical port.

[0087] Figure 20 In this process, the side of the remaining protective structure connected to the molding compound is integrated with other parts of the encapsulation body, and the remaining protective structure will not fall off due to the lack of support below.

[0088] For cases where the electrical chip area is large enough (e.g., the electrical chip integrates a DSP), a process route can be adopted where a TSV is grown on the electrical chip, and then the optical chip is mounted on it. In this case, the pressure balance gap (the gap between the electrical chip and the protective structure) can also be used to insert optical fibers to achieve vertical coupling.

[0089] Figure 22 A schematic diagram of a three-dimensional optoelectronic integrated packaging structure with fiber edge coupling according to another embodiment of the present invention is shown.

[0090] like Figure 22 As shown, the three-dimensional optoelectronic integrated packaging structure formed by the above embodiments includes a substrate 401, an electrical chip 402, an optical chip 403, and an optical fiber 404.

[0091] The electrical chip 402 is disposed on the substrate 401.

[0092] The electrical chip 402 has redistribution RDLs on both its front and back sides, and has through-silicon vias (TSVs) electrically connected to the redistribution RDLs. Solder balls are disposed on the redistribution RDL surface on the back side of the electrical chip 402.

[0093] The optical chip 403 is flip-chip mounted on the electrical chip 402, with a base filler filling between them. The electrical chip 402 and the optical chip 403 are electrically connected. The front edge of the optical chip 403 has an optical port 4031.

[0094] Optical fiber 404 is coupled to the optical port of optical chip 403 from the side.

[0095] Figure 23 A schematic diagram of a three-dimensional optoelectronic integrated packaging structure with vertical fiber coupling according to an embodiment of the present invention is shown.

[0096] like Figure 23 As shown, the three-dimensional optoelectronic integrated packaging structure formed by the above embodiments includes a substrate 501, an electrical chip 502, an optical chip 503, an optical fiber 504, and a protective structure 505.

[0097] The electrical chip 502 and the protective structure 505 are arranged side by side on the substrate 501, and there is a gap between them.

[0098] The electrical chip 502 has redistribution RDLs on both its front and back sides, and has through-silicon vias (TSVs) electrically connected to the redistribution RDLs. Solder balls are disposed on the redistribution RDL surface on the back side of the electrical chip 502.

[0099] The optical chip 503 is flip-chip mounted on the electrical chip 502, with a base filler filling between them. The electrical chip 502 and the optical chip 503 are electrically connected. The front side of the optical chip 503 has an optical port 5031. A portion of the optical chip 503 extends beyond the gap and is located above the protective structure, with the optical port located above the gap.

[0100] Optical fiber 404 extends through the gap and couples with the optical port of optical chip 403.

[0101] The aforementioned three-dimensional optoelectronic integrated packaging structure also includes a thin film layer, which covers the left and right sides of the optical chip 503, the upper surface of the protective structure 505, and the right side of the electrical chip 502.

[0102] It also includes the encapsulation layer, the portion covered by the encapsulation film layer.

[0103] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A method of forming a three-dimensional optoelectronic integrated package structure, comprising: The method comprises the following steps: arranging an optical chip and a protection structure on a carrier in a normal direction, wherein a gap exists between the protection structure and the optical chip, the edge of the front surface of the optical chip has an optical port, and the optical port is opposite to the protection structure; arranging an electrical chip on the optical chip in a reverse direction, and a part of the electrical chip extends over the gap to the top of the protection structure; forming a film layer covering the protection structure, the optical chip and the electrical chip; forming a plastic encapsulation layer, and integrally encapsulating the protection structure, the optical chip and the electrical chip, then thinning the plastic encapsulation layer and the film layer above the electrical chip to expose the electrical chip; removing the carrier, and cutting the electrical chip along the gap between the protection structure and the optical chip to expose the optical port; and coupling an optical fiber with the optical port of the optical chip. After the film layer is formed, the protection structure, the optical chip, the electrical chip, the film layer and the carrier form a closed space; 2. The method of claim 1, wherein, the part of the electrical chip extending out has no transistor and circuit; the front surface and the back surface of the optical chip have a redistribution layer (RDL), and the optical chip has a through silicon via (TSV) which is electrically connected with the RDL. The method further comprises the following steps:

3. The method of claim 1, wherein, arranging solder balls on the surface of the RDL on the back surface of the optical chip after the electrical chip is cut; and attaching the structure in which the optical chip and the electrical chip are encapsulated together to a substrate. The method comprises the following steps: arranging an electrical chip and a protection structure on a carrier in a normal direction, wherein a gap exists between the protection structure and the electrical chip; 4. A method of forming a three-dimensional optoelectronic integrated package structure, comprising: arranging an optical chip on the electrical chip in a reverse direction, and a part of the optical chip extends over the gap to the top of the protection structure, wherein the front surface of the optical chip has an optical port, the distance between the optical port and the edge of the optical chip is 0.08-0.3 mm, and the optical port is above the protection structure; forming a film layer covering the protection structure, the electrical chip and the optical chip; forming a plastic encapsulation layer, and integrally encapsulating the protection structure, the optical chip and the electrical chip, thinning the plastic encapsulation layer and the film layer above the optical chip to expose the optical chip, and removing the carrier; cutting the structure after the plastic encapsulation layer is thinned, the cutting line passes through the optical port, and the side surface of the optical waveguide of the optical port is exposed; and coupling an optical fiber with the optical port of the optical chip. The method comprises the following steps: arranging an electrical chip and a protection structure on a carrier in a normal direction, wherein a gap exists between the protection structure and the electrical chip; 5. A method of forming a three-dimensional optoelectronic integrated package structure, comprising: arranging an optical chip on the electrical chip in a reverse direction, and a part of the optical chip extends over the gap to the top of the protection structure, wherein the front surface of the optical chip has an optical port, and the optical port is above the gap; forming a film layer covering the protection structure, the electrical chip and the optical chip; forming a plastic encapsulation layer, and integrally encapsulating the protection structure, the optical chip and the electrical chip, thinning the plastic encapsulation layer and the film layer above the optical chip to expose the optical chip, and removing the carrier; cutting the protection structure; and coupling an optical fiber with the optical port of the optical chip from the gap. After cutting, the part of the plastic encapsulation layer and the film layer above the protection structure is reserved, and the space surrounded by the protection structure, the electrical chip, the optical chip, the plastic encapsulation layer and the film layer can only be accessed through the gap between the protection structure and the electrical chip. After the film layer is formed, the protection structure, the optical chip, the electrical chip, the film layer and the carrier form a closed space; the front surface and the back surface of the electrical chip have a redistribution layer (RDL), and the electrical chip has a through silicon via (TSV) which is electrically connected with the RDL.

6. The method of claim 5, wherein, The method comprises the following steps:

7. The method according to claim 4 or 5, characterized in that, an optical chip, the front surface of the optical chip has an optical port; an electrical chip, the electrical chip is electrically connected with the optical chip; 8. A three-dimensional optoelectronic integrated package structure formed by the method of claim 4, wherein, an optical fiber, the optical fiber is coupled with the optical port of the optical chip. ​ ​ ​ 9. The structure of claim 8, wherein The front surface of the electric chip is opposite to the front surface of the optical chip, and the light port is located at the edge of the optical chip, and the optical fiber is coupled with the light port of the optical chip from the side surface; The optical chip or the electric chip has a through silicon via and a redistribution layer (RDL) on the front surface and the back surface, and the through silicon via is electrically connected with the redistribution layer (RDL).

10. The structure of claim 8, wherein A protection structure is further included, which is arranged side by side with the electric chip, and a gap is formed between the electric chip and the protection structure.

11. The structure of claim 10, wherein The optical chip is flip-chip mounted on the electric chip, and a part of the optical chip extends over the gap to be located above the protection structure, and the light port is located above the gap; The optical fiber extends into the gap to be coupled with the light port of the optical chip.

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