Data reading method, system and electronic device
The data reading method improves efficiency by converting protocols and using a ping-pong cache to pre-read data, addressing inefficiencies in data transmission between non-volatile storage controllers and external memories.
Patent Information
- Application Number
- CN202411319903.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2044-09-20
AI Technical Summary
The data transmission rate between non-volatile storage controllers and external memories, such as flash memory and solid-state drives, is inefficient due to mismatched bit widths, leading to low overall data reading efficiency and resource waste.
Implement a data reading method that involves protocol conversion of read commands, caching data in a ping-pong cache area, and pre-reading data to optimize data retrieval without waiting for subsequent commands.
This method enhances data reading efficiency by caching and pre-reading data, reducing the need for repeated access to external memory and minimizing resource waste.
Smart Images
Figure CN118860294B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of data reading, and in particular to a data reading method, system and electronic device. Background Art
[0002] A non-volatile storage controller is a hardware device or chip used to manage and control non-volatile storage media (such as flash memory, solid-state drives, etc.). It usually contains components such as processors, storage control logic, cache, and interface circuits. It communicates with the host system through standard interfaces (such as SATA and PCIe) and provides high-speed data transmission and low-latency storage access. Based on this, non-volatile storage controllers are widely used in various devices, including personal computers, servers, embedded systems, mobile devices, etc.
[0003] When the host reads data from an external memory such as a flash memory or a solid-state drive, it usually generates a corresponding read command and transmits the read command to the external memory. The external memory receives the read command and responds to return the data and store it in the static random access memory (SRAM) inside the chip for the host or the slave corresponding to the host to read.
[0004] Among them, the memory bit width is 1 bit, the AXI slave bit width is 32 bits, and the SRAM bit width is also 32 bits. It can be seen that the data transmission rate of the external memory is slow, and the data transmission rate is quite different from that of the AXI slave and SRAM. Therefore, this leads to low overall data reading efficiency and waste of resources. Summary of the invention
[0005] The purpose of the embodiments of the present application is to provide a data reading method, system and electronic device, which can effectively improve data reading efficiency and avoid waste of resources.
[0006] In a first aspect, an embodiment of the present application provides a data reading method, comprising:
[0007] Obtaining a first data read command, and transmitting the first data read command to a cache processing module according to a first transmission protocol, where the first transmission protocol is a transmission protocol followed within the electronic device to which the cache processing module belongs;
[0008] Performing protocol conversion on the first data read command according to a second transmission protocol, so as to read first target data from an external memory based on the converted first data read command, wherein the second transmission protocol is a transmission protocol followed by the external memory;
[0009] Cache the first target data into a target ping-pong cache area in a cache processing module;
[0010] Determine a first maximum address corresponding to the first target data in the target ping-pong cache area, and determine a second maximum address of the target ping-pong cache area;
[0011] In the case where the second first data read command is not obtained, the second target data is pre-read from the external memory, and the second target data is cached to the area corresponding to the first maximum address and the second maximum address, the second first data read command is used to instruct to read the second target data, and there is no response relationship between the second target data and the first data read command.
[0012] In a possible implementation manner, obtaining the first data read command includes:
[0013] A first data read command is generated for a target storage area of the internal memory, wherein the first data read command includes first address information.
[0014] In a possible implementation manner, caching the first target data into a target ping-pong cache area in a cache processing module includes:
[0015] The first target data are sequentially cached in a target ping-pong cache area in a cache processing module according to an address sequence corresponding to the first target data, wherein the address sequence is a sequence corresponding to storage addresses of the first target data on the external memory.
[0016] In a possible implementation manner, the preset address bit of the target storage area is the same as the preset address bit of the cache processing module, and there is a mapping relationship between the address of the cache processing module and the target ping-pong cache area;
[0017] The step of sequentially caching the first target data into a target ping-pong cache area in a cache processing module includes:
[0018] Based on the second address information of the target storage area included in the first data read command, the first target data is sequentially cached to a target ping-pong cache area in a cache processing module.
[0019] In a possible implementation manner, pre-reading the second target data from the external memory and caching the second target data to an area corresponding to the first maximum address and the second maximum address includes:
[0020] determining a target length based on the first maximum address and the second maximum address;
[0021] Read the data of the target length from the external memory to obtain the second target data;
[0022] According to the address sequence corresponding to the second target data, the second target data is sequentially cached to the area corresponding to the first maximum address and the second maximum address.
[0023] In a possible implementation manner, after caching the first target data in a target ping-pong cache area in a cache processing module, the method includes:
[0024] The first target data is transmitted to the target storage area of the internal memory through the cache processing module.
[0025] In a possible implementation, a plurality of target ping-pong cache areas are provided in the cache processing module, and each of the ping-pong cache areas is provided with two sub-cache areas.
[0026] In a possible implementation manner, after transferring the first target data to the internal memory, the method includes:
[0027] Determining whether the second target data is cached in a sub-cache area, or determining whether there is a sub-cache area that meets a preset condition between two sub-cache areas, wherein the preset condition is that all data in the sub-cache area is transferred to the internal memory;
[0028] If yes, determine a target sub-cache area, the target sub-cache area does not include the second target data, or the target sub-cache area is a sub-cache area that does not meet a preset condition;
[0029] updating the address of the target sub-cache area according to the second maximum address;
[0030] Pre-read third target data from the external memory, and cache the third target data in the target sub-cache area.
[0031] In a second aspect, an embodiment of the present application further provides a data reading system, including a control module, a cache processing module and an external memory, wherein the cache processing module is data-connected to the control module and the external memory;
[0032] The control module generates a first data read command, and transmits the first data read command to the cache processing module according to a first transmission protocol, where the first transmission protocol is a transmission protocol followed inside the electronic device to which the cache processing module belongs;
[0033] The cache processing module performs protocol conversion on the first data read command according to a second transmission protocol, so as to read the first target data from the external memory based on the converted first data read command, wherein the second transmission protocol is the transmission protocol followed by the external memory; the first target data is cached to a target ping-pong cache area in the cache processing module; a first maximum address corresponding to the first target data in the target ping-pong cache area is determined, and a second maximum address of the target ping-pong cache area is determined; in the case where a second first data read command is not obtained, the second target data is pre-read from the external memory, and the second target data is cached to an area corresponding to the first maximum address and the second maximum address, wherein the second first data read command is used to indicate reading of the second target data, and there is no response relationship between the second target data and the first data read command.
[0034] The control module generates a first data read command for a target storage area of an internal memory, wherein the first data read command includes address information.
[0035] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via a bus, and when the machine-readable instructions are executed by the processor, the steps of the data reading method are executed.
[0036] In a fourth aspect, an embodiment of the present application further provides a storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of any one of the above-mentioned data reading methods are executed.
[0037] In the data reading method provided in the embodiment of the present application, after obtaining a first data read command, based on the first transmission protocol and the second transmission protocol, after reading the first target data corresponding to the first data read command from the external memory, the first target data is cached in the target ping-pong cache area in the cache processing module, so as to continue to read the second target data from the external memory based on the first maximum address corresponding to the first target data in the target ping-pong cache area and the second maximum address of the target ping-pong cache area if the second data read command is not obtained, that is, the second target data is read in advance and stored in the area corresponding to the first maximum address and the second maximum address in the target ping-pong cache area, so that when the second data read command indicating to read the second target data is obtained, the time for reading the second target data can be greatly shortened, thereby avoiding waste of resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0039] Figure 1 A flow chart of a data reading method provided by the present application is shown;
[0040] Figure 2 A schematic diagram showing a data reading operation process provided by an embodiment of the present application is shown;
[0041] Figure 3 A schematic diagram of the structure of a cache processing module provided by the present application is shown;
[0042] Figure 4 A schematic diagram showing the structure of a target ping-pong cache area provided by the present application is shown;
[0043] Figure 5 A schematic diagram showing the structure of the updated target ping-pong cache area provided by the present application is shown;
[0044] Figure 6 A structural schematic diagram of a data reading system provided by the present application is shown;
[0045] Figure 7 A schematic structural diagram of an electronic device provided by the present application is shown. DETAILED DESCRIPTION
[0046] Various aspects and features of the present application are described herein with reference to the accompanying drawings.
[0047] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.
[0048] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.
[0049] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.
[0050] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to determine that many other equivalent forms of the present application have the features described in the present application and are therefore within the scope of protection defined thereby.
[0051] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.
[0052] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.
[0053] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.
[0054] The embodiment of the present application provides a data reading method, which can effectively improve the data reading efficiency and avoid resource waste. To facilitate understanding of the present application, a data reading method provided by the present application is first introduced in detail.
[0055] like Figure 1 As shown, it is a flow chart of the data reading method provided in an embodiment of the present application, wherein the specific steps include S101-S105.
[0056] S201, obtaining a first data read command, and transmitting the first data read command to a cache processing module according to a first transmission protocol, where the first transmission protocol is a transmission protocol followed within the electronic device to which the cache processing module belongs.
[0057] In a specific implementation, since the storage space of the internal memory of the electronic device is small, the data can be stored in an external memory with a larger storage space. When the data stored in the external memory needs to be read, the data is read through a non-volatile storage controller.
[0058] Further, when it is determined that the data stored in the external memory needs to be read, a first data read command is generated, wherein the first data read command instructs to read the data to be read from the external memory and return to a designated area.
[0059] After obtaining the first data read command, the first data read command is transmitted to the cache processing module according to the first transmission protocol, where the first transmission protocol is a transmission protocol followed inside the electronic device to which the cache processing module belongs. Figure 2 A schematic diagram of a data reading operation process provided by an embodiment of the present application is shown. Figure 2 In the embodiment, the AXI slave, the cache processing module, the IO interface and the external memory are connected in sequence. The host corresponding to the AXI slave generates a first data read command, and after obtaining the first data read command, the AXI slave transmits the first data read command to the cache processing module according to the first transmission protocol, that is, the AXI protocol followed by the AXI slave.
[0060] S102, performing protocol conversion on the first data read command according to a second transmission protocol, so as to read first target data from the external memory based on the converted first data read command, wherein the second transmission protocol is a transmission protocol followed by the external memory.
[0061] Further, according to the transmission protocol followed by the external memory, that is, the second transmission protocol, the first data read command is converted into a protocol, so as to read the first target data from the external memory based on the converted first data read command. Figure 2 After obtaining the first data read command, the cache processing module converts the first data read command according to the transmission protocol followed by the external memory, that is, the second transmission protocol, to obtain a conversion instruction, and transmits the conversion instruction to the IO interface, so as to transmit it to the external memory through the IO interface according to the transmission protocol followed by the external memory, so that the external memory receives and responds to the conversion instruction and returns the first target data, thereby achieving the purpose of responding to the first data read command.
[0062] Similarly, when the external memory returns the first target data to the internal memory, data conversion is also required to comply with the AXI protocol, thereby enabling the AXI slave to store the first target data in the internal memory.
[0063] S103: Cache the first target data into a target ping-pong cache area in the cache processing module.
[0064] After reading the first target data, the first target data is cached in the target ping-pong cache area in the cache processing module. As one example, the first target data is cached in sequence in the target ping-pong cache area in the cache processing module according to the address sequence corresponding to the first target data, and the address sequence is the sequence corresponding to the storage address of the first target data on the external memory.
[0065] For example, the address sequence corresponding to the first target data is 0001-0008. When the first target data is cached to the target ping-pong cache area in the cache processing module, the first target data is cached in the target ping-pong cache area in the cache processing module in sequence according to the sequence of 0001-0008, that is, data access follows the first-in-first-out principle.
[0066] Optionally, the cache processing module includes a static random access memory (SRAM), and the SRAM is used as an internal cache space. Of course, other registers can also be used. Preferably, it is set to SRAM. Compared with other registers, using SRAM can save chip volume.
[0067] The SRAM is provided with a plurality of ping-pong cache areas, each of which is provided with two sub-cache areas. The two sub-cache areas can be used alternately in a multi-threaded environment to perform read and write operations, thereby effectively improving the read and write efficiency.
[0068] As an example, Figure 3 shows a schematic diagram of the structure of the cache processing module, Figure 3 The cache processing module in the embodiment includes four ping-pong cache areas, namely, ping-pong cache area A, ping-pong cache area B, ping-pong cache area C and ping-pong cache area D. Each cache processing module is provided with two sub-cache areas, namely, sub-cache area 1 and sub-cache area 2. Of course, the number of ping-pong cache areas in the cache processing module can be determined according to actual needs, and the cache space of each ping-pong cache area can be the same or different.
[0069] In a specific implementation, different AXI hosts may correspond to one or more ping-pong cache areas, and other AXI hosts cannot access the one or more ping-pong cache areas corresponding to the AXI host. When the first data read command is obtained, the ping-pong cache area corresponding to the AXI host to which the first data read command belongs can be found according to the first data read command, and the ping-pong cache area corresponding to the AXI host to which the first data read command belongs is determined as the target ping-pong cache area. It should be noted that even if an AXI host corresponds to multiple ping-pong cache areas, the addresses in the multiple ping-pong cache areas are sorted independently and do not affect each other.
[0070] Furthermore, the target ping-pong cache area is also provided with cache addresses that increase in sequence. In a specific implementation, such as 0x8000-0x8040, if the target ping-pong cache area has not cached data, 0x8000, which is the initial address in the target ping-pong cache area, is used to cache data. If the target ping-pong cache area has cached data and has not been transferred to the internal memory, the minimum address of the uncached data is used as the initial address to cache the data.
[0071] As another example, in the embodiment of the present application, the preset address bits of the target storage area are set to be the same as the preset address bits of the cache processing module, for example, the lower 7 bits of the address of the target storage area are the same as the address of the cache processing module or the lower 7 bits of the address, and at the same time, there is a mapping relationship between the address of the cache processing module and the target ping-pong cache area, so that when the first target data is cached to the target ping-pong cache area, the initial address can be determined according to the second address information of the target storage area included in the first data read command, that is, the address with the same preset address bits as the preset address bits in the second address is used as the initial address, and then data is cached from the initial address. Therefore, when reading data from the cache processing module and storing it in the target storage area, the storage position in the target storage area can be accurately determined without calculating the address, which is conducive to timing convergence.
[0072] After determining the initial address in the target ping-pong cache area, the first target data is sequentially cached to the target ping-pong cache area in the cache processing module starting from the initial address according to the address sequence corresponding to the first target data.
[0073] S104, determining a first maximum address corresponding to the first target data in the target ping-pong cache area, and determining a second maximum address of the target ping-pong cache area.
[0074] After the first target data is cached in the target ping-pong cache area, a first maximum address corresponding to the first target data in the target ping-pong cache area is determined.
[0075] Optionally, the address of the target ping-pong cache area is variable, that is, after the cache data of the target ping-pong cache area is transferred to the internal memory and the cache data is deleted, the address corresponding to the deleted cache data is updated. Based on this, while determining the first maximum address, the second maximum address of the target ping-pong cache area is determined.
[0076] Reference Figure 4A schematic diagram of the structure of the target ping-pong cache area is shown, wherein the address of the target ping-pong cache area is 0x8040-0x80bf, and the storage address corresponding to the first target data in the target ping-pong cache area is 0x8070-0x80a4. At this time, the first maximum address is 0x80a4 and the second maximum address is 0x80bf.
[0077] It should be noted that the storage address may be in hexadecimal, binary, octal or other formats, and accordingly, different address formats may have different preset address bits, which may be set according to actual needs. This embodiment of the present application does not specifically limit this.
[0078] S105, in the case where the second data read command is not obtained, the second target data is pre-read from the external memory, and the second target data is cached to the area corresponding to the first maximum address and the second maximum address. The second data read command is used to instruct to read the second target data, and there is no response relationship between the second target data and the first data read command.
[0079] After determining the first maximum address and the second maximum address, and when the second data read command for instructing to read the second target data is not obtained, the corresponding second target data is pre-read from the external memory based on the first maximum address and the second maximum address, that is, the second target data has no response relationship with the first data read command. Afterwards, the pre-read second target data is cached in the target ping-pong cache area, that is, the area corresponding to the first maximum address and the second maximum address, so that when the second target data is subsequently read, the second target data can be quickly returned to the internal memory without passing through the external memory, which greatly improves the reading efficiency of the second target data.
[0080] Optionally, when reading the second target data from the external memory, a target length is determined based on the first maximum address and the second maximum address, and then data of the target length is read from the external memory to obtain the second target data, wherein the second target data is continuous with the first target data.
[0081] After obtaining the second target data, the second target data is sequentially cached to the area corresponding to the first maximum address and the second maximum address according to the address sequence corresponding to the second target data. Figure 4 , the area corresponding to the first maximum address and the second maximum address is the area corresponding to 0x80a4-0x80bf.
[0082] In the data reading method provided in the embodiment of the present application, after the first target data corresponding to the first data read command is read from the external memory, the first target data is cached in the target ping-pong cache area in the cache processing module, and based on the first maximum address corresponding to the first target data in the target ping-pong cache area and the second maximum address of the target ping-pong cache area, the second target data continues to be read from the external memory without obtaining the second data read command, that is, the second target data is read in advance and stored in the area corresponding to the first maximum address and the second maximum address in the target ping-pong cache area. When the second data read command indicating to read the second target data is obtained, the time for reading the second target data can be greatly shortened, that is, the data reading efficiency is effectively improved and resource waste is avoided.
[0083] As one example, when obtaining the first data read command, the first data read command is generated for the target storage area of the internal memory, and the first data read command includes first address information. Accordingly, the first target data returned by the external memory is the data corresponding to the first address information in the external memory.
[0084] Optionally, a first data read command is generated for a target storage area of the internal memory, where the target storage area is a storage area of the first target data in the internal memory. The first data read command includes first address information, which includes at least the first address and / or last address of the external memory and the data length, that is, the first data read command can be generated according to the first address and / or last address of the external memory, the data length, and the address or identifier of the target storage area of the internal memory.
[0085] After the data read instruction is generated, the first data read command is transmitted to the external memory through the cache processing module, so that the external memory responds to the first data read command and then returns corresponding data.
[0086] Receive the first target data returned by the external memory, the first target data being the data corresponding to the first address information in the external memory. For example, the first data read command includes the first address and the data length, and accordingly, the external memory selects the data with the data length according to the first address as the first target data.
[0087] In a specific implementation, after the first target data is cached in the target ping-pong cache area in the cache processing module, the first target data is transmitted to the target storage area of the internal memory through the cache processing module to complete the data reading.
[0088] At the same time, after the first target data is transferred to the internal memory, it is further determined whether the second target data is cached in a sub-cache area, or whether there is a sub-cache area that meets the preset condition in the two sub-cache areas, and the preset condition is that all the data in the sub-cache area is transferred to the internal memory. If so, the target sub-cache area is determined, the target sub-cache area does not include the second target data, or the target sub-cache area is a sub-cache area that does not meet the preset condition. Afterwards, according to the second maximum address, the address of the target sub-cache area is updated to pre-read the third target data from the external memory, and cache the third target data to the target sub-cache area.
[0089] Continue to refer to Figure 4 , after transferring the first target data to the target storage area of the internal memory, determining whether the second target data is cached in the sub-cache area 1 or the sub-cache area 2, or determining whether all the data in the sub-cache area 1 and the sub-cache area 2 are transferred to the internal memory, Figure 4 In the example, the second target data is only cached in the sub-cache area 1, and all the data in the sub-cache area 2 is transferred to the internal memory. At this time, the sub-cache area 2 is determined to be the target sub-cache area.
[0090] After determining the target sub-cache area, the address of the target sub-cache area is updated according to the second largest address, that is, the largest address in the target ping-pong cache area. Specifically, the second largest address, that is, 0x80bf, is arranged in sequence. Figure 5 The schematic diagram of the structure of the updated target ping-pong cache area is shown, and the address corresponding to the sub-cache area 2 is 0x80c0-0x80ff.
[0091] Afterwards, the third target data is pre-read from the external memory and cached in the target sub-cache area, that is, the data length of the third target data is determined according to the target sub-cache area. Therefore, when the third target data is subsequently read, the third target data can be quickly returned to the internal memory without passing through the external memory, which greatly improves the reading efficiency of the third target data.
[0092] It should be noted that in the scenario where multiple AXI hosts access external memory at the same time, for example, multiple CPUs or multiple cores in a CPU access the same flash memory at the same time, each CPU or each core corresponds to a ping-pong cache area, and the ping-pong cache area corresponding to one CPU or one core has the following Figure 5 After the address in is updated, data is pre-read for the updated address of the ping-pong cache area, and the addresses of the ping-pong cache areas corresponding to other CPUs or cores are independent of each other and do not affect each other, thereby ensuring the accuracy of data read by each CPU or core.
[0093] According to the above method, two sub-cache areas are used alternately to store pre-read data, which effectively improves data reading efficiency and avoids resource waste.
[0094] Based on the same inventive concept, the second aspect of the present application also provides a data reading system corresponding to a data reading method. Since the principle of solving the problem by the data reading system in the present application is similar to that of the above-mentioned data reading method of the present application, the implementation of the system can be determined by referring to the implementation of the method, and the repeated parts will not be repeated.
[0095] Figure 6 The structure diagram of the data reading system provided in the embodiment of the present application is shown. It can be seen from the figure that the data reading system includes a control module 601, a cache processing module 602 and an external memory 603, and the cache processing module 602 is data-connected with the control module 601 and the external memory 603;
[0096] The control module 601 generates a first data read command and transmits it to the cache processing module 602;
[0097] The cache processing module 602 performs protocol conversion on the first data read command according to the second transmission protocol, so as to read the first target data from the external memory 603 based on the converted first data read command, wherein the second transmission protocol is the transmission protocol followed by the external memory 603; the first target data is cached to the target ping-pong cache area in the cache processing module 602; a first maximum address corresponding to the first target data in the target ping-pong cache area is determined, and a second maximum address of the target ping-pong cache area is determined; in the case where the second data read command is not obtained, the second target data is pre-read from the external memory 603, and the second target data is cached to the area corresponding to the first maximum address and the second maximum address, wherein the second data read command is used to indicate reading of the second target data, and there is no response relationship between the second target data and the first data read command.
[0098] In the data reading system provided in the embodiment of the present application, after obtaining a first data read command, based on the first transmission protocol and the second transmission protocol, after reading the first target data corresponding to the first data read command from the external memory, the first target data is cached in the target ping-pong cache area in the cache processing module, so as to continue to read the second target data from the external memory based on the first maximum address corresponding to the first target data in the target ping-pong cache area and the second maximum address of the target ping-pong cache area if the second data read command is not obtained, that is, the second target data is read out in advance and stored in the area corresponding to the first maximum address and the second maximum address in the target ping-pong cache area, so that when the second data read command indicating to read the second target data is obtained, the time for reading the second target data can be greatly shortened, that is, the data reading efficiency is effectively improved and resource waste is avoided.
[0099] An embodiment of the present application provides a storage medium, which is a computer-readable medium and stores a computer program. When the computer program is executed by a processor, the method provided by any embodiment of the present application is implemented, including the following steps S11 to S15:
[0100] S11, obtaining a first data read command, and transmitting the first data read command to a cache processing module according to a first transmission protocol, where the first transmission protocol is a transmission protocol followed within the electronic device to which the cache processing module belongs;
[0101] S12, performing protocol conversion on the first data read command according to a second transmission protocol, so as to read first target data from an external memory based on the converted first data read command, wherein the second transmission protocol is a transmission protocol followed by the external memory;
[0102] S13, caching the first target data into a target ping-pong cache area in a cache processing module;
[0103] S14, determining a first maximum address corresponding to the first target data in the target ping-pong cache area, and determining a second maximum address of the target ping-pong cache area;
[0104] S15, in the case where the second data read command is not obtained, the second target data is pre-read from the external memory, and the second target data is cached to the area corresponding to the first maximum address and the second maximum address, the second data read command is used to instruct to read the second target data, and there is no response relationship between the second target data and the first data read command.
[0105] An embodiment of the present application provides an electronic device. The structural diagram of the electronic device can be as follows: Figure 7As shown, at least a memory 701 and a processor 702 are included, the memory 701 stores a computer program, and the processor 702 implements the method provided by any embodiment of the present application when executing the computer program on the memory 701. Exemplarily, the steps of the electronic device computer program are as follows S21 to S25:
[0106] S21, obtaining a first data read command, and transmitting the first data read command to a cache processing module according to a first transmission protocol, where the first transmission protocol is a transmission protocol followed within the electronic device to which the cache processing module belongs;
[0107] S22, performing protocol conversion on the first data read command according to a second transmission protocol, so as to read first target data from an external memory based on the converted first data read command, wherein the second transmission protocol is a transmission protocol followed by the external memory;
[0108] S23, caching the first target data into a target ping-pong cache area in a cache processing module;
[0109] S24, determining a first maximum address corresponding to the first target data in the target ping-pong cache area, and determining a second maximum address of the target ping-pong cache area;
[0110] S25, in the case where the second data read command is not obtained, pre-read the second target data from the external memory, cache the second target data to the area corresponding to the first maximum address and the second maximum address, the second data read command is used to instruct to read the second target data, and there is no response relationship between the second target data and the first data read command.
[0111] In the data reading method provided in the embodiment of the present application, after obtaining a first data read command, based on the first transmission protocol and the second transmission protocol, after reading the first target data corresponding to the first data read command from the external memory, the first target data is cached in the target ping-pong cache area in the cache processing module, so as to continue to read the second target data from the external memory based on the first maximum address corresponding to the first target data in the target ping-pong cache area and the second maximum address of the target ping-pong cache area if the second data read command is not obtained, that is, the second target data is read out in advance and stored in the area corresponding to the first maximum address and the second maximum address in the target ping-pong cache area. When the second data read command indicating to read the second target data is obtained, the time for reading the second target data can be greatly shortened, that is, the data reading efficiency is effectively improved and resource waste is avoided.
[0112] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
[0113] It should also be understood that the memory mentioned in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct RAM bus random access memory (DR RAM).
[0114] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.
[0115] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.
[0116] In addition to the data bus, the bus may also include a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity, various buses are marked as buses in the figure.
[0117] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.
[0118] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0119] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.
[0120] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0121] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0122] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0123] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0124] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0125] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.
[0126] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A data reading method, comprising: Obtaining a first data read command, and transmitting the first data read command to a cache processing module according to a first transmission protocol, where the first transmission protocol is a transmission protocol followed within the electronic device to which the cache processing module belongs; Performing protocol conversion on the first data read command according to a second transmission protocol, so as to read first target data from an external memory based on the converted first data read command, wherein the second transmission protocol is a transmission protocol followed by the external memory; Cache the first target data into a target ping-pong cache area in the cache processing module; Determine a first maximum address corresponding to the first target data in the target ping-pong cache area, and determine a second maximum address of the target ping-pong cache area; In the case where the second data read command is not obtained, pre-reading the second target data from the external memory, and caching the second target data to the area corresponding to the first maximum address and the second maximum address, wherein the second data read command is used to instruct to read the second target data, and there is no response relationship between the second target data and the first data read command; The obtaining of the first data reading command comprises: generating a first data read command for a target storage area of the internal memory, wherein the first data read command includes first address information; The step of caching the first target data into a target ping-pong cache area in a cache processing module includes: According to the address sequence corresponding to the first target data, an initial address is determined based on the second address information of the target storage area included in the first data read command, and the first target data is sequentially cached to the target ping-pong cache area in the cache processing module according to the initial address; The address sequence is the sequence corresponding to the storage address of the first target data on the external memory; the preset address bit of the target storage area is the same as the preset address bit of the cache processing module, and there is a mapping relationship between the address of the cache processing module and the target ping-pong cache area; the initial address is an address where the preset address bit in the cache processing module is the same as the preset address bit in the second address information.
2. The data reading method according to claim 1, wherein the pre-reading of the second target data from the external memory and caching the second target data to an area corresponding to the first maximum address and the second maximum address comprises: determining a target length based on the first maximum address and the second maximum address; Read the data of the target length from the external memory to obtain the second target data; According to the address sequence corresponding to the second target data, the second target data is sequentially cached to the area corresponding to the first maximum address and the second maximum address.
3. The data reading method according to claim 1, after caching the first target data into the target ping-pong cache area in the cache processing module, comprises: The first target data is transmitted to the target storage area of the internal memory through the cache processing module. 4 . The data reading method according to claim 3 , wherein the cache processing module is provided with a plurality of ping-pong cache areas, and each of the ping-pong cache areas is provided with two sub-cache areas.
5. The data reading method according to claim 4, after transferring the first target data to the internal memory, comprising: Determining whether the second target data is cached in a sub-cache area, or determining whether there is a sub-cache area that meets a preset condition between two sub-cache areas, wherein the preset condition is that all data in the sub-cache area is transferred to the internal memory; If yes, determine a target sub-cache area, the target sub-cache area does not include the second target data, or the target sub-cache area is a sub-cache area that does not meet a preset condition; updating the address of the target sub-cache area according to the second maximum address; Pre-read third target data from the external memory, and cache the third target data in the target sub-cache area.
6. A data reading system, comprising a control module, a cache processing module and an external memory, wherein the cache processing module is data-connected to the control module and the external memory; The control module generates a first data read command for a target storage area of the internal memory, and transmits the first data read command to the cache processing module according to a first transmission protocol, where the first transmission protocol is a transmission protocol followed inside the electronic device to which the cache processing module belongs, and the first data read command includes first address information; The cache processing module performs protocol conversion on the first data read command according to a second transmission protocol, so as to read the first target data from the external memory based on the converted first data read command, wherein the second transmission protocol is a transmission protocol followed by the external memory; Cache the first target data into a target ping-pong cache area in a cache processing module; Determine a first maximum address corresponding to the first target data in the target ping-pong cache area, and determine a second maximum address of the target ping-pong cache area; In the case where the second data read command is not obtained, second target data is read from the external memory, and the second target data is cached in an area corresponding to the first maximum address and the second maximum address, wherein the second data read command is used to instruct to read the second target data, and there is no response relationship between the second target data and the first data read command; The cache processing module determines an initial address according to the address sequence corresponding to the first target data and based on the second address information of the target storage area included in the first data read command, and sequentially caches the first target data to the target ping-pong cache area in the cache processing module according to the initial address; The address sequence is the sequence corresponding to the storage address of the first target data on the external memory; the preset address bit of the target storage area is the same as the preset address bit of the cache processing module, and there is a mapping relationship between the address of the cache processing module and the target ping-pong cache area; the initial address is an address where the preset address bit in the cache processing module is the same as the preset address bit in the second address information.
7. An electronic device comprising: A processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via a bus, and when the machine-readable instructions are executed by the processor, the steps of the data reading method as described in any one of claims 1 to 5 are performed.