Hardware description language code generation method, flash memory controller and integrated circuit

Abstract

The present invention discloses a hardware description language code generation method, a flash memory controller and an integrated circuit. The hardware description language code generation method comprises: based on the design parameters of the flash memory, a plurality of function modules designed for the flash memory controller, first logic relationship data and first function parameter data of each function module, editing and generating a first hardware description language code file of the flash memory controller; when it is recognized that the function of the function module has changed, obtaining second logic relationship data and second function parameter data required to meet the function change from the function parameter configuration file; according to the second logic relationship data and the second function parameter data, modifying the first hardware description language code file to regenerate the second hardware description language code file. The present invention realizes automatic design of the flash memory controller hardware description language code based on the function parameter configuration file, improves the reusability of the flash memory controller, and avoids the problems of manual coding errors and long development time.

Description

Technical Field

[0001] The present application relates to the technical field of chip digital front-end design, and in particular to a hardware description language code generation method, a flash memory controller and an integrated circuit. Background Art

[0002] With the development of the chip industry, eflash (flash memory) is also constantly updated and iterated. Because different chips need to choose whether to add ECC verification, scrambling, encryption and decryption and other functions when reading and writing data to flash memory, the original flash memory controller cannot be reused in the new chip.

[0003] The design of the flash memory controller involves multiple aspects such as function selection, interface protocol, and timing control. Therefore, the workload of redesigning the flash memory controller is huge, which not only prolongs the chip development time, but also easily leads to partial failure of chip functions due to neglect of the details of designing the flash memory controller. For example, the flash memory is usually used to store the boot code. When some functions of the flash memory controller fail, the chip will fail as a whole because it cannot be started. Summary of the invention

[0004] The purpose of the present invention is to provide a hardware description language code generation method, a flash memory controller and an integrated circuit, which can realize automatic design of a flash memory controller hardware circuit code file, improve the reusability of the flash memory controller, and avoid the problems of manual coding errors and long development time.

[0005] The technical solution provided by the present invention is as follows:

[0006] The present invention provides a method for generating hardware description language codes, comprising the following steps:

[0007] Based on the design parameters of the flash memory, the flash memory controller is designed with multiple functional modules, the first logical relationship data and the first functional parameter data of each functional module, and the first hardware description language code file of the flash memory controller is edited and generated; the functional modules include necessary functional modules and non-essential functional modules.

[0008] When it is recognized that the function of the functional module has changed, the second logical relationship data and the second functional parameter data required to meet the functional change are obtained from the functional parameter configuration file; the functional parameter configuration file is set or modified according to the functional requirements of the chip for the functional module.

[0009] The first hardware description language code file is modified according to the second logical relationship data and the second functional parameter data to regenerate the second hardware description language code file.

[0010] Specifically, through the hardware description language code generation method proposed in the present invention, on the basis of the first hardware description language code file of the original eflash controller, the functional parameter data and logical relationship data of the existing functional parameter configuration file are parsed, and the first functional parameter data and the first logical relationship data are modified into the second functional parameter data and the second logical relationship data to generate a second hardware description language code file. The logic circuit of the eflash controller is automatically generated without human intervention, which can avoid timing, connection and other errors caused by design negligence.

[0011] Furthermore, before obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file, the method includes:

[0012] Extract design parameters from the data sheet of the flash memory device and design the functional module of the flash memory controller; extract functional requirements from the document of the chip's functional requirements for the flash memory controller; write the design parameters corresponding to the functional requirements of the functional module into a type of sub-file in the functional parameter configuration file; one type of sub-file includes the logical relationship and functional parameters of the same functional module; write the design parameters corresponding to some functions that meet the functional requirements into another type of sub-file in the functional parameter configuration file; another type of sub-file includes the logical relationship and functional parameters of multiple functional modules.

[0013] Specifically, according to the design parameters of the flash memory and the functional requirements of the chip for the flash memory controller, the functional design parameters corresponding to the functional requirements are written into the functional parameter configuration file to facilitate subsequent analysis and extraction of logical relationships and functional parameters.

[0014] Further, obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file includes:

[0015] When it is identified that the function of a non-essential functional module has changed, the second logical relationship sub-data and second functional parameter sub-data of the non-essential functional module are obtained from the sub-file of the corresponding category of the functional parameter configuration file; and the second logical relationship sub-data and second functional parameter sub-data of other related functional modules are obtained.

[0016] The second logical relationship sub-data of the non-essential functional module and the second logical relationship sub-data of other related functional modules are used as the second logical relationship data; the second function parameter sub-data of the non-essential functional module and the second function parameter sub-data of other related functional modules are used as the second function parameter data.

[0017] Furthermore, obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file also includes:

[0018] When it is identified that the function of the necessary function module has changed, the second logical relationship data and the second function parameter data of the necessary function module are obtained from the sub-file of the corresponding category of the function parameter configuration file.

[0019] Furthermore, before obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file, the method further includes:

[0020] Based on the disabling functions of the non-essential functional modules or some devices in the essential functional modules defined in the first hardware design code file, the disabling functions of the non-essential functional modules or some devices in the essential functional modules are turned on or off.

[0021] Specifically, the complexity of generating a flash memory controller can be reduced by disabling the function, making the code in the code file more modular, and improving the maintainability and readability of the eflash controller hardware design code file.

[0022] Furthermore, before obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file, the method further includes:

[0023] Based on the modifications made in the function parameter configuration files, changes in the functions of the function modules are identified.

[0024] Further, modifying the first hardware description language code file according to the second logical relationship data and the second function parameter data includes:

[0025] When it is recognized that the functional requirements of a function module have changed, the top-level instance of the function module is adapted and modified, or the annotation of the function module is modified; when it is recognized that the functional requirements of a function module have changed, if the modification of the function module exceeds the preset modification range, a modification error of the function module is prompted.

[0026] Specifically, during the parsing process, the modification operations performed on each sub-file are also different. When the functional requirements of the functional modules change, the connections between the functional modules are adaptively adjusted through the top-level instances. If the functional requirements do not support the modification, the designer is notified through an alarm so that the generated hardware description language code file of the eflash controller can be intervened in time.

[0027] Furthermore, the necessary functional modules include a main state control module, a bus interface module, an interface timing control module, a register bit and read-write control module, and an FBIST control interface; the non-essential functional modules include a pre-fetch control module, a programming control module, a scrambling module, and an error correction code module.

[0028] The present invention also provides a flash memory controller, which is generated by any one of the hardware description language code generation methods described above.

[0029] The present invention further provides an integrated circuit, comprising the above-mentioned flash memory controller, the integrated circuit further comprising:

[0030] The chip and the flash memory, the chip reads and writes data to the flash memory through the embedded flash controller.

[0031] Through the hardware description language code generation method, flash memory controller and integrated circuit provided by the present invention, the functional modules of the flash memory controller are standardized and parameterized, and the hardware description language code file of the flash memory controller is automatically generated according to the functional parameter configuration file, which solves the problem that the flash memory controller needs to be rewritten due to the different requirements of different chips for the flash memory controller, thereby improving the reusability of the flash memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 is a structural diagram of an embodiment of an integrated circuit of the present invention;

[0034] Figure 2 is a structural diagram of an embodiment of a flash memory controller of the present invention;

[0035] Figure 3 is a flow chart of an embodiment of a method for generating hardware description language codes according to the present invention;

[0036] Figure 4 is a flow chart of an original design flash memory controller of the present invention;

[0037] Figure 5 is a flowchart of another embodiment of a method for generating hardware description language codes according to the present invention;

[0038] Figure 6 is a flowchart of another embodiment of a method for generating hardware description language codes according to the present invention;

[0039] Figure 7 is a flowchart of another embodiment of a method for generating hardware description language codes according to the present invention;

[0040] Figure 8is a flowchart of another embodiment of a method for generating hardware description language codes according to the present invention;

[0041] Fig. 9 The present invention is a flowchart of an embodiment of a method for generating a flash memory controller using a hardware description language code. DETAILED DESCRIPTION

[0042] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0043] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0044] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0045] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0047] In chip design, the eflash controller (flash memory controller) is directly integrated into the chip, forming a SoC (System on Chip) together with the processor core, memory and other peripherals. The design and implementation of the flash memory controller has a direct impact on the performance, security and reliability of the entire chip.

[0048] However, different chips have different requirements for flash memory controllers, mainly because they differ in design, function, performance, and application scenarios. There are several main reasons: system architecture differences. Different SoC designs may require different flash memory controllers. live controller architecture to meet specific system architecture and bus protocol requirements. live Controllers have different performance requirements for read and write speeds, data throughput, and response time. Security: Some applications may require higher levels of data protection and security features, such as encryption and secure boot, which requires flash live The controller provides corresponding safety features.

[0049] Re-align live When designing the controller, the Verilog code of the flash memory controller of the previous chip needs to be changed. The Verilog code base is large and complex in structure, involving a lot of coding and debugging work. New errors may be accidentally introduced during the modification process, increasing the instability of the flash memory controller.

[0050] Therefore, the present invention provides a method for generating hardware description language codes of a flash memory controller. live Modularize the functions of the controller, and then modify the function parameter data and logical relationship data in the function parameter configuration file to regenerate the flash live The controller's hardware description language code file improves the flash live Reusability of controllers.

[0051] Based on the method proposed in the present invention, the hardware description language code file of the flash memory controller is automatically generated to avoid errors such as timing and connection caused by manual design negligence, so that the functional division of the flash memory controller is more standardized and modularized, and the flash memory controller is not divided into different parts due to different requirements of different chips for the flash memory controller. live The controller needs to be redesigned.

[0052] The following is a description with reference to the accompanying drawings:

[0053] In one embodiment of the present invention, Figure 1 , which shows a schematic diagram of the structure of an integrated circuit provided in some embodiments of the present disclosure. The integrated circuit 100 includes: a flash memory controller 110 , a chip 120 and a flash memory 130 .

[0054] The chip 120 and the flash memory 130 , the chip 120 reads and writes data to the flash memory 130 through the flash memory controller 110 .

[0055] Specifically, the flash memory 130 is a non-volatile memory integrated inside the chip 120 for storing data. Different from an external flash memory, the flash memory 130 is directly embedded in a system on chip (SOC) or other integrated circuits.

[0056] Through the integrated circuit proposed in the present invention, the flash controller 110 and the flash memory 130 are integrated on the chip 120, which can speed up the startup process of the chip 120, improve the stability and reliability of the chip system, and also provide flexibility and optimization space for the design of the chip system.

[0057] In one embodiment of the present invention, Figure 2 Shown is a flash controller 110 .

[0058] Specifically, the flash controller 110 is a hardware component specially designed to manage the flash memory 130. It is responsible for controlling the read and write operations, data management, error correction and other tasks of the flash memory 130. The design of the flash controller 110 needs to be based on the technical specifications such as the operation interface, timing requirements, and function description specified in the eflashIP data manual.

[0059] The flash memory controller 110 includes a pre-fetch control 111 , a programming control 112 , a scrambling code 113 , an ECC 114 , a master state control 115 , a bus interface 116 , an interface timing control 117 , a register bit and read / write control 118 , and an FBIST control interface 119 .

[0060] The flash controller 110 receives read / write requests and control commands through the bus interface 116, and sets the operating parameters and behaviors of the flash controller 110 based on the register bits and the read / write control 118. When writing data, the data can be continuously written through the programming control 112; when reading data, the data can be loaded into the pre-fetch buffer in advance through the pre-fetch control 111.

[0061] The main state control 115 controls the behavior of the flash memory controller 110 according to the current operation and state. The main state control 115 includes initialization control, power-on verification control, read-write protection control, state machine control, physical address mapping and other internal parameters.

[0062] Scrambling code 113 and ECC114 (error correction code) are usually used to improve the reliability of data storage. When writing data, error correction code verification is performed to ensure the accuracy of the data. When reading data, scrambling code 113 performs scrambling and descrambling operations, and cooperates with the error correction code algorithm to detect and correct possible errors. ECC114 can detect and correct common data corruption problems, such as single-bit errors, and detect uncorrectable double-bit errors.

[0063] The interface timing control 117 converts various operation events into accurate timing signals to ensure that data can be correctly and reliably transmitted between the flash memory controller 110 and the flash memory 130 .

[0064] The FBIST control interface 119 allows triggering of a self-test process to check if the hardware components are functioning properly and provides test results after the self-test is completed, including a pass or fail status and possible error codes or fault information.

[0065] The flash memory controller 110 includes non-essential functional modules and essential functional modules. The non-essential functional modules include pre-fetch control 111, programming control 112, scrambling 113, and ECC 114; the essential functional modules include master state control 115, bus interface 116, interface timing control 117, register bit and read / write control 118, and FBIST control interface 119.

[0066] Among the non-essential modules and necessary modules that make up the flash controller 110, the non-essential functional modules can directly choose whether to add them as a whole according to the functional requirements of the chip 120 for the flash controller 110. For example, the removal of the programming control 112 of the non-essential functional module will not affect the use of other functional modules. However, the necessary functional modules generally cannot be removed, and some devices of some necessary functional modules can be disabled. For example, the register bits and read-write control 118 of the necessary functional module cannot be completely removed, and the registers in the module can only be reduced, because the register bits and read-write control 118 are used to configure functions such as the programming control module.

[0067] The flash memory controller 110 proposed in the present invention can realize the storage, management, protection, optimization and access of data in the chip system based on the flash memory 130 and the flash memory controller 110.

[0068] In one embodiment of the present invention, Figure 3 As shown, it shows a flow chart of a method for generating a hardware description language code provided in some embodiments of the present disclosure, and the generated hardware description language code file can form a new embedded flash memory controller 110. The following steps are included:

[0069] S100 edits and generates a first hardware description language code file of the flash memory controller based on the design parameters of the flash memory and the first logical relationship data and first functional parameter data of each functional module designed for the flash memory controller; the functional modules include necessary functional modules and non-essential functional modules.

[0070] S200 When it is recognized that the function of the functional module has changed, the second logical relationship data and the second functional parameter data required to meet the function change are obtained from the functional parameter configuration file; the functional parameter configuration file is set or modified according to the functional requirements of the chip for the functional module.

[0071] S300 modifies the first hardware description language code file according to the second logical relationship data and the second function parameter data to regenerate the second hardware description language code file.

[0072] Specifically, the design of a flash memory controller is a highly customized process that requires the selection and implementation of corresponding functional modules based on the specific flash memory type, application requirements, and design constraints. When designing a flash memory controller based on the design parameters of the flash memory, it involves the construction of multiple functional modules, which can be divided into necessary functional modules and non-essential functional modules. Necessary functional modules are required to ensure the basic operation of the flash memory controller, such as master status control, interface timing control, and bus interface; non-essential functional modules provide additional functions or optimizations, such as error correction code (ECC), data encryption, prefetch control, etc., which can be selectively implemented according to specific application requirements.

[0073] In the process of designing the first hardware description language code file, the first logic relationship data and the first function parameter data need to be extracted based on each functional module. The first logic relationship data defines the interaction mode between modules, including the flow direction of signals, control logic, etc.; the first function parameter data includes specific parameters of module operation, such as timing parameters, thresholds, configuration options, etc. Using these design parameters, the first hardware description language code file (i.e., Verilog design code) of the flash memory controller can be edited and generated. Among them, Verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form. Therefore, the first hardware description language code file can be regarded as the circuit diagram of the flash memory controller.

[0074] When the function of a functional module of the flash controller changes, the necessary second logical relationship data and second functional parameter data are obtained from a predefined functional parameter configuration file. The functional parameter configuration file contains a detailed description of all parameters and logical relationships required for different functional modules in different operating environments. It is set or modified according to the specific functional requirements of the chip for the functional module, and may involve multiple aspects such as performance optimization and security enhancement.

[0075] The second logic relationship data and the second function parameter data are modification directions for generating the second hardware description language code file. These data are applied to the first hardware description language code file to modify timing parameters, threshold settings, configuration registers, etc. According to the new function parameter data and logic relationship data, the logic structure and function in the first hardware description language code file are adjusted or redesigned to realize the generation of the second hardware description language code file of the required flash memory controller.

[0076] like Figure 4As shown, the design of the original flash memory controller is to manually intervene in the original Verilog code file to modify the circuit of the embedded flash memory controller. Compared with the design process proposed by the present invention, new errors may be accidentally introduced during the modification process, increasing the instability of the system.

[0077] The non-essential functional modules involved in the above step S100 include pre-fetch control module, programming control module, scrambling module, and error correction code module; the necessary functional modules include main state control module, bus interface module, interface timing control module, register bit and read-write control module, and FBIST control interface.

[0078] Non-essential function modules are only related to their own functions. When a non-essential function module is removed alone, it does not affect the use of other function modules. When a non-essential function module is added, only the parameters inside this non-essential function module need to be instantiated. There is a certain correlation between the necessary function modules. Removing them will affect other function modules and cannot be an independent unit module.

[0079] By using the hardware description language code generation method proposed in the present invention, the logical relationship data and functional parameter data of the flash memory controller are modified, the design of the flash memory controller can be modularized and converted into a specific description implemented on hardware. The logical circuit diagram of the embedded flash memory controller is automatically generated without human intervention, which can avoid timing, connection and other errors caused by design negligence.

[0080] In one embodiment of the present invention, before modifying the function parameter configuration file of the flash memory controller, such as Figure 5 As shown, the above step S200 may include:

[0081] S210 extracts design parameters from a data sheet of the flash memory and designs a functional module of the flash memory controller.

[0082] S220 extracts the functional requirements from the document of the chip's functional requirements for the flash memory controller.

[0083] S230 writes the design parameters corresponding to the functional module satisfying the functional requirements into a type of sub-file in the functional parameter configuration file; the type of sub-file includes the logical relationship and functional parameters of the same functional module.

[0084] S240 writes the design parameters corresponding to the partial functions that meet the functional requirements into another type of sub-file in the functional parameter configuration file; the other type of sub-file includes the logical relationship and functional parameters of multiple functional modules.

[0085] Specifically, an eflash IP (Embedded Flash Intellectual Property) data sheet is usually a detailed technical document that provides information about the specifications, functions, and usage of the flash memory IP core. It provides all the necessary information required to integrate and use the eflash IP in the system.

[0086] The functional requirements of the flash memory controller are usually proposed by architecture engineers. Different application scenarios may require different flash memory controller solutions. The functional requirements of the flash memory controller need to be defined based on the design goals and performance requirements of the entire chip.

[0087] The design parameters in the IP data sheet of the flash memory are combined with the functional requirements, and the information that needs to be modified is modified in the functional parameter configuration file. Among them, the functional parameter configuration file includes multiple files, which store different categories of functions of the flash memory controller, and different categories of functions correspond to different logical relationships (connection relationships).

[0088] When the functional requirements change, the functional parameter configuration file also needs to be modified accordingly. The functional parameter configuration file has multiple configuration sub-files.

[0089] One type of subfile in the function parameter configuration file only includes the logical relationship and function parameters of the same function module, such as eflash IP option subfile, eflash IP interface change subfile, eflash IP timing parameter subfile, initialization phase definition subfile, register definition subfile, etc. For example, the eflash IP option subfile includes IP programming bit width, IP data write bit width, read bit width, etc.

[0090] Another type of subfile includes the logical relationship and function parameters of multiple functional modules, such as the controller function option subfile, mode overview subfile, Read subfile, etc. For example, the controller function option subfile includes multiple functional modules such as scrambling, ECC, AHB bus programming bit width support, continuous programming support, and single programming data.

[0091] Through the hardware description language code generation method proposed in the present invention, the corresponding functional design parameters are written into the functional parameter configuration file according to the functional requirements of the chip for the embedded flash memory controller, which facilitates the analysis and extraction of the second functional parameter data and the second logical relationship data.

[0092] After completing the modification of the function parameter configuration file, such as Figure 6 As shown, the above step S240 also includes:

[0093] S241 identifies changes in the functions of the functional modules based on the modifications in the functional parameter configuration files.

[0094] S242: based on the disabling functions of the non-essential functional modules or some components in the essential functional modules defined in the first hardware description language code file, turning on or off the disabling functions of the non-essential functional modules or some components in the essential functional modules.

[0095] Specifically, when the functional parameters in the functional parameter configuration file are adjusted, these changes may directly affect the behavior or performance of the functional module, thereby causing the overall function of the functional module to change. Such a mechanism not only improves the reusability of the flash memory controller, but also helps to quickly respond to functional changes and ensure the stability and reliability of the software system.

[0096] The first hardware description language code file not only defines necessary functional modules to ensure that the core functions of the flash memory controller are realized, but may also include some non-essential functional modules to provide customized requirements.

[0097] In some cases, in order to optimize the performance of the flash controller, reduce complexity, or adapt to specific application requirements, it may be necessary to disable or enable non-essential functional modules in the flash controller or certain devices in the essential functional modules. By setting specific switch conditions or configuration options, these functional modules can be flexibly turned on or off. This flexible control mechanism not only helps to improve the adaptability and scalability of the flash controller, but also enables more sophisticated resource management and performance optimization in different application scenarios. For example, when disabling the error correction module in the non-essential functional module, it will not affect the use of other modules such as the main control status module and the bus interface module.

[0098] The disabling function can reduce the overall complexity of the system, make the circuit described in the hardware description language code file more modular, and improve the maintainability and readability of the flash memory controller hardware design code.

[0099] In one embodiment of the present invention, when obtaining the second logical relationship data and the second functional parameter data from the functional parameter configuration file, two situations can be identified. The situation where a non-essential functional module is identified is now described. Figure 7 As shown, the above step S200 also includes:

[0100] S250 When it is identified that the function of a non-essential functional module has changed, the second logical relationship sub-data and second functional parameter sub-data of the non-essential functional module are obtained from the sub-file of the corresponding category of the functional parameter configuration file; and the second logical relationship sub-data and second functional parameter sub-data of other related functional modules are obtained.

[0101] S260 takes the second logical relationship sub-data of the non-essential functional module and the second logical relationship sub-data of other related functional modules as the second logical relationship data; takes the second function parameter sub-data of the non-essential functional module and the second function parameter sub-data of other related functional modules as the second function parameter data.

[0102] Specifically, when a non-essential functional module of a flash memory controller changes, the function parameter configuration sub-files of the corresponding category are first involved. These sub-files include the logical relationship and parameter data within the non-essential functional module. Secondly, in order to ensure the overall performance and stability of the flash memory controller, the logical relationship and parameter data of other related functional modules are also obtained from the sub-files of the same category, and the possible impact of changes in non-essential functional modules on the entire flash memory controller (including potential dependencies, conflicts, etc.) is fully considered.

[0103] The situation where a necessary function module is identified is now explained. The above step S200 also includes: when it is identified that the function of the necessary function module has changed, obtaining the second logical relationship data and the second function parameter data of the necessary function module from the sub-file of the corresponding category of the function parameter configuration file.

[0104] Specifically, when a change in the function of a necessary function module is identified, it usually means a potential impact on the core operation or key performance of the flash controller. The second logical relationship data describes in detail the logical structure and interdependencies within the necessary function module, while the second functional parameter data includes specific parameter settings of the necessary function module, which directly affect the behavior and performance of the module.

[0105] In this way, the interactions and impacts between non-essential functional modules and essential functional modules can be fully understood and evaluated, so that more precise and effective adjustments can be made, improving the overall coordination and scalability of the flash memory controller.

[0106] In one embodiment of the present invention, in the process of generating the second hardware description language code file by combining the first hardware description language code file, as follows Figure 8 As shown, the above step S300 may include:

[0107] S310: When it is identified that the functional requirement of a functional module has changed, the top-level instance of the functional module is modified or the annotation of the functional module is modified.

[0108] S320: When it is identified that the functional requirement of the functional module has changed and the modification of the functional module exceeds the preset modification range, a modification error of the functional module is prompted.

[0109] Specifically, after reading the sub-files of different categories in the function parameter configuration file in sequence and modifying the first function parameter data in the first hardware description language code file to the second function parameter data, it is also necessary to adapt and modify the top-level instance for the function module, and make special comments on the modified parts to facilitate the manual modification of the hardware description language code file of the flash memory controller later. Among them, the top-level instance is the modification of the connection between the function modules and the adjustment of the internal logic.

[0110] During the parsing of the function parameter configuration file, if it is found that the second function parameter data or the second logical relationship data exceeds the preset modification range and does not support modification, the designer is reminded through an error message to promptly intervene in the generated hardware description language code file (logic circuit) of the flash memory controller to avoid the designed flash memory controller being unusable.

[0111] like Fig. 9 As shown, after modifying multiple sub-files of the function parameter configuration file, a hardware logic circuit of a flash memory controller is generated according to the relevant second function parameter data and the second logic relationship data. For example, when there are sub-files such as register definition and eflash IP interface change in the function parameter configuration file, the register definition sub-file can parse out the function design parameters such as register name, address, bit width, function, and attribute, and the register bit and read-write control module can be modified according to the parsed second function parameter, and the top-level instance can be modified at the same time; the eflash IP interface change sub-file can parse out the key interface name, replace the corresponding interface name in the first hardware description language code file according to the change of the interface name, and make special comments on the interface with function change for subsequent manual processing; for the read enable signal, low effective and rising edge effective can be supported in advance.

[0112] Through the hardware description language code generation method proposed in the present invention, after modifying the functional parameter data and the logical relationship data, corresponding adaptive support is made for the changed parts, and a logic circuit of a flash memory controller can be directly generated according to the relevant parameters and logical relationships.

[0113] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0115] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A method for generating hardware description language code, applied to a flash memory controller, characterized in that: The following steps are involved: Based on the design parameters of the flash memory, the first logic relationship data and the first function parameter data of each function module designed for the flash memory controller are edited to generate a first hardware description language code file of the flash memory controller; the function modules include necessary function modules and non-essential function modules; the first logic relationship data defines the interaction mode between modules, including the flow direction of signals and control logic; the first function parameter data includes the timing parameters, thresholds, and configuration options of module operations; When it is recognized that the function of the functional module has changed, the second logical relationship data and the second functional parameter data required to meet the functional change are obtained from the functional parameter configuration file; the functional parameter configuration file is set or modified according to the functional requirements of the functional module by the chip, and the functional parameter configuration file includes the functional parameters and logical relationships required by different functional modules in different operating environments; The first hardware description language code file is modified according to the second logical relationship data and the second functional parameter data to regenerate a second hardware description language code file.

2. The method for generating hardware description language code according to claim 1, characterized in that: Before obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file, the method includes: Extract design parameters from the data sheet of the flash memory and design the functional modules of the flash memory controller; Extracting the functional requirement from a document of the functional requirement of the chip to the flash controller; Writing the design parameters corresponding to the functional module satisfying the functional requirements into a sub-file in the functional parameter configuration file; the sub-file includes the logical relationship and functional parameters of the same functional module; The design parameters corresponding to the partial functions that meet the functional requirements are written into another type of sub-file in the functional parameter configuration file; the another type of sub-file includes the logical relationship and functional parameters of multiple functional modules.

3. The method for generating hardware description language code according to claim 1, characterized in that: The obtaining of the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file includes: When it is identified that the function of the non-essential functional module has changed, obtaining the second logical relationship sub-data and the second functional parameter sub-data of the non-essential functional module from the sub-file of the corresponding category of the functional parameter configuration file; and obtaining the second logical relationship sub-data and the second functional parameter sub-data of other related functional modules; The second logical relationship sub-data of the non-essential functional module and the second logical relationship sub-data of other related functional modules are used as the second logical relationship data; the second function parameter sub-data of the non-essential functional module and the second function parameter sub-data of other related functional modules are used as the second function parameter data.

4. The method for generating hardware description language codes according to claim 1, characterized in that: The method of obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file further includes: When it is recognized that the function of the necessary function module has changed, the second logical relationship data and the second function parameter data of the necessary function module are obtained from the sub-file of the corresponding category of the function parameter configuration file.

5. The method for generating hardware description language codes according to claim 1, wherein: Before obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file, the method further includes: Based on the disabling functions of some components in the non-essential functional modules or the essential functional modules defined in the first hardware description language code file, the disabling functions of some components in the non-essential functional modules or the essential functional modules are turned on or off.

6. The method for generating hardware description language codes according to claim 1, characterized in that: Before obtaining the second logical relationship data and the second functional parameter data required to satisfy the function change from the functional parameter configuration file, the method further includes: Based on the modification in the function parameter configuration file, it is identified that the function of the function module has changed.

7. The method for generating hardware description language codes according to claim 1, characterized in that: The step of modifying the first hardware description language code file according to the second logical relationship data and the second function parameter data includes: When it is identified that the functional requirements of the functional module have changed, adapt and modify the top-level instance of the functional module, or modify the annotation of the functional module; When it is identified that the functional requirement of the functional module has changed and the modification of the functional module exceeds a preset modification range, a modification error of the functional module is prompted.

8. The method for generating hardware description language code according to any one of claims 1 to 7, characterized in that: The necessary function modules include a main state control module, a bus interface module, an interface timing control module, a register bit and read-write control module, and an FBIST control interface; the non-essential function modules include a pre-fetch control module, a programming control module, a scrambling module, and an error correction code module.

9. A flash memory controller, characterized in that: The flash memory controller is generated according to the hardware description language code generation method according to any one of claims 1-8.

10. An integrated circuit, characterized in that: include: The flash memory controller of claim 9, wherein the integrated circuit further comprises: A chip and a flash memory, wherein the chip reads and writes data to the flash memory through the flash memory controller.

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