A method, apparatus, electronic device, and storage medium for acquiring register information.

Abstract

This application discloses a method, apparatus, electronic device, and storage medium for acquiring register information. The register information acquisition method is applied to a hardware device, which includes a processor and an IC chip. The method includes: the IC chip acquiring a processor fault detection signal; if it is determined based on the processor fault detection signal that a fault information acquisition condition is met, then acquiring the processor's register information, which includes fault-related information of the processor; and storing the processor's register information in a preset non-volatile storage area. Thus, the acquisition and recording of the processor's register information is achieved without increasing hardware costs.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method, apparatus, electronic device and storage medium for acquiring register information. Background Technology

[0002] Processor registers, such as the CPU (Central Processing Unit) core registers, are internal storage areas used by the CPU to store data. They can be used to temporarily store data involved in calculations, calculation results, and CPU operating information. For example, the CSR (Configuration and Status Register) and MSR (Model Specific Registers) are CPU core registers. The MSR is used to control CPU operation, enable / disable functions, debug, trace program execution, and monitor CPU performance. Internally, the MSR can be read and written using the RDMSR (read) and WRMSR (write) instructions. The MSR can monitor the CPU's status. The CSR is used to configure and record some CPU operating status information. The CSR can store CPU configuration information and I / O (Input / Output) interface status information.

[0003] When a CPU malfunctions, especially a malfunction that is difficult to reset, the fault-related information is recorded in CPU core registers such as MSR and CSR. Externally, an SMBus (System Management Bus) interface can be provided for external devices to obtain CPU core register information.

[0004] In related technologies, CPU core register information is mainly obtained through the following three methods:

[0005] The first method involves deploying dedicated software on the CPU to access and record CPU core register information. This method obtains CPU core register information through CPU instructions without increasing hardware costs. However, when the CPU experiences a catastrophic failure that causes it to hang, the dedicated software will be unusable, making it impossible to obtain the fault information stored in the CPU core registers.

[0006] The second approach is to deploy a BMC (Baseboard Manager Controller) system on the network device or server to which the CPU belongs. When the CPU fails and hangs, the BMC system can obtain the CPU core register information through the SMBus interface as soon as possible, providing a basis for analyzing the cause of the CPU failure. However, the deployment of the BMC system requires advance design and planning, which will increase hardware costs and deployment difficulty.

[0007] The third method involves connecting one end of a dedicated SMBus adapter to the CPU via the SMBus bus and the other end to a fault analysis device via a USB interface. Dedicated fault analysis software is then run on the fault analysis device to obtain CPU core register information and perform fault analysis. However, this method requires maintaining the fault scene during use, and can only be used after maintenance personnel have installed the dedicated SMBus adapter and software. It is more suitable for obtaining and recording CPU core register information in test scenarios, but not for use in actual business scenarios. Furthermore, the need for a dedicated SMBus adapter increases hardware costs.

[0008] Therefore, how to acquire and record CPU core register information without increasing hardware costs has become one of the urgent technical problems to be solved in the existing technology. Summary of the Invention

[0009] To address the problems in the background art, this application provides a method, apparatus, electronic device, and storage medium for acquiring register information, which achieves the acquisition and recording of CPU core register information without increasing hardware costs.

[0010] In a first aspect, embodiments of this application provide a register information acquisition method, applied to a hardware device, the hardware device including a processor and an integrated circuit (IC) chip, the method comprising:

[0011] The IC chip acquires processor fault detection signals;

[0012] If the fault information acquisition conditions are met based on the processor fault detection signal, then the processor's register information is acquired, and the processor's register information contains fault-related information of the processor.

[0013] The processor's register information is stored in a preset non-volatile memory area.

[0014] In one possible implementation, the processor fault detection signal includes a processor fault signal and a platform reset signal;

[0015] The step of determining whether the fault information acquisition conditions are met based on the processor fault detection signal specifically includes:

[0016] If the processor fault signal is determined to be low and the platform reset signal is high, then the fault information acquisition conditions are met.

[0017] In one possible implementation, the processor fault detection signal includes a system reset signal;

[0018] The step of determining whether the fault information acquisition conditions are met based on the processor fault detection signal specifically includes:

[0019] If the system reset signal is determined to be low, then the fault information acquisition condition is determined to be met.

[0020] In one possible implementation, when the IC chip is a complex programmable logic device (CPLD), the preset non-volatile memory area includes the CPLD's user flash memory (UFM); or,

[0021] When the IC chip is a Field Programmable Gate Array (FPGA), the preset non-volatile memory area includes an Electrically Erasable Programmable Read-Only Memory (EEPROM); or,

[0022] When the IC chip is a microcontroller unit (MCU) device, the preset non-volatile storage area includes an electrically erasable programmable read-only memory (EEPROM).

[0023] In one possible implementation, when the system reset signal is determined to be low, the method further includes:

[0024] If it is determined that the current operating state of the processor meets the reset conditions, then the processor is reset;

[0025] If it is determined that the current operating state of the processor does not meet the reset conditions, the processor is reset after obtaining the processor's register information.

[0026] In one possible implementation, determining that the current operating state of the processor satisfies the reset condition specifically includes:

[0027] If the processor is currently running in a state where the BIOS is not started, then the processor is determined to meet the reset conditions.

[0028] In one possible implementation, the registers of the IC chip contain hardware information of the hardware device;

[0029] The step of storing the processor's register information into a preset non-volatile memory area specifically includes:

[0030] The acquired register information of the processor is cached in the random access memory (RAM) of the IC chip; and

[0031] After the processor's register information has been acquired, the processor's register information and the hardware information are stored in the preset non-volatile storage area.

[0032] In one possible implementation, the register of the IC chip further includes data write flag information and data read flag information for the preset non-volatile memory area;

[0033] The method further includes:

[0034] The system receives updated data read flag information sent by an external device. The updated data read flag information indicates that the processor's register information has been read. The updated data read flag information is sent by the external device after reading the processor's register information and the hardware information contained in the preset non-volatile memory area when the data write flag information in the IC chip's register indicates that the preset non-volatile memory area has been written to the processor's register information and the data read flag information indicates that the processor's register information has not been read.

[0035] In one possible implementation, the method further includes:

[0036] After determining that the hardware device or the IC chip has restarted, the processor's register information and hardware information stored in the preset non-volatile memory area are retrieved; and

[0037] The processor's register information and hardware information are sent to the IC chip's RAM for caching, so that the external device can read them.

[0038] Secondly, embodiments of this application provide a register information acquisition device, applied to a hardware device, the hardware device including a processor and an integrated circuit (IC) chip, the device comprising:

[0039] The first acquisition unit is used to acquire processor fault detection signals;

[0040] The second acquisition unit is used to acquire the processor's register information if it is determined based on the processor fault detection signal that the fault information acquisition conditions are met. The processor's register information includes fault-related information of the processor.

[0041] A storage unit is used to store the processor's register information into a preset non-volatile storage area.

[0042] In one possible implementation, the processor fault detection signal includes a processor fault signal and a platform reset signal;

[0043] The second acquisition unit is specifically used to determine that the fault information acquisition conditions are met if the processor fault signal is low and the platform reset signal is high.

[0044] In one possible implementation, the processor fault detection signal includes a system reset signal;

[0045] The second acquisition unit is specifically used to determine that the fault information acquisition condition is met if the system reset signal is determined to be low.

[0046] In one possible implementation, when the IC chip is a complex programmable logic device (CPLD), the preset non-volatile memory area includes the CPLD's user flash memory (UFM); or,

[0047] When the IC chip is a Field Programmable Gate Array (FPGA), the preset non-volatile memory area includes an Electrically Erasable Programmable Read-Only Memory (EEPROM); or,

[0048] When the IC chip is a microcontroller unit (MCU) device, the preset non-volatile storage area includes an electrically erasable programmable read-only memory (EEPROM).

[0049] In one possible implementation, when the system reset signal is determined to be low, the device further includes:

[0050] The reset unit is configured to reset the processor if it is determined that the current operating state of the processor meets the reset conditions; and to reset the processor after obtaining the register information of the processor if it is determined that the current operating state of the processor does not meet the reset conditions.

[0051] In one possible implementation, the reset unit is specifically configured to determine that the current operating state of the processor meets the reset conditions if the current operating state of the processor is that the BIOS is in an unbooted state.

[0052] In one possible implementation, the registers of the IC chip contain hardware information of the hardware device;

[0053] The storage unit is specifically used to cache the acquired register information of the processor in the random access memory (RAM) of the IC chip; and after the register information of the processor is acquired, to store the register information of the processor and the hardware information in the preset non-volatile storage area.

[0054] In one possible implementation, the register of the IC chip further includes data write flag information and data read flag information for the preset non-volatile memory area;

[0055] The device further includes:

[0056] A receiving unit is configured to receive updated data read flag information sent by an external device. The updated data read flag information indicates that the processor's register information has been read. The updated data read flag information is sent by the external device after reading the processor's register information and the hardware information contained in the preset non-volatile memory area when the data write flag information in the IC chip's register indicates that the preset non-volatile memory area has been written to the processor's register information and the data read flag information indicates that the processor's register information has not been read.

[0057] In one possible implementation, the device further includes:

[0058] The extraction unit is used to extract the processor's register information and hardware information stored in the preset non-volatile memory area after determining that the hardware device or the IC chip has restarted.

[0059] The transmitting unit is used to send the processor's register information and the hardware information to the RAM of the IC chip for caching, so that the external device can read them.

[0060] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the register information acquisition method described in this application.

[0061] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps in the register information acquisition method described in this application.

[0062] The beneficial effects of this application are as follows:

[0063] The register information acquisition method, apparatus, electronic device, and storage medium provided in this application are applied to hardware devices, including processors and integrated circuits (ICs). In this application, an IC chip (integrated circuit) acquires a processor fault detection signal. If the fault information acquisition condition is met based on the processor fault detection signal, the IC chip acquires the processor's register information, which includes processor fault-related information. The IC chip then stores the acquired processor register information in a preset non-volatile memory area. Compared to existing technologies, this application uses an IC chip in a hardware device to determine whether the processor is in a fault state based on the acquired processor fault detection signal. If the fault information acquisition condition is met, the IC chip automatically acquires and stores the processor fault-related information in the processor's register information. Since the determination of the processor fault state and the acquisition and storage of the processor's register information are both implemented by the IC chip within the hardware device itself, no additional hardware cost is required. Furthermore, when the processor malfunctions, the IC chip can still operate normally to acquire and store the processor's register information. The IC chip stores the acquired processor register information in a non-volatile memory area, ensuring that the processor's register information is not lost even when the hardware device is powered off. Therefore, successful acquisition and recording of the processor's register information is achieved without increasing hardware costs.

[0064] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0065] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0066] Figure 1 This is a schematic diagram illustrating an application scenario of the register information acquisition method provided in the embodiments of this application;

[0067] Figure 2 A schematic diagram illustrating the implementation flow of the register information acquisition method provided in this application embodiment;

[0068] Figure 3 A schematic diagram illustrating the implementation process of storing processor register information into a preset non-volatile memory area in the IC chip provided in this application embodiment;

[0069] Figure 4A schematic diagram illustrating the external fault handling process provided in this application embodiment;

[0070] Figure 5 A schematic diagram illustrating the implementation process of an external device reading processor register information from an IC chip, as provided in this application embodiment;

[0071] Figure 6 This is a diagram illustrating the implementation of the calling method for the non-volatile memory region of an IC chip provided in an embodiment of this application.

[0072] Figure 7 This application provides a diagram illustrating the storage of CPU core register information and the reading of CPU core register information by an external device.

[0073] Figure 8 A schematic diagram illustrating the implementation process of an external device actively reading fault scene information from the RAM of an IC chip, as provided in this application embodiment;

[0074] Figure 9 This is a schematic diagram of the register information acquisition device provided in the embodiments of this application;

[0075] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0076] To address the problems in the background art, embodiments of this application provide a register information acquisition method, apparatus, electronic device, and storage medium, which achieves the acquisition and recording of CPU core register information without increasing hardware costs.

[0077] It should be noted that "multiple or several" in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0078] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein.

[0079] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0080] First refer to Figure 1This is a schematic diagram illustrating an application scenario of the register information acquisition method provided in this application embodiment. It may include a hardware device 101 and an external device 102. The hardware device 101 may include, but is not limited to, any device containing a processor, such as a network device, server, or terminal device. The network device may include a switch, and the processor may be, but is not limited to, a CPU. This application embodiment does not limit this. The external device 102 may include, but is not limited to, a BMC, a main control management board, an FPGA (Field Programmable Gate Array), a server, or a terminal device. This application embodiment does not limit this. The hardware device 101 includes a processor 1011 and an IC chip 1012. The IC chip 1012 may be, but is not limited to, a logic device, an MCU (Microcontroller Unit), or a single-chip microcomputer or other host computer. This application embodiment does not limit this. Taking a switch as an example, the processor 101 and IC chip 1012 can be mounted on a processor card, and the CPU card can be mounted on a line card of the switch. Taking a CPU as an example, the processor card is equivalent to a CPU card. IC chip 1012 includes register 1012-1, RAM (Random Access Memory) 1012-2 and non-volatile storage area 1012-3. Register 1012-1 of IC chip 1012 can be used to record hardware information of the hardware device 101 to which IC chip belongs, such as power status information, voltage status information, interrupt signals and fault signals output by each main chip on the hardware device. If IC chip 1012 uses a CPLD (Complex Programmable Logic Device) in logic devices, then the CPLD's register, namely CPLD_Reg (i.e., the CPLD on-chip register), can be used to record hardware information of the hardware device to which the CPLD belongs. The CPLD's RAM can use dual-port RAM (DPRAM) or single-port RAM. This application embodiment does not limit this. This application embodiment only uses dual-port RAM as an example for illustration. The non-volatile storage area of ​​the CPLD is the user-defined and writable Flash (UFM) on the CPLD. UFM is a non-volatile memory, and the data will not be lost after power failure. Using non-volatile memory to store CPU core register information can ensure that the CPU core register information is not lost after power failure.If IC chip 1012 uses an FPGA (Field Programmable Gate Array) logic device, which includes FPGA registers and RAM, then the non-volatile storage area can use EEPROM (Electrically Erasable Programmable Read-Only Memory), a type of memory chip that does not lose data after power failure, is plug-and-play, convenient, and low-cost. The non-volatile storage area can also use EMMC (Embedded Multi Media Card), a type of flash memory card. If IC chip 1012 uses an MCU device, which includes registers and RAM, then the non-volatile storage area can use EEPROM or EMMC. Other non-volatile memory can also be used for the non-volatile storage area; this application embodiment does not limit this. The processor 1011 and the IC chip 1012 can be connected via a first preset bus (BUS1) and a second preset bus (BUS2). The IC chip 1012 and the external device 102 can be connected via a third preset bus (BUS3). BUS1 is the communication path for the IC chip 1012 to obtain register information from the processor. BUS2 is the communication path for the processor 1011 to access the non-volatile memory area 1012-3. BUS3 is a reserved communication channel for the IC chip 1012 to the outside world. The external device 102 can obtain register information from the IC chip 1012 via BUS3. In implementation, the first, second, and third preset buses can be the same or different buses, and can be configured according to requirements. For example, but not limited to, I2C (Inter-Integrated Circuit), LPC (Low Pin Count, a 33MHz 4-bit parallel bus protocol based on Intel standards), SPI (Serial Peripheral Interface), and PECI (Platform Environment Control) buses can be used. The embodiments of this application do not limit the types of interfaces (platform environment control interface) buses. In this application, the processor 1011 is only described as a CPU. The register information of the processor obtained by the IC chip 1012 from the processor 1011 side is the CPU core register information. The CPU core register information includes, but is not limited to, the information recorded in the MSR and the information recorded in the CSR. The embodiments of this application do not limit the types of information.

[0081] Based on the above application scenarios, the following will refer to the appendix. Figures 2-8 The exemplary embodiments of this application are described in more detail below. It should be noted that the above application scenarios are shown only to facilitate understanding of the spirit and principles of this application, and the implementation methods of this application are not limited in any way. On the contrary, the implementation methods of this application can be applied to any applicable scenario.

[0082] like Figure 2 The diagram shown is a schematic representation of the implementation flow of the register information acquisition method provided in this application embodiment. The register information acquisition method can be applied to... Figure 1 The hardware device 101 shown herein, the method for obtaining register information may include the following steps:

[0083] S21, the IC chip acquires the processor fault detection signal.

[0084] In practical implementation, this application only uses the CPU as an example for illustration. During CPU operation, the CPU core register MSR is used to control CPU operation, function switches, debugging, program execution tracing, and CPU performance detection. The MSR records the CPU's operating status, while the CPU core register CSR is used to configure and record some CPU operating states, storing CPU configuration information and I / O interface status information. When a CPU malfunctions, such as a CPU failure caused by factors like temperature, cache memory, or the PECI bus (a high-speed serial computer expansion bus standard) (e.g., CPU hang), the MSR and CSR record CPU fault-related information, i.e., record fault scene information, such as the status of various CPU signals.

[0085] In practice, processor fault detection signals include processor fault signals, platform reset signals, and may also include system reset signals.

[0086] Specifically, the CPU can actively send CPU fault detection signals (i.e., processor fault detection signals) to the IC chip, including: CPU fault signals and platform reset signals. The CPU can send CPU fault signals to pins connected to the IC chip through its CATERR pin. For example, when the IC chip uses a CPLD, the CPU fault signal is CATERR_N_CPLD. The platform reset signal PLTRST_N can be used as a flag bit for CPU operation. When the platform reset signal PLTRST_N is high, the CPU is running normally. At this time, the BIOS (Basic Input Output System) of the hardware device is running normally. PLTRST_N can also be used as a signal to reset external components. When other chips, modules, or other external components controlled by the CPU in the hardware device need to be reset, the CPU can set the platform reset signal PLTRST_N low (i.e., pull the platform reset signal PLTRST_N low) to reset the external components controlled by the CPU to their initial state. The external components controlled by the CPU may include MAC (Medium Access Control) chips, PHY (Physical Layer) chips, gating devices, etc. When both the CPU fault signal CATERR_N_CPLD and the platform reset signal PLTRST_N are high, the CPU is running normally. When the CPU fault signal CATERR_N_CPLD is low and the platform reset signal PLTRST_N is high, it indicates that the CPU has failed. This is because a serious CPU failure may not necessarily pull the CPU fault signal CATERR_N_CPLD low. However, if the CPU pulls the CPU fault signal CATERR_N_CPLD low while it is running (i.e., the platform reset signal PLTRST_N is high), it indicates that the CPU has failed seriously.

[0087] In another implementation, when the CPU malfunctions, such as when the CPU fails to control external components, an external reset source can send a CPU fault detection signal (i.e., a processor fault detection signal) to the IC chip to reset the CPU. The CPU fault detection signal sent by the external reset source includes the system reset signal: SYS_RST_N. The external reset source can be of various types. For example, if an external timer (watchdog) fails to reset after a timeout, the reset pin will be pulled low. In this case, the external timer will set the system reset signal SYS_RST_N to a low level and send the system reset signal SYS_RST_N to the IC chip, such as a CPLD.

[0088] After the IC chip acquires the processor fault detection signal, it can store the processor fault detection signal in the IC chip's register. The IC chip's register also records hardware information of the hardware device, such as power status information, voltage status information, interrupt signals and fault signals output by each main chip on the hardware device.

[0089] Specifically, when the IC chip receives a CPU fault signal and a platform reset signal from the CPU, or a system reset signal from an external reset source, it can store the CPU fault signal, platform reset signal, and system reset signal in the IC chip's register (such as CPLD_Reg).

[0090] S22. If the fault information acquisition conditions are met based on the processor fault detection signal, then the processor register information is acquired.

[0091] In practice, when a processor malfunctions, the conditions for obtaining fault information are determined. Specifically, a processor malfunction can be determined in the following ways:

[0092] If the processor fault signal is determined to be low and the platform reset signal is high, then the processor is determined to have malfunctioned, and the conditions for obtaining fault information are met.

[0093] Alternatively, if the system reset signal is determined to be low, then the CPU is determined to have malfunctioned, and the conditions for obtaining fault information are met.

[0094] In practical implementation, the following IC chips will all use CPLD as an example for illustration. The fault information acquisition condition is determined to be met when either or both of the following conditions are satisfied:

[0095] Scenario 1: When the CPU fault signal CATERR_N_CPLD received by the CPLD register CPLD_Reg is low and the platform reset signal PLTRST_N is high, it is determined that the CPU has failed, and the fault information acquisition conditions are met.

[0096] Scenario 2: When the system reset signal SYS_RST_N issued by the external reset source and received in the CPLD_Reg register of the CPLD is at a low level, it is determined that the CPU has failed, and the fault information acquisition conditions are met.

[0097] In addition to the two situations mentioned above that trigger the acquisition of CPU core register information, the IC chip can also be actively triggered to acquire CPU core register information. In this case, the conditions or timing of active triggering can be set according to actual needs. For example, active triggering can be performed according to a preset time period. This application embodiment does not limit this.

[0098] Once the conditions for obtaining fault information are met, the IC chip can obtain the processor's register information from the processor side through BUS1, which is connected to the processor.

[0099] Specifically, when it is determined that the fault information acquisition conditions are met, the IC chip can obtain CPU core register information from the CPU side through BUS1, which is connected to the CPU: such as MSR register information and CSR register information. BUS1 can be, but is not limited to, using PECI bus, SMBus bus, LPC bus or SPI bus, or any other bus. This application embodiment does not limit this.

[0100] S23. Store the processor's register information to a preset non-volatile memory area.

[0101] In practical implementation, the IC chip can be implemented as follows: Figure 3 The process shown stores the acquired processor register information into a preset non-volatile memory area, including the following steps:

[0102] S31. The acquired processor register information is cached in the RAM of the IC chip.

[0103] In practice, the IC chip will cache the CPU core register information obtained from the CPU core register in the IC chip's RAM.

[0104] Specifically, taking the use of CPLD in IC chips as an example, CPLD will store CPU core register information such as MSR register information and CSR register information into its own DPRAM for caching.

[0105] S32. After the processor's register information is acquired, store the processor's register information and the hardware information of the hardware devices contained in the IC chip's registers into a preset non-volatile storage area.

[0106] In specific implementation, the registers of the IC chip also include preset data write flag information and read flag information for the non-volatile memory area. Data read / write flag bits can be preset, namely: a data write flag bit and a data read flag bit. The data write flag bit stores information indicating whether the processor's register information has been written to the non-volatile memory area. The data read flag bit stores information indicating whether the processor's register information in the non-volatile memory area has been read. The specific content of the data write flag information and the data read flag information can be set independently. For example, the data write flag information can be set to "0xA5" to indicate that the non-volatile memory area has been written to the processor's register information, and the data write flag information can be set to "0xFF" to indicate that the non-volatile memory area has not been written to the processor's register information. Similarly, the data read flag information can be set to "0xA5" to indicate that the processor's register information in the non-volatile memory area has been read, and the data read flag information can be set to "0xFF" to indicate that the processor's register information in the non-volatile memory area has not been read. This application embodiment does not limit this. The data read flag information is set by the external device and stored in the IC chip's register. Initially, the data write flag and the data read flag can be set to "0XFF". After the IC chip writes the processor's register information to the non-volatile memory area, the IC chip can set the data write flag to "0XA5" to indicate that the processor's register information has been stored in the non-volatile memory area. When the processor's register information in the non-volatile memory area has been read and stored by the external device, the external device can set the data read flag to "0XA5" and store the updated data read flag "0XA5" in the IC chip's register. If the external device has not stored the processor's register information, it will not update the read flag information, and the read flag information will remain "0XFF".

[0107] Specifically, after the CPU core register information is fully acquired and cached in the RAM of the IC chip, the IC chip stores the CPU core register information cached in its RAM, as well as the hardware information of the hardware devices and the CPU fault detection signal contained in the IC chip's registers, in the non-volatile memory area of ​​the IC chip. After the IC chip has finished writing the CPU core register information and the IC chip's register information (i.e., the hardware information of the hardware devices and the CPU fault detection signal) into the non-volatile memory area, the data write flag is set to "0XA5" to indicate that data has been written into the non-volatile memory area.

[0108] Specifically, taking the use of a CPLD in an IC chip as an example, the CPLD stores the CPU core register information cached in the DPRAM and the hardware information of the hardware devices and CPU fault detection signals stored in the CPLD_Reg register into the UFM. After the data writing is complete, the data write flag is set to "0XA5". In this way, since the information stored in the CPLD's UFM will not be lost when the hardware device is powered off, fault-related information during CPU faults can be recorded and protected. Furthermore, since the UFM is a non-volatile memory area on the CPLD chip, no additional hardware cost is required.

[0109] If the IC chip uses an FPGA, the FPGA stores the CPU core register information cached in its RAM, the hardware information stored in the FPGA registers, and the CPU fault detection signals into its connected EEPROM (or EMMC). After the data writing is complete, the data write flag is set to "0xA5". When the IC chip uses an FPGA, the CPU core register information can be stored by connecting non-volatile memory such as EEPROM or EMMC as a non-volatile storage area. Connecting the FPGA to EEPROM or EMMC is easy to implement and has a low cost, and can achieve the same function of acquiring and storing CPU core register information as a CPLD.

[0110] Furthermore, after the IC chip stores the CPU core register information in the non-volatile memory area, it determines whether the CPU needs to be restarted. If PLTRST_N is high at this time, it indicates that the CPU has not performed a spontaneous restart and the current state can be preserved. If PLTRST_N is low, it indicates that the CPU has performed a spontaneous restart. Since the fault-related information contained in the CPU core register has been stored in the non-volatile memory area, the fault state information is latched.

[0111] In practice, when the system reset signal is determined to be low, the method further includes:

[0112] If it is determined that the processor's current operating state meets the reset conditions, then the processor is reset; if it is determined that the processor's current operating state does not meet the reset conditions, then the processor is reset after obtaining the processor's register information.

[0113] In practice, if the processor's current operating state is that the BOIS (Basic Input Output System) is not started, then the processor's current operating state is determined to meet the reset conditions; if the processor's current operating state is that the BOIS is started, then the processor's current operating state is determined not to meet the reset conditions.

[0114] Specifically, if it is determined that the current operating state of the CPU meets the reset conditions, the CPU is reset; if it is determined that the current operating state of the CPU does not meet the reset conditions, the CPU is reset after obtaining the CPU core register information.

[0115] During implementation, if the CPU fails to control external components and is reset via an external reset source, the system reset signal SYS_RST_N sent by the external reset source will be low. If the current operating state of the CPU is that the BIOS is not started, then the current operating state of the CPU meets the reset conditions, and the CPU can be reset directly. If the current operating state of the CPU is that the BIOS is started, then the current operating state of the CPU does not meet the reset conditions, and the CPU will be reset after the process of obtaining CPU core register information from the CPU side is completed.

[0116] Regarding the case of resetting the CPU using an external reset source, the following section will discuss... Figure 4 The process for handling external faults is detailed, including the following steps:

[0117] S41. Obtain the system reset signal sent by an external reset source.

[0118] In practice, the system reset signal SYS_RST_N issued by an external reset source is obtained from the register of the IC chip.

[0119] S42. Perform low pulse width detection on the system reset signal.

[0120] In practice, the IC chip performs low-pulse-width detection on the system reset signal SYS_RST_N to determine whether the system reset signal SYS_RST_N can effectively reset the CPU.

[0121] S43. Determine whether the low pulse width of the system reset signal is greater than or equal to the set threshold. If yes, proceed to step S44; otherwise, proceed to step S41.

[0122] The threshold can be set based on experience, for example, it can be set to 16ms or other durations. This application embodiment does not limit this. If the low pulse width of the system reset signal SYS_RST_N is greater than or equal to the set threshold, then the system reset signal SYS_RST_N is determined to be low, which can effectively reset the CPU.

[0123] S44. Determine whether the current operating state of the CPU meets the reset condition. If yes, proceed to step S410; otherwise, proceed to step S45.

[0124] In this step, if the CPU's current operating state is that the BIOS is not booted, then the CPU's current operating state meets the reset conditions. If the CPU's current operating state is that the BIOS is booted, then the CPU's current operating state does not meet the reset conditions. If the CPU's current operating state is that the BIOS is not booted, then step S410 can be executed directly: reset the CPU.

[0125] S45. Determine whether CPU core register information is being obtained from the CPU side. If yes, proceed to step S46; otherwise, proceed to step S47.

[0126] In this step, the IC chip determines whether it is currently in the state of obtaining CPU core register information from the CPU side when a new valid trigger occurs. If the IC chip is obtaining CPU core register information from the CPU side, this can be in the first case where the fault information acquisition condition is met, that is, when the IC chip receives a low-level CPU fault signal from the CPU and a high-level platform reset signal, the CPU core register information acquisition process has been triggered. Alternatively, it can be in the case where the user has actively triggered the CPU core register information acquisition process. In this case, step S46 is executed. If the function is in an idle state, step S47 is executed.

[0127] S46. Determine whether the MSR register information has been obtained. If yes, proceed to step S47. If no, continue to step S46.

[0128] In this step, when the IC chip obtains CPU core register information from the CPU side, it can first obtain the CSR register information, and then obtain the MSR register information. If the MSR register information has been obtained, it is determined that the IC chip has completed obtaining the CPU core register information from the CPU side. Specifically, this can be done by first checking whether the CSR register is busy. If the CSR is not busy, it can then check whether the MSR register is busy. If the MSR register is busy, it is determined that the CSR register information has been obtained, but the MSR register information has not. If neither the CSR nor the MSR register is busy, it is determined that the MSR register information has been obtained, and thus the CPU core register information has been obtained. If the CSR is busy, it waits until the CSR becomes unbusy before checking whether the MSR register is busy, and so on, until the MSR register is also unbusy. At this point, it is determined that the MSR register information has been obtained, and thus the CPU core register information has been obtained. If the MSR register information has not been fully acquired, the process continues to determine whether the MSR register information has been acquired until it is fully acquired. At this point, the CPU core registers (i.e., the CSR register and the MSR register) are updated from the busy state to the non-busy state, and step S47 is executed.

[0129] S47. Determine whether the data write flag information of the data write flag bit indicates that data has been written to the non-volatile storage area. If yes, proceed to step S410; otherwise, proceed to step S48.

[0130] In this step, if the CPU core registers are not in a busy state (i.e., neither CSR nor MSR is busy), it indicates that the IC chip is not currently obtaining CPU core register information from the CPU side. The step then checks if the data write flag indicates that data has been written to the non-volatile memory area. If the data write flag is "0xA5", it confirms that data has been written to the non-volatile memory area, meaning the IC chip has obtained CPU core register information from the CPU side and written it to the non-volatile memory area. If the data write flag is "0xFF", it confirms that no data has been written to the non-volatile memory area, meaning the IC chip has not yet obtained CPU core register information from the CPU side. If the IC chip has written the CPU core register information obtained from the CPU side to the non-volatile memory area, then step S410 is executed: the CPU is reset.

[0131] S48. Obtain CPU core register information from the CPU side and store the CPU core register information in a non-volatile memory area.

[0132] In this step, if the IC chip has not yet obtained the CPU core register information from the CPU side, it will obtain the CPU core register information from the CPU side. First, it can obtain the CSR register information, then obtain the MSR register information, and store the obtained CPU core register information in the RAM of the IC chip for caching. After the CPU core register information is obtained, the CPU core register information and the hardware information of the hardware devices contained in the registers of the IC chip and the CPU fault detection signal are stored in the non-volatile memory area.

[0133] S49. Set the data write flag information of the data write flag bit to indicate that data has been written to the non-volatile storage area.

[0134] In this step, after the IC chip stores the acquired CPU core register information into the non-volatile memory area, it sets the data write flag information of the data write flag bit to "0XA5" to indicate that data has been written into the non-volatile memory area, and stores the data write flag information into the IC chip's register.

[0135] S410: Reset the CPU.

[0136] In this step, the IC chip can reset the CPU by pulling the reset signal RSTBTN_N low.

[0137] Specifically, the system reset signal SYS_RST_N is a signal from an external reset source to reset the CPU. The IC chip, as an input terminal, determines whether the system reset signal SYS_RST_N can effectively reset the CPU. If the system reset signal SYS_RST_N is low, it is determined that it can effectively reset the CPU. At this time, if the reset condition is met, that is, the BIOS is currently in a non-boot state, the IC chip can reset the CPU by pulling the reset signal RSTBTN_N low. If the reset condition is not met, that is, the BIOS is currently in a boot state, the IC chip obtains the CPU core register information from the CPU side and stores it in the non-volatile memory area, and then pulls the reset signal RSTBTN_N low to reset the CPU. The reset signal RSTBTN_N is also a signal from an external reset source to reset the CPU. The CPU, as an input terminal, can directly connect the reset signal RSTBTN_N to the CPU's pin.

[0138] In one implementation, when the power is not off at the fault site but the fault phenomenon has disappeared, external devices can obtain the fault site information latched by the IC chip through the interface pre-set by the IC chip. This information includes: CPU core register information, hardware information of the hardware devices recorded in the IC chip's registers (such as power status information, voltage status information, interrupt signals and fault signals output by each main chip on the hardware device, etc.), and CPU fault detection signals. This information can be used as a basis for maintenance personnel to determine the cause of the CPU fault.

[0139] like Figure 5 The diagram illustrates the process of an external device reading register information from an IC chip, and may include the following steps:

[0140] S51. External devices obtain data writing flag information and data reading flag information from the registers of the IC chip.

[0141] In practice, external devices can read data write flag information and data read flag information stored in the IC chip's preset non-volatile memory area from the IC chip's registers via BUS3 (such as I2C bus, LPC bus or SPI bus).

[0142] S52. If the external device determines that the data write flag indicates that the preset non-volatile memory area has been written to the processor's register information and the data read flag indicates that the processor's register information has not been read, then it reads and stores the processor's register information and hardware information of the hardware device contained in the preset non-volatile memory area.

[0143] In specific implementation, if the data write flag information is "0XA5", it is determined that the non-volatile memory area of ​​the IC chip has been written with CPU core register information, hardware information of hardware devices, and CPU fault detection signals. If the data read flag information is "0XFF", it is determined that the CPU core register information, hardware information of hardware devices, and CPU fault detection signals in the non-volatile memory area have not been read by external devices. External devices can then read the CPU core register information, hardware information of hardware devices, and CPU fault detection signals stored in the non-volatile memory area through the communication channel BUS3 reserved by the IC chip (such as I2C bus, LPC bus, or SPI bus) and store them in the local storage of the hardware device or other storage devices.

[0144] S53. External device updates data read flag information. The updated data read flag information indicates that the processor's register information has been read.

[0145] In practice, after the external device stores the CPU core register information, hardware information of the hardware device, and CPU fault detection signal it reads, it updates the data read flag information to indicate that data has been read. The data read flag information can be set to "0XA5".

[0146] S54. The external device sends the updated data read flag information to the IC chip.

[0147] The external device sends the updated data read flag information to the IC chip. The IC chip receives the updated data read flag information returned by the external device and stores the updated data read flag information in the IC chip's register to replace the previous data read flag information.

[0148] In one embodiment, after each hardware device or IC chip restart, the non-volatile memory area of ​​the IC chip can be initialized upon power-on. The register information of the processor and the hardware information of the hardware device in the non-volatile memory area are loaded into the RAM of the IC chip for buffering, so that external devices can read them. The hardware device restart can be a restart after CPU reset or a restart after the hardware device is powered off. This application embodiment does not limit this.

[0149] In practice, after the hardware device or IC chip is determined to be restarted, the processor's register information and the hardware device's hardware information are extracted from the preset non-volatile storage area; the processor's register information and the hardware device's hardware information are sent to the IC chip's RAM for caching so that external devices can read them.

[0150] Specifically, taking the use of CPLD in IC chips as an example, if it is determined that the hardware device or CPLD is powered off and restarted, the CPLD extracts the stored CPU core register information and CPLD_Reg register information (i.e., hardware information of the hardware device and CPU fault detection signal) from its UFM, and sends the extracted CPU core register information and CPLD_Reg register information to DPRAM for caching so that external devices can read them.

[0151] In this scenario, the external device reads the processor register information and hardware information of the hardware device contained in a preset non-volatile memory area, specifically including:

[0152] External devices read CPU core register information and hardware information of hardware devices from the RAM of the IC chip.

[0153] In practical implementation, taking the use of CPLD in IC chip as an example, when external device reads CPU core register information from IC chip, external device can obtain CPU core register information and CPLD_Reg register information (i.e. hardware information of hardware device and CPU fault detection signal) from CPLD's DPRAM through BUS3.

[0154] like Figure 6The diagram illustrates the implementation of non-volatile memory area access in an IC chip. Taking a CPLD as an example, the DPRAM in the CPLD includes at least the following pins for reading and writing data: WE (Write Enable), ADDR (Address), WADTA (Write Data), and RDATA (Read Data). WE is the write enable pin; when WE is high (WE=1), it indicates that the acquired CPU core register information and CPLD_Reg register information will be written to the DPRAM. ADDR is a shared address port for reading and writing. Since reading and writing cannot occur simultaneously, ADDR serves as a shared address port for providing addresses for both. WDATA is the write port, used to write the acquired CPU core register information and CPLD_Reg register information to the DPRAM when WE is high. RDATA is the read port, allowing external devices to read data from the DPRAM. The CPLD also includes a Store pin, a Load pin, and a Busy pin. The Store pin indicates that data in the DPRAM should be flushed to the UFM flash memory; that is, the Store pin is the trigger instruction to flush data from DPRAM to the UFM. The Load pin is used to load historical CPU core register information and CPLD_Reg register information stored in the UFM into the DPRAM when the CPLD or hardware device is restarted, for external devices to read. The Busy pin indicates that the UFM is busy; that is, either DPRAM is writing data to the UFM, or DPRAM is loading data from the UFM into DPRAM. The CPLD also includes a SYS_CLK (System clock) pin and a system reset pin SYS_RST_N.

[0155] like Figure 7The diagram illustrates the storage of CPU core register information and the reading of CPU core register information by external devices. Taking the IC chip using a CPLD as an example, after the CPLD obtains the CPU core register information from the CPU through the BUS1 bus interface, it converts the BUS1 bus interface into an internal bus interface. Then, the obtained CPU core register information is stored in the DPRAM cache through the converted internal bus interface. After the CPU core register information is obtained, the CPLD_Reg register information and the CPU core register information cached in the DPRAM are stored in the UFM. The internal bus interface can be a unified bus interface different from BUS1 and BUS3. A first external device can read CPU core register information from the DPRAM via one of the BUS3 bus interfaces: the first external access interface. A second external device can also read CPU core register information from the DPRAM via one of the BUS3 bus interfaces: the second external access interface. The first and second external access interfaces are different bus interfaces. For example, the first external access interface can be an I2C bus interface, and the second external access interface can be an LPC bus interface, or other bus interfaces such as an SPI bus interface. The number of external access interfaces can be set by the user, and this embodiment does not limit this. When an external device requests to read CPU core register information from the CPLD, the CPLD also needs to convert the external access interface into an internal bus interface. The external device reads and stores the CPLD_Reg register information and CPU core register information in the DPRAM through the internal bus interface.

[0156] When an external device uses the I2C bus interface, there may be situations where it is impossible to read all the DPRAM stored information due to the limited read address (e.g., allocating an I2C device address can only read 256 bytes of data). In this case, the access address content can be expanded by writing special registers. In this way, the DPRAM stored information can be read completely at once through the I2C device address and page turning operation.

[0157] Taking the use of a CPLD in an IC chip as an example, external devices can read the CPU core register information and CPLD_Reg register information extracted from the non-volatile memory area into the CPLD's RAM, which is the fault scene information, such as... Figure 8 The diagram illustrates the implementation process of an external device reading fault scene information from the CPLD's RAM, and may include the following steps:

[0158] S61. External devices obtain data write flag information and data read flag information from CPLD_Reg.

[0159] S62. If it is determined that the data write flag indicates that data has been written to the UFM and the data read flag indicates that the data in the UFM has not been read, then read the data in the UFM and save it.

[0160] In this step, when the write flag information is "0XA5" and the data read flag information is "0XFF", that is, when the CPU core register information has been written to the UFM and not read by the external device, the external device reads the fault scene information latched in the UFM, namely: CPU core register information and CPLD_Reg register information (i.e., hardware information of the hardware device and CPU fault detection signal), and stores it in the local storage device or other storage devices.

[0161] Specifically, if the fault scene information latched in the UFM has been extracted to the DPRAM by the CPLD, the external device can directly read the CPU core register information and CPLD_Reg register information from the DPRAM and save the read CPU core register information and CPLD_Reg register information to the local storage device or other storage devices.

[0162] S63. Set the data read flag information of the data read flag bit to indicate that the UFM data has been read.

[0163] In this step, the external device can update the data read flag information of the data read flag bit to "0XA5" and return the updated data read flag information to the CPLD. The CPLD will then replace the data read flag information in CPLD_Reg with the updated data read flag information.

[0164] S64. If it is determined that the data write flag indicates that data has been written to the UFM and the data read flag indicates that the data of the UFM has been read, then the process ends.

[0165] In this step, if the written flag information is "0XA5" and the data read flag information is "0XA5", the process can be ended and the external device does not need to repeatedly obtain the fault site information.

[0166] The register information acquisition method provided in this application uses an IC chip (such as a logic device, MCU device, or microcontroller) in a hardware device to determine whether the CPU is in a fault state based on the acquired CPU fault detection signal. If the fault information acquisition conditions are met, the IC chip automatically acquires and stores the CPU fault-related information from the CPU core register information. In this way, since both the determination of the CPU fault state and the acquisition of the CPU core register information are implemented by the IC chip contained in the hardware device itself, no additional hardware cost is required. Moreover, when the CPU malfunctions, the IC chip can still operate normally to acquire and store the CPU core register information. Furthermore, since the IC chip stores the acquired CPU core register information in a non-volatile storage area, the CPU core register information will not be lost even when the hardware device is powered off. Thus, the successful acquisition and recording of CPU core register information is achieved without increasing hardware costs.

[0167] Based on the same inventive concept, this application also provides a register information acquisition device. Since the principle of the register information acquisition device in solving the problem is similar to that of the register information acquisition method, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0168] like Figure 9 As shown, it is a schematic diagram of the register information acquisition device provided in the embodiment of this application.

[0169] The above-mentioned device is applied to a hardware device, the hardware device including a processor and an IC chip, and the device includes:

[0170] The first acquisition unit 71 is used to acquire processor fault detection signals;

[0171] The second acquisition unit 72 is used to acquire the processor's register information if it is determined based on the processor fault detection signal that the fault information acquisition conditions are met. The processor's register information includes the processor's fault-related information.

[0172] Storage unit 73 is used to store the register information of the processor into a preset non-volatile storage area.

[0173] In one possible implementation, the processor fault detection signal includes a processor fault signal and a platform reset signal;

[0174] The second acquisition unit 72 is specifically used to determine that the fault information acquisition conditions are met if the processor fault signal is low and the platform reset signal is high.

[0175] In one possible implementation, the processor fault detection signal includes a system reset signal;

[0176] The second acquisition unit 72 is specifically used to determine that the fault information acquisition condition is met if the system reset signal is determined to be low.

[0177] In one possible implementation, when the IC chip is a complex programmable logic device (CPLD), the preset non-volatile memory area includes the CPLD's user flash memory (UFM); or,

[0178] When the IC chip is a Field Programmable Gate Array (FPGA), the preset non-volatile memory area includes an Electrically Erasable Programmable Read-Only Memory (EEPROM); or,

[0179] When the IC chip is a microcontroller unit (MCU) device, the preset non-volatile storage area includes an electrically erasable programmable read-only memory (EEPROM).

[0180] In one possible implementation, when the system reset signal is determined to be low, the device further includes:

[0181] The reset unit is configured to reset the processor if it is determined that the current operating state of the processor meets the reset conditions; and to reset the processor after obtaining the register information of the processor if it is determined that the current operating state of the processor does not meet the reset conditions.

[0182] In one possible implementation, the reset unit is specifically configured to determine that the current operating state of the processor meets the reset conditions if the current operating state of the processor is that the BIOS is in an unbooted state.

[0183] In one possible implementation, the registers of the IC chip contain hardware information of the hardware device;

[0184] The storage unit 73 is specifically used to cache the acquired register information of the processor in the random access memory (RAM) of the IC chip; and after the register information of the processor is acquired, to store the register information of the processor and the hardware information in the preset non-volatile storage area.

[0185] In one possible implementation, the register of the IC chip further includes data write flag information and data read flag information for the preset non-volatile memory area;

[0186] The device further includes:

[0187] A receiving unit is configured to receive updated data read flag information sent by an external device. The updated data read flag information indicates that the processor's register information has been read. The updated data read flag information is sent by the external device after reading the processor's register information and the hardware information contained in the preset non-volatile memory area when the data write flag information in the IC chip's register indicates that the preset non-volatile memory area has been written to the processor's register information and the data read flag information indicates that the processor's register information has not been read.

[0188] In one possible implementation, the device further includes:

[0189] The extraction unit is used to extract the processor's register information and hardware information stored in the preset non-volatile memory area after determining that the hardware device or the IC chip has restarted.

[0190] The transmitting unit is used to send the processor's register information and the hardware information to the RAM of the IC chip for caching, so that the external device can read them.

[0191] Based on the same technical concept, this application also provides an electronic device 800, referring to... Figure 10 As shown, the electronic device 800 is used to implement the register information acquisition method described in the above-described method embodiments. The electronic device 800 in this embodiment may include: a memory 801, a processor 802, and a computer program stored in the memory and executable on the processor, such as a CPU core register information acquisition program. When the processor executes the computer program, it implements the steps in the various register information acquisition method embodiments described above, for example... Figure 2 The step S21 shown. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the above-described device embodiments, such as 71.

[0192] This application embodiment does not limit the specific connection medium between the memory 801 and the processor 802. This application embodiment... Figure 10 The memory 801 and the processor 802 are connected via a bus 803, and the bus 803 is in Figure 10 The connections between other components are shown in bold and are for illustrative purposes only, not as limiting information. The bus 803 can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 10 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0193] Memory 801 may be volatile memory, such as random access memory (RAM); memory 801 may also be non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 801 may be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. Memory 801 may be a combination of the above-mentioned memories.

[0194] Processor 802, used to implement such Figure 2 The method for obtaining register information shown includes:

[0195] The processor 802 is used to call the computer program stored in the memory 801 to execute, such as Figure 2 The steps shown are: S21, IC chip acquires processor fault detection signal; S22, if it is determined based on processor fault detection signal that the fault information acquisition condition is met, then acquire processor register information; and S23, store processor register information in preset non-volatile memory area.

[0196] This application also provides a computer-readable storage medium storing computer-executable instructions required to execute the processor, including a program required to execute the processor.

[0197] In some possible implementations, various aspects of the register information acquisition method provided in this application can also be implemented as a program product, which includes program code. When the program product is run on an electronic device, the program code is used to cause the electronic device to perform the steps in the register information acquisition method according to the various exemplary embodiments of this application described above. For example, the electronic device can perform actions such as... Figure 2 The steps shown are: S21, IC chip acquires processor fault detection signal; S22, if it is determined based on processor fault detection signal that the fault information acquisition condition is met, then acquire processor register information; and S23, store processor register information in preset non-volatile memory area.

[0198] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0199] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0200] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0201] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0202] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0203] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A register information acquisition method characterized by comprising: The method is applied to a hardware device including a processor and an IC chip, and comprises the following steps: The IC chip acquires a processor fault detection signal, wherein the processor fault detection signal includes a processor fault signal and a platform reset signal; If it is determined that a fault information acquisition condition is met based on the processor fault detection signal, register information of the processor is acquired, and the register information of the processor includes fault-related information of the processor; The register information of the processor is stored in a preset non-volatile storage area; The method further comprises the following steps: If it is determined that the processor fault signal is at a low level and the platform reset signal is at a high level, it is determined that the fault information acquisition condition is met.

2. The method of claim 1, wherein, The processor fault detection signal includes a system reset signal; If it is determined that the system reset signal is at a low level, it is determined that the fault information acquisition condition is met.

3. The method of claim 1, wherein: when the IC chip is a complex programmable logic device (CPLD), the preset non-volatile storage area includes a user flash memory (UFM) of the CPLD; or when the IC chip is a field programmable gate array (FPGA), the preset non-volatile storage area includes an electrically erasable programmable read-only memory (EEPROM); or when the IC chip is a micro control unit (MCU) device, the preset non-volatile storage area includes an electrically erasable programmable read-only memory (EEPROM). When it is determined that the system reset signal is at a low level, the method further comprises the following steps:

4. The method of claim 2, wherein, If it is determined that a current running state of the processor meets a reset condition, the processor is reset; If it is determined that the current running state of the processor does not meet the reset condition, the processor is reset after the register information of the processor is acquired. The determination that the current running state of the processor meets the reset condition specifically comprises the following step:

5. The method of claim 4, wherein, If the current running state of the processor is that a BIOS is in an unstarted state, it is determined that the current running state of the processor meets the reset condition. The register of the IC chip includes hardware information of the hardware device; 6. The method of claim 1, wherein, The storage of the register information of the processor in the preset non-volatile storage area specifically comprises the following steps: The acquired register information of the processor is cached in a random access memory (RAM) of the IC chip; and After the register information of the processor is acquired, the register information of the processor and the hardware information are stored in the preset non-volatile storage area. The register of the IC chip further includes data write flag information and data read flag information of the preset non-volatile storage area; 7. The method of claim 6, wherein, The method further comprises the following steps: ​ receive updated data read flag information sent by the external device, the updated data read flag information identifying that the register information of the processor has been read, wherein the updated data read flag information is sent by the external device after reading the register information of the processor and the hardware information included in the preset non-volatile storage area when it is determined that the data write flag information in the register of the IC chip identifies that the preset non-volatile storage area has written the register information of the processor and the data read flag information identifies that the register information of the processor has not been read.

8. The method of claim 7, wherein, Further comprising: extract the stored register information of the processor and the hardware information from the preset non-volatile storage area after it is determined that the hardware device or the IC chip is restarted; and send the register information of the processor and the hardware information to the RAM of the IC chip for caching, so as to be read by the external device.

9. A register information acquisition apparatus characterized by comprising: The application is applied to a hardware device, and the hardware device comprises a processor and an integrated circuit (IC) chip. The device comprises: a first obtaining unit configured to obtain a processor fault detection signal, wherein the processor fault detection signal comprises a processor fault signal and a platform reset signal; a second obtaining unit configured to obtain register information of the processor if it is determined that a fault information obtaining condition is met based on the processor fault detection signal, wherein the register information of the processor comprises fault-related information of the processor; a storage unit configured to store the register information of the processor to a preset non-volatile storage area. The determination that the fault information obtaining condition is met based on the processor fault detection signal specifically comprises: if it is determined that the processor fault signal is at a low level and the platform reset signal is at a high level, it is determined that the fault information obtaining condition is met.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the register information obtaining method according to any one of claims 1 to 8.

11. A computer readable storage medium having stored thereon a computer program, characterized in that The program is executed by the processor to implement the steps in the register information obtaining method according to any one of claims 1 to 8.

Images