A method, device and medium for evaluating total dose effects of a through-silicon via link based on an equivalent circuit model

Abstract

The application belongs to the technical field of three-dimensional integrated circuits, and discloses a through-silicon via link total dose effect evaluation method, equipment and medium based on an equivalent circuit model, wherein the method comprises the following steps: establishing a total dose equivalent circuit topology structure according to a through-silicon via structure; determining a parasitic electric parameter calculation equation in the total dose effect equivalent circuit; calculating the value of the electric parameter under normal conditions, and comparing the S parameter obtained through simulation calculation with the actually measured S parameter to verify the total dose effect equivalent circuit model; optimizing the design, extracting the electric parameter in the equivalent circuit under different radiation dose conditions; extracting the electric parameter change curve with the radiation dose; fitting the equation of the material attribute change with the radiation dose; and predicting the S parameter of the through-silicon via link at any radiation dose point. The equipment and medium are used for realizing the through-silicon via link total dose effect evaluation method based on the equivalent circuit model. The evaluation factors are comprehensive, the actual irradiation conditions can be better matched, and the performance of the through-silicon via link under the actual radiation conditions can be more accurately simulated.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of three-dimensional integrated circuits, and particularly relates to a through-silicon via (TSV) link total ionizing dose (TID) effect evaluation method and device based on an equivalent circuit model, and a medium, which can be used for three-dimensional integrated circuit radiation effect simulation. BACKGROUND

[0002] With the development of semiconductor technology, device size is approaching the physical limit of the material, and Moore's law is ending. The vigorous development of information technology and the rise of emerging industries have increased the demand for high-performance chips. In aerospace applications, these chips must overcome challenges related to interconnect bandwidth, integration density, and power consumption. Post-Moore's law proposes three-dimensional (3D) integration technology, including three-dimensional integration of active integrated circuits (ICs), 2.5-dimensional (2.5D) integration of passive silicon or glass interconnects, and heterogeneous chip integration. Through-silicon via (TSV) technology is a vertical interconnection solution that has become a key technology for continuing Moore's law due to its potential to shorten interconnection distances, reduce power consumption, increase packaging density, and enable device miniaturization and multifunctionality.

[0003] Through-silicon via (TSV) technology provides numerous advantages for high-performance chips, but the signal integrity problem of through-silicon via (TSV) in a radiation environment cannot be ignored. Through-silicon via (TSV) is a metal-oxide-semiconductor (MOS) structure that is highly sensitive to ionizing radiation. Total ionizing dose (TID) radiation can cause degradation of through-silicon via (TSV) materials, and in addition, the total ionizing dose (TID) radiation-induced products can change the parasitic resistance, capacitance, and inductance of the TSV, which in turn leads to signal loss in the through-silicon via (TSV). In order to use through-silicon via (TSV) technology in high-performance chips in a radiation environment, it is necessary to evaluate the total ionizing dose (TID) effect of the through-silicon via (TSV) link. However, the total ionizing dose (TID) effect evaluation of through-silicon via (TSV) by irradiation testing has the disadvantages of high cost and poor flexibility.

[0004] Chinese patent document CN114595521A discloses a total dose effect modeling method for microsystem three-dimensional interconnection structure transmission of high frequency signal. This method models the total ionizing dose (TID) effect of through-silicon via (TSV) based on an equivalent circuit model of three-dimensional interconnection structure, and uses numerical fitting to functionally fit the changes of through-silicon via (TSV) resistance and oxide layer capacitance with radiation dose. This method does not consider the capacitance and conductance of the silicon substrate, the capacitance and inductance of the redistribution layer (RDL), the capacitance and inductance of the bump, and the crosstalk effect between signal through-silicon vias (TSVs) in the three-dimensional interconnection structure when numerically fitting.

[0005] The patent application with the publication number CN114878921A discloses a method for analyzing the performance change of TSV structure material under total dose effect. The method uses high-frequency structure simulator (HFSS) software to extract the dielectric constant of silicon and silicon dioxide (SiO2) in the through-silicon via (TSV) structure under different irradiation dose conditions, and then predicts the material parameters of the through-silicon via (TSV) structure under any irradiation condition. This method does not consider the influence of total dose (TID) effect on the conductivity of silicon, the dielectric constant and conductivity of the filling material.

[0006] In summary, the existing technology does not comprehensively consider the factors when building the total dose (TID) effect model of the through-silicon via (TSV) and fitting the mathematical relationship between the irradiation dose and the material properties, which fails to reflect the real radiation situation and cannot realize the total dose (TID) effect evaluation of the through-silicon via (TSV) link. SUMMARY

[0007] In order to overcome the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a through-silicon via link total dose (TID) effect evaluation method, device and medium based on equivalent circuit model, to build a complete through-silicon via (TSV) total dose (TID) effect equivalent circuit model, extract all parasitic electrical parameters and material properties of the through-silicon via (TSV) under total dose (TID) effect, and realize the evaluation of the total dose (TID) effect S parameter of the through-silicon via (TSV) link, which has the characteristics of comprehensive evaluation factors and better reflects the real radiation situation.

[0008] In order to achieve the above-mentioned purpose, the technical solution adopted by the present application is as follows:

[0009] A through-silicon via link total dose effect evaluation method based on equivalent circuit model, comprising the following steps:

[0010] Step 1: According to the actual layout structure of the through-silicon via (TSV) link, the through-silicon via (TSV) link is divided into top re-distribution layer (RDL), bottom re-distribution layer (RDL), through-silicon via (TSV) and bump four parts, and the total dose (TID) effect equivalent circuit topology structure of each part is established, then the total dose (TID) effect equivalent circuit topology structures of each part are connected to build a complete total dose (TID) effect equivalent circuit topology structure of the through-silicon via (TSV) link;

[0011] Step 2: Determine the calculation equation of the parasitic electrical parameters in the total dose (TID) effect equivalent circuit;

[0012] Step 3: Calculate the value of the parasitic electrical parameters under normal conditions by the calculation equation determined in step 2, and substitute the calculated value of the parasitic electrical parameters into the complete total ionizing dose (TID) effect equivalent circuit topology constructed in step 1 to obtain a total ionizing dose (TID) effect equivalent circuit model, and then simulate the total ionizing dose (TID) effect equivalent circuit model to obtain S parameters, and when the average relative error between the simulated S parameters and the actually measured S parameters under normal conditions is less than or equal to the expected value Error, the total ionizing dose (TID) effect equivalent circuit model is available, and step 4 is continued to be executed;

[0013] Step 4: Perform the optimization design of the total ionizing dose (TID) effect equivalent circuit model in the ADS software, take the S parameters actually measured under each radiation dose as the optimization target, and use the optimization algorithm built in the ADS software to iteratively adjust the parasitic electrical parameters in the total ionizing dose (TID) effect equivalent circuit so as to minimize the difference between the simulated S parameters of the total ionizing dose (TID) effect equivalent circuit and the actually measured S parameters.

[0014] Step 5: Perform the optimization design in step 4, extract the parasitic electrical parameters in the total ionizing dose (TID) effect equivalent circuit under each radiation dose, and draw the curve of the change of the parasitic electrical parameters with the radiation dose.

[0015] Step 6: Based on the curve of the change of each parasitic electrical parameter with the radiation dose drawn in step 5, extract the material attribute values of the through silicon via (TSV) link under each radiation dose according to the calculation equation of each parasitic electrical parameter determined in step 2, and use polynomial fitting to obtain the equation of the change of the material attribute values with the radiation dose.

[0016] Step 7: Substitute the equation of the change of the material attribute values with the radiation dose fitted in step 6 into the parasitic electrical parameter calculation equation determined in step 2, simulate the total ionizing dose (TID) effect equivalent circuit in the ADS software, and predict the S parameters of the through silicon via (TSV) link at any radiation dose point.

[0017] The total ionizing dose (TID) effect equivalent circuit topology of each part in step 1 is as follows:

[0018] Top layer redistribution layer (RDL) part:

[0019] The top layer signal redistribution layer (RDL) is equivalent to a series connection of a resistance R RDL_Top and an inductance L RDL_Top , the capacitance between the top layer signal redistribution layer (RDL) and the top layer ground redistribution layer (RDL) is equivalent to C RDL_Top , and the capacitance C RDL_Top is connected in parallel with the resistance R RDL_Top and the inductance L RDL_TopThe equivalent capacitance between the top ground redistribution layer (RDL) and the top signal redistribution layer (RDL), and between the top ground redistribution layer (RDL) and the silicon substrate is C. Fill Capacitor C Fill The resistor R connected in series in the top redistribution layer (RDL) RDL_Top Inductor L RDL_Top The resistance between the top ground redistribution layer (RDL) and the silicon substrate is equivalent to R. Si_RDL resistance R Si_RDL Parallel connection to capacitor C Fill between;

[0020] The underlying redistribution layer (RDL) section:

[0021] The underlying signal redistribution layer (RDL) is equivalent to a resistor R. RDL_Bot and inductor L RDL_Bot In series, the capacitance between the bottom signal redistribution layer (RDL) and the bottom ground redistribution layer (RDL) is equivalent to C. RDL_Bot Capacitor C RDL_Bot It is connected in parallel between the underlying signal redistribution layer (RDL) and the underlying ground redistribution layer (RDL);

[0022] Through-Silicon Vias (TSV) section:

[0023] A signal through-silicon via (TSV) is equivalent to a resistor R. TSV and inductor L TSV The series connection, the oxide layer around the signal through silicon via (TSV) is equivalent to C oxs Oxide layer C oxs Parallel to resistor R TSV and inductor L TSV At both ends, the oxide layer around the through-silicon via (TSV) is equivalent to C. oxg Oxide layer C oxg Connected in parallel across the two ends of a through-silicon via (TSV), the silicon substrate between a single signal TSV and its surrounding individual TSVs is equivalent to a silicon substrate resistance R. Si and silicon substrate capacitor C Si The signal via (TSV) and the ground via (TSV) are connected in parallel. The crosstalk between adjacent signal vias (TSVs) is equivalent to the crosstalk resistance R. Si_noise and crosstalk capacitor C Si_noise The parallel connection is between adjacent signal through silicon vias (TSVs);

[0024] Bump section:

[0025] A bump is equivalent to a resistor R. Bump and inductor LBump The equivalent capacitance between a single signal bump and its surrounding ground bumps is C Bump .

[0026] The calculation equation of the parasitic electrical parameters in the equivalent circuit of the total dose (TID) effect in step 2 is as follows:

[0027] Top RDL portion:

[0028] Top RDL resistance:

[0029] Top RDL DC resistance:

[0030] Top RDL AC resistance:

[0031] Top RDL skin depth:

[0032] Top RDL inductance:

[0033] Top RDL capacitance:

[0034] Filling material capacitance between top RDL and silicon substrate:

[0035] First type of complete elliptic integral parameter of filling material capacitance:

[0036] Penetration resistance between top RDL and silicon substrate:

[0037] Penetration conductivity between top RDL and silicon substrate:

[0038] Penetration depth between top RDL and silicon substrate:

[0039] Where t RDL_Top is the thickness of the top RDL, s RDL_Top is the width of the insulating material between the top signal RDL and the ground RDL, l RDL_Top is the length of the single-ended top RDL, ω RDL_Top is the width of the top RDL, and h Fillh is the height of the fill material between the top redistribution layer (RDL) and the silicon substrate Bump h is the height of the bump Si p is the height of the silicon substrate RDL_Top p is the height of the silicon substrate RDL_Top p is the height of the silicon substrate RDL_Top p is the height of the silicon substrate ox p is the height of the silicon substrate Si p is the height of the silicon substrate

[0040] Bottom redistribution layer (RDL) portion:

[0041] Bottom redistribution layer (RDL) resistance:

[0042] Bottom redistribution layer (RDL) DC resistance:

[0043] Bottom redistribution layer (RDL) AC resistance:

[0044] Bottom redistribution layer (RDL) skin depth:

[0045] Bottom redistribution layer (RDL) inductance:

[0046] Bottom redistribution layer (RDL) capacitance:

[0047] where t RDL_Bot p is the height of the silicon substrate RDL_Bot p is the height of the silicon substrate RDL_Bot p is the height of the silicon substrate RDL_Bot p is the height of the silicon substrate RDL_Bot p is the height of the silicon substrate RDL_Bot p is the height of the silicon substrate RDL_Bot p is the height of the silicon substrate

[0048] Through silicon via (TSV) portion:

[0049] Through silicon via (TSV) resistance:

[0050] Through silicon via (TSV) DC resistance:

[0051] Through Silicon Via (TSV) AC resistance:

[0052] Through Silicon Via (TSV) skin depth:

[0053] Through Silicon Via (TSV) proximity factor:

[0054] Through Silicon Via (TSV) inductance:

[0055] Signal Through Silicon Via (TSV) oxide layer capacitance:

[0056] Ground Through Silicon Via (TSV) oxide layer capacitance: C oxg = 1.5 x C oxs ;

[0057] Silicon substrate capacitance between signal Through Silicon Via (TSV) and ground TSV:

[0058] Silicon substrate resistance between signal Through Silicon Via (TSV) and ground Through Silicon Via (TSV):

[0059] Cross-talk capacitance between signal Through Silicon Via (TSV) and signal Through Silicon Via (TSV):

[0060] Cross-talk resistance between signal Through Silicon Via (TSV) and signal Through Silicon Via (TSV):

[0061] where h TSV is the Through Silicon Via (TSV) height, r TSV is the Through Silicon Via (TSV) radius, d TSV is the Through Silicon Via (TSV) diameter, p TSV is the Through Silicon Via (TSV) material resistivity, s TSV is the Through Silicon Via (TSV) material conductivity, p TSV is the Through Silicon Via (TSV) material permeability, p TSV is the minimum center distance between a single signal Through Silicon Via (TSV) and its surrounding single ground Through Silicon Via (TSV), p STSV is the center distance between two signal Through Silicon Vias (TSVs), t ox is the oxide layer thickness, s Si is the silicon substrate permittivity, s Si is the silicon substrate material conductivity, s Fill is the relative permittivity of the filling material between signal Through Silicon Vias (TSVs).Fill Electrical conductivity of the filling material between signal through silicon vias (TSVs);

[0062] Bump portion:

[0063] Bump resistance:

[0064] Bump direct current resistance:

[0065] Bump alternating current resistance:

[0066] Bump skin depth:

[0067] Bump proximity factor:

[0068] Bump inductance:

[0069] Capacitance between signal bump and ground bump:

[0070] wherein h Bump is a bump height, r Bump is a bump radius, d Bump is a bump diameter, p Bump is a center distance between bumps, p Bump is a bump material resistivity, s Bump is a bump material conductivity, m Bump is a bump material permeability, e fill is a dielectric constant of the filling material between bumps.

[0071] The step 3 specifically comprises:

[0072] Substitute the physical size and material properties of the through silicon via (TSV) link into the calculation equation in step 2 to obtain the values of the electrical parameters under normal conditions, construct the total ionizing dose (TID) effect equivalent circuit topology in step 1 in the ADS software, and substitute the calculated electrical parameters into the total ionizing dose (TID) effect equivalent circuit topology to start simulation.

[0073] View the simulated S parameters in the simulation results of the ADS software, save the results, plot the simulated S parameters and the actually measured S parameters in the Matlab software, and calculate the average relative error of the simulation results and the actual results of the S parameters in the entire frequency range.

[0074] If the average relative error is less than or equal to the expected value Error, the total dose (TID) effect equivalent circuit model is verified under normal conditions and can be used for subsequent operations, and step 4 is performed.

[0075] If the average relative error is greater than the expected value Error, the total dose (TID) effect equivalent circuit model is not verified under normal conditions, and the total dose (TID) effect equivalent circuit topology and electrical parameter calculation equation need to be adjusted according to the specific through silicon via (TSV) link structure.

[0076] The step 4 specifically includes:

[0077] The total dose (TID) effect equivalent circuit topology established in step 1 is built in the ADS software, and the controls "DataAccessComponent", "S-PARAMETERS", "OPTIM" and "GOAL" are added. The S parameter files measured at each dose point are read in the control "DataAccessComponent". The start and stop frequencies and step length of the S parameters are set in the control "S-PARAMETERS". The optimization algorithm and iteration number are set in the control "OPTIM". The difference between the S parameters measured in the test and the S parameters obtained by the equivalent circuit simulation is set as the optimization target in the control "GOAL".

[0078] The step 5 specifically includes:

[0079] First, the S parameter files actually measured under each radiation dose condition are loaded in the control "DataAccessComponent" added in step 4, and the optimization design is performed to obtain the parasitic electrical parameters under each radiation dose condition. Then, the curves of each parasitic electrical parameter changing with the radiation dose are plotted in the Matlab software.

[0080] The step 6 specifically includes:

[0081] According to the parasitic electrical parameters in the total dose (TID) effect equivalent circuit under each radiation dose condition extracted in step 5, and combining the parasitic electrical parameter calculation equation determined in step 2, the material property values in the parasitic electrical parameter calculation equation are inversely deduced to obtain the material property values under each radiation dose condition. In the Matlab software, the polynomial fitting method is used to obtain the equation of the material property changing with the radiation dose:

[0082] Relative dielectric constant of silicon substrate: ε Si = a n dose n + a n-1 dose n-1 +... + a0.

[0083] Conductivity of silicon substrate: σ Si =b n dose n +b n-1 dose n-1 +...+b0;

[0084] Relative permittivity of the filler material: ε fill =c n dose n +c n-1 dose n-1 +...+c0;

[0085] Relative permittivity of oxide layer: ε ox =m n dose n +m n-1 dose n-1 +...+m0;

[0086] Electrical conductivity of filler material: σ fill =z n dose n +z n-1 dose n-1 +...+z0;

[0087] Where, dose is the radiation dose, ε Si σ is the relative permittivity of the silicon substrate. Si ε is the conductivity of the silicon substrate. fill ε is the relative permittivity of the filling material. ox σ is the relative permittivity of the oxide layer. fill Let a be the electrical conductivity of the filling material, 0,...,n-1, and n be the degree of the polynomial, and a0,...,a n-1 ,a n ,b0,...b n-1 ,b n ,c0,...c n-1 ,c n ,m0,...m n-1 ,m n ,z0,...z n-1 ,z n These are the polynomial coefficients.

[0088] Step 7 specifically includes:

[0089] The equation of the material property value obtained in step 6 with the radiation dose is substituted into the parasitic electrical parameter calculation equation determined in step 2 to obtain a radiation-related parasitic electrical parameter calculation equation, and according to the requirements, any radiation dose value is substituted to calculate the corresponding parasitic electrical parameter and perform simulation to predict the S parameters of the through-silicon via (TSV) link at any radiation dose point.

[0090] A through-silicon via link total dose (TID) effect evaluation device based on an equivalent circuit model, comprising:

[0091] A memory for storing a computer program for implementing the method for evaluating the total dose (TID) effect of a through-silicon via link based on an equivalent circuit model according to any one of claims 1-8;

[0092] A processor for implementing the method for evaluating the total dose (TID) effect of a through-silicon via link based on an equivalent circuit model according to any one of claims 1-8 when executing the computer program.

[0093] A computer-readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps of the method for evaluating the total dose (TID) effect of a through-silicon via link based on an equivalent circuit model.

[0094] Compared with the prior art, the present application has the following advantages:

[0095] First, when evaluating the total dose (TID) effect of a through-silicon via (TSV) link based on an equivalent circuit model, the present application introduces the crosstalk effect between the signal through-silicon vias (TSVs), which is equivalent to the crosstalk resistance and capacitance of the filling material between the signal through-silicon vias (TSVs), which is more accurate and more realistic than the equivalent circuit model of the prior art. And when extracting the parasitic electrical parameters of the equivalent circuit model, the controls "DataAccessComponent", "S-PARAMETERS", "OPTIM" and "GOAL" in the ADS software are used to configure the same parameters as in actual measurement for optimization design, which lays a foundation for more accurate evaluation of the total dose (TID) effect of the through-silicon via (TSV) link.

[0096] Second, the present application combines the effects of radiation on parasitic electrical parameters and material properties, and the number of parasitic electrical parameters and the number of material properties are more comprehensive and more realistic than the prior art, which can more accurately simulate the performance of the through-silicon via (TSV) link under actual radiation conditions and realize the prediction and evaluation of the S parameters of the through-silicon via (TSV) link.

[0097] Thirdly, the application acquires the change of the parasitic electrical parameters in the total dose (TID) effect equivalent circuit with the radiation dose by the ADS software optimization design, fills the technical blank of no fixed equation to calculate the parasitic electrical parameters in the total dose (TID) effect equivalent circuit under the total dose (TID) radiation, provides important guarantee for extracting the correlation equation of the material properties and the radiation dose and further predicting the S parameters of the through silicon via (TSV) link under any radiation dose point.

[0098] In conclusion, the application has comprehensive evaluation factors, is more suitable for the actual irradiation condition, and has the technical effect of more accurately simulating the performance of the through silicon via (TSV) link under the actual radiation condition. BRIEF DESCRIPTION OF DRAWINGS

[0099] Figure 1 is the method flowchart of the application.

[0100] Figure 2 is the through silicon via (TSV) link structure schematic diagram in the embodiment of the application, wherein (a) is the top view of structure one, (b) is the top view of structure two, (c) is the top view of structure three, (d) is the bottom view of structure one, (e) is the bottom view of structure two, (f) is the bottom view of structure three, (g) is the cross-sectional view of structure one, (h) is the cross-sectional view of structure two, and (i) is the cross-sectional view of structure three.

[0101] Figure 3 is the three-dimensional structure diagram of the through silicon via (TSV) link structure in the embodiment of the application, wherein (a) is the three-dimensional diagram of structure one, (b) is the three-dimensional diagram of structure two, and (c) is the three-dimensional diagram of structure three.

[0102] Figure 4 is the division schematic diagram of the total dose (TID) effect equivalent circuit topology structure in the embodiment of the application.

[0103] Figure 5 is the total dose (TID) effect equivalent circuit topology structure diagram constructed in the embodiment of the application.

[0104] Figure 6 is the topology structure diagram of the redistribution layer (RDL) part in the total dose (TID) effect equivalent circuit topology structure diagram constructed in the embodiment of the application.

[0105] Figure 7 is the comparison of the S parameters obtained by simulation of the total dose (TID) effect equivalent circuit topology structure constructed in the embodiment of the application under normal conditions and the S parameters obtained by test measurement.

[0106] Figure 8is a schematic diagram of the required control in the optimization design of ADS software in the embodiment of the present application, wherein 16 represents "DataAccessComponent", 17 represents "S-PARAMETERS", 18 represents "GOAL", and 19 represents "OPTIM".

[0107] Figure 9 is a curve of the variation of the parasitic electrical parameters with the radiation dose extracted in the embodiment of the present application, wherein the left ordinate axis represents the silicon substrate capacitance, and the right ordinate axis represents the silicon substrate resistance.

[0108] Figure 10 is a curve of the variation of the parasitic electrical parameters with the radiation dose extracted in the embodiment of the present application, wherein the left ordinate axis represents the silicon substrate crosstalk capacitance, and the right ordinate axis represents the silicon substrate crosstalk resistance.

[0109] Figure 11 is a curve of the variation of the parasitic electrical parameters with the radiation dose extracted in the embodiment of the present application, wherein the left ordinate axis represents the top RDL capacitance, the bottom RDL capacitance, and the RDL and the silicon substrate interlayer capacitance, and the right ordinate axis represents the TSV inductance, the top RDL inductance, and the bottom RDL inductance.

[0110] Figure 12 is a curve of the variation of the parasitic electrical parameters with the radiation dose extracted in the embodiment of the present application, wherein the left ordinate axis represents the oxide layer capacitance, and the right ordinate axis represents the bump capacitance.

[0111] Figure 13 is a curve equation of the variation of the material properties with the radiation dose fitted in the embodiment of the present application, wherein the left ordinate axis represents the relative dielectric constant of the silicon substrate, and the right ordinate axis represents the conductivity of the silicon substrate.

[0112] Figure 14 is a curve equation of the variation of the material properties with the radiation dose fitted in the embodiment of the present application, wherein the left ordinate represents the relative dielectric constant of the signal TSV interlayer material and the relative dielectric constant of the oxide layer, and the right ordinate axis represents the conductivity of the signal TSV interlayer material.

[0113] In the figure, 1 is a signal through silicon via (TSV), 2 is a ground through silicon via (TSV), 3 is a top layer ground redistribution layer (RDL), 4 is a silicon dioxide layer, 5 is a second polyimide (PI) layer, 6 is a bump, 7 is a top layer signal redistribution layer (RDL), 8 is a top layer oxide isolation layer, 9 is a silicon substrate, 10 is a bottom layer ground redistribution layer (RDL), 11 is a bottom layer signal redistribution layer (RDL), 12 is a bottom layer oxide isolation layer, 13 is a second epoxy molding compound (EMC), 14 is a first polyimide (PI) layer, and 15 is a first epoxy molding compound (EMC). DETAILED DESCRIPTION

[0114] In order to make the purpose, technical solution and advantages of the present application more clear and explicit, the present application is further described in detail below with reference to the accompanying drawings.

[0115] Reference Figure 1 The implementation steps of the embodiment are as follows:

[0116] Step 1: In order to consider the applicability and actual modeling of the through silicon via (TSV), it is crucial to analyze the through silicon via (TSV) channel including not only the through silicon via (TSV) itself, but also the bump and redistribution layer (RDL). In the vertical interconnection of the chip, the bump plays a key role as an indispensable unit, and the redistribution layer (RDL) is crucial in establishing horizontal interconnection and realizing signal redistribution in various chips. Therefore, when designing a link with a through silicon via (TSV), the bump and the redistribution layer (RDL) should be considered simultaneously; according to the actual layout structure of the through silicon via (TSV) link, the through silicon via (TSV) link is divided into four parts: top redistribution layer (RDL), bottom redistribution layer (RDL), through silicon via (TSV) and bump, and the total dose (TID) effect equivalent circuit topology structure of each part is established, then the total dose (TID) effect equivalent circuit topology structures of each part are connected to construct a complete total dose (TID) effect equivalent circuit topology structure of the through silicon via (TSV) link. The equivalent circuit topology structure of the through silicon via (TSV) link constructed in this way not only considers the horizontal interconnection of the top redistribution layer (RDL) and the bottom redistribution layer (RDL), but also considers the vertical interconnection of the bump, and the hierarchy is clear, which lays a foundation for determining the calculation equation of the parasitic electrical parameters in the total dose (TID) effect equivalent circuit in step 2;

[0117] Firstly, a through silicon via (TSV) link is designed as shown in Figure 2 , Figure 3Three kinds of through silicon via (TSV) structures are shown, wherein the planar size of structure one is 1800 μm x 1075 μm, and the planar size of structure two and structure three is 2295 μm x 1075 μm. The bottom layer of the three kinds of through silicon via (TSV) structures is a first epoxy molding compound (EMC) layer 15; a first polyimide (PI) layer 14 is covered on the first epoxy molding compound (EMC) layer 15; the bottom layer is a bottom layer ground redistribution layer (RDL) 10 and a bottom layer signal redistribution layer (RDL) 11 above the polyimide (PI) layer 14, and the bottom layer ground redistribution layer (RDL) 10 and the bottom layer signal redistribution layer (RDL) 11 are isolated by a bottom layer oxide isolation layer 12; a second epoxy molding compound (EMC) layer 13 is above the bottom layer redistribution layer (RDL), and a silicon substrate layer 9 is embedded in the second epoxy molding compound (EMC) layer 13, wherein one silicon substrate layer 9 is embedded in structure one, two silicon substrate layers 9 are embedded in structure two and structure three, two signal through silicon vias (TSV) 1 and a plurality of ground through silicon vias (TSV) 2 are arranged in the silicon substrate layer 9, a silicon dioxide layer 4 is arranged around the signal through silicon via (TSV) 1 and the ground through silicon via (TSV) 2, a top layer ground redistribution layer (RDL) 3 and a top layer signal redistribution layer (RDL) 7 are above the second epoxy molding compound (EMC) layer, and the top layer ground redistribution layer (RDL) 3 and the top layer signal redistribution layer (RDL) 7 are isolated by a top layer oxide isolation layer 8; a bump 6 is arranged between each signal through silicon via (TSV) 1 and ground through silicon via (TSV) 2 and the top layer signal redistribution layer (RDL) 7 and the top layer ground redistribution layer (RDL) 3; and a second polyimide (PI) layer 5 is arranged around the top layer ground redistribution layer (RDL).

[0118] The difference between the three kinds of through silicon via (TSV) structures is that structure one contains one silicon substrate layer 9, so that the filling material between the two signal through silicon vias (TSV) 1 is the silicon substrate layer 9, and structure two and structure three contain two silicon substrate layers 9, so that the filling material between the two signal through silicon vias (TSV) 1 is the second epoxy molding compound (EMC) layer 13. In addition, structure one contains 6 ground through silicon vias (TSV) 2, and structure two and structure three contain 12 ground through silicon vias (TSV) 2. The center distance between the two signal through silicon vias (TSV) 1 in structure one and structure three is 500 μm, and the center distance between the two signal through silicon vias (TSV) 1 in structure two is 1000 μm.

[0119] According to the design of the three kinds of TSV structures as shown in Figure 2 and Figure 3 , a general equivalent circuit topology structure of the three kinds of TSV links is constructed, and the following is achieved:

[0120] Referring to Figure 4The equivalent circuit topology is divided into four parts: top redistribution layer (RDL), bottom redistribution layer (RDL), through-silicon vias (TSVs), and bumps. The overall topology is as follows: Figure 5 As shown;

[0121] Top-level redistribution layer (RDL):

[0122] Reference Figure 6 The top-level signal redistribution layer (RDL) 7 is equivalent to a resistor R. RDL_Top and inductor L RDL_Top The capacitance between the top-level signal redistribution layer (RDL) 7 and the top-level ground redistribution layer (RDL) 3 is equivalent to C. RDL_Top Capacitor C RDL_Top The resistor R is connected in parallel to the top signal redistribution layer (RDL) 7. RDL_Top Inductor L RDL_Top The equivalent capacitance between the top ground redistribution layer (RDL) 3 and the top signal redistribution layer (RDL) 7, and between the top ground redistribution layer (RDL) 3 and the silicon substrate 9 is C. Fill Capacitor C Fill The resistor R connected in series in the top redistribution layer (RDL) 7 RDL_Top Inductor L RDL_Top The equivalent resistance between the top ground redistribution layer (RDL) 3 and the top signal redistribution layer (RDL) 7 and the silicon substrate 9 is R. Si_RDL resistance R Si_RDL Connected in parallel to capacitor C Fill between;

[0123] The underlying redistribution layer (RDL) section:

[0124] See Figure 6 The underlying signal redistribution layer (RDL) 11 is equivalent to a resistor R. RDL_Bot and inductor L RDL_Bot The series connection between the bottom signal redistribution layer (RDL) 11 and the bottom ground redistribution layer (RDL) 10 has an equivalent capacitance of C. RDL_Bot Capacitor C RDL_Bot It is connected in parallel between the bottom signal redistribution layer (RDL) 11 and the bottom ground redistribution layer (RDL) 10;

[0125] Through-Silicon Vias (TSV) section:

[0126] See Figure 5 The signal through-silicon via (TSV) 1 is equivalent to a resistor R. TSV and inductor L TSV The series connection, the oxide layer around the signal through silicon via (TSV) 1 is equivalent to C oxs Oxide layer capacitance C oxs Parallel to resistor RTSV and inductance L TSV The oxide around the TSV 2 in parallel with the capacitance C oxg The oxide capacitance C oxg The silicon substrate between the single signal TSV 1 and its surrounding single ground TSV 2 in parallel with the resistance R Si and C Si The crosstalk between adjacent signal TSV 1 in parallel with the resistance R Si_noise and C Si_noise in parallel between adjacent signal TSV 1 ;

[0127] Bump part:

[0128] Referring to Figure 5 The bump 6 in parallel with the resistance R Bump and inductance L Bump The capacitance between the single signal bump 6 and its surrounding ground bump 6 in parallel with the capacitance C Bump .

[0129] Step 2: Determine the calculation equation of the parasitic electrical parameters in the total ionizing dose (TID) effect equivalent circuit to calculate the value of the parasitic electrical parameters in the equivalent circuit under normal conditions, provide data support for comparing the calculation results of the parasitic electrical parameters in the equivalent circuit under normal conditions with the simulation results in step 3, and lay the foundation for substituting the equation of the fitted material property value changing with the radiation dose into the calculation equation of the parasitic electrical parameters and simulating the total ionizing dose (TID) effect equivalent circuit in the ADS software in step 7 to predict the S parameter of the TSV link at any radiation dose point;

[0130] According to the equivalent circuit topology established in step 1, referring to Figure 5 and Figure 6 The calculation equation of the parasitic electrical parameters in the total ionizing dose (TID) effect equivalent circuit is as follows:

[0131] Top RDL part:

[0132] Top RDL resistance:

[0133] Top RDL DC resistance:

[0134] Top RDL AC resistance:

[0135] Top RDL skin depth:

[0136] Top RDL inductance:

[0137] Top RDL capacitance:

[0138] Top RDL to silicon substrate via fill material capacitance:

[0139] First class full elliptic integral parameter for fill material capacitance:

[0140] Top RDL to silicon substrate via penetration resistance:

[0141] Top RDL to silicon substrate via penetration conductivity:

[0142] Top RDL to silicon substrate via penetration depth:

[0143] where t is the thickness of the top RDL, s is the width of the insulating material between the top signal RDL and the ground RDL, l is the length of the single ended top RDL, ω is the width of the top RDL, h is the height of the fill material between the top RDL and the silicon substrate, h is the height of the bump, h is the height of the silicon substrate, p is the resistivity of the top RDL material, μ is the permeability of the top RDL material, f is the frequency, σ is the conductivity of the top RDL material, μ0 is the vacuum permeability, ε is the relative permittivity of the oxide layer, ε0 is the vacuum permittivity, σ is the silicon substrate conductivity. RDL_Top RDL_Top RDL_Top RDL_Top Fill Bump Si RDL_Top RDL_Top RDL_Top ox Si

[0144] Bottom RDL portion:

[0145] Bottom RDL resistance:

[0146] ​​​​​​​​​​​​Bottom RDL DC resistance:

[0147] Bottom RDL AC resistance:

[0148] Bottom RDL skin depth:

[0149] Bottom RDL inductance:

[0150] Bottom RDL capacitance:

[0151] where t RDL_Bot is the thickness of the bottom RDL, s RDL_Bot is the width of the insulating material between the bottom signal RDL and the ground RDL, l RDL_Bot is the length of the bottom RDL, ω RDL_Bot is the width of the bottom RDL, p RDL_Bot is the resistivity of the bottom RDL material, m RDL_Bot is the permeability of the bottom RDL material, s RDL_Bot is the conductivity of the bottom RDL material;

[0152] TSV portion:

[0153] TSV resistance:

[0154] TSV DC resistance:

[0155] TSV AC resistance:

[0156] TSV skin depth:

[0157] TSV proximity factor:

[0158] TSV inductance:

[0159] Signal TSV oxide layer capacitance:

[0160] Ground TSV oxide layer capacitance: C oxg = 1.5 x C oxs ;

[0161] Silicon substrate capacitance between signal through silicon via (TSV) and ground TSV:

[0162] Silicon substrate resistance between signal through silicon via (TSV) and ground TSV:

[0163] Cross-talk capacitance between signal through silicon via (TSV) and signal TSV:

[0164] Cross-talk resistance between signal through silicon via (TSV) and signal TSV:

[0165] where h TSV is the through silicon via (TSV) height, r TSV is the through silicon via (TSV) radius, d TSV is the through silicon via (TSV) diameter, p TSV is the through silicon via (TSV) material resistivity, s TSV is the through silicon via (TSV) material conductivity, p TSV is the through silicon via (TSV) material permeability, p TSV is the minimum center distance between a single signal through silicon via (TSV) and its surrounding single ground through silicon via (TSV), p STSV is the center distance between two signal through silicon vias (TSVs), t ox is the oxide layer thickness, s Si is the silicon substrate permittivity, s Si is the silicon substrate material conductivity, s Fill is the relative permittivity of the filling material between signal through silicon vias (TSVs), s Fill is the conductivity of the filling material between signal through silicon vias (TSVs);

[0166] Bump portion:

[0167] Bump resistance:

[0168] Bump direct current resistance:

[0169] Bump alternating current resistance:

[0170] Bump skin depth:

[0171] Bump proximity factor:

[0172] bump inductors:

[0173] Capacitance between the signal bump and the ground bump:

[0174] Among them, h Bump r is the height of the bump. Bump Let d be the radius of the bump. Bump p is the diameter of the bump. Bump ρ is the center distance between bumps. Bump The resistivity of the bump material is σ. Bump The conductivity of the bump material is expressed in μ. Bump ε is the permeability of the bump material. fill It is the dielectric constant of the material filling the space between the bumps.

[0175] See Figure 2 In TSV (Through Silicon Via) link structures one and three, the sum of the center distances between a single signal TSV 1 and its single-sided ground TSV 2 is: In structure 2, the sum of the center distances between a single signal through-silicon via (TSV) 1 and its single-sided ground through-silicon via (TSV) 2 is: Therefore, in calculation Figure 5 Silicon substrate capacitor C Si At that time, for structure one and structure three, there is For structure two, then we have calculate Figure 5 The silicon substrate resistor R Si At that time, for structure one and structure three, there is For structure two, then we have

[0176] Step 3: To verify the total dose (TID) effect equivalent circuit model under normal conditions, and to provide a prerequisite for optimizing the design in ADS in Step 4 to extract the values ​​of parasitic electrical parameters under total dose (TID) radiation, the values ​​of parasitic electrical parameters under normal conditions are calculated using the calculation equations determined in Step 2. The calculated values ​​of parasitic electrical parameters are then substituted into the complete total dose (TID) effect equivalent circuit topology constructed in Step 1 to obtain the total dose (TID) effect equivalent circuit model. The total dose (TID) effect equivalent circuit model is then simulated to obtain S-parameters. When the average relative error between the simulated S-parameters and the actual measured S-parameters under normal conditions is less than or equal to the expected value Error, the total dose (TID) effect equivalent circuit model is usable, and Step 4 is continued.

[0177] The physical size and material properties of the through-silicon via (TSV) link are substituted into the calculation equation in step 2 to obtain the values of the electrical parameters under normal conditions, the total dose (TID) effect equivalent circuit topology in step 1 is constructed in the ADS software, and the calculated electrical parameters are substituted into the total dose (TID) effect equivalent circuit topology to start simulation;

[0178] The simulation obtained S parameters are viewed in the simulation results of the ADS software, and the results are saved, the simulation obtained S parameters and the actually measured S parameters are plotted as shown in Figure 7 The average relative error of the simulation results and the actual results of the S parameters in the entire frequency range is calculated, Figure 7 The average relative deviation of the simulation obtained S parameters and the test measured S parameters in the entire frequency range is: 22.9% for structure one, 27.8% for structure two, and 15.9% for structure three, all less than the expected value 50%;

[0179] If the average relative error is less than or equal to the expected value Error, the total dose (TID) effect equivalent circuit model is qualified under normal conditions, and can be used for subsequent operations, and step 4 is performed;

[0180] If the average relative error is greater than the expected value Error, the total dose (TID) effect equivalent circuit model is unqualified under normal conditions, and the total dose (TID) effect equivalent circuit topology and the electrical parameter calculation equation need to be adjusted according to the specific through-silicon via (TSV) link structure.

[0181] Step 4: The total dose (TID) effect equivalent circuit model has been verified under normal conditions in step 3, however, the parasitic electrical parameters in the equivalent circuit will change under the influence of total dose (TID) radiation, and there is no fixed equation to accurately calculate these change values. In order to quantitatively analyze the influence of total dose (TID) radiation on the electrical parameters of the through-silicon via (TSV) channel, the optimization design of the total dose (TID) effect equivalent circuit model is implemented in the ADS software, the S parameters corresponding to each radiation dose actually measured are taken as the optimization target, and the optimization algorithm built in the ADS software is used to iteratively adjust the parasitic electrical parameters in the total dose (TID) effect equivalent circuit, so that the difference between the simulation S parameters of the total dose (TID) effect equivalent circuit and the actually measured S parameters is minimized;

[0182] The total dose (TID) effect equivalent circuit topology established in step 1 is built in the ADS software, as shown in Figure 8As shown, the control "DataAccessComponent" 16, "S-PARAMETERS" 17, "OPTIM" 18 and "GOAL" 19 are added, the S parameter files measured at each dose point are read in the control "DataAccessComponent" 16, the start and end frequencies and step length of the S parameters are set in the control "S-PARAMETERS" 17, the optimization algorithm and iteration number are set in the control "OPTIM" 19, and the difference between the S parameters measured in the experiment and the S parameters obtained by simulation of the equivalent circuit is set as the optimization target in the control "GOAL" 18.

[0183] Step 5: Perform the optimization design in step 4, extract the parasitic electrical parameters in the equivalent circuit of total ionizing dose (TID) effect under each radiation dose condition, draw the curve of the parasitic electrical parameters changing with the radiation dose, and obtain the change of the parasitic electrical parameters in the through silicon via (TSV) link under the total ionizing dose (TID) radiation condition.

[0184] The S parameter files actually measured under each radiation dose condition are loaded in the control "DataAccessComponent" 16 added in step 4, the optimization design is performed, the parasitic electrical parameters under each radiation dose condition are obtained, and the curve of each parasitic electrical parameter changing with the radiation dose is drawn in the Matlab software, as shown in Figure 9 , Figure 10 , Figure 11 , Figure 12 The S parameters under four dose points of 0krad(Si), 60krad(Si), 120krad(Si) and 180krad(Si) are measured in the experiment, wherein 0krad(Si) is the normal condition.

[0185] The measurement results show that the silicon substrate capacitance, silicon substrate resistance, crosstalk capacitance, crosstalk resistance, top redistribution layer (RDL) capacitance, bottom redistribution layer (RDL) capacitance, filling material capacitance, through silicon via (TSV) inductance, top redistribution layer (RDL) inductance, bottom redistribution layer (RDL) inductance, oxide layer capacitance and bump capacitance of the through silicon via (TSV) link changing with the radiation dose can be obtained by using the present application, which lays a data foundation for extracting the change equation of the material properties with the radiation dose.

[0186] Step 6: All parasitic electrical parameters in the total dose (TID) effect equivalent circuit of the through silicon via (TSV) link have the size parameters of the through silicon via (TSV) radius, through silicon via (TSV) height or through silicon via (TSV) pitch, and the material parameters of relative permittivity and conductivity, and the total dose (TID) radiation generally does not cause mechanical stress, so the through silicon via (TSV) size parameters do not change, and only the material properties change; therefore, based on the change curves of the parasitic electrical parameters with the radiation dose drawn in step 5, according to the calculation equations of the parasitic electrical parameters determined in step 2, the material property values of the through silicon via (TSV) link under each radiation dose condition are extracted, and a polynomial fitting is used to obtain the equation of the change of the material property value with the radiation dose;

[0187] According to the parasitic electrical parameters in the total dose (TID) effect equivalent circuit under each radiation dose condition extracted in step 5, combined with the calculation equations of the parasitic electrical parameters determined in step 2, the material property values in the calculation equations of the parasitic electrical parameters are inversely deduced, to obtain the material property values under each radiation dose condition, and a polynomial fitting method is used in the Matlab software to obtain the equation of the change of the material property with the radiation dose, as shown in Figure 13 and Figure 14

[0188] Relative permittivity of the silicon substrate: ε Si = 2.569 × 10 -6 dose 2 + 2.858 × 10 -4 dose + 11.9;

[0189] Conductivity of the silicon substrate: σ Si = -1.389 × 10 -6 dose 2 - 1.217 × 10 -3 dose + 10;

[0190] Relative permittivity of the filling material: ε fill = 4.861 × 10 -6 dose 2 + 4.417 × 10 -4 dose + 3.7;

[0191] Relative permittivity of the oxide layer: ε ox = 1.73 × 10 -5 dose 2 + 2.458 × 10 -3 dose + 4;

[0192] Conductivity of the filling material: σ fill = -6.944 × 10 -11 dose 2 ​-1.858 x 10 -7 dose+0.1;

[0193] wherein dose is the radiation dose, ε Si is the relative permittivity of the silicon substrate, σ Si is the conductivity of the silicon substrate, ε fill is the relative permittivity of the filling material, ε ox is the relative permittivity of the oxide layer, σ fill is the conductivity of the filling material.

[0194] The above calculation results show that: through the present application, five material properties, i.e. the relative permittivity of the silicon substrate, the conductivity of the silicon substrate, the relative permittivity of the filling material, the relative permittivity of the oxide layer and the conductivity of the filling material, can be obtained as a polynomial equation varying with the radiation dose. This provides guarantee for calculating the value of the parasitic electrical parameter in the total dose (TID) effect equivalent circuit of the through silicon via (TSV) link at any radiation dose point, and further predicting the S parameter of the through silicon via (TSV) at any radiation dose point, and fills the technical blank of the calculation of the parasitic electrical parameter in the equivalent circuit under the influence of the total dose (TID) radiation;

[0195] Step 7: substituting the equation of the material property value varying with the radiation dose obtained in step 6 into the parasitic electrical parameter calculation equation determined in step 2, constructing the parasitic electrical parameter calculation equation in the equivalent circuit at any radiation dose, simulating the total dose (TID) effect equivalent circuit in the ADS software, and predicting the S parameter of the through silicon via (TSV) link at any radiation dose point.

[0196] Substituting the equation of the material property value varying with the radiation dose obtained in step 6 into the parasitic electrical parameter calculation equation determined in step 2, obtaining the radiation-related parasitic electrical parameter calculation equation, substituting any radiation dose value according to the requirement, calculating the corresponding parasitic electrical parameter and performing simulation, and predicting the S parameter of the through silicon via (TSV) link at any radiation dose point.

[0197] A through silicon via link total dose (TID) effect evaluation device based on an equivalent circuit model, comprising:

[0198] a memory: for storing a computer program for implementing a through silicon via link total dose (TID) effect evaluation method based on an equivalent circuit model;

[0199] a processor: for implementing a through silicon via link total dose (TID) effect evaluation method based on an equivalent circuit model when the computer program is executed.

[0200] The application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the TSV link total dose (TID) effect evaluation method based on an equivalent circuit model.

[0201] In summary, compared with the total dose effect modeling method for microsystem three-dimensional interconnection structure transmission high-frequency signal of CN114595521A, the method of the application not only considers the TSV resistance and oxide layer capacitance, but also considers the silicon substrate capacitance and conductance, the capacitance and inductance of the redistribution layer (RDL), the capacitance and inductance of the bump, and the crosstalk effect between the signal TSVs. In addition, compared with the analysis method for the change of TSV structure material performance caused by total dose effect of CN114878921A, the method of the application not only considers the influence of total dose (TID) radiation on the dielectric constant of silicon and silicon dioxide, but also considers the influence of total dose (TID) radiation on the conductivity of silicon, the dielectric constant and conductivity of the filling material.

[0202] The above is only a specific embodiment of the application, but the protection scope of the application is not limited thereto, and any modification, equivalent replacement and improvement made by those skilled in the art within the technical range disclosed by the application and within the spirit and principle of the application shall be covered within the protection scope of the application.

Claims

1. A method for evaluating the total dose effect of through-silicon via (TSV) links based on an equivalent circuit model, characterized in that, Includes the following steps: Step 1: Based on the actual layout structure of the through-silicon via (TSV) link, divide the TSV link into four parts: top redistribution layer (RDL), bottom redistribution layer (RDL), TSV, and bump. Establish the total dose (TID) effect equivalent circuit topology for each part, and then connect the total dose (TID) effect equivalent circuit topology for each part to construct the complete total dose (TID) effect equivalent circuit topology for the TSV link. Step 2: Determine the calculation equations for parasitic electrical parameters in the equivalent circuit of the total dose (TID) effect; Step 3: Calculate the values ​​of parasitic electrical parameters under normal conditions using the calculation equations determined in Step 2, and substitute the calculated parasitic electrical parameter values ​​into the complete total dose (TID) effect equivalent circuit topology constructed in Step 1 to obtain the total dose (TID) effect equivalent circuit model. Then, simulate the total dose (TID) effect equivalent circuit model to obtain S-parameters. When the average relative error between the simulated S-parameters and the actual measured S-parameters under normal conditions is less than or equal to the expected value Error, the total dose (TID) effect equivalent circuit model is usable, and continue to Step 4. Step 4: Implement the optimization design of the total dose (TID) effect equivalent circuit model in ADS software. Taking the S-parameters corresponding to each radiation dose obtained by actual measurement as the optimization target, the optimization algorithm built into ADS software is used to iteratively adjust the parasitic electrical parameters in the total dose (TID) effect equivalent circuit to minimize the difference between the simulated S-parameters and the actual measured S-parameters of the total dose (TID) effect equivalent circuit. Step 5: Perform the optimization design in Step 4, extract the parasitic electrical parameters in the equivalent circuit of the total dose (TID) effect under each radiation dose condition, and plot the curves of parasitic electrical parameters as a function of radiation dose; Step 6: Based on the curves of parasitic electrical parameters as a function of radiation dose plotted in Step 5, extract the material property values ​​of the through silicon via (TSV) links under each radiation dose condition according to the calculation equations of each parasitic electrical parameter determined in Step 2, and use polynomial fitting to obtain the equations of material property values ​​as a function of radiation dose. Step 7: Substitute the equation of material property values ​​obtained in Step 6 as a function of radiation dose into the equation for calculating parasitic electrical parameters determined in Step 2, simulate the equivalent circuit of total dose (TID) effect in ADS software, and predict the S-parameters of the through silicon via (TSV) link at any radiation dose point.

2. The method for evaluating the total dose effect of a through-silicon via (TSV) link based on an equivalent circuit model according to claim 1, characterized in that, The equivalent circuit topology of the total dose (TID) effect for each part in step 1 is as follows: Top-level redistribution layer (RDL) section: The top-level signal redistribution layer (RDL) is equivalent to a resistor R. RDL_Top and inductor L RDL_Top The series connection between the top-level signal redistribution layer (RDL) and the top-level ground redistribution layer (RDL) has an equivalent capacitance of C. RDL_Top Capacitor C RDL_Top The resistor R is connected in parallel to the top redistribution layer (RDL). RDL_Top Inductor L RDL_Top The equivalent capacitance between the top ground redistribution layer (RDL) and the top signal redistribution layer (RDL), and between the top ground redistribution layer (RDL) and the silicon substrate is C. Fill Capacitor C Fill The resistor R connected in series in the top redistribution layer (RDL) RDL_Top Inductor L RDL_Top The resistance between the top ground redistribution layer (RDL) and the silicon substrate is equivalent to R. Si_RDL resistance R Si_RDL Connected in parallel to capacitor C Fill between; The underlying redistribution layer (RDL) section: The underlying signal redistribution layer (RDL) is equivalent to a resistor R. RDL_Bot and inductor L RDL_Bot In series, the capacitance between the bottom signal redistribution layer (RDL) and the bottom ground redistribution layer (RDL) is equivalent to C. RDL_Bot Capacitor C RDL_Bot It is connected in parallel between the underlying signal redistribution layer (RDL) and the underlying ground redistribution layer (RDL); Through-Silicon Vias (TSV) section: A signal through-silicon via (TSV) is equivalent to a resistor R. TSV and inductor L TSV The series connection, the oxide layer around the signal through silicon via (TSV) is equivalent to C oxs Oxide layer C oxs Parallel to resistor R TSV and inductor L TSV At both ends, the oxide layer around the through-silicon via (TSV) is equivalent to C. oxg Oxide layer C oxg Connected in parallel across the two ends of a through-silicon via (TSV), the silicon substrate between a single signal TSV and its surrounding individual TSVs is equivalent to a silicon substrate resistance R. Si and silicon substrate capacitor C Si The signal via (TSV) and the ground via (TSV) are connected in parallel. The crosstalk between adjacent signal vias (TSVs) is equivalent to the crosstalk resistance R. Si_noise and crosstalk capacitor C Si_noise The parallel connection is between adjacent signal through silicon vias (TSVs); Bump section: A bump is equivalent to a resistor R. Bump and inductor L Bump In a series configuration, the capacitance between a single signal bump and its surrounding ground bumps is equivalent to C. Bump .

3. The method for evaluating the total dose effect of a through-silicon via (TSV) link based on an equivalent circuit model according to claim 1, characterized in that, The equations for calculating the parasitic electrical parameters in the equivalent circuit of the total dose (TID) effect described in step 2 are as follows: Top-level redistribution layer (RDL) section: Top redistribution layer (RDL) resistor: Top redistribution layer (RDL) DC resistance: Top redistribution layer (RDL) AC resistance: Skin depth of top redistribution layer (RDL): Top redistribution layer (RDL) inductor: Top redistribution layer (RDL) capacitor: Capacitance of the fill material between the top redistribution layer (RDL) and the silicon substrate: The first-order complete elliptic integral parameters of the filled material capacitor are: Transmission resistance between the top redistribution layer (RDL) and the silicon substrate: Transmission conductivity between the top redistribution layer (RDL) and the silicon substrate: Penetration depth between the top redistribution layer (RDL) and the silicon substrate: Among them, t RDL_Top The thickness of the top redistribution layer (RDL), s RDL_Top The width of the insulating material between the top signal redistribution layer (RDL) and the ground redistribution layer (RDL), l RDL_Top ω is the length of the single-ended top redistribution layer (RDL). RDL_Top h is the width of the top redistribution layer (RDL). Fill h is the height of the fill material between the top redistribution layer (RDL) and the silicon substrate. Bump h is the height of the bump. Si ρ is the height of the silicon substrate. RDL_Top The resistivity of the top redistribution layer (RDL) material, μ RDL_Top σ is the permeability of the top redistribution layer (RDL) material, f is the frequency, and σ is the magnetic permeability. RDL_Top The conductivity of the top redistribution layer (RDL) material is μ0, the permeability of free space is μ0, and ε is ε. ox ε0 is the relative permittivity of the oxide layer, ε0 is the vacuum permittivity, and σ0 is the relative permittivity of the oxide layer. Si The conductivity of the silicon substrate; The underlying redistribution layer (RDL) section: Underlying redistribution layer (RDL) resistor: DC resistance of the bottom redistribution layer (RDL): AC resistance of the bottom redistribution layer (RDL): Skin depth of the underlying redistribution layer (RDL): Lowest redistribution layer (RDL) inductor: Underlying redistribution layer (RDL) capacitors: Among them, t RDL_Bot The thickness of the underlying redistribution layer (RDL), s RDL_Bot The width of the insulating material between the bottom signal redistribution layer (RDL) and the ground redistribution layer (RDL), l RDL_Bot ω is the length of the underlying redistribution layer (RDL). RDL_Bot ρ is the width of the underlying redistribution layer (RDL). RDL_Bot The resistivity of the underlying redistribution layer (RDL) material, μ RDL_Bot σ represents the magnetic permeability of the underlying redistribution layer (RDL) material. RDL_Bot The conductivity of the underlying redistribution layer (RDL) material; Through-Silicon Vias (TSV) section: Through-Silicon Via (TSV) Resistors: Through-Silicon Via (TSV) DC Resistance: Through-Silicon Via (TSV) AC Resistance: Through-Silicon Via (TSV) Skin Depth: Through-Silicon Via (TSV) Proximity Factor: Through-Silicon Via (TSV) Inductors: Through-Silicon Via (TSV) Oxide Capacitance: Through-Silicon Via (TSV) Oxide Capacitance: C oxg =1.5×C oxs ; Silicon substrate capacitance between signal through-silicon via (TSV) and ground TSV: Silicon substrate resistance between signal through-silicon via (TSV) and ground through-silicon via (TSV): Crosstalk capacitance between signal through silicon vias (TSVs): Crosstalk resistance between signal through silicon vias (TSVs): Among them, h TSV r is the height of the through silicon via (TSV). TSV Where d is the radius of the through silicon via (TSV). TSV ρ is the diameter of the through-silicon via (TSV). TSV The resistivity of the through-silicon via (TSV) material is σ. TSV The conductivity of the through-silicon via (TSV) material is expressed in μ. TSV p represents the magnetic permeability of the through-silicon via (TSV) material. TSV p is the minimum center-to-center distance between a single signal via (TSV) and its surrounding single ground via (TSV). STSV t is the center distance between two signal through silicon vias (TSVs). ox ε represents the oxide layer thickness. Si σ is the dielectric constant of the silicon substrate. Si ε is the conductivity of the silicon substrate material. Fill σ is the relative permittivity of the filling material between signal through-silicon vias (TSVs). Fill The conductivity of the filling material between signal through silicon vias (TSVs); Bump section: Bump resistor: Bump DC resistance: Bump AC resistor: Bump skin depth: Bump proximity coefficient: bump inductors: Capacitance between the signal bump and the ground bump: Among them, h Bump r is the height of the bump. Bump Let d be the radius of the bump. Bump p is the diameter of the bump. Bump ρ is the center distance between bumps. Bump The resistivity of the bump material is σ. Bump The conductivity of the bump material is expressed in μ. Bump ε is the permeability of the bump material. fill It is the dielectric constant of the material filling the space between the bumps.

4. The method for evaluating the total dose effect of a through-silicon via (TSV) link based on an equivalent circuit model according to claim 1, characterized in that, Step 3 specifically includes: Substitute the physical dimensions and material properties of the through-silicon via (TSV) link into the calculation equation in step 2 to obtain the values ​​of each electrical parameter under normal conditions. Construct the equivalent circuit topology of the total dose (TID) effect in step 1 in ADS software, and substitute the calculated electrical parameters into the equivalent circuit topology of the total dose (TID) effect to start the simulation. View the simulated S-parameters in the simulation results of ADS software and save the results. Plot the simulated S-parameters and the actual measured S-parameters in Matlab software, and calculate the average relative error between the simulation results and the actual results of S-parameters over the entire frequency range. If the average relative error is less than or equal to the expected value Error, then the total dose (TID) effect equivalent circuit model has been verified under normal conditions and can be used for subsequent operations. Proceed to step 4. If the average relative error is greater than the expected value Error, the total dose (TID) effect equivalent circuit model fails the verification under normal conditions. The total dose (TID) effect equivalent circuit topology and electrical parameter calculation equations need to be adjusted according to the specific through-silicon via (TSV) link structure.

5. The method for evaluating the total dose effect of a through-silicon via (TSV) link based on an equivalent circuit model according to claim 1, characterized in that, Step 4 specifically includes: In ADS software, construct the total dose (TID) effect equivalent circuit topology established in step 1, and add the controls "DataAccessComponent", "S-PARAMETERS", "OPTIM" and "GOAL". In the "DataAccessComponent" control, read the S-parameter file obtained from each dose point measurement. In the "S-PARAMETERS" control, set the start and end frequencies and step size of the S-parameters. In the "OPTIM" control, set the optimization algorithm and number of iterations. In the "GOAL" control, set the difference between the experimentally measured S-parameters and the S-parameters obtained from the equivalent circuit simulation as the optimization target.

6. The method for evaluating the total dose effect of a through-silicon via (TSV) link based on an equivalent circuit model according to claim 5, characterized in that, Step 5 specifically includes: First, load the S-parameter files actually measured under each radiation dose condition into the "DataAccessComponent" control added in step 4, perform optimization design, obtain the parasitic electrical parameters under each radiation dose condition, and then plot the curves of each parasitic electrical parameter with radiation dose in Matlab software.

7. The method for evaluating the total dose effect of a through-silicon via (TSV) link based on an equivalent circuit model according to claim 1, characterized in that, Step 6 specifically includes: Based on the parasitic electrical parameters in the equivalent circuit of the total dose (TID) effect under each radiation dose condition extracted in step 5, and combined with the parasitic electrical parameter calculation equation determined in step 2, the material property values ​​in the parasitic electrical parameter calculation equation are derived in reverse, thus obtaining the material property values ​​under each radiation dose condition. Using a polynomial fitting method in Matlab software, the equations for the material properties changing with radiation dose are obtained: Relative permittivity of silicon substrate: ε Si =a n dose n +a n-1 dose n-1 +...+a0; Conductivity of silicon substrate: σ Si =b n dose n +b n-1 dose n-1 +...+b0; Relative permittivity of the filler material: ε fill =c n dose n +c n-1 dose n-1 +...+c0; Relative permittivity of oxide layer: ε ox =m n dose n +m n-1 dose n-1 +...+m0; Electrical conductivity of filler material: σ fill =z n dose n +z n-1 dose n-1 +...+z0; Where, dose is the radiation dose, ε Si σ is the relative permittivity of the silicon substrate. Si ε is the conductivity of the silicon substrate. fill ε is the relative permittivity of the filling material. ox σ is the relative permittivity of the oxide layer. fill Let a be the electrical conductivity of the filling material, 0,...,n-1, and n be the degree of the polynomial, and a0,...,a n-1 ,a n ,b0,...b n-1 ,b n ,c0,...c n-1 ,c n ,m0,...m n-1 ,m n ,z0,...z n-1 ,z n These are the polynomial coefficients.

8. The method for evaluating the total dose effect of a through-silicon via (TSV) link based on an equivalent circuit model according to claim 1, characterized in that, Step 7 specifically includes: Substitute the equation for the material property values ​​obtained in step 6 as a function of radiation dose into the equation for calculating parasitic electrical parameters determined in step 2 to obtain the equation for calculating radiation-related parasitic electrical parameters. Substitute any radiation dose value as required to calculate the corresponding parasitic electrical parameters and perform simulation to predict the S-parameters of the through-silicon via (TSV) link at any radiation dose point.

9. A device for assessing the total dose (TID) effect of a through-silicon via (TSV) link based on an equivalent circuit model, characterized in that, include: Memory: for storing a computer program that implements the method for evaluating the total dose (TID) effect of a through-silicon via link based on an equivalent circuit model as described in any one of claims 1 to 8; Processor: Used to implement, when executing the computer program, a method for evaluating the total dose (TID) effect of a through-silicon via (TSV) link based on an equivalent circuit model as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for evaluating the total dose (TID) effect of a through-silicon via link based on an equivalent circuit model.

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