Calibration Method, Device and Storage Medium for Floating-Gate Memory TCAD Simulation Model

Abstract

The present invention discloses a calibration method, device and storage medium for a floating gate memory TCAD simulation model. An actual floating gate memory and a corresponding TCAD simulation model are built for the floating gate memory; then the simulation model is calibrated; by adding a capacitor between the control gate and the floating gate of the floating gate memory, the capacitive coupling ratio between the control gate and the floating gate is finely adjusted, the fixed charge parameters of the oxide layer during the programming and erasing processes of the device are calibrated, the mobility model parameters and the interface state parameters are calibrated, and electrical property test calibration is achieved; by calibrating the distribution of Si / SiO2 interface states, bulk oxide traps and near-interface oxide traps, reliability test calibration is achieved. The method of the present invention significantly improves the expression accuracy of the TCAD simulation model.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and relates to a calibration method, device and storage medium for a TCAD simulation model of a floating-gate memory. Background Art

[0002] In modern automobiles, local real-time electrical control and real-time processing of sensor data are carried out. With the introduction of electrical control in the automotive control system, there are more than 200 flash memory MCUs in each vehicle. With the growth of demand, the performance requirements for automotive MCU embedded flash memory are also increasing. A new type of split-gate charge storage floating-gate memory Flash-EEPROM (electrically erasable programmable read-only memory) structure with good anti-interference characteristics, data retention and durability is proposed. This structure has comprehensive advantages when applied to the automotive electronics market for embedded MCUs.

[0003] Based on the process flow and electrical analysis of the new split-gate memory, TCAD simulations are carried out on high-end memories, and their reliability, mainly including durability and data retention, has been widely studied. TCAD is a physics-based numerical simulation method that can accurately simulate the manufacturing process and electrical characteristics of microelectronic devices. Among them, the simulation of TCAD is based on physical calculations and various process models and device model theories such as various physical mechanisms, finite element analysis, partial differential equations, etc. It is equivalent to realizing theoretical process experiments and device manufacturing experiments on the software platform side. In actual process development, it is also often used to accurately adjust and optimize semiconductor device structures and processes to achieve the best combination of speed, mass production, leakage and reliability. However, there is currently a lack of a calibration method applicable to all floating-gate memory simulation models, and the calibration is cumbersome, time-consuming and has low accuracy. Summary of the Invention

[0004] The purpose of the present invention is to propose a calibration method, device and storage medium for a TCAD simulation model of a floating-gate memory in view of the deficiencies of the prior art.

[0005] In a first aspect, the present invention provides a calibration method for a TCAD simulation model of a floating-gate memory, and the method includes:

[0006] Step S1: Complete the layout design of the floating-gate memory and perform actual wafer processing to obtain an actual floating-gate memory; perform electrical performance tests on the actual floating-gate memory to obtain actual test data;

[0007] Step S2: Import the layout design file of the floating-gate memory into a TCAD tool to perform process modeling of the floating-gate memory to obtain a simulation model; then perform electrical performance tests on the simulation model to obtain simulation test data; then use the actual test data in Step S1 to calibrate the simulation test data;

[0008] The calibration includes electrical test calibration and reliability test calibration;

[0009] The electrical test calibration specifically is:

[0010] First, by adding a capacitor between the control gate and the floating gate of the floating-gate memory, the capacitive coupling ratio between the control gate and the floating gate is finely adjusted until it matches the actual floating-gate memory;

[0011] Second, the fixed charge parameters of the oxide layer during the programming and erasing processes of the device are calibrated until the simulated threshold voltage value of the simulation model matches the actual threshold voltage value of the actual floating-gate memory;

[0012] Finally, the mobility model parameters and interface state parameters are calibrated until the simulated test data of the programming and erasing windows match the actual test data;

[0013] The mobility model parameters and interface state parameters are calibrated until the simulated IV curve value of the simulation model after programming and erasing operations has a higher fitting degree than the actual IV curve value of the actual floating-gate memory, and the simulated working window value of the programming and erasing operation simulation model matches the actual working window value of the actual floating-gate memory;

[0014] The reliability test calibration specifically is:

[0015] By calibrating the distribution of Si / SiO2 interface states, bulk oxide traps, and near-interface oxide traps until the simulation model matches the actual floating-gate memory.

[0016] Preferably, the programming operation in the working state of the simulation model device is realized through the hydrodynamic model of carrier transport and the spherical harmonic function expansion distribution of channel hot carrier injection. The defects generated by channel hot carrier injection are mainly distributed in the drain region and the near-drain region. The defects generated by channel hot carrier injection include Si / SiO2 interface states, bulk oxide traps (for holes and electrons), and near-interface oxide traps.

[0017] Preferably, the erasing operation in the working state of the simulation model device is realized through the non-local tunneling model.

[0018] Preferably, the degradation principle of the simulation model device is verified through the interface traps generated by the breaking of Si-H bonds at the Si / SiO2 interface under the action of high electric fields during the tunneling process. The traps generated in this process are evenly distributed along the Si / SiO2 interface. The programming process, erasing process, working window, and device cycle stability in the working state of the flash memory device are accurately represented by the non-uniformly distributed traps at the Si / SiO2 interface and inside the SiO2.

[0019] Second aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed in a computer, the computer is made to execute the method according to any one of claims 1-6.

[0020] Third aspect, the present invention provides a computing device, including a memory and a processor. An executable code is stored in the memory. When the processor executes the executable code, the method according to any one of claims 1-6 is implemented.

[0021] The present invention uses a hydrodynamic model of carrier transport, a spherical harmonic function expansion distribution of channel hot carrier injection, a non-local tunneling model (Non-Local Tunneling), and traps with non-uniform distribution at the Si / SiO2 interface and inside SiO2 to accurately represent the programming process, erasing process, operating window, and device cycle stability in the working state of a flash memory device, improving the accuracy of the simulation model representation.

[0022] In addition, in order to accurately describe the programming process of the device, a capacitance model is added between the control gate and the floating gate during the simulation process. Electrical test calibration of the simulation model is achieved through adjustment of the floating gate capacitance coupling ratio, threshold voltage, mobility model parameters, and interface state parameters; reliability test calibration of the simulation model is achieved through the distribution of defects along the SiO2 gate oxide layer and the Si / SiO2 interface during the Flash programming process.

[0023] The calibration method of the present invention can improve the coincidence degree between experimental data of a simple real tape-out and simulation data of TCAD software, and can describe the correctness of process flow simulation and device electrical simulation. An accurate simulation model plays a key role in the cell optimization of a flash memory device, and can greatly save the development cycle of high-performance and high-reliability flash memories. Brief Description of the Drawings

[0024] Figure 1 Shows a simulation process of a novel 1.5T floating gate type FLASH memory cell according to the present invention;

[0025] Figure 2 Shows a schematic structural diagram of a novel 1.5T floating gate type FLASH memory cell according to the present invention; where SG (select gate) is equivalent to the word-line, FG (float gate) stores charges, CG (control gate) controls programming and reading, and EP (erase poly) gives a high voltage during erasing;

[0026] Figure 3 Shows a schematic diagram of TCAD simulation related physical models of a FLASH memory device according to the present invention. Detailed Description of the Embodiments

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0028] As used in the embodiments of the present invention, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes other steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0029] The embodiments of the present invention provide a calibration method, device, and storage medium for a floating-gate memory TCAD simulation model. First, a high-end memory simulation model is constructed, and corresponding physical mechanism research is carried out in combination with multiple physical fields. By solving partial differential equations, after setting the corresponding condition parameters and constructing the relevant models, through the coupling of multiple physical fields, high-precision calculations are performed using the solution of partial differential equations in different physical fields. The key points of this method are the modeling of hot carrier injection and non-local tunneling models. The main process of using TCAD to study related physical problems can be summarized as: establishing a geometric model, setting relevant parameters, mesh generation, calculation and solution, and then parameter optimization after obtaining preliminary results. High-precision calibration of the TCAD model requires electrical experimental data.

[0030] In addition, the present invention uses Sentaurus Device in the TCAD tool to construct an electrical performance simulation model for this memory cell. This model needs to use the hydrodynamic model of carrier transport, the spherical harmonic function expansion distribution of channel hot carrier injection, the non-local tunneling model (Non-Local Tunneling), and traps with non-uniform distribution at the Si / SiO2 interface and inside SiO2 to accurately represent the programming process, erasing process, operating window, and device cycle stability under the working state of the flash memory device.

[0031] The calibration of the TCAD device model for FLASH memory cells is the key to this invention. To accurately describe the device programming process, a capacitance model needs to be added between the control gate and the floating gate during the simulation process. The role of this capacitance model is to fine-tune the floating gate capacitance coupling ratio to match the actual value of 0.55. In addition, the threshold voltage, as a key parameter characterizing the device programming and erasing processes, can be calibrated by adjusting the charge parameters in the bottom oxide layer and the inter-gate oxide layer. Similarly, the simulated values of the IV curves after programming and erasing operations need to have a high degree of fit with the actual values, which can be achieved by adjusting the mobility model parameters and the interface state parameters. The closing of the threshold voltage window during the degradation process is mainly caused by the decrease in the threshold voltage of the programmed state after cycling operations. To accurately simulate the degradation process, it is necessary to consider the distribution of defects along the SiO2 gate oxide layer and the Si / SiO2 interface during the Flash programming process. The defects generated by channel hot electrons (CHE) during the programming process are mainly located in the drain region and the near-drain region and will be accelerated by the strong lateral electric field. Therefore, it is necessary to consider the distribution of Si / SiO2 interface states, bulk oxide traps, and near-interface oxide traps.

[0032] The agreement between the experimental data of actual wafer fabrication and the TCAD software simulation data can describe the correctness of the process flow simulation and the device electrical property simulation. An accurate simulation model plays a key role in the unit optimization of flash memory devices and can greatly save the development cycle of high-performance and high-reliability flash memories.

[0033] That is to say, the method of this invention uses Sentaurus Sentaurus of TCAD TM Process tool to reproduce all the process steps of wafer fabrication on the memory structure, and the simulated structure has the same material and structural parameters as the sliced result of the actual wafer fabrication. In addition, using Sentaurus TMFurther electrical performance simulation of the device is carried out. In actual electrical tests, after programming and erasing the device, the corresponding IV curve is read to characterize the size of the programming / erasing window. In TCAD simulation, the programming and erasing working mechanisms of the flash memory, namely the hot carrier injection and FN tunneling mechanisms, need to be considered, and the corresponding physical models are selected. For the reliability requirements that the flash memory device needs to meet, relevant endurance and cycling stability tests are required, and this test can also be achieved through TCAD simulation software. It is mainly manifested in the phenomenon that the programming / erasing window closes after 1 million cycles of the flash memory device, which is also called the degradation phenomenon. This is caused by the defects located at the Si / SiO2 interface and inside SiO2 after repeated programming and erasing operations. Accurate description of the defects can achieve the reliability simulation of the flash memory. The simulation data is compared with the real data under the same electrical test conditions, and the model is calibrated by adjusting the mobility, interface state parameters, etc., so that the simulation values are consistent with the real experimental data. In summary, a TCAD model that accurately simulates the device structure, process, and electrical properties plays a key role in the subsequent flash cell optimization work and can save process development time.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] This embodiment provides the construction of a TCAD process simulation model for a novel 1.5T floating gate type FLASH memory, realizing the saving of process development time in the flash cell optimization work, as shown in Figure 1 , including the following steps:

[0036] Step S1: Complete the layout design of the 1.5T floating gate type FLASH memory and perform actual chip flow based on the layout.

[0037] Step S2: Import the layout file of the 1.5T floating gate type FLASH memory into the TCAD tool for process modeling of this storage unit. Figure 2 It is a schematic diagram of the structure of a novel 1.5T floating gate type FLASH storage unit shown in the present invention. The model structure at this time is consistent with the sliced structure of the actual chip flow.

[0038] Use the TCAD tool (Sentaurus Sentaurus of TCAD TM Process tool) to construct a silicon substrate, and sequentially simulate the growth process of the bottom dielectric layer and the deposition, ion implantation, photolithography, and etching processes of the select gate on the silicon substrate.

[0039] Form an inter-gate silicon oxide - silicon nitride - silicon oxide (ONO) dielectric layer on the sidewalls of the select gate in sequence.

[0040] Simulate the floating gate deposition step and the ion implantation process. Then simulate etching away the redundant ONO dielectric layer and part of the floating gate to obtain an "L-shaped" floating gate with a sharp-corner structure at the top.

[0041] Use the corresponding script commands to simulate the formation process of the ion-implanted source region. Then sequentially simulate the formation of the inter-gate silicon oxide - silicon nitride - silicon oxide layer and the control gate structure (including ion implantation simulation). At this time, the control gate structure is semi-covered by the "L-shaped" floating gate, which is highly consistent with the actual wafer structure.

[0042] Simulate the formation of the top dielectric layer and the erase gate structure and perform ion implantation to form the drain regions on both sides. Then simulate the contact hole layer to facilitate the electrode intervention for the electrical simulation of the subsequent flash memory cells. This structure is a symmetric structure, and after building half of it, the other half is simulated through the mirror operation command.

[0043] The modeling used in Sentaurus Device is based on the hydrodynamic model of carrier transport (Hydrodynamic model), the spherical harmonics expansion (Spherical Harmonics Extension, SHE) distribution of channel hot carrier injection into the floating gate during programming, the non-local tunneling model during erasure, and the introduction of trap simulation degradation mechanisms at the Si / SiO2 interface and inside SiO2.

[0044] This embodiment also provides the calibration of the above 1.5T floating gate type FLASH memory TCAD simulation model, and the main contents are as follows:

[0045] First, by increasing the capacitance between the control gate and the floating gate, finely adjust the capacitance coupling ratio of the device's floating gate - control gate to make it consistent with the actual value of 0.55;

[0046] Secondly, modify the fixed charge parameters in the corresponding oxide layers during programming and erasing to regulate the threshold voltage of the simulation model to be consistent with the actual threshold voltage of the actual floating gate type memory;

[0047] Finally, adjust the mobility model parameters and interface state parameters until the simulation values of the IV curves after programming and erasing have a fitting degree with the actual values > 0.98, and the simulation values of the programming and erasing working windows are close to the real values, with a difference < 0.3V;

[0048] In addition to basic electrical tests, it is also necessary to test and simulate the reliability of the device. The simulation of memory degradation problems involves the distribution of Si / SiO2 interface states, bulk oxide traps, and near-interface oxide traps. The simulation model of device degradation can be calibrated by adjusting the distribution of these defects to make it consistent with the actual device. The test conditions include: 1. After the device undergoes 1 million programming / erasing cycles, read the programming and erasing IV curves; 2. After the device is baked at 250 °C for 72 hours, test the programming / erasing IV curves.

[0049] Figure 3 Schematic diagram of the TCAD simulation-related physical model of the FLASH memory device shown in the present invention.

[0050] Based on the device programming operation mechanism, the modeling needs to consider the hydrodynamic model of carrier transport and the spherical harmonic expansion distribution of channel hot carrier injection. Spherical harmonic expansion (SHE) distribution of hot carrier injection To obtain the hot carrier injection current, it is necessary to accurately understand the non-equilibrium electron-energy distribution. The SHE distribution hot carrier injection model uses the non-equilibrium energy distribution f obtained from the lowest-order SHE of the semiclassical Boltzmann transport equation (BTE) to calculate the hot carrier injection current. The formula for the total hot carrier injection current is as follows:

[0051]

[0052] where A and g v are factors; P ins is the probability that an electron moves from the interface to the barrier peak without scattering; g is the density of states of spin; v is the magnitude of the electron velocity; Г is the transmission coefficient; mins is the effective mass of the insulator. ∫ds is the integral along the semiconductor-insulator interface. To use the SHE distribution hot carrier injection model, the distribution function must be obtained by solving the SHE method (see the spherical harmonic expansion method).

[0053] Based on the device erasing operation mechanism, the modeling needs to consider the non-local tunneling model. The tunneling current depends on the band-edge profile along the entire path between the tunneling connection points and is a non-local process. Generally, the band-edge profile has a complex shape and is calculated by Sentaurus Device by solving the transport equation and the Poisson equation. The non-local tunneling model has multiple fitting parameters that need to be adjusted, which will all affect the electrical simulation of the device during the erasing process.

[0054] Based on the device degradation principle, the modeling process needs to consider the interface traps generated by the breaking of Si-H bonds at the Si / SiO2 interface under the action of electrical stress due to the high electric field in the tunneling process. The traps generated in this process are evenly distributed along the Si / SiO2 interface. In addition, the defects generated by channel hot carrier injection are mainly distributed in the drain region and the near-drain region, and these defects mainly include Si / SiO2 interface states, bulk oxide traps (for holes and electrons), and near-interface oxide traps. By designing the non-uniform distribution of traps at the Si / SiO2 interface and inside the SiO2, the programming process, erasing process, operating window, and device cycle stability under the working state of the flash memory device can be accurately represented.

[0055] In summary, the TCAD simulation model of the floating gate memory cell that fits well with the experimental data of the actual chip fabrication plays a key role in the research on the cell optimization of flash memory devices and also plays a key role in the development of high-performance and high-reliability flash memories.

[0056] The present invention uses computer-aided design technology (TCAD) to simulate the closing situation of the programming window of a 1.5T floating gate memory cell after 1 million cycles.

Claims

1. A method for calibrating a floating gate memory TCAD simulation model, characterized in that The method comprises: Step S1: completing the layout design of the floating gate memory, and performing actual tape-out to obtain an actual floating gate memory; performing electrical performance testing based on the actual floating gate memory to obtain actual test data; Step S2: importing the layout design file of the floating gate memory into the TCAD tool to perform process modeling of the floating gate memory to obtain a simulation model; then performing electrical performance testing based on the simulation model to obtain simulation test data; then calibrating the simulation test data using the actual test data of step S1; The calibration includes electrical test calibration and reliability test calibration; The electrical test calibration is specifically: First, by adding capacitance between the control gate and the floating gate of the floating gate memory, the capacitance coupling ratio between the control gate and the floating gate is fine-tuned until it matches the actual floating gate memory; Secondly, calibrate the fixed charge parameters of the oxide layer of the device during programming and erasing until the threshold voltage simulation value of the simulation model is higher than the actual threshold voltage value of the actual floating gate memory; Finally, the mobility model parameters and interface state parameters are calibrated until the simulation test data of the programming and erasing windows are consistent with the actual test data; Calibrate the mobility model parameters and the interface state parameters until the IV curve simulation value of the simulation model after programming and erasing operations is higher than the actual value of the IV curve of the actual floating gate memory, and the working window simulation value of the programming and erasing operation simulation model is consistent with the actual value of the working window of the actual floating gate memory; The reliability test calibration is specifically: The distribution of Si / SiO2 interface states, bulk oxide traps, and near-interface oxide traps is calibrated until the simulation model is consistent with the actual floating gate memory.

2. The method according to claim 1, characterized in that The programming operation of the simulation model device under working state is realized through the fluid mechanics model of carrier transport and the spherical harmonic function expansion distribution of channel hot carrier injection.

3. The method according to claim 2, characterized in that The defects caused by channel hot carrier injection are mainly distributed in the drain region and the near-drain region.

4. The method according to claim 3, characterized in that The defects generated by channel hot carrier injection include Si / SiO2 interface states, bulk oxide traps and near-interface oxide traps.

5. The method according to claim 1, characterized in that The erase operation of the simulation model device in working state is realized through the non-local tunneling model.

6. The method according to claim 1, characterized in that The device degradation principle of the simulation model is verified by the interface traps generated by the breaking of Si-H bonds at the Si / SiO2 interface under the action of electric stress caused by the high electric field during the tunneling process; the traps generated by this process are evenly distributed along the Si / SiO2 interface; the programming process, erasing process, working window and device cycle stability of the flash memory device under the working state are accurately represented by the non-uniformly distributed traps at the Si / SiO2 interface and the traps inside SiO2.

7. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method according to any one of claims 1 to 6.

8. A computing device, comprising a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the method according to any one of claims 1 to 6 is implemented.

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