Method, system and storage medium for detecting manufacturability of a detection chip carrier

Abstract

The present application provides a method, a system and a storage medium for detecting the manufacturability of a chip carrier. In the layout design file of the chip carrier, one or more auxiliary layers for manufacturability detection are added to the carrier hierarchy, and each layer of the carrier hierarchy and the auxiliary layers are mapped to the corresponding hierarchies predefined in the design rule check file for manufacturability detection. Moreover, the design rule check is performed on the layout design file of the chip carrier by using the design rule check file to obtain the detection result. This solution can flexibly set and adjust the inspection items related to manufacturability detection, has strong scalability and fully relies on tool automation inspection without visual inspection, which not only improves the reliability of the detection result, but also shortens the inspection time and improves the production yield of the carrier.

Description

Technical Field

[0001] This application relates to chip package testing, and particularly to the detection of the manufacturability of chip carriers. Background Art

[0002] The statements in this section are only for providing background information related to the technical solutions of this application to facilitate understanding, and they do not necessarily constitute the prior art for the technical solutions of this application.

[0003] A chip carrier is a basic component used in the chip packaging process to protect the bare chip (Die) and achieve electrical interconnection between the integrated circuit on the bare chip and external electronic circuits. The chip carrier can be regarded as a special printed circuit board and also adopts a multi-layer structure formed by laminating and bonding alternating conductive pattern layers and dielectric material layers. However, different from the conventional printed circuit board, the chip carrier has the characteristics of high density, high precision, miniaturization, and thinness.

[0004] With the rapid development of the semiconductor integrated circuit field, the chip integration level is getting higher and higher, and the functions are getting more and more, resulting in the chip carrier size getting larger and larger, the number of laminations getting more and more, and the carrier design gradually becoming more complex. In order to minimize the development cycle of the chip carrier and reduce the project cost, it is a very important and essential step to check the manufacturability of the chip carrier before tape-out, which directly affects the production yield of the chip carrier.

[0005] It should be noted that the above content is only used to help understand the technical solutions of this application and does not serve as the basis for evaluating the prior art of this application. Summary of the Invention

[0006] In view of the above problems, this application provides a method, a system, and a storage medium for detecting the manufacturability of chip carriers.

[0007] According to the first aspect of the embodiments of this application, a method for detecting the manufacturability of a chip carrier is provided, which includes adding one or more auxiliary layers for manufacturability detection to the carrier hierarchy in the layout design file of the chip carrier, where the auxiliary layer includes a positioning frame indicating the positions and sizes of one or more inspection items; mapping each layer and the auxiliary layer of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchies predefined in the design rule check file for manufacturability detection; and performing a design rule check on the layout design file of the chip carrier based on the design rule check file and outputting a detection result.

[0008] In this embodiment, before transferring the carrier design file to the carrier manufacturer, a comprehensive and detailed automated check of the manufacturability of the carrier is performed using the design rule check file, which avoids repeated iterations between the design team and the carrier manufacturer, improves the efficiency of manufacturability checks and shortens the check time, thereby increasing the first-pass yield of carrier design and reducing the process communication cost. Moreover, through the auxiliary layer and the configurable design rule check file in the carrier hierarchy for indicating the positions and dimensions of one or more check items, it is possible to flexibly set and adjust which manufacturability detections are performed on the carrier hierarchy, thus having good scalability.

[0009] In some embodiments, one of the one or more auxiliary layers at least includes a positioning frame indicating the position and dimensions of the chip and a positioning frame indicating the boundary of the chip carrier. The one or more check items may include one or more combinations of the following: capacitors, resistors, chips, lids for encapsulating chips, positioning marks, carrier identifiers. Through the auxiliary layer for indicating the positions and dimensions of one or more check items, it is possible to flexibly set which parts of the carrier design file are subjected to manufacturability detection.

[0010] In some embodiments, the design rule check file may include check items related to manufacturability detection, rule definitions related to each check item, carrier hierarchy definitions, and check operations for each level. The method may further include: obtaining the items to be checked from a configuration file or a user interface; adding one or more auxiliary layers corresponding to the obtained items to be checked to the carrier hierarchy according to the obtained items to be checked; setting the check items related to manufacturability detection in the design rule check file according to the obtained items to be checked; performing a design rule check on the carrier layout design file based on the adjusted design rule check file, and outputting the detection result.

[0011] In these embodiments, relevant check items and check rules can be dynamically adjusted or added at any time based on simple modifications to the design rule check file, thereby continuously improving the content of manufacturability detection, not only having good scalability but also making the check results more comprehensive and reliable.

[0012] In some embodiments, the method may further include turning on or off the corresponding check items in the design rule check file according to the auxiliary layer of the carrier hierarchy in the currently to-be-detected layout design file, thereby enabling more targeted manufacturability detection according to actual needs.

[0013] According to the first aspect of the embodiments of the present application, another method for detecting the manufacturability of a chip carrier is provided, including:

[0014] Identify one or more auxiliary layers for manufacturability detection from the received layout design file of the chip carrier, where the auxiliary layers include positioning frames indicating the positions and dimensions of one or more inspection items; enable the inspection items associated with the identified auxiliary layers in the design rule check file; map each layer and the auxiliary layers of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchies predefined in the design rule check file; and start the design rule check file to check the layout design file of the chip carrier to obtain a detection result.

[0015] In some embodiments, the method may further include locating the position where an error is reported and its related inspection items according to the obtained detection result, and marking or mapping them to the corresponding hierarchies in the layout design file of the chip carrier.

[0016] In some embodiments, the method may further include, in response to a request from a user to add inspection items, inserting the received inspection items, their related inspection rules and inspection operations into the corresponding part of the design rule check file, and recompiling the updated rule check file.

[0017] In some embodiments, the design rule check file is developed and compiled based on a layout physical verification tool for the chip. In some embodiments, the layout format file adopts the GDSII format, and the layout physical verification tool is Calibre.

[0018] According to a third aspect of the embodiments of the present application, a system for detecting the manufacturability of a chip carrier is provided, which includes a mapping module, an execution module, and a reporting module. The mapping module is configured to identify one or more auxiliary layers for manufacturability detection from the received layout design file of the chip carrier, enable the inspection items associated with the identified auxiliary layers in the design rule check file, and map each layer and the auxiliary layers of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchies predefined in the design rule check file; where the auxiliary layers include positioning frames indicating the positions and dimensions of one or more inspection items. The execution module is configured to start the design rule check file to check the layout design file of the chip carrier to obtain a detection result. The reporting module is configured to locate the position where an error is reported and its related inspection items according to the obtained detection result, and mark or map them to the corresponding hierarchies in the layout design file of the chip carrier.

[0019] In yet another embodiment, the system may further include a rule compilation module, configured to insert the received inspection items, their related inspection rules and inspection operations into the corresponding part of the design rule check file, and recompiling the updated rule check file.

[0020] According to a fourth aspect of the embodiments of the present application, there is provided a computer-readable storage medium, on which computer instructions are stored, and when the computer instructions are executed by a processor, the method according to the first aspect or the second aspect of the embodiments of the present application is implemented.

[0021] Compared with the traditional method of joint inspection by multiple software, the solution according to the embodiments of the present application reduces the repeated iteration between the design team and the carrier manufacturer, improves the efficiency of manufacturability inspection and shortens the inspection time, thereby improving the first-pass rate of carrier design and reducing the process communication cost. And this solution can flexibly set and adjust the inspection items related to manufacturability detection through the auxiliary layer and the configurable design rule check file for indicating the position and size of one or more inspection items in the carrier hierarchy. It has strong scalability and fully automated inspection, does not require visual inspection, and the detection results are very reliable.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:

[0024] Figure 1 FIG. is a flowchart of a method for detecting the manufacturability of a detection chip carrier according to an embodiment of the present application;

[0025] Figure 2 FIG. is a schematic diagram of an auxiliary layer according to an embodiment of the present application;

[0026] Figure 3 FIG. is a flowchart of a method for detecting the manufacturability of a detection chip carrier according to another embodiment of the present application;

[0027] Figure 4 FIG. is a schematic diagram of functional modules of a system for detecting the manufacturability of a detection chip carrier according to another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] To make the objectives, technical solutions and advantages of the present application more clear and understandable, the following provides a further detailed description of the present application through specific embodiments in conjunction with the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0029] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0030] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0031] The flowcharts shown in the drawings are only exemplary illustrations and do not necessarily include all the contents and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0032] The design and manufacturing process of a chip can be simply divided into three stages: design, manufacturing, and packaging and testing. The chip design stage starts from the chip architecture design and ends with the generation of the physical layout GDS (Graphics Display System). The designed physical layout is transferred to the foundry in the form of a GDSII format file. In the chip manufacturing stage, after receiving the GDSII format file, the foundry manufactures the corresponding integrated circuit (IC) on the silicon wafer of the wafer to obtain a bare die, that is, a bare chip. Then, the bare chip is packaged and tested by a semiconductor packaging and testing factory to make a chip that can work properly.

[0033] A chip carrier is a basic component used in the chip packaging process to protect the bare chip and achieve electrical interconnection between the integrated circuit on the bare chip and external electronic circuits. There are usually three ways of electrical interconnection between the bare chip and the carrier: wire bonding, tape automated bonding, and flip chip bonding. Wire bonding connects the pads on the bare chip and the corresponding pads on the carrier with fine metal wires. Tape automated bonding mounts and interconnects the bare chip to a flexible metallized polymer tape, where the inner leads of the tape are bonded to the bare chip and the outer leads are bonded to the external circuit. Flip chip bonding means that the active surface of the bare chip faces down and is connected to the carrier, and the electrical interconnection between the bare chip and the carrier is achieved through the bump structure on the bare chip and the bonding material on the carrier. There is no unified classification standard for chip carriers. According to the packaging method, they can be divided into: ball grid array carriers, chip scale package carriers, flip chip carriers, multi-chip module carriers, etc. According to the substrate materials used, they can be divided into two categories: organic carriers and inorganic carriers. Organic carriers mainly include phenolic carriers, polyester carriers, and epoxy resin carriers, etc. Inorganic carriers mainly include ceramic carriers and glass carriers.

[0034] In fact, a chip carrier can be regarded as a special printed circuit board for carrying a bare chip (thus it can also be called a carrier board). Its top layer is provided with interfaces for electrical interconnection with the bare chip and other related electrical components, its bottom layer is provided with interfaces for interconnection with the external circuit, and the middle layer is mainly used for arranging signal lines, power lines, ground lines, etc. The electrical interconnection between layers is achieved through metallized holes. The number of middle layers can usually be determined by considering factors such as the scale of the circuit, the size of the carrier, the wiring signal quality, and the wiring density requirements.

[0035] Essentially, a chip carrier is a multi-layer structure composed of alternating conductive pattern layers and dielectric materials. Similar to ordinary printed circuit boards, chip carriers are also made based on copper-clad laminates. A copper-clad laminate is made by laminating copper foil on one or both sides of a dielectric material and then thermally pressing. During the manufacturing process, hole processing, copper plating, etching, etc. are performed on the copper-clad laminate to obtain the required circuit patterns (i.e., conductive pattern layers). The conductive patterns and hole position patterns processed on the copper-clad laminate can be collectively referred to as the layout. The layout can be simply understood as a set of nested patterns, and the layout of each layer corresponds to the mask pattern under different processes. The layout file is the starting point for processing and manufacturing. In the layout file of a chip carrier, the carrier hierarchical structure usually includes one or more wiring layers (Layer), drilling layers (Drills), solder mask layers (SolderMask), silk screen layers (Silk Screen), etc. Different from ordinary printed circuit boards, chip carriers have the characteristics of high density, high precision, miniaturization, and thinness, and the manufacturing process of ordinary printed circuit boards cannot meet the production requirements of chip carriers. After the current chip carriers are designed, they are usually transferred to specialized carrier manufacturers for production.

[0036] With the rapid development of the semiconductor integrated circuit field, the chip integration level is getting higher and higher, and the functions are becoming more and more numerous, resulting in an increasing chip carrier size and more and more laminations. Such design requirements for high-density multi-layer carriers in a limited space increase the complexity of chip carrier research, design, and manufacturing. If the carrier design fails to meet the requirements of carrier manufacturing, it will lead to delays in the overall product schedule, an extended development cycle, increased costs, a high product repair rate, and potential quality hazards in the product. Therefore, the manufacturability detection of the chip carrier is one of the very important links before the chip carrier is taped out, directly affecting the production yield of the chip carrier.

[0037] The manufacturability detection of the chip carrier starts from the manufacturing perspective, analyzes the design documents of the carrier according to the production process specifications, and checks whether the design documents match the process capabilities, so as to detect design defects and deficiencies before taping out, and try to improve the first-pass yield of carrier manufacturing and reduce the process communication cost. The manufacturability detection of the chip carrier mainly detects whether the positions, sizes, spacings, etc. of the patterns on each mask-related layer in the layout conform to the manufacturing process specifications. It usually includes the following aspects: 1) Circuit analysis (line width, line pitch, routing angle, distance from line to hole, distance from line to border, restricted area, etc.); 2) Drilling analysis (hole diameter, hole position, distance between holes, distance from hole to border, hole density, etc.); 3) Solder mask analysis (solder mask spacing, solder mask opening position and size, optical recognition points, etc.); 4) Character analysis (character size, silk screen direction, silk screen distance, etc.); 5) Device analysis (device spacing, device position and size, distance from device to border, etc.); 6) Pin analysis (pin position, pin pitch); 7) Pad analysis (pad position, pad size, pad spacing, etc.); 8) Mechanical parameters (board thickness, number of layers, copper thickness, conductor density, board size, etc.).

[0038] The manufacturability detection of the existing carrier is jointly completed by the Electronic Design Automation (EDA) software of the carrier design team, the Computer Aided Manufacturing (CAM) software of the carrier manufacturer, and the Process Designer (PD) software. During the layout and wiring process using the EDA software (such as the Advanced Package Designer APD of Cadence Corporation in the United States), the design team will consider the manufacturing-related constraints and check whether the carrier design file conforms to the predetermined design rules. However, the number of check items usually does not exceed 100, so the check is not comprehensive. In many cases, designers still need to manually adjust the layout and wiring. After handing over the carrier layout design to the carrier manufacturer, the carrier manufacturer will also use the CAM software to detect whether the carrier layout design meets the relevant production and process requirements, and use the PD software for the planning, analysis, confirmation, and optimization of the production process. After the above process is confirmed to be correct, the wafer is started for production. But if problems that cannot be solved by correction are found in the above process, the relevant carrier design team needs to be notified to modify the relevant design files again.

[0039] In the above manufacturability detection process, multiple rounds of data transmission and format conversion are required between the three software, and data is repeatedly imported and exported to each other, with relatively low efficiency and accuracy. Moreover, the multiple round trips between the design team and the carrier manufacturer also extend the inspection time. The inspections in the actual operation process of each software are not comprehensive, and only part of the errors can be detected. It also depends on the experience of specific operators for visual inspection, resulting in unreliable inspection quality. Moreover, the above manufacturability detection completely relies on the fixed inspection functions built in each software itself, with poor flexibility and scalability.

[0040] In the embodiments of the present invention, a method and system for detecting the manufacturability of a chip carrier are provided, which can comprehensively and meticulously perform automated inspection on the manufacturability of the designed carrier before transferring the carrier design file to the carrier manufacturer, minimize the repeated iteration between the design team and the carrier manufacturer as much as possible, improve the manufacturability inspection efficiency and shorten the inspection time, thereby improving the first-pass yield of the carrier design and reducing the process communication cost. And this method no longer depends on the pre-set fixed inspection items, but can dynamically adjust or add relevant inspection items at any time, with good scalability. And as the inspection items are continuously increased and improved, the inspection results are more comprehensive and reliable.

[0041] Figure 1The process schematic diagram of a method for detecting the manufacturability of a chip carrier according to an embodiment of the present application is given. The method mainly includes: S1) In the layout design file of the chip carrier, add one or more auxiliary layers for manufacturability detection to the carrier hierarchy; S2) Map each layer and auxiliary layer of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchy predefined in the design rule check file; S3) Perform design rule check on the layout design file of the chip carrier based on the design rule check file, and output the detection result. In this embodiment, through the auxiliary layer and the configurable design rule check file in the carrier hierarchy for indicating the positions and dimensions of one or more check items, the check items related to manufacturability detection can be flexibly set and adjusted, thus having good scalability.

[0042] More specifically, in step S1), in the layout design file of the carrier, add one or more auxiliary layers to the carrier hierarchy. The auxiliary layers here are only used for manufacturability detection and are not the actual layers of the carrier; they are only used in the design stage and will not be included in the carrier layout file finally transferred to the carrier manufacturer. Each auxiliary layer can be regarded as a graphic layer, which includes positioning frames indicating the positions and dimensions of one or more check items. The positioning frames can be in the form of rectangles, squares or other polygons, and this is not limited herein. The auxiliary layer is actually a graphic composed of one or more positioning frames with different positions, shapes and sizes.

[0043] Although in the layout file of the carrier, the carrier hierarchy already includes corresponding graphics such as wiring layers, drilling layers, solder mask layers, silk screen layers, etc., only the detection of conventional fixed check items is performed based on these graphics, such as line width, line spacing, metal density, aperture, hole spacing, solder mask opening position and size, silk screen direction, silk screen distance, etc. Such checks are not comprehensive, and there are many rules related to manufacturing processes that cannot be detected. In this embodiment, by adding one or more auxiliary layers to the carrier hierarchy to assist, supplement or adjust the detection of one or more check items related to manufacturability detection. For example, if it is necessary to check the distances from lines, holes, etc. to the carrier boundary and the chip boundary during manufacturability detection, an auxiliary layer related to the carrier boundary and the chip boundary can be added to the carrier hierarchy. As Figure 2 shown, this auxiliary layer includes a positioning frame indicating the position and size of the chip and a positioning frame indicating the boundary of the chip carrier. In this way, based on the graphics of this auxiliary layer, the relevant checks on the distances from lines, holes and other unit devices to the carrier boundary and the chip boundary can be realized. Another example is that when it is necessary to detect the check items related to specific components (such as capacitors, resistors, etc.) on the carrier, an auxiliary layer related to this component can be added, and the positions and sizes of the corresponding components are marked on this auxiliary layer through positioning frames.

[0044] In one embodiment, one or more inspection items for manufacturability inspection can be added according to requirements, and an auxiliary layer related to the inspection item can be added. These inspection items can be set according to the manufacturing process requirements of the same carrier manufacturer or different carrier manufacturers. The inspection items related to the auxiliary layer can include, but are not limited to, one or more of the following combinations: capacitors, resistors, chips, lids for encapsulating chips, alignment marks (for alignment between layers), carrier identification (such as QR codes printed on the carrier), etc. The position and size of the inspection item are marked by the auxiliary layer related to the inspection item, and relevant rule inspections for the inspection item can be conveniently carried out during subsequent manufacturability inspection. For example, based on these auxiliary layers, the distance between capacitors and resistors, the distance between capacitors and resistors and chips, carrier boundaries, lids, the distance between alignment marks and chips, carrier boundaries, lids, the size of the QR code, the distance between the QR code and capacitors, resistors, alignment marks, chips, lids, and (in the case of multi-chip module packaging) the distance between chips, etc. can be detected.

[0045] In one embodiment, one or more auxiliary layers associated therewith can be added to each layer in the carrier hierarchy to facilitate the detection of one or more inspection items for that layer. For example, when it is necessary to detect a capacitor in the top layer of the carrier hierarchy, an auxiliary layer related to the capacitor can be set for the top layer, and the auxiliary layer includes a positioning frame indicating the position and size of one or more capacitors in the top layer. In yet another embodiment, an auxiliary layer shared by all layers in the carrier hierarchy can be added, such as the auxiliary layer related to the carrier boundary and chip boundary mentioned above. In still other embodiments, a graphic layer more conducive to manufacturability inspection can be formed by performing operations such as AND, OR, and NOT on the graphics of each auxiliary layer.

[0046] Continue to refer to Figure 1 , after the addition of the auxiliary layer for manufacturability inspection is completed, in step S2), each layer and the auxiliary layer of the carrier hierarchy in the layout design file of the chip carrier are mapped to the corresponding layers predefined in the Design Rule Check (DRC) file. Here, the DRC file is a rule check file pre-written according to the relevant manufacturing process rules for manufacturability inspection. The design rule check file is used to detect whether the various dimensions of the graphics on each mask-related layer in the layout conform to the manufacturing process rules. The manufacturing process rules are usually set according to the minimum size, minimum width, minimum spacing, etc. that can be produced by a specific process line. The minimum line width can prevent circuit open caused by breakage during process manufacturing, and the minimum spacing avoids short circuit caused by contact during graphic manufacturing. The inspection of various geometric graphic relationships in the layout includes not only the inspection of the width and spacing of geometric graphics on the same layer, but also the inspection of the spacing and overlay spacing between graphics on different layers.

[0047] In this embodiment, the design rule check file is written in the Standard Verification Rule Format (SVRF) language commonly used in the industry by Mentor Corporation of the United States, and is run on the company's Calibre platform for execution. The DRC file at least includes the following parts: 1) inspection items related to manufacturability detection; 2) rule definitions related to each inspection item; 3) hierarchical structure definitions; 4) inspection operations for each level.

[0048] 1. Inspection items related to manufacturability detection

[0049] In the DRC file, the inspection items related to manufacturability detection may include conventional inspection items related to the patterns of each layer in the carrier hierarchical structure, such as circuits, vias, solder masks, silk screens, pins, pads, etc.; and also include the inspection items related to the auxiliary layers mentioned above, such as capacitors, resistors, chips, lids for packaged chips, positioning marks, carrier identifiers, etc. It should be understood that the above inspection items related to manufacturability detection can be selected and set according to actual requirements and actual carrier manufacturing processes, and this article does not impose any restrictions on this. As introduced above in conjunction with step S1, any inspection items related to manufacturability detection can be supplemented, added, or adjusted by adding auxiliary layers to the carrier hierarchical structure.

[0050] In another embodiment, in the DRC file, the inspection items related to manufacturability detection can be set in the form of switch options. In this way, the user can decide whether to turn on the switch according to design and test requirements. If it is turned on, it means to detect this item; if it is not turned on, it means not to check this item. For example, #DEFINE VIA_CHECK means to check the relevant rules for vias; / / #DEFINE VIA_CHECK means not to check the relevant rules for vias.

[0051] In another embodiment, the corresponding inspection items in the DRC file can be turned on or off according to the auxiliary layers in the received or to-be-detected layout file's carrier hierarchical structure. That is, in addition to the conventional inspection items, only the inspection items related to the current auxiliary layer are turned on.

[0052] 2. Rule definitions related to each inspection item;

[0053] In this DRC file, the rule definitions related to each inspection item are set according to factors such as the manufacturing process rules and design requirements of the carrier manufacturer. This article does not impose any restrictions on the rule content. Taking the wiring layer as an example, the rules related to it usually include the minimum line width, the minimum distance between lines, the minimum line length, the metal density, the routing angle, etc. The rules related to each inspection item in this DRC file can be defined in the form of "variable + assignment". For example:

[0054] VARIABLE BU_METAL_W_1 14.995

[0055] VARIABLE BU_METAL_S_1 14.995

[0056] VARIABLE BU_METAL_L_1 3500

[0057] VARIABLE ACUTE_ANGLE 30

[0058] The above four variable statements respectively represent the following four inspection rules for the wiring layer:

[0059] The minimum line width is 14.995um;

[0060] The minimum distance between lines is 14.995um;

[0061] The minimum line length is 3500um;

[0062] The minimum routing angle is 30.

[0063] In another embodiment, the DRC file may include a set of rule definitions corresponding to different manufacturing processes. Under different manufacturing processes, the assignments corresponding to the same variable are different. The rule definition set corresponding to a specific manufacturing process can be selected for rule checking by setting the process option. In this way, the manufacturability detection requirements of different types of carriers and different carrier manufacturers can be supported or compatible more flexibly.

[0064] 3. Hierarchical Structure Definition

[0065] In this DRC file, the carrier hierarchy and the auxiliary layers related to each inspection item are defined in advance. The subsequent inspection operations for each layer in this DRC file are carried out based on the layers defined in this part; for example, the layer numbers used in the subsequent inspection operation commands are the layer identifiers of each layer defined in advance in this part.

[0066] In addition to the above hierarchical structure definition, the DRC file also includes a hierarchical mapping table. This hierarchical mapping table stores the mapping relationship between the carrier hierarchical structure in the layout file to be inspected and the hierarchical structure predefined in the DRC file. When performing rule checking on a certain carrier layout file using the DRC file, it is necessary to map the carrier hierarchical structure in the currently inspected layout file to the hierarchical structure predefined in the DRC file.

[0067] 4) Inspection operations for each level

[0068] The inspection operations for each level are completed through inspection command statements. That is, according to the above predefined hierarchical structure and the rules related to each inspection item, the DRC basic commands are used to write inspection command statements for various dimensions. The form of the inspection command is usually: <error condition><error output>, which means that <error output> is executed when the error condition represented by <error condition> is true. The basic composition of <error condition> includes: inspection command, layer number, rule variable. The inspection operations of DRC can usually be divided into inner edge inspection, outer inspection, dimension inspection, coverage inspection, etc. Inner edge inspection refers to checking the inner spacing of polygons, that is, the corresponding relationship of the inner edges of polygons. Outer inspection refers to checking the outer spacing of polygons, that is, the relative relationship of the outer edges of polygons, mainly for checking the distance between polygons or rectangles and other graphics. Dimension inspection refers to checking the allowed line length, graphic area, etc. Coverage inspection is used to check polygon overlap. Common inspection commands such as Width, SPACE, INT, EXT, ABUT, DENSITY, etc.

[0069] For example, some inspection operations for the level with the predefined layer number L1 can be as follows:

[0070] L1.W.1{@L1 Width>=^BU_METAL_W_1

[0071] INT L1<BU_METAL_W_1ABUT<ACUTE_ANGLE SINGULAR REGION

[0072] }

[0073] Among them, BU_METAL_W_1 is the inspection rule for line width defined in the above part 2, and ACUTE_ANGLE is the routing angle defined in the above part 2. The inspection operations performed by the above inspection command statements are: an error is reported when the inner line width of level L1 is less than the defined width of BU_METAL_W_1 (14.995um), or the routing angle is less than ACUTE_ANGLE (30 degrees).

[0074] The above inspection operations for each level are performed based on the carrier hierarchy predefined in the DRC file and the auxiliary layers related to each inspection item. Therefore, when receiving the layout design file of the chip carrier in step S2), it is necessary to map the hierarchy of the carrier in the layout file to the corresponding levels predefined in the design rule check file, so as to facilitate the execution of subsequent inspection operations.

[0075] In one embodiment, before performing the above hierarchical mapping, the method further includes converting the received layout design file of the chip carrier into a layout format file recognizable by the design rule check file. Still taking the DRC file of the Calibre platform as an example, the supported layout file format is a file in GDSII format. If the layout design file of the chip carrier to be detected is not in GDSII format, perform the corresponding format conversion.

[0076] In a file in GDSII format, all data is composed of a series of linked data blocks, which respectively define the file header, library file header, library file library name, data unit, module structure header, module structure name, graphic element, layer name, data type, graphic element coordinates, graphic element tail, module structure tail, and then followed by the second module structure header... and so on, and finally ends with the file tail. GDSII usually has seven graphic elements: filled polygon (BOUNDARY), line with a certain width (PATH), inserted module (Reference Structure), array composed of inserted modules (Array), text (Text), circuit topology structure (Node), and frame structure (Box). In a GDSII file, all layers are represented by a number (layer number), such as 1, 2, 3... etc. Therefore, when performing rule checks on each level of the carrier, it is necessary to establish a mapping relationship between the carrier hierarchy in the layout file to be inspected and the hierarchy predefined in the DRC file by adjusting and configuring the layer mapping table in the DRC file.

[0077] Continue to refer to Figure 1 , after mapping each layer and the auxiliary layers of the carrier hierarchy in the layout design file of the chip carrier to be subjected to manufacturability detection to the corresponding levels predefined in the rule detection file for manufacturability detection, in step S3), based on the above design rule check file, perform the preset inspection operations on each level of the carrier according to the rules related to each inspection item, that is, check whether the various dimensions of the graphics on each layer in the carrier layout violate the preset inspection rules. In the Calibre platform, the above design rule check file can be used to check the layout after compilation. The detection results are saved in a pre-specified output file.

[0078] In yet another embodiment, the method further includes locating the position where the error is reported and its related inspection items according to the detection result output in step S3), and presenting them in the layout design file of the chip carrier, so as to facilitate the modification of the corresponding layout design file. Then, the above steps are repeatedly executed on the modified carrier layout design file until no error occurs in the detection result.

[0079] In the above embodiment, applying the design rule check DRC for the chip layout to the manufacturability check of the chip carrier, through the auxiliary layer used to indicate the position and size of one or more inspection items in the carrier hierarchy and the configurable design rule check file, the inspection items related to the manufacturability check can be flexibly set and adjusted. It has strong scalability and fully relies on tool automation for inspection without the need for visual inspection, greatly shortening the inspection time, and at the same time the detection result is very reliable. Compared with the traditional method of joint inspection by multiple software, the method of this embodiment shortens the time, reduces the multiple rounds of repeated iterations between the design team and the carrier manufacturer, and can effectively improve the production yield of the carrier. It should be understood that although the above embodiment is introduced by taking Calibre DRC as an example, this is only for illustrative purposes and not for any limitation. After adaptive adjustment or transformation, the method of the embodiments of the present application can also be applied to scenarios using other chip layout physical verification platforms.

[0080] In yet another embodiment, the method further includes: obtaining the inspection items to be checked from a configuration file or a user interface; adding one or more auxiliary layers corresponding to the obtained inspection items to the carrier hierarchy according to the obtained inspection items; and setting the inspection items related to the manufacturability check in the DRC file according to the obtained inspection items; performing a design rule check on the current carrier layout design file based on the adjusted DRC file, and outputting a detection result. This embodiment allows the user to dynamically change the inspection items related to the manufacturability check at any time during the design and detection process according to actual needs through the configuration file or interface, and perform the manufacturability check more flexibly.

[0081] Figure 3 A flowchart of a method for detecting the manufacturability of a chip carrier according to yet another embodiment of the present application is given. As Figure 3As shown, in S301, one or more auxiliary layers for manufacturability detection are identified from the received layout design file of the chip carrier. As mentioned above, each auxiliary layer includes a positioning frame indicating the positions and dimensions of one or more inspection items. In step S302, the inspection items associated with the identified auxiliary layer are enabled in the design rule check file. As mentioned above, in the design rule check file, the inspection items to be inspected can be selected through switch options. In step S303, each layer and auxiliary layer in the carrier hierarchy in the layout design file of the chip carrier are mapped to the corresponding hierarchies predefined in the design rule check file. For example, adjustment and configuration are performed through the layer mapping table in the above-mentioned design rule check file to establish the mapping between each layer of the carrier in the current layout file and the hierarchies predefined in the design rule check file. In step S304, the design rule check file is started to check the layout design file of the chip carrier to obtain the detection result. The design rule check file here can be used to check the relevant layout file after being compiled. Usually, the design rule check file also includes an environment parameter setting section related to execution, and through this section, the format of the input layout file, the specific path and file name of the input layout file, and the name of the output check result file are specified. For example:

[0082] LAYOUT SYSTEM GDS-II (used to indicate that the input file format is GDS-II format)

[0083] LAYOUT PATH'myPath / Test.gds' (used to indicate the specific path of the input GDS-II file)

[0084] DRC RESULTS DATABASE 'DRC.db' (used to indicate the name of the output check result file)

[0085] In this way, the compiled design rule check file can read the layout file to be detected from the specified path according to its environment parameter settings to perform relevant detections, and the detection results are saved in the check result file specified by the environment parameters.

[0086] Continuing to refer to Figure 3 , the method further includes step S305, positioning the error reporting location and its related inspection items according to the obtained detection results, and marking or mapping them (such as in the form of a file or a graphical form, etc.) to the corresponding layer in the layout design file of the chip carrier to facilitate the modification of the corresponding layout design file.

[0087] In yet another embodiment, the method further includes: in response to a request from a user to add inspection items, inserting the received inspection items, the inspection rules and inspection operations associated therewith into the corresponding parts of the design rule check file, and recompiling the updated rule check file. This embodiment improves the configurability of the design rule check file and makes it more convenient to supplement or add inspection items related to manufacturability at any time.

[0088] Through the above embodiments, the automatic inspection of the carrier layout design file is realized, and visual inspection by designers is no longer required. Not only is the inspection time greatly shortened, but also the detection results are very reliable. And through the auxiliary layer used to indicate the position and size of one or more inspection items in the carrier hierarchy and the configurable design rule check file, the inspection items related to manufacturability detection can be flexibly set and adjusted, effectively improving the flexibility and scalability of manufacturability detection.

[0089] Figure 4 The functional module schematic diagram of a system for detecting the manufacturability of a chip carrier according to yet another embodiment of the present application is shown. As Figure 4 shown, the system 400 includes a mapping module 401, an execution module 402, and a reporting module 403. The mapping module 401 is used to identify one or more auxiliary layers for manufacturability detection from the received layout design file of the chip carrier, and turn on the inspection items associated with the identified auxiliary layers in the design rule check file; and is used to map each layer and auxiliary layer of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchies predefined in the design rule check file. The execution module 402 is used to start the design rule check file to check the layout design file of the chip carrier to obtain the detection result. The reporting module 403 is used to locate the error reporting position and its related inspection items according to the obtained detection result, and mark or map them to the corresponding hierarchies in the layout design file of the chip carrier to facilitate the modification of the corresponding layout design file.

[0090] In yet another embodiment, the system may further include a rule compilation module, which is used to insert the received inspection items, the inspection rules and inspection operations associated therewith into the corresponding parts of the design rule check file, and recompile the updated rule check file.

[0091] In yet another embodiment of the present application, a computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the method described above in combination with Figure 1 or Figure 3 In the present application, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device.

[0092] It should be understood that for the steps, processes or methods mentioned in this text, in addition to being implemented in the form of pure computer-readable program code, they can completely be realized by logically programming the corresponding functional modules, processes or steps in such a way that these modules are in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers, etc. to achieve the same functions. Therefore, the modules or devices thus implemented can be regarded as a kind of hardware components, and the sub-modules included therein for realizing various functions can also be regarded as the internal structures of the hardware components. Alternatively, the devices for realizing various functions can be regarded as either software modules for implementing the relevant processes or method steps or structures within the hardware components.

[0093] References in this specification to "each embodiment", "some embodiments", "an embodiment", or "embodiments", etc. refer to specific features, structures, or properties described in connection with the above embodiments being included in at least one embodiment. Thus, the appearances of the phrases "in each embodiment", "in some embodiments", "in an embodiment", or "in embodiments", etc. throughout the specification are not necessarily referring to the same embodiment. In addition, the specific features, structures, or properties can be combined in any suitable manner in one or more embodiments. Therefore, the specific features, structures, or properties shown or described in connection with one embodiment can be combined with the features, structures, or properties of one or more other embodiments wholly or partially without limitation, as long as the combination is not illogical or inoperable.

[0094] Expressions of terms such as "including" and "having" and similar meanings in this specification are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices. "A" or "an" does not exclude the case of multiple. Additionally, the elements in the drawings of this application are only for illustrative purposes and are not drawn to scale.

[0095] Although this application has been described through the above embodiments, this application is not limited to the embodiments described herein, and various changes and variations are also included without departing from the scope of this application.

Claims

1. A method for detecting the manufacturability of a chip carrier, comprising: obtaining one or more inspection items from a configuration file or a user interface; in a layout design file of the chip carrier, adding one or more auxiliary layers for manufacturability detection to the carrier hierarchy, where the auxiliary layer includes a positioning frame indicating the position and size of one or more inspection items; mapping each layer and the auxiliary layer of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchies predefined in a design rule check file for manufacturability detection; setting the inspection items related to manufacturability detection in the design rule check file according to the obtained one or more inspection items; performing a design rule check on the layout design file of the chip carrier based on the design rule check file and outputting a detection result.

2. The method according to claim 1, wherein at least one of the one or more auxiliary layers includes a positioning frame indicating the position and size of the chip and a positioning frame indicating the boundary of the chip carrier.

3. The method according to claim 1, wherein the one or more inspection items include a combination of one or more of the following: capacitance, resistance, chip, lid for packaging the chip, positioning mark, carrier identification.

4. The method according to any one of claims 1-3, wherein the design rule check file includes inspection items related to manufacturability detection, rule definitions related to each inspection item, carrier hierarchy definitions, and inspection operations for each hierarchy.

5. The method according to claim 4, further comprising converting the layout design file of the chip carrier into a layout format file recognizable by the design rule check file.

6. The method according to claim 4, further comprising turning on or off the corresponding inspection items in the design rule check file according to the auxiliary layer of the carrier hierarchy in the layout design file to be currently detected.

7. A method for detecting the manufacturability of a chip carrier, comprising: identifying one or more auxiliary layers for manufacturability detection from a received layout design file of the chip carrier, where the auxiliary layer includes a positioning frame indicating the position and size of one or more inspection items; turning on the inspection items associated with the identified auxiliary layer in a design rule check file; mapping each layer and the auxiliary layer of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchies predefined in the design rule check file; starting the design rule check file to check the layout design file of the chip carrier to obtain a detection result.

8. The method according to claim 7, further comprising positioning the location of the error reporting and its related inspection items according to the obtained detection result and marking or mapping them to the corresponding hierarchies in the layout design file of the chip carrier.

9. The method according to claim 7, further comprising in response to a request from a user to add an inspection item, inserting the received inspection item, its related inspection rules and inspection operations into the corresponding part of the design rule check file and recompiling the updated rule check file.

10. A system for detecting the manufacturability of a chip carrier, comprising: A mapping module, configured to identify one or more auxiliary layers for manufacturability detection from the received layout design file of the chip carrier, enable the check items associated with the identified auxiliary layers in the design rule check file, and map each layer and the auxiliary layer of the carrier hierarchy in the layout design file of the chip carrier to the corresponding hierarchies predefined in the design rule check file; wherein the auxiliary layer includes a positioning frame indicating the positions and sizes of one or more check items; An execution module, configured to start the design rule check file to check the layout design file of the chip carrier to obtain a detection result; A reporting module, configured to locate the error reporting positions and their related check items according to the obtained detection results, and mark or map them to the corresponding hierarchies in the layout design file of the chip carrier.

11. The system according to claim 10, further comprising a rule compilation module, configured to insert the received check items, the related check rules and check operations into the corresponding parts of the design rule check file, and recompile the updated rule check file.

12. A computer-readable storage medium, having stored thereon computer instructions, which when executed by a processor, implement the method according to any one of claims 1-9.

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