A scalable image processor module architecture and data processing method

Abstract

The present invention discloses an expandable image processor module architecture and data processing method, wherein the architecture includes an IO module electrically connected to a CPU and several GPM modules, wherein the IO module is directly electrically connected to each GPM module; a state table is configured, wherein the state table includes GPM number information and state information, wherein each GPM module has unique GPM number information, and the state information includes an operational state and a non-operable state; the state table is called and a task allocation instruction including target task data and target GPM number information is generated in combination with current task processing requirements, wherein the state information corresponding to the target GPM number information is an operational state; the target task data is transmitted to the corresponding GPM module through the IO module, and the state information corresponding to the target GPM number information in the state table is updated to a non-operable state. The present invention can improve the computing power of a graphics processor and avoid problems such as load imbalance and task segmentation.

Description

Technical Field

[0001] The present invention relates to the technical field of computer graphics processing, and in particular to an expandable image processor module architecture and a data processing method. Background Art

[0002] In the field of modern computer graphics processing technology, especially when processing artificial intelligence applications, multiple graphics processors (GPUs) are usually required to perform parallel operations and then return the results to the central processing unit. The performance growth of a single GPU chip is slowed down by the increase in the number of transistors per unit area, and the size and performance of a single GPU chip are limited by the maximum chip area (reticle size) and gradually reach saturation. However, as the large models of artificial intelligence increase the computing power of graphics processors, the demand for chip computing power continues to grow. Therefore, the current common solution is to add more graphics processors to meet the demand for higher computing power.

[0003] In the prior art, a multi-module GPU packaging structure is constructed to meet the demand for higher computing power. Figure 1 As shown in the figure, a logical GPU is packaged by building multiple GPUs, an IO module and high-bandwidth connections between modules. In this structure, the IO module is only connected to a specific GPU, and each GPU is connected to other GPUs separately. This structure is technically called a "full mesh structure". Although this technical solution can improve the computing power of the graphics processor, it has the following shortcomings.

[0004] First, in parallel computing, in order to reduce load imbalance or cross-board time delay, it is best to maximize the number of GPU clusters under the scheduling management of the same CPU. However, as the number of GPUs increases, the amount of data that needs to be exchanged also increases. Simple topology connections often result in a decrease in marginal computing power as the number of GPUs increases.

[0005] Secondly, when building a multi-module GPU, if you simply build multiple independent GPUs to interconnect, it will lead to a series of problems such as task segmentation, orchestration affinity scheduling, load imbalance, etc., resulting in the performance not being able to increase linearly with the increase in the number of modules.

[0006] In addition, the existing "full mesh structure" graphics processor architecture is that one CPU corresponds to multiple graphics processors, and the graphics processor frequently exchanges data with the CPU, which in turn affects the CPU's processing performance for other instructions.

[0007] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0008] The purpose of the present invention is to provide an expandable image processor module architecture and data processing method, which can improve the computing power of the graphics processor while avoiding problems such as load imbalance and task segmentation caused by the increase of image processing modules.

[0009] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0010] An expandable image processor module architecture includes an IO module and a plurality of GPM modules, wherein the IO module is configured to be electrically connected to a CPU, and the IO module is directly electrically connected to each of the GPM modules;

[0011] A state table is configured inside the image processor module, and the state table stores GPM module information corresponding to each GPM module, the GPM module information includes GPM number information and state information with corresponding relationship, each GPM module has unique GPM number information, and the state information includes an operational state and a non-operational state;

[0012] Calling the state table and generating a task allocation instruction in combination with the current task processing requirements, the task allocation instruction includes target task data and target GPM number information, the target GPM number information is one of the GPM number information and the state information corresponding thereto is an executable state;

[0013] The IO module transmits the target task data to the GPM module corresponding to the target GPM number information in response to receiving the task allocation instruction;

[0014] The GPM module is configured to receive and process the target task data, and update the state information corresponding to the target GPM number information in the state table to a non-operable state.

[0015] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the CPU is connected to the IO module in a two-way communication manner, and the IO module is connected to each of the GPM modules in a two-way communication manner;

[0016] The GPM module obtains corresponding processed data after completing the processing of the target task data, and the processed data is configured to be transmitted to the CPU through the IO module;

[0017] The CPU receives the processed data and updates the status table accordingly, including updating the status information of the GPM module corresponding to the processed data returned in the status table to the executable state.

[0018] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the IO module also includes a cross switch matrix, and the cross switch matrix is ​​configured to control the CPU and one or more GPM modules to transmit data through the IO module.

[0019] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the status table also includes task information corresponding to each task, the task information includes a task name, a task type and a task status with a corresponding relationship, each task has a unique task name, different types of tasks correspond to different task types, and the same type of tasks correspond to the same task type, and the task status includes to be completed and completed;

[0020] The task status corresponding to the target task data is to be completed, and the task status corresponding to the processed data is completed.

[0021] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the task information also includes a completion time corresponding to the task name;

[0022] If there are multiple GPM modules in the executable state at the same time, the processing time of each GPM module for the same task type is determined based on the task type, completion time and GPM number information in the status table, and the target task data is allocated to the GPM module with a short processing time. The processing time corresponds to the completion time, and the processing time is determined according to the completion time.

[0023] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the IO module adopts IODie; and / or,

[0024] The IO module includes a bus interface and a GPM interface, the bus interface is configured to be connected to the CPU, and the GPM interface is configured to be connected to the GPM module; and / or,

[0025] The IO module comprises an IO preset interface, and the IO preset interface is configured to be connected to another IO module; and / or,

[0026] The different GPM modules are connected in bidirectional communication via the IO module.

[0027] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the number of the IO modules is at least two, and the CPU is electrically connected to the multiple IO modules in series in sequence;

[0028] Each of the IO modules is directly electrically connected to a plurality of the GPM modules, and one GPM module is directly electrically connected to only one IO module.

[0029] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, a serializer and a deserializer are configured between the two IO modules that are electrically connected to each other.

[0030] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, data transmission is performed between the two IO modules electrically connected to each other based on a private protocol; or,

[0031] Data is transmitted between the two IO modules electrically connected to each other based on the universal protocol PCIe.

[0032] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the number of the IO modules is at least two, and each of the IO modules is electrically connected to the CPU respectively;

[0033] Each of the IO modules is directly electrically connected to a plurality of the GPM modules, and one GPM module is directly electrically connected to only one IO module.

[0034] According to another aspect of the present invention, the present invention provides a data processing method, comprising the following steps:

[0035] configuring the IO module to be directly electrically connected to each of the plurality of GPM modules;

[0036] A state table is configured, wherein the state table stores GPM module information corresponding to each GPM module, wherein the GPM module information includes GPM number information and state information having a corresponding relationship, wherein each GPM module has unique GPM number information, and the state information includes an operational state and a non-operational state;

[0037] Calling the state table and generating a task allocation instruction in combination with the current task processing requirements, the task allocation instruction includes target task data and target GPM number information, the target GPM number information is one of the GPM number information and the state information corresponding thereto is an executable state;

[0038] Based on the task allocation instruction, the target task data is transmitted to the GPM module corresponding to the target GPM number information through the IO module, and the GPM module is configured to receive and process the target task data;

[0039] The status information corresponding to the target GPM number information in the status table is updated to a non-operable state.

[0040] Any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps:

[0041] The GPM module obtains corresponding processed data after completing the processing of the target task data, and the processed data is configured to be transmitted back through the IO module;

[0042] Updating the state table includes updating the state information of the GPM module corresponding to the processed data returned in the state table to the executable state.

[0043] Any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps:

[0044] The status table also includes task information corresponding to each task, the task information includes a task name, a task type and a task status having a corresponding relationship, each task has a unique task name, different types of tasks correspond to different task types, and the same types of tasks correspond to the same task type, and the task status includes to be completed and completed;

[0045] The task status corresponding to the target task data is to be completed, and the task status corresponding to the processed data is completed.

[0046] Any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps:

[0047] The task information also includes a completion time corresponding to the task name;

[0048] If there are multiple GPM modules in the executable state at the same time, the processing time of each GPM module for the same task type is determined based on the task type, completion time and GPM number information in the status table, and the target task data is allocated to the GPM module with a short processing time, and the processing time corresponds to the completion time.

[0049] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0050] a. The scalable image processor module architecture provided by the present invention can quickly and conveniently expand the number of GPM modules by adding GPM modules to connect with IO modules without increasing circuit complexity and wiring space occupation to meet the growing computing power requirements, and will not cause problems such as load imbalance and task segmentation due to adding GPM modules;

[0051] b. The topological structure of the image processor module architecture provided by the present invention can reduce the large number of input and output requests of multiple GPM modules to the CPU. Each graphics processor will make data requests to the CPU when running. In order to meet the computing power requirements of the AI ​​era, current computers and servers will be equipped with multiple graphics processors for a single CPU, so the CPU performance will be largely occupied by the graphics processor; constructing a logical GPU, integrating multiple graphics processors, and exchanging data with the CPU through a unique IO Die can solve technical problems such as more extensive GPU module expansion and efficiency compatibility;

[0052] c. The present invention integrates the GPM module of the IO module into a whole, configures a state table in the image processor, and uses the state table to track and process each task and the real-time status of each GPM module, thereby reducing interference to the CPU and improving the utilization rate of each GPM module;

[0053] d. The present invention tracks and records the processing time of each GPM module for the same type of tasks through a state table, and in each task allocation process, preferentially allocates the task to the GPM module with higher processing efficiency, which can effectively improve the efficiency of the image processor in task processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A schematic diagram of a module of a graphics processor architecture with a full mesh structure in the prior art;

[0056] Figure 2 A schematic diagram of a graphics processor architecture provided for an exemplary embodiment of the present invention;

[0057] Figure 3 A schematic diagram of an IO module provided for an exemplary embodiment of the present invention;

[0058] Figure 4A schematic diagram of a first processor architecture with multiple IO modules provided for an exemplary embodiment of the present invention;

[0059] Figure 5 A schematic diagram of a second type of processor architecture with multiple IO modules provided for an exemplary embodiment of the present invention;

[0060] Figure 6 A schematic diagram of a third type of module of a processor architecture with multiple IO modules provided for an exemplary embodiment of the present invention;

[0061] Figure 7 A flowchart of a data processing method provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0063] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0064] In one embodiment of the present invention, a scalable image processor module architecture is provided. Figure 2 and Figure 7 , which includes an IO module (input and output module) and several GPM modules (Graph Process Module, image processing module), the IO module is configured to be electrically connected to a CPU (processor, which can be set in the image processor module or an external CPU), and the IO module is directly electrically connected to each of the GPM modules;

[0065] A state table is configured inside the image processor module, and the state table stores GPM module information corresponding to each GPM module, the GPM module information includes GPM number information and state information with corresponding relationship, each GPM module has unique GPM number information, and the state information includes an operational state and a non-operational state;

[0066] Calling the state table and generating a task allocation instruction in combination with the current task processing requirements, the task allocation instruction includes target task data and target GPM number information, the target GPM number information is one of the GPM number information and the state information corresponding thereto is an executable state;

[0067] The IO module transmits the target task data to the GPM module corresponding to the target GPM number information in response to receiving the task allocation instruction;

[0068] The GPM module is configured to receive and process the target task data, and update the state information corresponding to the target GPM number information in the state table to a non-operable state.

[0069] Based on the scalable image processor module architecture provided by the present invention, the following technical problems can be solved:

[0070] (1) Without increasing circuit complexity and wiring space occupation, by increasing the connection between GPM modules and IO modules, the number of GPM modules can be quickly and easily expanded to meet the growing computing power requirements;

[0071] (2) It can maintain high performance while avoiding problems such as load imbalance and task splitting caused by the increase in the number of GPM modules;

[0072] (3) While increasing computing power, ensure data transmission efficiency between different chips and boards. Figure 1 The topology shown is indeed more efficient in transmitting data, but the difficulty in improving computing power will increase exponentially. Therefore, the improved topology proposed in this application improves computing power expansion while slightly reducing the transmission speed while still maintaining efficient transmission.

[0073] (4) It can reduce the large number of input and output requests from multiple graphics processors (GPM modules) to the CPU. Each graphics processor will request data from the CPU when running. In order to meet the computing power requirements of the AI ​​era, current computers and servers will be equipped with multiple graphics processors on a single CPU, so the CPU performance will be largely occupied by the graphics processor. Constructing a logical GPU, integrating multiple graphics processors, and using a single IO Die to exchange data with the CPU can solve technical problems such as a wider range of GPU module expansion and efficiency compatibility.

[0074] (5) Based on the status table, the GPM modules of each IO module are integrated into a whole, thereby reducing interference to the CPU and improving the utilization rate of each GPM module.

[0075] In this embodiment, the IO module preferably uses IO Die, which is a special chip that is mainly responsible for the data input and output functions of the CPU and integrates a DDR4 memory controller, a PCIE4.0 controller, and a USB and SATA controller. Figure 3 , the IO module includes at least one bus interface, several GPM interfaces and at least one IO preset interface. The bus interface is configured to be connected to the CPU, and the CPU and the IO module are bidirectionally communicated through the bus interface; one GPM interface is configured to be connected to a GPM module, and the IO module and the GPM module are bidirectionally communicated through the GPM interface; the IO preset interface is configured to be connected to another IO module, and the two IO modules connected through the IO preset interface are bidirectionally communicated.

[0076] like Figure 3 As shown, a crossbar is established in the IO module, which can exchange multiple groups of data at the same time, and control the CPU and one or more GPM modules to transmit data through the IO module by controlling the switch state of the crossbar, and control different GPM modules to transmit data through the IO module. The crossbar is a basic circuit design that can specify which line is connected by controlling whether the logic gate is turned on, and supports the simultaneous connection of array circuits.

[0077] The CPU receives the processed data and updates the state table accordingly, including updating the state information of the GPM module corresponding to the processed data in the state table to the operational state. Preferably, when the processed data is transmitted from the GPM module to the CPU, the state information of the corresponding GPM module in the state table is updated to the operational state. Based on the two-way transmission function, the CPU and the GPM module can transmit and send data at the same time, thereby improving the processing efficiency of the image processor.

[0078] It should be noted that the state table can be as follows Figure 3 As shown, it is set in the IO module and can also be set in the CPU. Task allocation and the update of the status table can be completed by the CPU or by the IO module. If the task allocation is completed by the IO module, the task flow execution order is that the CPU sends the task to the GPU (the whole of the IO module and each GPM module connected to it), the IO module of the GPU receives the task and divides the task into subtasks and assigns it to the GPM module for calculation. After the task is completed, the data is transmitted back to the CPU or other computer components such as memory through the IO module.

[0079] In one embodiment of the present invention, as shown in Table 1, the state table includes GPM module information and task information. The GPM module information includes GPM number information and state information, and the state information includes an operational state and a non-operable state. In Table 1, the operational state is represented by 1, and the non-operable state is represented by 0. When the state information corresponding to the GPM module is 1, it means that a task can be assigned to it; when the state information corresponding to the GPM module is 0, it means that a task cannot be assigned to it. Each GPM module has a unique GPM number, and the GPM number information and the state information have a corresponding relationship, so that the current state of each GPM module can be determined through the state table, and tasks can be reasonably assigned according to the current state of each GPM module.

[0080] The task information corresponds to each task. As shown in Table 1, the task information includes a task name, a task type, and a task status that have a corresponding relationship. Each task has a unique task name (as shown in Table 1 with D1 to D2). n Different types of tasks correspond to different task types (such as T1 to T n denoted by ), tasks of the same type correspond to the same task type, and the task status includes to be completed and completed. In Table 1, tasks to be completed are denoted by the letter P, and completed tasks are denoted by D. The task status corresponding to the target task data described above is to be completed P, and the task status corresponding to the processed data is completed D.

[0081]

[0082] In one embodiment of the present invention, the task information also includes a completion time corresponding to the task name. As shown in Table 1, for a completed task, it corresponds to the task completion time and records the GPM module that processes the task.

[0083] If there are multiple GPM modules in the executable state at the same time, the CPU is also configured to determine the processing time of each GPM module for the same task type based on the task type, completion time and GPM number information in the status table, and allocate the target task data to the GPM module with a short processing time.

[0084] If the task type corresponding to the target task to be assigned is T1, according to Table 1, the currently executable ones are G1, G2, G5, and G6, among which the GPM modules that have pre-processed the T1 task type are G1 and G6. Compare S1 and S6. If S1 is smaller, the target task is assigned to G1; if S6 is smaller, the target task is assigned to G6. In this way, the target task to be processed can be efficiently and quickly assigned to the GPM module with higher processing efficiency, which can improve the overall processing efficiency of the image processor.

[0085] The processing time corresponds to the completion time. Specifically, the processing time can be the most recent completion time of the task of the task type by the GPM module, or it can be the average of the previous completion times of the tasks of the task type by the GPM module. More preferably, the average of the recent completion times of the tasks of the task type by the GPM module is determined as the processing time. For example, a GPM module has previously processed and completed N1 times (such as 300 times) for a task of type T1, and the average of the most recent N2 (such as 20 times) completion times is determined as the processing time of the task of the type T1 by the GPM module, 0<N2<N1. In this way, the adverse effects caused by the fluctuation of the single processing efficiency can be reduced, and it is more in line with the current performance of each GPM module, thereby improving the efficiency of task processing by the graphics processor.

[0086] Preferably, in the image processor module architecture provided by this embodiment, different GPM modules can also transmit data through the IO module. Based on data dependency, when the task operated by the GPM module requires the structure of other GPM modules to operate on the task, data can be directly obtained from the corresponding GPM module.

[0087] In one embodiment of the present invention, the number of the IO modules in the image processor module architecture is at least two, and the CPU is electrically connected to the plurality of IO modules in series in sequence. Each IO module is directly electrically connected to the plurality of GPM modules, and one GPM module is electrically connected to only one IO module.

[0088] For example, Figure 4 As shown, the image processor module architecture includes two IO modules, and the two IO modules are connected in series with the CPU in sequence. The IO module farther from the CPU can also be electrically connected to other CPUs, thereby realizing the expansion of one CPU chip to other CPU modules.

[0089] Preferably, when the image processor module architecture includes a plurality of the IO modules, the status table also includes an IO number, the IO number corresponds to the IO module one-to-one, and the IO number corresponding to each IO module is unique. The plurality of IO modules are connected in series, and the IO number corresponds to the distance between each IO module and the CPU. For example, the IO number is formed by numbering each IO module in the order of the transmission distance between the IO module and the CPU from near to far.

[0090] For example, Figure 5 As shown, the image processor module architecture includes three IO modules, and the three IO modules are connected in series with the CPU in sequence.

[0091] For the image processor module architecture including multiple IO modules, a serializer and a deserializer are configured between two IO modules electrically connected to each other for long-distance transmission. Data is transmitted between the two IO modules electrically connected to each other based on the universal protocol PCIe. PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. It is both a physical interface for connecting various expansion cards and devices inside a computer, and a set of specifications or protocols that define how these connections work. More preferably, data is transmitted between the two IO modules electrically connected to each other based on private protocols to increase the speed of data transmission.

[0092] In one embodiment of the present invention, the number of the IO modules is at least two, and each of the IO modules is electrically connected to the CPU. Figure 6 Each of the IO modules is directly electrically connected to a plurality of the GPM modules, and one GPM module is only electrically connected to one IO module.

[0093] In one embodiment of the present invention, a data processing method is provided. Figure 7 , the method comprises the following steps:

[0094] configuring the IO module to be directly electrically connected to each of the plurality of GPM modules;

[0095] A state table is configured, wherein the state table stores GPM module information corresponding to each GPM module, wherein the GPM module information includes GPM number information and state information having a corresponding relationship, wherein each GPM module has unique GPM number information, and the state information includes an operational state and a non-operational state;

[0096] Calling the state table and generating a task allocation instruction in combination with the current task processing requirements, the task allocation instruction includes target task data and target GPM number information, the target GPM number information is one of the GPM number information and the state information corresponding thereto is an executable state;

[0097] Based on the task allocation instruction, the target task data is transmitted to the GPM module corresponding to the target GPM number information through the IO module, and the GPM module is configured to receive and process the target task data;

[0098] The status information corresponding to the target GPM number information in the status table is updated to a non-operable state.

[0099] The GPM module obtains corresponding processed data after completing the processing of the target task data, and the processed data is configured to be transmitted back to the CPU or other devices connected to the IO module through the IO module; updating the status table includes updating the status information of the GPM module corresponding to the processed data transmitted back in the status table to the executable state.

[0100] Preferably, the status table also includes task information corresponding to each task, the task information includes a task name, a task type, a task status and a completion time with corresponding relationships, each task has a unique task name, different types of tasks correspond to different task types, and the same types of tasks correspond to the same task types, and the task status includes to be completed and completed. The task status corresponding to the target task data is to be completed, and the task status corresponding to the processed data is completed.

[0101] If there are multiple GPM modules in the executable state at the same time, the processing time of each GPM module for the same task type is determined based on the task type, completion time and GPM number information in the status table, and the target task data is allocated to the GPM module with a short processing time, and the processing time corresponds to the completion time.

[0102] It should be noted that the data processing method embodiment provided by the present invention has the same inventive concept as the above-mentioned scalable image processor module architecture embodiment, and all the contents of the scalable image processor module architecture embodiment are incorporated into the data processing method embodiment by introduction.

[0103] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0104] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A scalable image processor module architecture, characterized in that: It includes an IO module and several GPM modules, wherein the IO module is configured to be electrically connected to the CPU, and the IO module is directly electrically connected to each of the GPM modules; A state table is configured inside the image processor module, and the state table stores GPM module information corresponding to each GPM module, the GPM module information includes GPM number information and state information with a corresponding relationship, each GPM module has a unique GPM number information, and the state information includes an operational state and a non-operational state; Calling the state table and generating a task allocation instruction in combination with the current task processing requirements, the task allocation instruction includes target task data and target GPM number information, the target GPM number information is one of the GPM number information and the state information corresponding thereto is an executable state; The IO module transmits the target task data to the GPM module corresponding to the target GPM number information in response to receiving the task allocation instruction; The GPM module is configured to receive and process the target task data, and update the state information corresponding to the target GPM number information in the state table to a non-operable state.

2. The scalable image processor module architecture according to claim 1, characterized in that: The CPU is connected to the IO module for bidirectional communication, and the IO module is connected to each of the GPM modules for bidirectional communication; The GPM module obtains corresponding processed data after completing the processing of the target task data, and the processed data is configured to be transmitted to the CPU through the IO module; The CPU receives the processed data and updates the status table accordingly, including updating the status information of the GPM module corresponding to the processed data returned in the status table to the executable state.

3. The scalable image processor module architecture according to claim 1, characterized in that: The IO module further includes a crossbar switch matrix configured to control the CPU and one or more GPM modules to perform data transmission through the IO module.

4. The scalable image processor module architecture according to claim 1, characterized in that: The status table also includes task information corresponding to each task, the task information includes a task name, a task type and a task status having a corresponding relationship, each task has a unique task name, different types of tasks correspond to different task types, and the same types of tasks correspond to the same task type, and the task status includes to be completed and completed; The task status corresponding to the target task data is to be completed, and the task status corresponding to the processed data is completed.

5. The scalable image processor module architecture according to claim 4, characterized in that: The task information also includes a completion time corresponding to the task name; If there are multiple GPM modules in the executable state at the same time, the processing time of each GPM module for the same task type is determined based on the task type, completion time and GPM number information in the status table, and the target task data is allocated to the GPM module with a short processing time, and the processing time corresponds to the completion time.

6. The scalable image processor module architecture according to claim 1, characterized in that: The IO module adopts IO Die; and / or, The IO module includes a bus interface and a GPM interface, the bus interface is configured to be connected to the CPU, and the GPM interface is configured to be connected to the GPM module; and / or, The IO module comprises an IO preset interface, and the IO preset interface is configured to be connected to another IO module; and / or, The different GPM modules are connected in bidirectional communication via the IO module.

7. The scalable image processor module architecture according to any one of claims 1 to 6, characterized in that: The number of the IO modules is at least two, and the CPU is electrically connected in series with the plurality of IO modules in sequence; Each of the IO modules is directly electrically connected to a plurality of the GPM modules, and one GPM module is electrically connected to only one IO module.

8. The scalable image processor module architecture according to claim 7, characterized in that: A serializer and a deserializer are configured between the two IO modules that are electrically connected to each other.

9. The scalable image processor module architecture according to claim 7, characterized in that: Data is transmitted between the two IO modules electrically connected to each other based on a private protocol; or, Data is transmitted between the two IO modules electrically connected to each other based on the universal protocol PCIe.

10. The scalable image processor module architecture according to any one of claims 1 to 6, characterized in that: The number of the IO modules is at least two, and each of the IO modules is electrically connected to the CPU respectively; Each of the IO modules is directly electrically connected to a plurality of the GPM modules, and one GPM module is electrically connected to only one IO module.

11. A data processing method, characterized in that: The following steps are involved: configuring the IO module to be directly electrically connected to each of the plurality of GPM modules; A state table is configured, wherein the state table stores GPM module information corresponding to each GPM module, wherein the GPM module information includes GPM number information and state information having a corresponding relationship, wherein each GPM module has unique GPM number information, and the state information includes an operational state and a non-operational state; Calling the state table and generating a task allocation instruction in combination with the current task processing requirements, the task allocation instruction includes target task data and target GPM number information, the target GPM number information is one of the GPM number information and the state information corresponding thereto is an executable state; Based on the task allocation instruction, the target task data is transmitted to the GPM module corresponding to the target GPM number information through the IO module, and the GPM module is configured to receive and process the target task data; The status information corresponding to the target GPM number information in the status table is updated to a non-operable state.

12. The data processing method according to claim 11, characterized in that: The following steps are also included: The GPM module obtains corresponding processed data after completing the processing of the target task data, and the processed data is configured to be transmitted back through the IO module; Updating the state table includes updating the state information of the GPM module corresponding to the processed data returned in the state table to the executable state.

13. The data processing method according to claim 12, characterized in that: The following steps are also included: The status table also includes task information corresponding to each task, the task information includes a task name, a task type and a task status having a corresponding relationship, each task has a unique task name, different types of tasks correspond to different task types, and the same types of tasks correspond to the same task type, and the task status includes to be completed and completed; The task status corresponding to the target task data is to be completed, and the task status corresponding to the processed data is completed.

14. The data processing method according to claim 13, characterized in that: The following steps are also included: The task information also includes a completion time corresponding to the task name; If there are multiple GPM modules in the executable state at the same time, the processing time of each GPM module for the same task type is determined based on the task type, completion time and GPM number information in the status table, and the target task data is allocated to the GPM module with a short processing time, and the processing time corresponds to the completion time.

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