Display method and display device

Abstract

The display method and the display device relate to the technical field of display. The display method is applied to a display device. The display device comprises a display panel. The display method comprises: a first stage, providing first display data to the display panel to display a first picture on a first display side of the display panel; and a second stage, providing second display data to the display panel to display a second picture on a second display side of the display panel; wherein the first display side is arranged opposite to the second display side, and the first stage and the second stage are alternately performed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display method and a display device. BACKGROUND

[0002] With the development of vehicle control systems and the increase of vehicle functions, users' requirements for vehicle display are gradually increasing. Vehicle display can provide the most intuitive experience for users, can provide navigation information for drivers, and can provide movies, games and other entertainment information for passengers, thereby improving users' ride experience. SUMMARY

[0003] The present disclosure provides a display method applied to a display device, the display device comprising a display panel, the display method comprising:

[0004] a first stage of providing first display data to the display panel to display a first picture on a first display side of the display panel; and

[0005] a second stage of providing second display data to the display panel to display a second picture on a second display side of the display panel;

[0006] wherein the first display side is arranged opposite to the second display side, and the first stage and the second stage are alternately performed.

[0007] In some embodiments, the first stage comprises M frame periods, the first picture is refreshed once in one frame period of the first stage, and the M is greater than or equal to 1.

[0008] The second stage comprises N frame periods, the second picture is refreshed once in one frame period of the second stage, and the N is greater than or equal to 1.

[0009] In some embodiments, the M is equal to the N.

[0010] In some embodiments, the display panel is a liquid crystal display panel, and between adjacent first stages and second stages, the display method further comprises:

[0011] a third stage of providing third display data to the display panel to display a black picture on a liquid crystal display panel in a common black mode, or to display a white picture on a liquid crystal display panel in a common white mode.

[0012] In some embodiments, the third stage comprises L frame periods, the L is greater than 0 and less than or equal to 1.

[0013] In some embodiments, the display panel is a liquid crystal display panel, the display device further comprises a first backlight module and a second backlight module, the first backlight module is configured to provide backlight to the first display side, the second backlight module is configured to provide backlight to the second display side, the steps of the first stage further comprise:

[0014] controlling the first backlight module to be turned on and the second backlight module to be turned off;

[0015] the steps of the second stage further comprise:

[0016] controlling the second backlight module to be turned on and the first backlight module to be turned off.

[0017] In some embodiments, the first stage comprises a first refresh stage and a first holding stage in the same frame period, the second stage comprises a second refresh stage and a second holding stage in the same frame period, the step of providing the display panel with first display data comprises:

[0018] in the first refresh stage, providing the display panel with first display data;

[0019] the step of controlling the first backlight module to be turned on comprises:

[0020] in the first holding stage, controlling the first backlight module to be turned on;

[0021] the step of providing the display panel with second display data comprises:

[0022] in the second refresh stage, providing the display panel with second display data;

[0023] the step of controlling the second backlight module to be turned on comprises:

[0024] in the second holding stage, controlling the second backlight module to be turned on.

[0025] In some embodiments, the display device further comprises a first buffer, a memory and a driving chip, the first buffer is configured to buffer the first display data, before the steps of the first stage, the display device further comprises:

[0026] detecting whether the amount of data in the first buffer meets a first write condition;

[0027] if yes, generating a first write command, and writing the first display data in the first buffer into the memory according to the first write command, the first display data in the memory is configured to be transmitted to the display panel via the driving chip in the first stage.

[0028] In some embodiments, the display device further comprises a second buffer for buffering the second display data, after the step of detecting whether the amount of data in the first buffer meets the write condition, and before the step of the second phase, the display device further comprises:

[0029] If no, detecting whether the amount of data in the second buffer meets a second write condition;

[0030] If yes, generating a second write command, and writing the second display data in the second buffer into the memory according to the second write command, the second display data in the memory is used to be transmitted to the display panel via the driving chip in the second phase.

[0031] In some embodiments, after the step of detecting whether the amount of data in the second buffer meets the write condition, the display device further comprises:

[0032] If no, generating a read command, and reading out the first display data or the second display data from the memory according to the read command.

[0033] In some embodiments, the display device further comprises a command buffer and a data buffer, the step of writing the first display data in the first buffer into the memory according to the first write command comprises:

[0034] writing the first write command into the command buffer, and writing the first display data in the first buffer into the data buffer;

[0035] when detecting that there is a command written in the command buffer, writing the first display data in the data buffer into the memory according to the address and the amount of data in the first write command;

[0036] the step of writing the second display data in the second buffer into the memory according to the second write command comprises:

[0037] writing the second write command into the command buffer, and writing the second display data in the second buffer into the data buffer;

[0038] when detecting that there is a command written in the command buffer, writing the second display data in the data buffer into the memory according to the address and the amount of data in the second write command;

[0039] the step of reading out the first display data or the second display data from the memory according to the read command comprises:

[0040] writing the read command into the command buffer;

[0041] reading out the first display data or the second display data from the memory according to the address and the data amount in the read command when detecting that a command is written into the command buffer.

[0042] In some embodiments, the display device further comprises a memory, and before the first stage and the second stage, further comprises:

[0043] synchronously performing the steps of writing data into the first storage area and reading data from the second storage area; or

[0044] synchronously performing the steps of reading data from the first storage area and writing data into the second storage area;

[0045] wherein the first storage area and the second storage area are different storage areas in the memory.

[0046] The present disclosure provides a display device, comprising:

[0047] a display panel; and

[0048] a control module, connected with the display panel, configured to provide first display data to the display panel in a first stage to display a first picture on a first display side of the display panel, and provide second display data to the display panel in a second stage to display a second picture on a second display side of the display panel; wherein the first display side and the second display side are oppositely arranged, and the first stage and the second stage are alternately performed.

[0049] In some embodiments, the display panel is a liquid crystal display panel, and the display device further comprises:

[0050] a first backlight module configured to provide backlight to the first display side; and

[0051] a second backlight module configured to provide backlight to the second display side.

[0052] The control module is further configured to control the first backlight module to be turned on and the second backlight module to be turned off in the first stage, and control the second backlight module to be turned on and the first backlight module to be turned off in the second stage.

[0053] In some embodiments, the control module comprises a first backlight chip, a second backlight chip and a master control chip.

[0054] The first backlight chip is connected with the master control chip and the first backlight module respectively, and is configured to receive a first control signal sent by the master control chip, and control the first backlight module to open or close in response to the first control signal.

[0055] The second backlight chip is connected with the master control chip and the second backlight module respectively, and is configured to receive a second control signal sent by the master control chip, and control the second backlight module to open or close in response to the second control signal.

[0056] The master control chip is configured to send the first control signal to the first backlight chip, and send the second control signal to the second backlight chip, so as to control the first backlight module to open and the second backlight module to close in the first stage, and control the second backlight module to open and the first backlight module to close in the second stage.

[0057] In some embodiments, the control module further comprises:

[0058] The driving chip is connected with the master control chip and the display panel, and is configured to receive first display data or second display data output by the master control chip, and output the first display data or the second display data to the display panel according to a preset timing sequence; and

[0059] The memory is connected with the master control chip, and is configured to store the first display data and the second display data.

[0060] In some embodiments, the memory comprises a first storage area and a second storage area, the first storage area is configured to store the first display data, and the second storage area is configured to store the second display data.

[0061] In some embodiments, the first storage area comprises a first sub-area and a second sub-area, and first display data of two adjacent first stages are stored in the first sub-area and the second sub-area respectively.

[0062] The second storage area comprises a third sub-area and a fourth sub-area, and second display data of two adjacent second stages are stored in the third sub-area and the fourth sub-area respectively.

[0063] In some embodiments, the storage capacity of the first sub-area, the second sub-area, the third sub-area and the fourth sub-area is the amount of display data of one frame period.

[0064] In some embodiments, the memory is a double data rate synchronous dynamic random access memory.

[0065] The above description is only a summary of the technical solutions of the present disclosure. In order to enable a clearer understanding of the technical means of the present disclosure, the contents of the specification can be implemented, and in order to enable the above and other purposes, features and advantages of the present disclosure to be more obvious and easy to understand, the specific embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0067] Figure 1 An exemplary connection diagram of a display device related to the present disclosure is shown;

[0068] Figure 2 An exemplary connection diagram of a display device related to the present disclosure is shown;

[0069] Figure 3 An exemplary connection diagram of a display device related to the present disclosure is shown;

[0070] Figure 4 A flowchart of a display method provided by the present disclosure is shown;

[0071] Figure 5 Two pictures of bilateral display are shown;

[0072] Figure 6 A timing diagram of display data and backlight control signals is shown;

[0073] Figure 7 An exemplary connection diagram of an FPGA internal module is shown;

[0074] Figure 8 An exemplary working flowchart of an analysis module is shown;

[0075] Figure 9 An exemplary flowchart of display data written into memory by ping-pong read-write control module is shown;

[0076] Figure 10 A timing signal diagram generated according to screen timing requirements is shown;

[0077] Figure 11 A timing signal simulation diagram generated by state machine control using FPGA internal logic resources is shown;

[0078] Figure 12 A ping-pong storage schematic diagram is exemplarily shown.

[0079] Figure 13 A space division schematic diagram of a memory is exemplarily shown. DETAILED DESCRIPTION

[0080] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0081] In the related art, due to the limitation of the size of a vehicle space, the vehicle display cannot simultaneously meet the navigation needs of a driver and the viewing needs of a passenger.

[0082] In the related art, a grating barrier or a column lens is generally used to guide the light of an odd-even pixel array into a set observation area to display different pictures at different viewing angles. This way displays two different pictures on the same screen at the same time, resulting in only half of the screen resolution for each picture.

[0083] Reference Figures 1 to 3 A connection schematic diagram of several display devices related to the present disclosure is exemplarily shown, which includes a display panel 11 and can also include a control module 12 connected with the display panel 11. The execution subject of the display method provided by the present disclosure can be the control module 12 in the display device.

[0084] Reference Figure 4 A flowchart of a display method provided by the present disclosure is shown, as shown in Figure 4 The display method includes the following steps:

[0085] Step S01: In a first stage, first display data is provided to the display panel 11 to display a first picture on a first display side of the display panel 11, as shown in the left picture in Figure 5 .

[0086] Step S02: In a second stage, second display data is provided to the display panel 11 to display a second picture on a second display side of the display panel 11, as shown in the right picture in Figure 5 .

[0087] The first display side is arranged opposite to the second display side, and the first stage and the second stage are alternately performed.

[0088] The display method provided by the present disclosure can realize the effect of bidirectional display without reducing the resolution, by outputting the display picture of one display side at the same time and outputting the display picture of the other display side at the next time, i.e., the display data of the two pictures is output alternately on the same display panel.

[0089] The display method provided by the present disclosure can be applied in vehicle display, the first picture can provide navigation information for the driver, and the second picture can provide entertainment information for the passenger, thereby providing a better driving or traveling experience for the user and enriching the functions of the vehicle system without affecting the driving safety.

[0090] In specific implementation, in order to avoid the flicker caused by refreshing being perceived by the human eye, the refreshing frequency of the unilateral display picture (such as the first picture and the second picture) can be above 60Hz, so that the screen refreshing frequency can be above 120Hz.

[0091] In some embodiments, the first stage includes M frame periods, the first picture is refreshed once in one frame period of the first stage, and M is greater than or equal to 1; the second stage includes N frame periods, the second picture is refreshed once in one frame period of the second stage, and N is greater than or equal to 1.

[0092] In some embodiments, M is equal to N.

[0093] For example, M=N=1, i.e., the first stage includes one frame period, and the second stage includes one frame period, which is equivalent to outputting the first picture and the second picture in an odd-even frame alternation manner. For example, as shown in FIG. 1, the first picture can be output in odd frames (such as the first frame f1, the third frame f3, etc.), and the second picture can be output in even frames (such as the second frame f2, the fourth frame f4, etc.); or the second picture can be output in odd frames, and the first picture can be output in even frames. Figure 6

[0094] For example, M=N=2, i.e., the first stage includes two frame periods, and the second stage includes two frame periods, which is equivalent to outputting in the manner of two frames of the first picture, two frames of the second picture, and then alternately. For example, the first picture can be output in the first frame and the second frame, the second picture can be output in the third frame and the fourth frame, the first picture can be output in the fifth frame and the sixth frame, and the like; or the second picture can be output in the first frame and the second frame, the first picture can be output in the third frame and the fourth frame, the second picture can be output in the fifth frame and the sixth frame, and the like.

[0095] It should be noted that M can also be not equal to N, which is not limited by the present disclosure.

[0096] ​In some embodiments, the display panel 11 is a liquid crystal display panel 11, and between the adjacent first stage and the second stage, the display device further comprises:

[0097] Step S03: a third stage, providing third display data to the display panel 11, so as to display a black picture on the liquid crystal display panel 11 in the normal black mode, and display a white picture on the liquid crystal display panel 11 in the normal white mode.

[0098] In the third stage, the liquid crystal molecules in the liquid crystal display panel 11 can be restored to the initial state, i.e. the state without power supply. By inserting the third stage between the first stage and the second stage, crosstalk between the first picture and the second picture can be avoided.

[0099] In some embodiments, the third stage comprises L frame periods, L is greater than 0 and less than or equal to 1. That is, the duration of the third stage can be greater than 0 and less than or equal to one frame duration, and the specific duration can be determined according to the actual display effect. In specific implementation, the duration of the third stage can also be greater than one frame duration, which is not limited in the present disclosure.

[0100] In some embodiments, the display panel 11 is a liquid crystal display panel, as shown in Figure 1 or Figure 2 The display device further comprises a first backlight module 13 and a second backlight module 14, the first backlight module 13 is used to provide backlight to the first display side, and the second backlight module 14 is used to provide backlight to the second display side,

[0101] In the present embodiment, step S01 can further comprise:

[0102] Step S11: controlling the first backlight module 13 to be turned on and the second backlight module 14 to be turned off.

[0103] In the present embodiment, step S02 can further comprise:

[0104] Step S12: controlling the second backlight module 14 to be turned on and the first backlight module 13 to be turned off.

[0105] In the present embodiment, by time-sharing driving the first backlight module 13 and the second backlight module 14, the first backlight module 13 can be controlled to provide backlight to the first display side only when the first picture is output, and the second backlight module 14 can be controlled to provide backlight to the second display side only when the second picture is output, so as to realize one-side display and avoid interference between the two display pictures.

[0106] In some embodiments, as shown in Figures 1 to 3In any of the embodiments, the control module 12 can include a first backlight chip 15, a second backlight chip 16, and a master chip 17. The first backlight chip 15 is connected to the master chip 17 and the first backlight module 13, respectively, for receiving a first control signal sent by the master chip 17 and controlling the first backlight module 13 to turn on or off in response to the first control signal. The second backlight chip 16 is connected to the master chip 17 and the second backlight module 14, respectively, for receiving a second control signal sent by the master chip 17 and controlling the second backlight module 14 to turn on or off in response to the second control signal. The master chip 17 is configured to send the first control signal to the first backlight chip 15 and the second control signal to the second backlight chip 16, so as to control the first backlight module 13 to turn on and the second backlight module 14 to turn off in the first stage, and control the second backlight module 14 to turn on and the first backlight module 13 to turn off in the second stage.

[0107] In some embodiments, the first stage includes a first refresh stage m1 and a first holding stage n1 in the same frame period, and the second stage includes a second refresh stage m2 and a second holding stage n2 in the same frame period.

[0108] In some embodiments, one frame period includes a refresh stage and a holding stage. The refresh stage is a data writing stage of a current frame, and the holding stage is a holding display stage after the data writing of the current frame is completed and before the data writing of a next frame is performed.

[0109] In the embodiment, the first display data is provided to the display panel 11 in step S01, which can include the following steps. Figure 6 In the embodiment, the first display data is provided to the display panel 11 in step S01, which can include the following steps. Figure 6 In the embodiment, the first backlight module 13 is controlled to turn on in step S11, which can include the following steps.

[0110] For example, in the first refresh stage m1, only data is written, the first backlight module 13 and the second backlight module 14 are turned off, and no backlight is provided to the first display side and the second display side. In the first holding stage n1 after the data writing is completed, the first control signal (e.g., the active signal of CTR1 in Table 1) capable of turning on the first backlight module 13 is provided to the first backlight chip 15, and the backlight is provided to the first display side. In this way, the residual image of the second image on the first display side can be avoided. Figure 6

[0111] In the embodiment, the second display data is provided to the display panel 11 in step S02, which can include the following steps. Figure 6 ​the valid signal of the CTR2) in the second holding stage n2, the step of controlling the second backlight module 14 to open in step S12 can include: controlling the second backlight module 14 to open in the second holding stage n2.

[0112] For example, in the second refresh stage m2, only data is written, the first backlight module 13 and the second backlight module 14 are closed, and no backlight is provided to the first display side and the second display side, while in the second holding stage n2 after the data writing is completed, the second backlight chip 16 is provided with the second control signal (such as Figure 6 the valid signal of the CTR2) capable of opening the second backlight module 14, and the backlight is provided to the second display side, so that the residual image of the first image on the second display side can be avoided.

[0113] In some embodiments, the master chip 17 is further configured to receive the input of two-way display data (such as Figures 1 to 3 INPUT) and output one-way display data at the same time, that is, output the first display data or the second display data.

[0114] Exemplarily, the input format of the first display data and the second display data can be both 1080p60, that is, the picture resolution is 1920x1080, and the frame rate is 60Hz. The output format can be 1080p240, which can include 120Hz black image, 60Hz first image, and 60Hz second image.

[0115] Exemplarily, the master chip 17 is a Field Programmable Gata Array (FPGA). For example, the FPGA includes a Top module, a DisplayPort IP 31, a DDR3 control and drive module 32, and a video timing control module 33. The connection structure of the four modules is as shown in Figure 7 .

[0116] The DisplayPort IP 31 module can be provided by Intel, and supports a scalable main link with 1, 2 or 4 lanes, each lane having 5 optional data rates: 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps and 10.0 Gbps. The main link Main Link can transmit video and audio streams through embedded clock to separate pixel and audio clock from transmission clock. The DisplayPort IP 31 module transmits data of the main link in the scrambled ANSI 8B / 10B format of DP1.4, or in the 128B / 132B format in DP2.0, and contains redundancy in data transmission for error detection. For auxiliary data (such as audio), the DisplayPort IP 31 module uses Reed Solomon encoding for error detection. The AUX channel in the DisplayPort IP 31 module is composed of AC-coupled terminated differential pairs. The AUX channel uses Manchester II encoding for channel coding, and provides a data rate of 1 Mbps. Each transaction takes less than 500 μs, and the maximum burst data size is 16 bytes.

[0117] The DDR3 control and drive module 32 includes a ping-pong read-write control module for receiving two-way display data input by the DisplayPort IP 31 module and generating read-write commands, and a parsing module for performing corresponding read-write operations on the memory 31 according to the read-write commands. The data read out from the memory 31 can pass through the video timing control module 33 and the DisplayPort IP 31 output main control chip 17 in sequence, for example.

[0118] In some embodiments, as shown in Figure 3 The display device further includes a first buffer, a memory 31 and a drive chip 18, the first buffer is used to buffer first display data, and before step S01, with reference to Figure 9 It can also include:

[0119] Step S21: detecting whether the amount of data in the first buffer meets a first write condition.

[0120] Exemplarily, the first write condition can include that the amount of data in the first buffer is greater than or equal to a first preset data amount. The first preset data amount can be determined according to the display data amount of one frame period, for example, the display data amount of one frame period can be determined as an integer multiple of the first preset data amount.

[0121] Exemplarily, for a display panel with a resolution of 1920x1080, the display data amount of one frame period is 1920x1080=2073600 bytes, and accordingly, the first preset data amount can be set as 64 bytes.

[0122] For example, when the first preset data amount is 64 bytes, the data amount in the first buffer (such as FIFO_SINK0 in FIG. 1) can be acquired first, and then it is determined whether the data amount in the first buffer meets the first write condition (such as 1st path data buffer≥64 in FIG. 1). Figure 9 Figure 9 If the data amount in the first buffer is greater than or equal to 64 bytes, it is determined that the first write condition is met; if the data amount in the first buffer is less than 64 bytes, it is determined that the first write condition is not met.

[0123] Step S22: If yes, a first write command is generated, and the first display data in the first buffer is written into the memory 31 according to the first write command, and the first display data in the memory 31 is used to be transmitted to the display panel 11 through the driving chip 18 in the first stage.

[0124] That is, the first write command is executed once every time the data amount in the first buffer is full of the first preset data amount.

[0125] Exemplarily, the first write command includes a first write data amount, which can be the first preset data amount described above. The first write command can also include a first write address, and can also include a burst length, a command type, etc.

[0126] In the present disclosure, the write data amount can refer to the write data length, and the read data amount can refer to the read data length.

[0127] Exemplarily, the display device further includes a command buffer and a data buffer, and step S22 can include:

[0128] Step S31: The first write command is written into the command buffer, and the first display data in the first buffer is written into the data buffer.

[0129] Step S32: When it is detected that there is a command written into the command buffer, the first display data in the data buffer is written into the memory 31 according to the address and data amount in the first write command.

[0130] Referring to Figure 9 ​WR_CMD0 writes the first write command to the command buffer in the parsing module. This first write command may include the first write address and the first write data amount. WR_SINK0 writes the "first write data amount" to the data buffer in the parsing module. During the write process, it is determined whether the write data amount is ≥64 bytes and whether there is a command to write in the command buffer. If not, WR_SINK0 continues to be executed; if so, WR_WAIT0 is executed.

[0131] like Figure 9 As shown, WR_WAIT0 is the function waiting for data to be written to memory 31. During the waiting process, it checks whether the write feedback ≥ 8 is true. If yes, the write is complete; otherwise, it returns WR_WAIT0. For a 64-byte data volume, the parsing module needs to execute 8 stored procedures, with each stored procedure corresponding to one feedback. When all 64 bytes of data have been stored, there will be 8 feedbacks. Therefore, when the write feedback is greater than or equal to 8, it indicates that the write is complete.

[0132] In some embodiments, the display device further includes a second buffer for buffering second display data, and may further include the following after step S21 and before step S02:

[0133] Step S23: If not, check whether the amount of data in the second buffer meets the second write condition.

[0134] For example, the second write condition includes that the amount of data in the second buffer is greater than or equal to a second preset data amount. The second preset data amount can be determined based on the amount of display data in one frame period, for example, the amount of display data in one frame period can be an integer multiple of the second preset data amount.

[0135] For example, for a display panel with a resolution of 1920×1080, the amount of display data in one frame cycle is 1920×1080=2073600 bytes, and correspondingly, the second preset data amount can be set to 64 bytes.

[0136] For example, when the second preset data size is 64 bytes, the second buffer (such as...) can be retrieved first. Figure 9 The system checks the amount of data in FIFO_SINK1 and then determines whether the amount of data in the second buffer satisfies the second write condition (e.g., ...). Figure 9 If the amount of data in the second buffer is greater than or equal to 64 bytes, the second write condition is satisfied; if the amount of data in the second buffer is less than 64 bytes, the second write condition is not satisfied.

[0137] Step S24: If yes, a second write command is generated, and the second display data in the second buffer is written into the memory 31 according to the second write command, the second display data in the memory 31 being used for transmission to the display panel 11 through the driving chip 18 in the second stage.

[0138] That is, the second write command can be executed once every time the amount of data in the second buffer reaches the second preset data amount.

[0139] Exemplarily, the second write command includes a second write data amount, which can be the second preset data amount described above. The second write command can also include a second write address, and can also include a burst length, a command type, and the like.

[0140] Exemplarily, the step S24 can include:

[0141] Step S33: The second write command is written into the command buffer, and the second display data in the second buffer is written into the data buffer.

[0142] Step S34: When it is detected that there is a command written into the command buffer, the second display data in the data buffer is written into the memory 31 according to the address and the data amount in the second write command.

[0143] Referring to Figure 9 , WR_CMD1 is used to write the second write command into the command buffer in the parsing module, the second write command can include a second write address and a second write data amount. WR_SINK1 is used to write the data of the "second write data amount" into the data buffer in the parsing module, and in the writing process, it is determined whether the write data amount ≥ 64 bytes is true and whether there is a command written into the command buffer, if not, WR_SINK1 is continuously executed, and if yes, WR_WAIT1 is executed.

[0144] As shown in Figure 9 , WR_WAIT1 is used to wait for data to be written into the memory 31, and in the waiting process, it is determined whether the write feedback ≥ 8 is true, if yes, the writing is completed, and if not, WR_WAIT1 is returned. For a data amount of 64 bytes, the parsing module needs to execute 8 storage processes, each storage process corresponds to one feedback, and when the storage of 64 bytes of data is completed, 8 times of feedback will be fed back. Therefore, when the write feedback is greater than or equal to 8, it means that the writing is completed.

[0145] In some embodiments, after the step S23, the method can further include:

[0146] Step S25: If no, a read command is generated, and the first display data or the second display data is read out from the memory 31 according to the read command.

[0147] Exemplarily, the read command comprises a read data amount, and the read data amount can be a third preset data amount. The third preset data amount can be determined according to a display data amount of one frame period, for example, the display data amount of one frame period can be an integer multiple of the third preset data amount.

[0148] Exemplarily, for a display panel with a resolution of 1920x1080, the display data amount of one frame period is 1920x1080=2073600 bytes, and accordingly, the third preset data amount can be set as 64 bytes.

[0149] The read command can further comprise a read address, and can further comprise a burst length, a command type, and the like.

[0150] Referring to Figure 9 , the FIFO_SOURCE generates the read command.

[0151] The DDR3_RD_READY indicates a read preparation. After the read command is generated, it can be determined whether the read preparation is ready, if yes, the first display data or the second display data is read out from the memory 31 according to the read command, and if no, the flow is ended.

[0152] Exemplarily, the step S25 can comprise:

[0153] The step S35 writes the read command into the command buffer.

[0154] The step S36 reads the first display data or the second display data from the memory 31 according to the address and the data amount in the read command when it is detected that the command is written into the command buffer.

[0155] Referring to Figure 9 , the RD_SOURCE writes the read command into the command buffer in the analysis module, and the read command can comprise a read address and a read data amount (i.e. the third preset data amount, such as 64 bytes). The RD_WART waits for the data to be read out from the memory 31, and during the waiting process, it is determined whether the read data amount ≥64 bytes is established, if yes, the reading is completed, and the flow is ended, and if no, the RD_WART is returned.

[0156] As shown in Figure 8 , after the flow is ended, the IDLE can be re-executed, and the next cycle is started. Through the cyclic execution of the steps S21 to S25, it can be ensured that the display data is not lost, and the display data can be continuously output to the display panel, so that the display panel is driven to perform the single-side display.

[0157] Exemplarily, the first buffer, the second buffer, the command buffer and the data buffer can be First Input First Output (FIFO) memories, and the present disclosure does not make any limitation in this regard.

[0158] Exemplarily, the first buffer and the second buffer can be located in the ping-pong read-write control module; and the command buffer and the data buffer can be located in the parsing module.

[0159] With reference to Figure 8 , the parsing module can first determine whether there is a command in the command buffer, and if so, read the command from the command buffer (such as GET_COMMAND in Figure 8 ); then determine the command type (such as PRE_READ_JUDGE in Figure 8 ); determine whether the command type is read (READ) or write (WRITE); if it is read, perform the operation of reading from the memory DDR3 (such as RD_DDR in Figure 8 ) until the reading is completed (such as RD_DDR_END in Figure 8 ); if it is write, perform the operation of writing to the memory DDR3 (such as WR_DDR in Figures 1 to 3 ).

[0160] Exemplarily, the memory 31 can be a double data rate synchronous dynamic random memory, such as a DDR3 memory, and the present disclosure does not make any limitation in this regard.

[0161] Exemplarily, the timing controller, the driving chip 18 and the backlight chip are all chips supporting high refresh frequency, which can support a refresh frequency greater than or equal to 60 Hz, and can even support a refresh frequency up to 2400 Hz.

[0162] In some embodiments, such as any of Figure 10 , the display device further comprises a memory 31, and before step S01 and step S02, further comprises:

[0163] Step S41: synchronously performing the steps of writing data to the first storage area and reading data from the second storage area. Alternatively, step S42: synchronously performing the steps of reading data from the first storage area and writing data to the second storage area. Wherein, the first storage area and the second storage area are different storage areas in the memory 31.

[0164] Since the DDR3 memory cannot read and write at the same time, that is, it cannot read data from the first storage area while writing data to the first storage area, and it also cannot read data from the second storage area while writing data to the second storage area.

[0165] Referring to Figure 11 The timing signal diagram generated according to the screen timing requirements is shown, wherein a diagram includes a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC in a frame period, and a diagram b includes a horizontal synchronization signal HSYNC, a pixel clock signal CLK, RGB display data and a data valid signal DEN in a line scanning period.

[0166] Referring to Figures 1 to 3 The timing signal simulation diagram generated by using the internal logic resources of the FPGA to control by the state machine is shown, including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, RGB data and a data valid signal DEN.

[0167] The display method provided by the present disclosure, the code design part can be completed in Quartus Prime Pro, using Quartus Prime Pro integrated development environment, through NIOS II, an embedded reduced instruction set CPU and system components, peripheral devices to establish image transmission IP. At the same time, Quartus Prime Pro is also responsible for completing the code compilation, synthesis and layout routing and other work, and completing the hardware platform design. The software programming part can be completed in NIOS II software build Tools tool, which is mainly responsible for the display port Display Port driving part.

[0168] The present disclosure also provides a display device, such as Figures 1 to 3 Any of the display device includes a display panel 11, and a control module 12 connected with the display panel 11, for providing first display data to the display panel 11 in a first stage to display a first picture on a first display side of the display panel 11, and providing second display data to the display panel 11 in a second stage to display a second picture on a second display side of the display panel 11, wherein the first display side is arranged opposite to the second display side, and the first stage and the second stage are alternately performed.

[0169] Those skilled in the art can understand that the display device provided by the present disclosure has the advantages of the display method described above. The display device provided by the present disclosure can be integrated in notebook computers, displays and other products, and can be used as a display screen in many fields such as vehicle-mounted display and consumer electronics.

[0170] As for the display device, the specific manner in which the control module 12 performs operations has been described in detail in the embodiments of the display method, and will not be described in detail here.

[0171] In some embodiments, such as Figures 1 to 3In any of the above, the display panel 11 is a liquid crystal display panel 11, and the display device further comprises: a first backlight module 13 configured to provide backlight to the first display side; and a second backlight module 14 configured to provide backlight to the second display side. Correspondingly, the control module 12 is further configured to, in the first stage, control the first backlight module 13 to be turned on and the second backlight module 14 to be turned off, and in the second stage, control the second backlight module 14 to be turned on and the first backlight module 13 to be turned off.

[0172] In some embodiments, as Figures 1 to 3 In any of the above, the control module 12 comprises: a first backlight chip 15, a second backlight chip 16, and a master control chip 17.

[0173] The first backlight chip 15 is connected with the master control chip 17 and the first backlight module 13 respectively, configured to receive a first control signal sent by the master control chip 17, and in response to the first control signal, control the first backlight module 13 to be turned on or turned off.

[0174] The second backlight chip 16 is connected with the master control chip 17 and the second backlight module 14 respectively, configured to receive a second control signal sent by the master control chip 17, and in response to the second control signal, control the second backlight module 14 to be turned on or turned off.

[0175] The master control chip 17 is configured to send the first control signal to the first backlight chip 15, and send the second control signal to the second backlight chip 16, so as to, in the first stage, control the first backlight module 13 to be turned on and the second backlight module 14 to be turned off, and in the second stage, control the second backlight module 14 to be turned on and the first backlight module 13 to be turned off.

[0176] The first control signal and the second control signal can comprise a pulse width modulation signal PWM and an enable signal EN, etc.

[0177] Exemplarily, the first backlight module 13 can comprise a first light bar 21 arranged at one side of the display panel 11, and an optical film piece capable of guiding light emitted by the first light bar 21 to the first display side, such as a light guide plate.

[0178] Exemplarily, the second backlight module 14 can comprise a second light bar 22 arranged at the other side of the display panel 11, and an optical film piece capable of guiding light emitted by the second light bar 22 to the second display side, such as a light guide plate.

[0179] Exemplarily, the master chip 17 can include at least one of a central processing unit (CPU), a microcontroller unit (MCU), a field programmable gata array (FPGA), and the like, and the present embodiment is not limited thereto.

[0180] In order to reduce the heat generated by high output power consumption of the FPGA, the first backlight module 13 and the second backlight module 14 can be powered separately, thereby reducing product heating.

[0181] In some embodiments, as shown in Figure 3 According to any of the embodiments, the control module 12 further includes a driving chip 18 connected with the driving chip 18 and the display panel 11, configured to receive the first display data or the second display data output by the master chip 17, and output the first display data or the second display data to the display panel 11 according to a preset timing.

[0182] In some embodiments, as shown in Figure 12 According to any of the embodiments, the control module 12 further includes a memory 31 connected with the master chip 17, configured to store the first display data and the second display data.

[0183] In the present embodiment, by writing the first display data and the second display data into the external memory 31, the occupation of the FPGA storage resource can be effectively reduced, and data loss can be avoided.

[0184] In some embodiments, as shown in Figure 13 According to any of the embodiments, the memory 31 includes a first storage area A and a second storage area B, the first storage area A is configured to store the first display data, and the second storage area B is configured to store the second display data.

[0185] In the present embodiment, by writing the first display data and the second display data into different storage areas of the memory 31, the storage bandwidth of the memory 31 can be maximized.

[0186] In some embodiments, as shown in Figure 12 According to any of the embodiments, the first storage area A includes a first sub-area A1 and a second sub-area A2, and the first display data of two adjacent first stages are respectively stored in the first sub-area A1 and the second sub-area A2; the second storage area B includes a third sub-area B1 and a fourth sub-area B2, and the second display data of two adjacent second stages are respectively stored in the third sub-area B1 and the fourth sub-area B2.

[0187] For example, first, the first display data can be written into the first sub-region Al, and the second display data can be written into the third sub-region Bl (the process of writing into the first sub-region Al and the process of writing into the third sub-region Bl are independent of each other and do not interfere with each other); at the same time, the first display data is read from the second sub-region A2 first, and then the second display data is read from the fourth sub-region B2 after the reading is completed.

[0188] In this way, after the first sub-region Al and the third sub-region Bl are filled with data, the data in the second sub-region A2 and the fourth sub-region B2 is read. When the next write command is executed, the data writing region needs to be switched from the first sub-region Al and the third sub-region Bl to the second sub-region A2 and the fourth sub-region B2; when the next read command is executed, the data reading region needs to be switched from the second sub-region A2 and the fourth sub-region B2 to the first sub-region Al and the third sub-region Bl. That is, the first display data of two adjacent first stages is respectively stored in the first sub-region Al and the second sub-region A2, and the second display data of two adjacent second stages is respectively stored in the third sub-region Bl and the fourth sub-region B2.

[0189] Then, the first display data can be written into the second sub-region A2, and the second display data can be written into the fourth sub-region B2 (the process of writing into the second sub-region A2 and the process of writing into the fourth sub-region B2 are independent of each other and do not interfere with each other); at the same time, the first display data is read from the first sub-region Al first, and then the second display data is read from the third sub-region Bl after the reading is completed.

[0190] It should be noted that the written first display data and the read first display data can be display data of the same frame or display data of different frames of the first picture, and the written second display data and the read second display data can be display data of the same frame or display data of different frames of the second picture.

[0191] Referring to Figure 12 A ping-pong storage diagram is shown, two solid arrows represent a process executed at the same time at one time, and two dashed lines are a process executed at the same time at another time. The simultaneous execution here refers to the execution process of the memory 31 hardware.

[0192] As ​ shown, the storage space of the memory 31 is divided into two parts of a first storage region A and a second storage region B. When the FPGA receives display data to be written into the memory 31, the first display data is written into the first storage region A, and the data in the second storage region B is read at the same time; then the second display data is written into the second storage region B, and the data in the first storage region A is read at the same time. …… In this way, the cyclic reading and writing can reduce the use of internal storage resources of the FPGA and fully utilize the advantage of fast reading and writing speed of the memory 31.

[0193] The embodiment adopts the ping-pong storage mode, and can fully utilize the bandwidth of the DDR3 memory under the premise of ensuring the continuity of input and output data.

[0194] In some embodiments, the storage capacity of the first sub-region A1, the second sub-region A2, the third sub-region B1 and the fourth sub-region B2 is the amount of display data of one frame period.

[0195] In some embodiments, the memory 31 is a double-rate synchronous dynamic random memory, such as a DDR3 memory.

[0196] In some embodiments, the display panel can be a self-luminous display panel, and the self-luminous display panel is internally provided with a light-emitting device, which can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a mini light-emitting diode (Mini LED) or a micro light-emitting diode (Micro LED), etc.

[0197] In the present disclosure, the meaning of "a plurality of" is two or more, and the meaning of "at least one" is one or more, unless otherwise explicitly and specifically limited.

[0198] In the present disclosure, the terms "upper", "lower", etc. indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0199] In this document, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, product or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or device that includes the element.

[0200] As used herein, the terms “one embodiment,” “some embodiments,” “certain embodiments,” “one or more embodiments,” “some implementations,” “one implementation,” “some examples,” “one example,” and the like are generally used to describe different features, structures, materials, or characteristics included in certain examples of the disclosure. The terminology used herein is for the purpose of describing selected embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms “and / or” and “one or more of the following” include any and all combinations of one or more of the associated listed items.

[0201] In this document, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0202] In describing some embodiments, the expressions “coupled” and “connected” can be used. For example, the term “connected” can be used to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term “coupled” can be used to indicate that two or more elements are in either direct physical or electrical contact with each other. However, the term “coupled” or “communicatively coupled” can also mean that two or more elements are not in direct contact with each other, but yet are still in cooperation or interaction with each other. The embodiments disclosed herein are not necessarily limited in scope to the terms used herein.

[0203] “at least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0204] “A and / or B” includes the following three combinations: only A, only B, and a combination of A and B.

[0205] As used herein, the term “if’ is optionally interpreted as meaning “when” or “upon” or “in response to a determination” or “in response to a detection” depending on the context. Similarly, the phrase “if determined” or “if detected [a stated condition or event]” is optionally interpreted as meaning “upon a determination” or “in response to a determination” or “upon a detection” or “in response to a detection” of [a stated condition or event], depending on the context.

[0206] The use of “for” or “configured to” herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0207] The use of "based on" or "according to" herein means open and inclusive. A process, step, calculation, or other action that is based on one or more recited conditions or values may, in practice, be based on other conditions or values beyond those recited. A process, step, calculation, or other action that is according to one or more recited conditions or values may, in practice, be according to other conditions or values beyond those recited.

[0208] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the recited value, as determined by one of ordinary skill in the art taking into account the measurement in question and the error associated with measuring the particular quantity (i.e., the limitations of the measurement system).

[0209] As used herein, "parallel," "perpendicular," "equal," "flush" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art taking into account the measurement in question and the error associated with measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable range of deviation of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable range of deviation of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable range of deviation of, for example, less than or equal to 5% of either of the two quantities being compared. "Flush" includes absolute flush and near flush, where near flush can be within an acceptable range of deviation of, for example, less than or equal to 5% of either of the two dimensions being compared.

[0210] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0211] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layer and regions are shown in the drawings with the same dimensions. For example, the thickness of layers and regions can be exaggerated in the drawings. Thus, the exemplary embodiments are not intended to be limited to the illustrations as shown in the drawings, but include variations as would be known to one of ordinary skill in the art. For example, etched regions shown as rectangular can typically have curved features. Thus, the regions illustrated in the drawings are schematic and not intended to be exact representations of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0212] It should be finally pointed out that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display method applied to a display device, the display device comprising a display panel, the display method comprising: a first stage of providing first display data to the display panel to display a first picture on a first display side of the display panel; and a second stage of providing second display data to the display panel to display a second picture on a second display side of the display panel; wherein the first display side is arranged opposite to the second display side, and the first stage and the second stage are alternately performed; the display device further comprising a first buffer for buffering the first display data, a memory and a driving chip, and further comprising a second buffer for buffering the second display data, before the step of the first stage, further comprising: detecting whether a data amount in the first buffer meets a first write condition; if yes, generating a first write command and writing the first display data in the first buffer into the memory according to the first write command, the first display data in the memory being used to be transmitted to the display panel via the driving chip in the first stage; if no, before the second stage, further comprising: detecting whether a data amount in the second buffer meets a second write condition; if yes, generating a second write command and writing the second display data in the second buffer into the memory according to the second write command, the second display data in the memory being used to be transmitted to the display panel via the driving chip in the second stage; if no, generating a read command and reading out the first display data or the second display data from the memory according to the read command; the display device further comprising a command buffer and a data buffer, the step of writing the first display data in the first buffer into the memory according to the first write command comprising: writing the first write command into the command buffer and writing the first display data in the first buffer into the data buffer; when detecting that there is a command written into the command buffer, writing the first display data in the data buffer into the memory according to an address and a data amount in the first write command; the step of writing the second display data in the second buffer into the memory according to the second write command comprising: writing the second write command into the command buffer and writing the second display data in the second buffer into the data buffer; when detecting that there is a command written into the command buffer, writing the second display data in the data buffer into the memory according to an address and a data amount in the second write command; the step of reading out the first display data or the second display data from the memory according to the read command comprising: writing the read command into the command buffer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ When a command write in the command buffer is detected, reading out the first display data or the second display data from the memory according to the address and the data amount in the read command.

2. The display method according to claim 1, wherein, The first stage includes M frame periods, and the first picture is refreshed once in one frame period of the first stage, and M is greater than or equal to 1. The second stage includes N frame periods, and the second picture is refreshed once in one frame period of the second stage, and N is greater than or equal to 1.

3. The display method according to claim 2, wherein, The M is equal to the N.

4. The display method according to claim 1, wherein The display panel is a liquid crystal display panel, and further includes, between adjacent first stages and second stages: A third stage, providing third display data to the display panel to display a black picture on a normally black mode liquid crystal display panel or a white picture on a normally white mode liquid crystal display panel.

5. The display method according to claim 4, wherein, The third stage includes L frame periods, and L is greater than 0 and less than or equal to 1.

6. The display method according to claim 1, wherein The display panel is a liquid crystal display panel, and the display device further includes a first backlight module and a second backlight module, the first backlight module is used to provide backlight to the first display side, and the second backlight module is used to provide backlight to the second display side, and the step of the first stage further includes: Controlling the first backlight module to be turned on and the second backlight module to be turned off; The step of the second stage further includes: Controlling the second backlight module to be turned on and the first backlight module to be turned off.

7. The display method according to claim 6, wherein The first stage includes a first refresh stage and a first holding stage in the same frame period, and the second stage includes a second refresh stage and a second holding stage in the same frame period, and the step of providing first display data to the display panel includes: In the first refresh stage, providing first display data to the display panel; The step of controlling the first backlight module to be turned on includes: In the first holding stage, controlling the first backlight module to be turned on; The step of providing second display data to the display panel includes: In the second refresh stage, providing second display data to the display panel; The step of controlling the second backlight module to be turned on includes: In the second holding stage, controlling the second backlight module to be turned on.

8. The display method according to any one of claims 1 to 7, wherein, The display device further includes a memory, and further includes, before the first stage and the second stage: Synchronously executing the steps of writing data to a first storage area and reading data from a second storage area; or Synchronously executing the steps of reading data from a first storage area and writing data to a second storage area; Wherein, the first storage area and the second storage area are different storage areas in the memory.

9. A display device, comprising: A display panel; And A control module connected with the display panel, used to provide first display data to the display panel in a first stage to display a first picture on a first display side of the display panel; and in a second stage, providing second display data to the display panel to display a second picture on a second display side of the display panel; wherein the first display side and the second display side are oppositely arranged, and the first stage and the second stage are alternately performed; The display device further comprises a first buffer, a memory and a driving chip, the first buffer is used for buffering the first display data, the display device further comprises a second buffer, the second buffer is used for buffering the second display data, and the control module is further used for performing the following steps before the first stage: detecting whether the data amount in the first buffer meets a first write condition; if yes, generating a first write command, and writing the first display data in the first buffer into the memory according to the first write command, the first display data in the memory being used for being transmitted to the display panel through the driving chip in the first stage; if no, before the second stage, the control module is further used for performing the following steps: detecting whether the data amount in the second buffer meets a second write condition; if yes, generating a second write command, and writing the second display data in the second buffer into the memory according to the second write command, the second display data in the memory being used for being transmitted to the display panel through the driving chip in the second stage; if no, generating a read command, and reading out the first display data or the second display data from the memory according to the read command; The display device further comprises a command buffer and a data buffer, the step of writing the first display data in the first buffer into the memory according to the first write command comprises: writing the first write command into the command buffer, and writing the first display data in the first buffer into the data buffer; when detecting that there is a command written into the command buffer, writing the first display data in the data buffer into the memory according to the address and the data amount in the first write command; The step of writing the second display data in the second buffer into the memory according to the second write command comprises: writing the second write command into the command buffer, and writing the second display data in the second buffer into the data buffer; when detecting that there is a command written into the command buffer, writing the second display data in the data buffer into the memory according to the address and the data amount in the second write command; The step of reading out the first display data or the second display data from the memory according to the read command comprises: writing the read command into the command buffer; when detecting that there is a command written into the command buffer, reading out the first display data or the second display data from the memory according to the address and the data amount in the read command.

10. The display device of claim 9, wherein, The display panel is a liquid crystal display panel, and the display device further comprises: The first backlight module is configured to provide backlight for the first display side. The second backlight module is configured to provide backlight for the second display side. The control module is further configured to control the first backlight module to be turned on and the second backlight module to be turned off in the first stage, and control the second backlight module to be turned on and the first backlight module to be turned off in the second stage.

11. The display device of claim 10, wherein, The control module comprises a first backlight chip, a second backlight chip and a master control chip. The first backlight chip is connected with the master control chip and the first backlight module respectively, configured to receive a first control signal sent by the master control chip, and control the first backlight module to be turned on or turned off in response to the first control signal. The second backlight chip is connected with the master control chip and the second backlight module respectively, configured to receive a second control signal sent by the master control chip, and control the second backlight module to be turned on or turned off in response to the second control signal. The master control chip is configured to send the first control signal to the first backlight chip and send the second control signal to the second backlight chip, so as to control the first backlight module to be turned on and the second backlight module to be turned off in the first stage, and control the second backlight module to be turned on and the first backlight module to be turned off in the second stage.

12. The display device of claim 11, wherein, The control module further comprises: a driving chip connected with the master control chip and the display panel, configured to receive first display data or second display data output by the master control chip, and output the first display data or the second display data to the display panel according to a preset timing sequence; and a memory connected with the master control chip, configured to store the first display data and the second display data.

13. The display device of claim 12, wherein, The memory comprises a first storage area and a second storage area, the first storage area is configured to store the first display data, and the second storage area is configured to store the second display data.

14. The display device of claim 13, wherein, The first storage area comprises a first sub-area and a second sub-area, and first display data of two adjacent first stages are stored in the first sub-area and the second sub-area respectively. The second storage area comprises a third sub-area and a fourth sub-area, and second display data of two adjacent second stages are stored in the third sub-area and the fourth sub-area respectively.

15. The display device of claim 14, wherein, The first sub-area, the second sub-area, the third sub-area and the fourth sub-area have a storage capacity of display data of one frame period.

16. A display device according to any one of claims 12 to 15, wherein, The memory is a double data rate synchronous dynamic random access memory.

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