Power control circuit and memory

Abstract

The present application relates to a power control circuit and memory. The power control circuit includes: a data channel having a first power receiving terminal and a second power receiving terminal, the first power receiving terminal being configured to receive a first power supply voltage; a first switching tube having a control terminal, a first terminal, and a second terminal, the first terminal of the first switching tube being connected to the second power receiving terminal of the data channel, and the second terminal of the first switching tube being configured to receive a second power supply voltage; and a control circuit connected to the control terminal of the first switching tube and configured to control the first switching tube to conduct when the data channel performs a read operation or a write operation, so as to transmit the second power supply voltage to the second power receiving terminal of the data channel. The use of this power control circuit can reduce subthreshold leakage, thereby reducing the static power consumption of the circuit and improving the reliability of the circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a power control circuit and a memory. Background Art

[0002] In the input / output (I / O) circuits of dynamic random access memory (DRAM), a large number of low-threshold devices are used to reduce circuit dynamic power consumption and improve performance.

[0003] To achieve a low threshold voltage, low-threshold devices are designed with a thin gate oxide layer. However, an excessively thin gate oxide layer can cause the device's gate voltage to fall below the threshold voltage required for the device to conduct, potentially leading to a small amount of leakage current between the device's source and drain (i.e., subthreshold leakage). Consequently, low-threshold devices exhibit relatively high subthreshold leakage, which can lead to excessive static power consumption in the circuit, seriously impacting its reliability and performance.

[0004] In traditional technology, manual adjustment of circuit parameters is usually used to reduce subthreshold leakage. However, due to some unavoidable physical limitations in actual application scenarios, it is still unable to effectively solve the problem of subthreshold leakage in low-threshold devices, resulting in higher static power consumption and lower reliability of the circuit. Summary of the Invention

[0005] Based on this, it is necessary to provide a power control circuit and a memory that can reduce the static power consumption of the circuit and improve the reliability of the circuit.

[0006] In a first aspect, the present application further provides a power control circuit, comprising:

[0007] a data channel having a first power receiving end and a second power receiving end, wherein the first power receiving end is configured to receive a first power supply voltage;

[0008] a first switch tube having a control end, a first end, and a second end, wherein the first end of the first switch tube is connected to the second power supply receiving end of the data channel, and the second end of the first switch tube is configured to receive a second power supply voltage;

[0009] The control circuit is connected to the control end of the first switch tube and is configured to control the first switch tube to be turned on when the data channel performs a read operation or a write operation, so as to transmit the second power supply voltage to the second power supply receiving end of the data channel.

[0010] The power control circuit includes a data channel, a first switching transistor, and a control circuit. The data channel has a first power receiving terminal and a second power receiving terminal, the first power receiving terminal being configured to receive a first power supply voltage. The first switching transistor has a control terminal, a first terminal, and a second terminal. The first terminal of the first switching transistor is connected to the second power receiving terminal of the data channel, and the second terminal of the first switching transistor is configured to receive a second power supply voltage. The control circuit is connected to the control terminal of the first switching transistor and is configured to control the first switching transistor to conduct when the data channel is performing a read or write operation, thereby transmitting the second power supply voltage to the second power receiving terminal of the data channel. When the data channel is not performing a read or write operation, the control circuit is configured to control the first switching transistor to conduct, thereby transmitting the second power supply voltage to the second power receiving terminal of the data channel. When the first switching transistor is in the off state, it prevents the second power receiving terminal of the data channel from receiving the second power supply voltage, thereby reducing subthreshold leakage in the data channel, thereby reducing static power consumption and improving circuit reliability.

[0011] In one embodiment, the data channel includes an inverter, which includes a first type transistor and a second type transistor, the control end of the first type transistor is connected to the control end of the second type transistor to serve as the input end of the inverter, the first end of the first type transistor is connected to the first end of the second type transistor to serve as the output end of the inverter, the second end of the first type transistor is connected to the first power supply receiving end, and the second end of the second type transistor is connected to the first end of the first switch tube.

[0012] In one embodiment, the second power supply voltage is lower than the first power supply voltage, the first type transistor is a P-type transistor, and the second type transistor is an N-type transistor.

[0013] In one embodiment, the type of the first switch transistor is the same as the type of the second type transistor.

[0014] In one embodiment, the threshold voltage of the first switch transistor is greater than the threshold voltage of the second type transistor.

[0015] In one embodiment, the control circuit is configured to receive a column address selection signal, a row address selection signal and a write command signal, and control the first switch tube to be turned on according to the column address selection signal, the row address selection signal and the write command signal.

[0016] In one embodiment, the data channel includes a data read channel, and the control circuit includes:

[0017] A first NOT gate, whose input terminal is used to receive the row address strobe signal;

[0018] a first NOR gate, wherein a first input terminal is connected to the output terminal of the first NOR gate, and a second input terminal is used to receive the column address selection signal;

[0019] a first NAND gate, having a first input terminal connected to the output terminal of the first NOR gate, and a second input terminal for receiving the write command signal;

[0020] The second NOT gate has an input end connected to the output end of the first NAND gate, and an output end connected to the control end of the first switch tube.

[0021] In one embodiment, the data channel includes the data write channel, and the control circuit includes:

[0022] A third NOT gate, whose input terminal is used to receive the row address strobe signal;

[0023] a second NOR gate, wherein a first input terminal is connected to the output terminal of the third NOR gate, and a second input terminal is used to receive the column address selection signal;

[0024] a fourth NOT gate, whose input terminal is used to receive the write command signal;

[0025] a second NAND gate, having a first input terminal connected to the output terminal of the first NOR gate, and a second input terminal connected to the output terminal of the fourth NOT gate;

[0026] A fifth NOT gate has an input end connected to the output end of the second NAND gate, and an output end connected to the control end of the first switch tube.

[0027] In one embodiment, the power control circuit further includes:

[0028] The anti-floating circuit is connected in parallel between the first end and the second end of the first switch tube, and is used to transmit the second power supply voltage to the second power supply receiving end of the data channel when the second type transistor is turned on.

[0029] In one embodiment, the anti-floating circuit includes:

[0030] The second switch tube has a first end connected to the first end of the first switch tube, a second end connected to the second end of the first switch tube, and a control end connected to the output end of the inverter.

[0031] In one embodiment, the type of the second switch transistor is opposite to the type of the second type transistor.

[0032] In one embodiment, the data channel includes a plurality of inverters cascaded in sequence, the power control circuit includes a plurality of first switching tubes corresponding one-to-one to the plurality of inverters, and the anti-floating circuit includes a plurality of second switching tubes corresponding one-to-one to the plurality of inverters; the first end of each first switching tube is connected to the second end of the second type transistor in the corresponding inverter, the first end of each second switching tube is connected to the first end of the corresponding first switching tube, the second end of each second switching tube is connected to the second end of the corresponding first switching tube, and the control end of each second switching tube is connected to the output end of the corresponding inverter.

[0033] In one embodiment, the data channel includes a plurality of inverters cascaded in sequence, the power control circuit includes two first switching tubes, and the anti-floating circuit includes two second switching tubes corresponding to the two first switching tubes; the first end of one first switching tube is connected to the second end of the second type transistor in the odd-numbered inverter, and the first end of another first switching tube is connected to the second end of the second type transistor in the even-numbered inverter; the first end of each second switching tube is connected to the first end of the corresponding first switching tube, and the second end of each second switching tube is connected to the second end of the corresponding first switching tube; the control end of one second switching tube is connected to the output end of the odd-numbered inverter, and the control end of another second switching tube is connected to the output end of the even-numbered inverter.

[0034] In one embodiment, the threshold voltage of the second switch is greater than or equal to the threshold voltage of the second type transistor.

[0035] In a second aspect, the present application further provides a memory, which includes the power control circuit in any one of the above embodiments.

[0036] The aforementioned memory includes a power control circuit. When the data channel is not performing a read or write operation, the control circuit in the power control circuit connects the second power receiving terminal of the data channel only to the first terminal of the first switching transistor. Because the first switching transistor is in the off state, it prevents the second power receiving terminal of the data channel from receiving the second power supply voltage, thereby reducing subthreshold leakage in the data channel, thereby lowering static power consumption and improving circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic diagram of the structure of a power control circuit provided by an embodiment;

[0039] Figure 2 A schematic structural diagram of a power control circuit provided in another embodiment;

[0040] Figure 3 A truth table of commands of the Electronic Component Manufacturing Federation standard provided in one embodiment;

[0041] Figure 4 A schematic structural diagram of a power control circuit provided in yet another embodiment;

[0042] Figure 5 A schematic structural diagram of a power control circuit provided in yet another embodiment;

[0043] Figure 6 A schematic structural diagram of a power control circuit provided in yet another embodiment;

[0044] Figure 7 A schematic structural diagram of a power control circuit provided in yet another embodiment;

[0045] Figure 8 A schematic structural diagram of a power control circuit provided in yet another embodiment;

[0046] Figure 9 A schematic structural diagram of a power control circuit provided in yet another embodiment.

[0047] Explanation of the accompanying drawings: 10-data channel, 101-inverter, 1011-first type transistor, 1012-second type transistor, 11-data read channel, 12-data write channel, 20-first switch tube, 30-control circuit, 301-first NOT gate, 302-first NOR gate, 303-first NAND gate, 304-second NOT gate, 305-third NOT gate, 306-second NOR gate, 307-second NAND gate, 308-fourth NOT gate, 309-fifth NOT gate, 40-anti-floating circuit, 401-second switch tube. DETAILED DESCRIPTION

[0048] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0050] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0051] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0052] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0053] like Figure 1As shown, the present application provides a power control circuit, which includes a data channel 10, a first switching tube 20, and a control circuit 30. The data channel 10 has a first power receiving terminal and a second power receiving terminal, and the first power receiving terminal is configured to receive a first power supply voltage. The first switching tube 20 has a control terminal, a first terminal, and a second terminal. The first terminal of the first switching tube 20 is connected to the second power receiving terminal of the data channel 10, and the second terminal of the first switching tube 20 is configured to receive a second power supply voltage. The control circuit 30 is connected to the control terminal of the first switching tube 20 and is configured to control the first switching tube 20 to conduct when the data channel 10 performs a read operation or a write operation, so as to transmit the second power supply voltage to the second power receiving terminal of the data channel 10.

[0054] The data channel 10 may be part of the I / O circuitry in a DRAM and may be used to transmit data for read or write operations. To reduce dynamic power consumption, the data channel 10 is typically composed of multiple low-threshold devices, making it susceptible to subthreshold leakage.

[0055] Typically, a data channel 10 can be configured to perform only read operations or only write operations, and the I / O circuit in a DRAM may include multiple data channels 10. The data channel 10 has a first power receiving terminal and a second power receiving terminal. The first power receiving terminal is used to receive a first power supply voltage, and the second power receiving terminal is used to receive a second power supply voltage. The first power supply voltage can be a power supply voltage (VDD), and the second power supply voltage can be a ground voltage (VSS). Alternatively, the first power supply voltage can be VSS, and the second power supply voltage can be VDD.

[0056] The control terminal of the first switching transistor 20 may be the gate of the first switching transistor 20. The first terminal of the first switching transistor 20 may be the source of the first switching transistor 20, and the second terminal may be the drain of the first switching transistor 20. Alternatively, the first terminal of the first switching transistor 20 may be the drain of the first switching transistor 20, and the second terminal may be the source of the first switching transistor 20.

[0057] When the data channel 10 is performing a read operation or a write operation, the control circuit 30 controls the first switch tube 20 to be turned on through the control terminal of the first switch tube 20, so that the second power supply voltage can be normally transmitted to the second power supply receiving terminal of the data channel 10. In this case, the first switch tube 20 does not affect the normal operation of the data channel 10. When the data channel 10 is not performing a read operation or a write operation, the control circuit 30 controls the first switch tube 20 to be turned off through the control terminal of the first switch tube 20. In this case, the second power supply receiving terminal of the data channel 10 is only connected to the first terminal of the first switch tube 20. Since the first switch tube 20 is in the off state, it can prevent the second power supply receiving terminal of the data channel 10 from receiving the second power supply voltage, thereby reducing the subthreshold leakage of the data channel 10, thereby reducing the static power consumption of the circuit and improving the reliability of the circuit.

[0058] By way of example, taking the data channel 10 as a data channel 10 for a read operation, the first power supply voltage being the power supply voltage VDD, and the second power supply voltage being the ground voltage VSS as an example, how this embodiment controls the normal operation of the data channel 10 and how to reduce the subthreshold leakage of the data channel 10 is specifically described:

[0059] During a read operation, the control circuit 30 controls the control terminal of the first switch 20 to turn on the first switch 20. At this time, since the first terminal of the first switch 20 is connected to the second power supply receiving terminal of the data channel 10, and the second terminal of the first switch 20 is configured to receive the ground voltage VSS, the second power supply receiving terminal of the data channel 10 can be smoothly grounded, allowing the data channel 10 to complete the read operation normally.

[0060] When a read operation is not in progress, the control circuit 30 controls the control terminal of the first switch 20 to turn off the first switch 20. At this time, because the first switch 20 is not conducting, the second power supply terminal of the data channel 10 is connected only to the first terminal of the first switch 20. Since the first switch 20 is in the off state, it prevents the second power supply terminal of the data channel 10 from receiving a ground voltage, thereby reducing subthreshold leakage generated by the data channel 10 when a read operation is not in progress.

[0061] The power control circuit of the above embodiment includes a data channel 10, a first switching transistor 20, and a control circuit 30. The data channel 10 has a first power receiving terminal and a second power receiving terminal, the first power receiving terminal being configured to receive a first power supply voltage. The first switching transistor 20 has a control terminal, a first terminal, and a second terminal. The first terminal of the first switching transistor 20 is connected to the second power receiving terminal of the data channel 10, and the second terminal of the first switching transistor 20 is configured to receive a second power supply voltage. The control circuit 30 is connected to the control terminal of the first switching transistor 20 and is configured to control the first switching transistor 20 to conduct when the data channel 10 is performing a read or write operation, thereby transmitting the second power supply voltage to the second power receiving terminal of the data channel 10. When the data channel 10 is not performing a read or write operation, the first switching transistor 20 is controlled to be off, so that the second power receiving terminal of the data channel 10 is connected only to the first terminal of the first switching transistor 20. Since the first switch tube 20 is in the off state, it can prevent the second power receiving end of the data channel 10 from receiving the second power voltage, thereby reducing the subthreshold leakage of the data channel 10, thereby reducing the static power consumption of the circuit and improving the reliability of the circuit.

[0062] In one embodiment, Figure 2 As shown, the data channel 10 includes an inverter 101, and the inverter 101 includes a first-type transistor 1011 and a second-type transistor 1012. The control end of the first-type transistor 1011 is connected to the control end of the second-type transistor 1012 to serve as the input end of the inverter 101, the first end of the first-type transistor 1011 is connected to the first end of the second-type transistor 1012 to serve as the output end of the inverter 101, the second end of the first-type transistor 1011 is connected to the first power supply receiving end, and the second end of the second-type transistor 1012 is connected to the first end of the first switch tube 20.

[0063] The data channel 10 may include a delay-locked loop (DLL), which may be composed of at least one inverter 101. The first-type transistor 1011 and the second-type transistor 1012 have opposite conductivity types. For example, when the first-type transistor 1011 is a P-type transistor, the second-type transistor 1012 is an N-type transistor; when the first-type transistor 1011 is an N-type transistor, the second-type transistor 1012 is a P-type transistor.

[0064] In addition, the conduction characteristic of the P-type transistor is that when a low-level signal is input to its control terminal, the P-type transistor is turned on, and when a high-level signal is input to its control terminal, the P-type transistor is turned off; and the conduction characteristic of the N-type transistor is that when a high-level signal is input to its control terminal, the N-type transistor is turned on, and when a low-level signal is input to its control terminal, the N-type transistor is turned off. Therefore, by connecting the control terminal of the first-type transistor 1011 and the control terminal of the second-type transistor 1012 to serve as the input terminal of the inverter 101, when a low-level signal or a high-level signal is input to the input terminal of the inverter 101, the switching of the first-type transistor 1011 and the second-type transistor 1012 between being turned on and off can be used to switch the output terminal of the inverter 101 between being connected to the first power supply voltage and being connected to the second power supply voltage, so that the output terminal of the inverter 101 can output a signal of a level opposite to that of the input terminal, thereby realizing the function of the inverter 101.

[0065] In addition, to facilitate understanding of this scheme, Figure 2 Only the first-type transistor 1011 and the second-type transistor 1012 included in the first inverter 101 are shown, and the remaining inverters 101 are represented by the circuit symbols of the inverter 101. In order to distinguish them, the first-type transistor 1011 uses the circuit symbol of a P-type transistor, while the second-type transistor 1012 uses the circuit symbol of an N-type transistor. However, the first-type transistor 1011 can also be an N-type transistor, and the second-type transistor 1012 can also be a P-type transistor. The specific types of the first-type transistor 1011 and the second-type transistor 1012 can be determined according to the specific application scenario, and this embodiment does not limit this.

[0066] In one embodiment, the second power supply voltage is lower than the first power supply voltage, the first type transistor 1011 is a P-type transistor, and the second type transistor 1012 is an N-type transistor.

[0067] The first power supply voltage may be VDD, and the second power supply voltage may be VSS, so that the second power supply voltage is lower than the first power supply voltage. In other words, the first power supply voltage may be regarded as a low-level signal, and the second power supply voltage may be regarded as a high-level signal.

[0068] Exemplarily, when a low-level signal is input to the input end of the inverter 101, the first-type transistor 1011 (i.e., the P-type transistor) is turned on and the second-type transistor 1012 (i.e., the N-type transistor) is turned off. At this time, the second end of the P-type transistor is connected to the first power supply receiving end of the data channel 10, and the first power supply receiving end is connected to VDD, so that the output end of the inverter 101 can output a high-level signal; when a high-level signal is input to the input end of the inverter 101, the P-type transistor is turned off and the N-type transistor is turned on. At this time, the second end of the N-type transistor is connected to the first end of the first switch tube 20, and the second end of the first switch tube 20 is configured to receive the second power supply voltage (i.e., VSS). Therefore, when the first switch tube 20 is turned on, the second end of the N-type transistor can receive VSS, so that the output end of the inverter 101 can output a low-level signal.

[0069] Furthermore, when inverter 101 is not performing a read or write operation, assuming that a low-level signal is input to the input of inverter 101, the P-type transistor is normally conducting, and theoretically the N-type transistor should be in an off state. However, since the N-type transistor is a low-threshold device, it is prone to subthreshold leakage, causing the N-type transistor to abnormally conduct at this time. That is, when the input of the inverter is a low-level signal, the P-type transistor is normally conducting, while the N-type transistor may be abnormally conducting due to subthreshold leakage, resulting in the output of inverter 101 being unable to output a normal level signal, increasing the static power consumption of the circuit and reducing the reliability of the circuit. However, by using control circuit 30 to control the first switch 20 to be off when inverter 101 is not performing a read or write operation, the first switch 20 is in an off state, which can prevent the N-type transistor included in inverter 101 from receiving the second power supply voltage, thereby reducing the occurrence of the N-type transistor abnormally conducting due to subthreshold leakage.

[0070] In this embodiment, by setting the second power supply voltage lower than the first power supply voltage, and setting the first-type transistor 1011 to be a P-type transistor and the second-type transistor 1012 to be an N-type transistor, the control circuit 30 can control the first switch 20 to be off when the inverter 101 is not performing a read operation or a write operation, so that the second power supply receiving terminal of the inverter 101 is connected only to the first terminal of the first switch 20. Since the first switch is in the off state, it can prevent the second-type transistor 1012 in the inverter 101 from receiving the second power supply voltage. Therefore, the occurrence of abnormal conduction of the second-type transistor 1012 due to subthreshold leakage can be reduced, thereby reducing the static power consumption of the circuit and further improving the reliability of the circuit.

[0071] In one embodiment, the type of the first switch transistor 20 is the same as the type of the second-type transistor 1012 , that is, the first switch transistor 20 may be an N-type transistor.

[0072] In one embodiment, the threshold voltage of the first switch 20 is greater than the threshold voltage of the second type transistor 1012 .

[0073] To reduce dynamic power consumption, the second-type transistor 1012 can be a low-threshold-voltage N-type transistor (LVNMOS). To prevent subthreshold leakage in the second-type transistor 1012, the first switch 20 can be a high-threshold-voltage N-type transistor (HV ...

[0074] In this embodiment, because the threshold voltage of the first switch 20 is greater than the threshold voltage of the second-type transistor 1012, the dynamic power consumption of the circuit can be reduced by using the second-type transistor 1012 with a lower threshold voltage when the data channel 10 is performing a read or write operation. When the data channel 10 is not performing a read or write operation, the second power receiving terminal of the data channel 10 is connected only to the first terminal of the first switch 20. Because the threshold voltage of the first switch 20 is greater than the threshold voltage of the second-type transistor 1012, when the first switch 20 is in the off state, the second power receiving terminal of the data channel 10 is prevented from receiving the second power supply voltage. This reduces the subthreshold leakage generated by the data channel 10 when the read operation is not performed, thereby reducing the static power consumption of the circuit and improving the reliability of the circuit.

[0075] In one embodiment, the control circuit 30 is configured to receive a column address strobe (CAS), a row address strobe (RAS) and a write command (WEcommand) signal, and control the first switch tube 20 to be turned on according to the column address strobe signal CAS_n, the row address strobe signal RAS_n and the write command signal WE_n.

[0076] like Figure 3 As shown in the Joint Electron Device Engineering Council Standard (JEDEC) command truth table, the combination of RAS_n, CAS_n, and WE_n signals is unique when performing a read or write operation. Figure 3It can be seen that when the data channel 10 performs a read operation, the column address selection signal CAS_n is a high-level signal (H), the row address selection signal RAS_n is a low-level signal (L), and the write command signal WE_n is a high-level signal (H); when the data channel 10 performs a write operation, the column address selection signal CAS_n is a high-level signal (H), the row address selection signal RAS_n is a low-level signal (L), and the write command signal WE_n is a low-level signal (L). That is to say, when and only when the data channel 10 performs a read operation, the level combination of the column address selection signal CAS_n, the row address selection signal RAS_n and the write command signal WE_n is respectively HLH, and any level combination other than this level combination (for example, HHH) can indicate that the data channel 10 is not performing a read operation; similarly, when and only when the data channel 10 performs a write operation, the level combination of the column address selection signal CAS_n, the row address selection signal RAS_n and the write command signal WE_n is respectively HLL, and any level combination other than this level combination (for example, LLL) can indicate that the data channel 10 is not performing a write operation.

[0077] In this embodiment, by configuring the control circuit 30 to receive the column address strobe signal CAS_n, the row address strobe signal RAS_n, and the write command signal WE_n, the control circuit 30 can accurately determine whether the data channel 10 is performing a read operation or a write operation based on the column address strobe signal CAS_n, the row address strobe signal RAS_n, and the write command signal WE_n. When the data channel 10 is performing a read operation, the control circuit 30 controls the first switch 20 to be turned on, thereby coordinating with the second power supply receiving terminal of the data channel 10 to receive the second power supply voltage for normal operation. When the data channel 10 is not performing a read operation or a write operation, the control circuit 30 controls the first switch 20 to be turned off, thereby reducing the subthreshold leakage of the data channel 10, thereby reducing the static power consumption of the circuit and further improving the reliability of the circuit.

[0078] In one embodiment, Figure 4 As shown, the data channel 10 includes a data read channel 11, and the control circuit 30 includes a first NOT gate 301, a first NOR gate 302, a first NAND gate 303, and a second NOT gate 304. The input of the first NOT gate 301 is used to receive the row address strobe signal RAS_n. The first NOR gate 302 has a first input connected to the output of the first NOT gate 301, and a second input connected to the column address strobe signal CAS_n. The first NAND gate 303 has a first input connected to the output of the first NOR gate 302, and a second input connected to the write command signal WE_n. The input of the second NOT gate 304 is connected to the output of the first NAND gate 303, and the output is connected to the control terminal of the first switch transistor 20.

[0079] The data reading channel 11 is the data channel 10 for performing the read operation. Figure 4 As shown, it can be understood that by designing the control circuit 30 as Figure 4 The logic circuit shown can realize that the output end of the second NOT gate 304 outputs a high-level signal (H) only when and only when the row address selection signal RAS_n is a high-level signal (H), the column address selection signal CAS_n is a low-level signal (L), and the write command signal WE_n is a high-level signal (H). That is, the output end of the control circuit 30 outputs a high-level signal (H); otherwise, the output end of the control circuit 30 outputs a low-level signal (L).

[0080] For example, assuming that the row address strobe signal RAS_n is high, the column address strobe signal CAS_n is low, and the write command signal WE_n is high, then: since the input of the first NOT gate 301 is the high value of the row address strobe signal RAS_n, the output of the first NOT gate 301 is low; since the input of the first NOR gate 302 is the low value of the output of the first NOT gate 301 and the low value of the column address strobe signal CAS_n, the output of the first NOR gate 302 is high; since the input of the first NAND gate 303 is the high value of the output of the first NOR gate 302 and the high value of the write command signal WE_n, the output of the first NAND gate 303 is low; since the input of the second NOT gate 304 is the low value of the output of the first NAND gate 302, the output of the second NOT gate 304 is high. The output of the second NOT gate 304 is the output of the control circuit 30, that is, the control circuit 30 will output high at this time.

[0081] Furthermore, assuming that the row address strobe signal RAS_n is high, the column address strobe signal CAS_n is high, and the write command signal WE_n is high, then: since the input of the first NOT gate 301 is the high row address strobe signal RAS_n, the output of the first NOT gate 301 is low; since the input of the first NOR gate 302 is the low output of the first NOT gate 301 and the high column address strobe signal CAS_n, the output of the first NOR gate 302 is low; since the input of the first NAND gate 303 is the low output of the first NOR gate 302 and the high write command signal WE_n, the output of the first NAND gate 303 is high; since the input of the second NOT gate 304 is the high output of the first NAND gate 302, the output of the second NOT gate 304 is low. The output of the second NOT gate 304 is the output of the control circuit 30, that is, the control circuit 30 will output low at this time.

[0082] Therefore, from the above examples, we can see that Figure 4 The control circuit 30 can output H when and only when the row address selection signal RAS_n is H, the column address selection signal CAS_n is L, and the write command signal WE_n is H; otherwise, the control circuit will output L.

[0083] In this embodiment, the control circuit 30, which is composed of the first NOT gate 301, the first NOR gate 302, the first NAND gate 303, and the second NOT gate 304, can ensure that, when the data channel 10 is the data reading channel 11 performing a read operation, the output terminal of the control circuit 30 outputs a high-level signal only when the data channel 10 is performing a read operation. Otherwise, the output terminal of the control circuit 30 outputs a low-level signal. Thus, the control circuit 30 can output a high-level signal to the control terminal of the first switch 20 to turn on the first switch 20 when the data reading channel 11 is performing a read operation, and output a low-level signal to the control terminal of the first switch 20 to keep the first switch 20 off when the data reading channel 11 is not performing a read operation, thereby reducing the static power consumption of the circuit and further improving the reliability of the circuit.

[0084] In one embodiment, Figure 5 As shown, the data channel 10 includes a data write channel 12, and the control circuit 30 includes a third NOT gate 305, a second NOR gate 306, a fourth NOT gate 308, a second NAND gate 307, and a fifth NOT gate 309. The input of the third NOT gate 305 is used to receive the row address strobe signal RAS_n. The first input of the second NOR gate 306 is connected to the output of the third NOT gate 305, and the second input is used to receive the column address strobe signal CAS_n. The input of the fourth NOT gate 308 is used to receive the write command signal WE_n. The first input of the second NAND gate 307 is connected to the output of the second NOR gate 306, and the second input is connected to the output of the fourth NOT gate 308. The input of the fifth NOT gate 309 is connected to the output of the second NAND gate 307, and the output is connected to the control terminal of the first switch transistor 20.

[0085] The data writing channel 12 is the data channel 10 for performing the writing operation. Figure 5 As shown, it can be understood that by designing the control circuit 30 as Figure 5 The logic circuit shown can realize that the output end of the second NOT gate 304 outputs a high-level signal (H) only when and only when the row address selection signal RAS_n is a high-level signal (H), the column address selection signal CAS_n is a low-level signal (L), and the write command signal WE_n is a high-level signal (L). That is, the output end of the control circuit 30 outputs a high-level signal (H); otherwise, the output end of the control circuit 30 outputs a low-level signal (L).

[0086] For example, assuming that the row address selection signal RAS_n is H, the column address selection signal CAS_n is L, and the write command signal WE_n is L, at this time: since the input of the third NOT gate 305 is the H of the row address selection signal RAS_n, the output of the third NOT gate 305 is L; since the input of the second NOR gate 306 is the L output of the third NOT gate 305 and the L of the column address selection signal CAS_n, the output of the second NOR gate 306 is H; since the input of the fourth NOT gate 308 is the L output of the write command signal WE_n, the output of the fourth NOT gate 308 is H; since the input of the second NAND gate 307 is the H output of the second NOR gate 306 and the H output of the fourth NOT gate 308, the output of the second NAND gate 307 is L; since the input of the fifth NOT gate 309 is the L output of the second NAND gate 307, the output of the fifth NOT gate 309 is H. The output of the fifth NOT gate 309 is the output of the control circuit 30 , that is, the control circuit 30 outputs H at this time.

[0087] Further, assuming that the row address selection signal RAS_n is L, the column address selection signal CAS_n is L, and the write command signal WE_n is L, at this time: since the input of the third NOT gate 305 is the L of the row address selection signal RAS_n, the output of the third NOT gate 305 is H; since the input of the second NOR gate 306 is the H output of the third NOT gate 305 and the L of the column address selection signal CAS_n, the output of the second NOR gate 306 is L; since the input of the fourth NOT gate 308 is the L of the write command signal WE_n, the output of the fourth NOT gate 308 is H; since the input of the second NAND gate 307 is the L output of the second NOR gate 306 and the H output of the fourth NOT gate 308, the output of the second NAND gate 307 is H; since the input of the fifth NOT gate 309 is the H output of the second NAND gate 307, the output of the fifth NOT gate 309 is L. The output of the fifth NOT gate 309 is the output of the control circuit 30 , that is, the control circuit 30 outputs L at this time.

[0088] Therefore, from the above examples, we can see that Figure 5 The control circuit 30 can output H when and only when the row address selection signal RAS_n is H, the column address selection signal CAS_n is L, and the write command signal WE_n is L; otherwise, the control circuit will output L.

[0089] In this embodiment, the control circuit 30, which is composed of the third NOT gate 305, the second NOR gate 306, the fourth NOT gate 308, the second NAND gate 307, and the fifth NOT gate 309, can ensure that, when the data channel 10 is a data write channel 12 undergoing a write operation, the output terminal of the control circuit 30 outputs a high-level signal only when the data channel 10 is undergoing a write operation. Otherwise, the output terminals of the control circuit 30 all output low-level signals. Thus, the control circuit 30 can output a high-level signal to the control terminal of the first switch 20 to turn on the first switch 20 when the data write channel 12 is undergoing a write operation, and output a low-level signal to the control terminal of the first switch 20 to keep the first switch 20 off when the data write channel 12 is not undergoing a write operation, thereby reducing the static power consumption of the circuit and further improving the reliability of the circuit.

[0090] In one embodiment, Figure 6 As shown, the power control circuit also includes an anti-floating circuit 40, which is connected in parallel between the first end and the second end of the first switch tube 20, and is used to transmit the second power supply voltage to the second power supply receiving end of the data channel 10 when the second type transistor 1012 is turned on.

[0091] It should be noted that when the data channel 10 is not performing a read or write operation, to avoid subthreshold leakage, the second power receiving terminal of the data channel 10 is connected to the first terminal of the first switch 20. This prevents the second power receiving terminal of the data channel 10 from receiving the second power supply voltage when the first switch 20 is turned off, thereby reducing subthreshold leakage in the data channel 10. However, when the data channel 10 is not performing a read or write operation, the input terminal of the data channel 10 still receives a low-level signal or a high-level signal, causing the first-type transistor 1011 to turn off and the second-type transistor 1012 to turn on. When the second-type transistor 1012 turns on, the potential of the output terminal of the data channel 10 is pulled to be consistent with the potential of the second power receiving terminal of the data channel 10. However, since the second power receiving terminal is not connected to the second power supply voltage at this time, the potential of the second power receiving terminal is uncontrollable. This uncontrollable potential is called floating. As a result, the output of the data channel 10 is also uncontrollable, that is, the data channel 10 generates a floating circuit.

[0092] For example, Figure 6 As shown, assuming that the first type transistor 1011 is a P-type transistor and the second type transistor 1012 is an N-type transistor, and the input end of the data channel 10 is a low level signal, then Figure 6Because the first inverter 101 receives a low-level signal, the first-type transistor 1011 in the first inverter 101 is turned on, and the second-type transistor 1012 is turned off. At this point, the potential at the output of the first inverter 101 is consistent with the first power supply voltage, and therefore, it normally outputs a high-level signal. That is, when a low-level signal is input, the first inverter 101 does not experience a circuit floating phenomenon. However, when the input of the data channel 10 is a high-level signal, the first-type transistor 1011 in the first inverter 101 is turned off, and the second-type transistor 1012 is turned on. At this point, the potential at the output of the first inverter 101 is consistent with the second power supply receiving terminal of the data channel 10. Since the second power supply receiving terminal of the data channel 10 is not connected to the second power supply voltage, the potential at the second power supply receiving terminal of the data channel 10 is uncontrolled, and therefore the potential at the output of the first inverter 101 is also uncontrolled. That is, when a high-level signal is input, the potential output by the first inverter 101 is uncontrollable, resulting in a circuit hanging phenomenon.

[0093] Furthermore, when the data channel 10 is not performing a read or write operation, the potential at its input terminal remains consistent. For example, when the data channel 10 is not performing a read or write operation, its input terminal will maintain an input low-level signal or a input high-level signal. However, the second-type transistor 1012 will be turned on when inputting a low-level signal, causing the output potential of the data channel 10 to be uncontrollable. Therefore, by providing an anti-floating circuit 40 and transmitting the second power supply voltage to the second power supply receiving terminal of the data channel 10 when the second-type transistor 1012 is turned on, the potential at the output terminal of the inverter 101 remains consistent with the second power supply voltage, thereby preventing the data channel 10 from experiencing circuit floating.

[0094] In this embodiment, an anti-floating circuit 40 is provided in parallel between the first end and the second end of the first switch tube 20. The anti-floating circuit 40 is used to transmit the second power supply voltage to the second power supply receiving end of the data channel 10 when the second type transistor 1012 is turned on, so that the potential of the second power supply receiving end can be consistent with the second power supply voltage, that is, the potential of the output end of the inverter 101 can be consistent with the second power supply voltage, thereby preventing the data channel 10 from causing circuit floating, thereby further improving the reliability of the circuit.

[0095] In one embodiment, Figure 7 As shown, the anti-floating circuit 40 includes a second switch tube 401 , a first end of the second switch tube 401 connected to the first end of the first switch tube 20 , a second end connected to the second end of the first switch tube 20 , and a control end connected to the output end of the inverter 101 .

[0096] It should be noted that, during a period of time after the data channel 10 switches from a read operation or a write operation to a non-read operation or the start of a write operation, the potential of the second power supply receiving end of the data channel 10 remains at the second power supply voltage. Therefore, by connecting the control end of the second switch tube 401 to the output end of the inverter 101.

[0097] At the same time, since the level signal input to the data channel 10 remains unchanged when no read operation or write operation is performed, still taking the first type transistor 1011 as a P-type transistor and the second type transistor 1012 as an N-type transistor as an example, when the data channel 10 inputs a low level signal, Figure 7 The second type transistor 1012 in the first inverter 101 in the circuit remains off, and the circuit does not become suspended; and when the data channel 10 inputs a high level signal, Figure 7 The second-type transistor 1012 in the first inverter 101 is turned on, causing the output terminal of the first inverter 101 to maintain the same potential as the second power supply terminal. At this point, because the data channel 10 has just switched to a state where it is not performing a read or write operation, the potential of the second power supply terminal remains at the second power supply voltage. That is, the output of the first inverter 101 remains consistent with the second power supply voltage. Consequently, the control terminal of the second switch is turned on because it maintains the same potential as the second power supply voltage. This reconnects the second power supply terminal of the data channel 10 to the second power supply voltage through the conduction of the second switch, thus preventing the occurrence of a circuit floating phenomenon.

[0098] In this embodiment, by connecting the control end of the second switch tube 401 to the output end of the inverter 101, the second end of the second type transistor 1012 can be connected to the second power supply voltage in time when the circuit of the second type transistor 1012 is floating, thereby avoiding the second type transistor 1012 from floating, thereby further improving the reliability of the circuit.

[0099] In one embodiment, the type of the second switch transistor 401 is opposite to that of the second-type transistor 1012 .

[0100] In one embodiment, Figure 8As shown, the data channel 10 includes a plurality of inverters 101 cascaded in sequence, the power control circuit includes a plurality of first switching tubes 20 corresponding one-to-one to the plurality of inverters 101, and the anti-floating circuit 40 includes a plurality of second switching tubes 401 corresponding one-to-one to the plurality of inverters 101; the first end of each first switching tube 20 is connected to the second end of the second type transistor 1012 in the corresponding inverter 101, the first end of each second switching tube 401 is connected to the first end of the corresponding first switching tube 20, the second end of each second switching tube 401 is connected to the second end of the corresponding first switching tube 20, and the control end of each second switching tube 401 is connected to the output end of the corresponding inverter 101.

[0101] It is understandable that, since each inverter 101 may have a circuit hanging, a first switch tube 20 and a second switch tube 401 may be provided for each inverter 101. Thus, the first switch tube 20 can prevent the inverter 101 from having subthreshold leakage, and the second switch tube 401 can prevent the second-type transistor 1012 from having a circuit hanging, thereby further improving the reliability of the circuit.

[0102] In one embodiment, Figure 9 As shown, the data channel 10 includes a plurality of inverters 101 cascaded in sequence, the power control circuit includes two first switching tubes 20, and the anti-floating circuit 40 includes two second switching tubes 401 corresponding to the two first switching tubes 20; the first end of one first switching tube 20 is connected to the second end of the second type transistor 1012 in the odd-sequence inverter 101, and the first end of the other first switching tube 20 is connected to the second end of the second type transistor 1012 in the even-sequence inverter 101; the first end of each second switching tube 401 is connected to the first end of the corresponding first switching tube 20, and the second end of each second switching tube 401 is connected to the second end of the corresponding first switching tube 20; the control end of one second switching tube 401 is connected to the output end of the odd-sequence inverter 101, and the control end of the other second switching tube 401 is connected to the output end of the even-sequence inverter 101.

[0103] It should be noted that the control terminal of a second switch tube 401 can be connected only to the output terminal of any odd-numbered inverter 101, or to the output terminals of all odd-numbered inverters 101. For example, the control terminal of a second switch tube 401 can be connected only to the output terminal of the first, third, or fifth inverter 101. This is because the level signals output by the output terminals of the odd-numbered inverters 101 remain consistent. For example, when the output terminal of the first inverter 101 is a low-level signal, the output terminal of the third inverter 101 is also a low-level signal. Therefore, the control terminal of a second switch tube 401 can be connected only to the output terminal of any odd-numbered inverter 101. Of course, it is also possible for the control terminal of a second switch tube 401 to be connected to the output terminals of all odd-numbered inverters 101, and this embodiment does not impose any limitation thereto.

[0104] Similarly, the control end of another second switch tube 401 can be connected to the output end of only one inverter 101 with an even number sequence, or connected to the output ends of all inverters 101 with an even number sequence.

[0105] For example, still taking the first type transistor 1011 as LVPMOS, the second type transistor 1012 as LVNMOS, and the second switch tube 401 as HVPMOS as an example, Figure 9 As shown, it is assumed that the data channel 10 includes four inverters 101 , wherein the first and third inverters 101 are each provided with a HVPMOS, and the second and fourth inverters 101 are each provided with a HVPMOS.

[0106] It is understandable that if Figure 9As shown, the control terminal of the HVPMOS corresponding to the odd-numbered inverter 101 can be connected only to the output terminal of the first inverter 101. When the input terminal of the first inverter 101 is a high-level signal, the LVNMOS in the first inverter 101 will be turned on, so that the potential of the output terminal of the first inverter 101 is consistent with the potential of the second power supply receiving terminal of the data channel 10. Since the data channel 10 has just switched to not performing a read operation or a write operation, the potential of the second power supply receiving terminal of the data channel 10 remains at the second power supply voltage, that is, it remains at a low-level signal. Then, the control terminal of the HVPMOS corresponding to the odd-numbered inverter 101 will receive the low-level signal output by the first inverter 101, so that the HVPMOS can be turned on. Therefore, a single HVPMOS can connect the second terminals of the first and third inverters 101 to the second power supply voltage, thereby preventing the first and third inverters 101 from being left floating. Similarly, the control terminal of the HVPMOS corresponding to the odd-numbered inverters 101 can be connected only to the output terminal of the third inverter 101. When the input terminal of the third inverter 101 is a high-level signal, the LVNMOS in the third inverter 101 will be turned on, so that the potential of the output terminal of the third inverter 101 is consistent with the potential of the second power supply receiving terminal of the data channel 10. Since the data channel 10 has just switched to not performing a read or write operation, the potential of the second power supply receiving terminal of the data channel 10 remains at the second power supply voltage, that is, remains at a low-level signal. Therefore, the control terminal of the HVPMOS corresponding to the odd-numbered inverter 101 will receive the low-level signal output by the third inverter 101, thereby turning on the HVPMOS. Therefore, the second ends of the first inverter 101 and the third inverter 101 can be connected to the second power supply voltage through an HVPMOS, thereby preventing the first inverter 101 and the third inverter 101 from being suspended.

[0107] Similarly, if Figure 9As shown, the control terminal of the HVPMOS corresponding to the even-numbered inverter 101 can be connected only to the output terminal of the second inverter 101. When the input terminal of the second inverter 101 is a high-level signal, the LVNMOS in the second inverter 101 will be turned on, so that the potential of the output terminal of the second inverter 101 is consistent with the potential of the second power supply receiving terminal of the data channel 10. Since the data channel 10 has just switched to not performing a read operation or a write operation, the potential of the second power supply receiving terminal of the data channel 10 remains at the second power supply voltage, that is, it remains at a low-level signal. Then, the control terminal of the HVPMOS corresponding to the even-numbered inverter 101 will receive the low-level signal output by the second inverter 101, so that the HVPMOS can be turned on. Therefore, through a single HVPMOS, the second terminals of the second and fourth inverters 101, 101 can be connected to the second power supply voltage, thereby preventing the second and fourth inverters 101, 101, from being left floating. Similarly, the control terminal of the HVPMOS corresponding to the even-ordered inverters 101 can also be connected only to the output terminal of the fourth inverter 101. When the input terminal of the fourth inverter 101 is a high-level signal, the LVNMOS in the fourth inverter 101 will be turned on, so that the potential of the output terminal of the fourth inverter 101 is consistent with the potential of the second power supply receiving terminal of the data channel 10. Since the data channel 10 has just switched to not performing a read or write operation, the potential of the second power supply receiving terminal of the data channel 10 remains at the second power supply voltage, that is, remains at a low-level signal. The control terminal of the HVPMOS corresponding to the even-ordered inverter 101 will receive the low-level signal output by the fourth inverter 101, thereby turning on the HVPMOS. Therefore, the second terminals of the second inverter 101 and the fourth inverter 101 can be connected to the second power supply voltage through an HVPMOS, thereby preventing the second inverter 101 and the fourth inverter 101 from being suspended.

[0108] In this embodiment, two first switching tubes 20 are provided, wherein one first switching tube 20 is used to prevent subthreshold leakage from occurring in the odd-numbered inverters 101, and the other first switching tube 20 is used to prevent subthreshold leakage from occurring in the even-numbered inverters 101. At the same time, a second switching tube 401 is provided for the odd-numbered inverters 101 to prevent circuit floating from occurring in the odd-numbered inverters 101, and a second switching tube 401 is provided for the even-numbered inverters 101 to prevent circuit floating from occurring in the even-numbered inverters 101, thereby further improving circuit reliability and reducing costs.

[0109] In one embodiment, the threshold voltage of the second switch 401 is greater than or equal to the threshold voltage of the second-type transistor 1012 .

[0110] In one embodiment, the on-resistance of the second switch tube 401 is greater than (eg, much greater than) the on-resistance of the first switch tube 20 , thereby further reducing power consumption while meeting the requirement of preventing circuit floating.

[0111] For example, the first-type transistor 1011 can be a low-threshold-voltage P-type transistor, and the second switch 401 can be a high-threshold-voltage P-type transistor (HVPMOS) or a low-threshold-voltage P-type transistor (LVPMOS). This is because when the data channel 10 is not performing a read or write operation, the potentials of the various output nodes of the data channel 10 remain unchanged, and there are no timing issues. Therefore, the second switch 401 does not need to have extremely fast switching capabilities.

[0112] Based on the same inventive concept, the present application also provides a memory device, comprising the power control circuit of any of the aforementioned embodiments. When the data channel is not performing a read or write operation, the control circuit in the aforementioned power control circuit connects the second power supply receiving terminal of the data channel only to the first terminal of the first switching transistor. Because the first switching transistor is in the off state, it prevents the second power supply receiving terminal of the data channel from receiving the second power supply voltage, thereby reducing subthreshold leakage in the data channel, thereby lowering the circuit's static power consumption and improving circuit reliability.

[0113] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0114] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A power control circuit, characterized in that: include: a data channel having a first power receiving end and a second power receiving end, wherein the first power receiving end is configured to receive a first power supply voltage; a first switch tube having a control end, a first end, and a second end, wherein the first end of the first switch tube is connected to the second power supply receiving end of the data channel, and the second end of the first switch tube is configured to receive a second power supply voltage; a control circuit connected to the control terminal of the first switch tube and configured to control the first switch tube to be turned on when the data channel performs a read operation or a write operation, so as to transmit the second power supply voltage to the second power receiving terminal of the data channel; The control circuit is configured to receive a column address strobe signal, a row address strobe signal and a write command signal, and control the first switch tube to be turned on according to the column address strobe signal, the row address strobe signal and the write command signal; The data channel includes a data reading channel, and the control circuit includes: A first NOT gate, whose input terminal is used to receive the row address strobe signal; a first NOR gate, wherein a first input terminal is connected to the output terminal of the first NOR gate, and a second input terminal is used to receive the column address selection signal; a first NAND gate, having a first input terminal connected to the output terminal of the first NOR gate, and a second input terminal for receiving the write command signal; The second NOT gate has an input end connected to the output end of the first NAND gate, and an output end connected to the control end of the first switch tube.

2. The power control circuit according to claim 1, wherein: The data channel includes an inverter, which includes a first type transistor and a second type transistor. The control end of the first type transistor is connected to the control end of the second type transistor to serve as the input end of the inverter. The first end of the first type transistor is connected to the first end of the second type transistor to serve as the output end of the inverter. The second end of the first type transistor is connected to the first power supply receiving end, and the second end of the second type transistor is connected to the first end of the first switching tube.

3. The power control circuit according to claim 2, wherein: The second power supply voltage is lower than the first power supply voltage, the first type transistor is a P-type transistor, and the second type transistor is an N-type transistor.

4. The power control circuit according to claim 3, wherein: The type of the first switching transistor is the same as that of the second type transistor.

5. The power control circuit according to claim 4, characterized in that: The threshold voltage of the first switch tube is greater than the threshold voltage of the second type transistor.

6. The power control circuit according to claim 1, wherein: The data channel further includes the data writing channel, and the control circuit further includes: A third NOT gate, whose input terminal is used to receive the row address strobe signal; a second NOR gate, wherein a first input terminal is connected to the output terminal of the third NOR gate, and a second input terminal is used to receive the column address selection signal; a fourth NOT gate, whose input terminal is used to receive the write command signal; a second NAND gate, having a first input terminal connected to the output terminal of the second NOR gate, and a second input terminal connected to the output terminal of the fourth NOT gate; A fifth NOT gate has an input end connected to the output end of the second NAND gate, and an output end connected to the control end of the first switch tube.

7. The power control circuit according to any one of claims 3 to 5, characterized in that: Also includes: The anti-floating circuit is connected in parallel between the first end and the second end of the first switch tube, and is used to transmit the second power supply voltage to the second power supply receiving end of the data channel when the second type transistor is turned on.

8. The power control circuit according to claim 7, wherein: The anti-hanging circuit includes: The second switch tube has a first end connected to the first end of the first switch tube, a second end connected to the second end of the first switch tube, and a control end connected to the output end of the inverter.

9. The power control circuit according to claim 8, characterized in that: The type of the second switch transistor is opposite to that of the second type transistor.

10. The power control circuit according to claim 9, characterized in that: The data channel includes a plurality of inverters cascaded in sequence, the power control circuit includes a plurality of first switching tubes corresponding one-to-one to the plurality of inverters, and the anti-floating circuit includes a plurality of second switching tubes corresponding one-to-one to the plurality of inverters; The first end of each first switching tube is connected to the second end of the second type transistor in the corresponding inverter, the first end of each second switching tube is connected to the first end of the corresponding first switching tube, the second end of each second switching tube is connected to the second end of the corresponding first switching tube, and the control end of each second switching tube is connected to the output end of the corresponding inverter.

11. The power control circuit according to claim 9, wherein: The data channel includes a plurality of inverters cascaded in sequence, the power control circuit includes two first switching tubes, and the anti-floating circuit includes two second switching tubes corresponding to the two first switching tubes; the first end of one first switching tube is connected to the second end of the second type transistor in the odd-numbered inverter, and the first end of another first switching tube is connected to the second end of the second type transistor in the even-numbered inverter; the first end of each second switching tube is connected to the first end of the corresponding first switching tube, and the second end of each second switching tube is connected to the second end of the corresponding first switching tube; the control end of one second switching tube is connected to the output end of the odd-numbered inverter, and the control end of another second switching tube is connected to the output end of the even-numbered inverter.

12. The power control circuit according to claim 8, wherein: The threshold voltage of the second switch tube is greater than or equal to the threshold voltage of the second type transistor.

13. A memory, characterized in that: The method comprises the power control circuit according to any one of claims 1 to 12.

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