A novel memory array architecture compatible with CMOS back-end processes and its preparation method

Abstract

The present invention discloses a novel memory array architecture compatible with CMOS back-end processes and a method for fabricating the same, belonging to the fields of semiconductor and CMOS hybrid integrated circuit technology. The present invention proposes a novel three-dimensional memory array architecture based on 2T2S2R cells. In addition to a transistor, each memory cell also has a selector, effectively suppressing write crosstalk and excess read current. Each cell is led out through a horizontal source line (SL), eliminating the need for read and write currents to pass through the long transistor channel. A common source line (SL) is used to form a substantial 2T2S2R cell, reducing the SL area overhead and thereby improving integration density. Compared to a planar 1S1R array, the present invention introduces transistors without significantly increasing the area overhead, significantly reducing the 1S1R array's requirements for selector nonlinearity.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and CMOS hybrid integrated circuits, and particularly relates to an array architecture based on a novel memory (Emerging Memory) integrated with CMOS and a preparation method thereof. Background Art

[0002] Traditional microprocessors typically use a three-tiered architecture: cache, main memory, and solid-state drive (SSD) to store and process data. Main memory, represented by dynamic random access memory (DRAM), and SSDs, represented by flash memory, differ significantly in speed and density. Meanwhile, with the recent development of artificial intelligence, cloud computing, and the Internet of Things, data growth has far outpaced Moore's Law. However, memories like DRAM and flash memory face numerous limitations, such as physical limits, during miniaturization, and their performance and density improvements lag behind Moore's Law. Against this backdrop, research on novel memories based on new materials, principles, and structures, such as resistive random access memory (RRAM), phase change memory (PCRAM), magnetoresistive memory (MRAM), and ferroelectric memory (FeRAM), as well as on three-dimensional, stackable, high-density memory architectures based on these novel memories, has become increasingly important.

[0003] Traditional array architectures of new memory devices can generally be divided into three categories: 1R, 1T1R, and 1S1R.

[0004] 1R array, word lines and bit lines overlap to form a Crossbar structure. The area of ​​each memory cell is determined by its overlapping part, which can achieve a minimum area of ​​4F. 2 However, various issues such as leakage paths and write crosstalk make large-scale arrays practically impossible.

[0005] 1T1R array, which is the most common structure at present. This structure uses transistors (transistors) as gating units to shut off the leakage path, but the area occupied by each memory cell is mainly determined by the three-terminal transistor as a switching device. Each memory cell occupies an area of ​​6F. 2 (F is the feature size), which weakens the advantage of RRAM's high scalability.

[0006] The 1S1R array connects RRAM and a nonlinear switch selector in series. The selector has excellent scalability and a simple structure, does not increase the extra area, and can be stacked in three dimensions. The effective unit area of ​​each memory cell is only 4F. 2The 1S1R array is considered to have the greatest potential for integration. However, the complex material system of the gate transistors leads to significant fluctuations in device performance, which increases the memory read voltage threshold. Furthermore, the gate transistors provide limited nonlinearity, and leakage remains significant in larger arrays. These issues have limited the practical application of 1S1R arrays. Summary of the Invention

[0007] In order to improve the storage density of the 1S1R array architecture of new memory represented by resistive random access memory (RRAM), the present invention proposes a new three-dimensional memory array architecture based on 2T2S2R cells and its process implementation method.

[0008] The technical solutions provided by the present invention are as follows:

[0009] A novel memory array architecture compatible with CMOS back-end processes, characterized by comprising a plurality of columns of vertical transistors, wherein in each column of vertical transistors, two vertical transistors connected in series above and below each other constitute a unit, an isolation dielectric layer is provided between each unit, the gates of all vertical transistors are connected to a word line WL, and a 1S1R unit and a bit line BL are connected in the horizontal direction of each vertical transistor, the 1S1R unit being a gate transistor connected in series with a novel memory, the 1S1R unit and the bit line BL constituting a functional layer, and an isolation dielectric layer is provided between the functional layers of the vertical transistors adjacent above and below. A source line SL layer, wherein the source line SL is directly connected to the channel of the vertical transistor. An isolation dielectric layer is provided between the functional layer and the source line SL layer. Adjacent 1S1R units located above and below share a source line SL to form a 2T2S2R unit. The 2T2S2R array is expanded in the vertical and horizontal directions. When operating the array, the vertical transistor in the column where the selected device is located is turned on, while the remaining vertical transistor columns are turned off. An operating voltage is applied between the source line SL and the bit line BL corresponding to the selected device, and the voltages of the remaining source lines SL and bit lines BL are set according to the 1 / 2 bias method.

[0010] The present invention further provides a method for implementing TCAM using a novel memory array architecture, characterized in that each 2T2S2R cell in the memory array is used to store one bit of data. In the 2T2S2R cell, if the upper 1S1R cell is in a high-impedance state and the lower 1S1R cell is in a low-impedance state, it represents '0'; if the upper 1S1R cell is in a low-impedance state and the lower memory is in a high-impedance state, it represents '1'; if both the upper and lower 1S1R cells are in a high-impedance state, it represents 'X'. When querying, each time a group of column vertical transistors controlled by the same WL is turned on, the query data is represented by the voltages on BL and BL', V BL =Vread, V BL’ = GND means searching for '0', V BL =GND, V BL’=Vread means searching for '1', V BL =GND, V BL’ =GND means searching for 'X'. When the stored data matches the query data, the total current on SL is 0; otherwise, it indicates a mismatch.

[0011] The present invention further provides a method for preparing an array architecture of a novel memory, wherein the functional layer formed by the 1S1R unit and the bit line BL is composed of a resistive material / phase change material, a gate material, and a bit line material connected to each other, wherein the resistive material / phase change material is connected to the channel of the vertical transistor, comprising the following steps:

[0012] 1) preparing an isolation dielectric layer, a bit line, an isolation dielectric layer, a source line, an isolation dielectric layer, and a bit line alternately stacked on a substrate;

[0013] 2) photolithographically etching all the alternating stacks prepared in step 1) to form a first vertical through hole;

[0014] 3) preparing a gate material, or obtaining the gate material by chemical reaction of the bit line material, removing the excess gate material by wet etching, and etching its edge;

[0015] 4) preparing a resistive switching material / phase change material; removing excess resistive switching material / phase change material by wet etching, where the resistive switching material / phase change material, the gate material, and the bit line together form a functional layer; etching away redundant connection portions in the functional layer to make the sidewalls smoother, thereby forming a second through hole;

[0016] 5) depositing a channel function layer of a vertical transistor in the second vertical through hole;

[0017] 6) growing a gate dielectric layer material on the vertical transistor channel functional layer and filling the second vertical through hole;

[0018] 7) preparing an alternately stacked isolation dielectric layer, a bit line, an isolation dielectric layer, a source line, and a bit line based on the existing structure;

[0019] 8) Repeat steps 2) to 7) several times;

[0020] 9) Photolithographically etching the gate dielectric layer material of the alternately stacked vertical transistors to form a third vertical through hole;

[0021] 10) A transistor gate material is prepared in the third vertical through hole, and finally a 2T2S2R high-density memory array is formed.

[0022] In the above step 1), the isolation dielectric layer is preferably silicon oxide SiO2 or a low dielectric constant material (Low-K dielectric), such as porous SiO2, porous SiCOH, etc. The preferred preparation process is chemical vapor deposition CVD, plasma enhanced chemical vapor deposition PECVD, and the dielectric layer thickness is 10-1000nm.

[0023] In step 1), the materials for the bit lines and source lines are preferably one or more of vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), platinum (Pt), palladium (Pd), copper (Cu), and alloys thereof. Alternatively, they may be doped polysilicon materials. The preferred preparation process is physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), with a dielectric layer thickness of 10-1000 nm. It should be noted that the bit lines and source lines should be made of materials with different reducibility and etching selectivity to facilitate subsequent processing.

[0024] The gate material in step 3) is preferably vanadium oxide (VOx), niobium oxide (NbOx), germanium telluride (GeTex), germanium telluride (GeTex), germanium selenide (GeSex), or one or more alloys thereof. The gate material is preferably prepared by physical vapor deposition (PVD), oxidation, or atomic layer deposition (ALD), or by thermal oxidation of the bitline material.

[0025] The etching process in the above steps 2) and 10) is preferably a dry etching process such as RIE (Reactive Ion Etching) or ICP (Inductively coupled plasma).

[0026] The etching process in the above steps 3) and 4) is preferably wet etching.

[0027] In the above step 4), the resistive switching layer material for the resistive memory is preferably one or more of tantalum oxide (TaOx), titanium oxide (TiOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), silicon oxide (SiOx), etc. and their alloys. The preparation process is preferably physical vapor deposition PVD, oxidation or atomic layer deposition ALD. The phase change layer material of the phase change memory is preferably germanium antimony tellurium alloy (GeTeSb), scandium antimony tellurium alloy (ScSbTe), InAgSbTe alloy, GeSb alloy, GeTe alloy, SbTe alloy, etc., and the preparation process is preferably atomic layer deposition ALD or physical vapor deposition PVD. The resistive switching layer material of the magnetoresistive memory is preferably aluminum borate (AlBO), magnesium oxide MgO and aluminum oxide AlOx, etc., and the preparation process is preferably atomic layer deposition ALD.

[0028] The technical effects of the present invention are as follows:

[0029] (1) In addition to a transistor, each memory cell also has an additional selector, which can effectively suppress write crosstalk and excess read current;

[0030] (2) Each cell is led out through a horizontal source line (SL) nearby, so that the read and write currents do not need to pass through a long transistor channel;

[0031] (3) Forming a substantial 2T2S2R cell through the common source line (SL) method, reducing the area overhead of the SL and thus improving the integration density;

[0032] (4) By dividing the array into blocks, crosstalk, wiring resistance, and parasitic capacitance are further reduced, and the driving capability of the storage unit is enhanced, thereby expanding the array scale. Compared with the planar 1S1R array, this method introduces transistors without significantly increasing the area overhead, which can significantly reduce the 1S1R array's requirements for the nonlinearity of the selector. In addition, in addition to being used as a new type of memory, the present invention is also suitable for advanced computing scenarios such as in-memory computing. For example, when used as a ternary content addressable memory (TCAM), it has the advantages of low power consumption and high parallelism. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a circuit principle diagram of the present invention;

[0034] Figure 2 It is a three-dimensional principle diagram of the array of the present invention;

[0035] Figure 3 This is a vertical structural cross-sectional view of the present invention:

[0036] Figure 4 It is a horizontal structural cross-sectional view of the present invention;

[0037] Figure 5 It is the correspondence between the structure of the present invention and the principle diagram;

[0038] Figure 6 Schematic diagram of the operation strategy for implementing TCAM in the present invention;

[0039] Figures 7 to 18 It is a schematic flow chart of the process preparation method of the present invention;

[0040] Figure 7 Represents the growth process of the dielectric layer, bit line and source line of the multi-layer stack;

[0041] Figure 8 It indicates that a vertical deep hole structure is formed after photolithography etching;

[0042] Figure 9 It shows the process of preparing the gate layer by oxidation of the bit line;

[0043] Figure 10 Indicates the process of corroding the edge of the gating layer;

[0044] Figure 11 Indicates the process of preparing the resistive switching layer;

[0045] Figure 12 Indicates the edge process of the clothing resistance change layer;

[0046] Figure 13 Represents the process of growing and preparing transistor channel materials;

[0047] Figure 14 Indicates the process of growing and preparing transistor gate dielectric materials;

[0048] Figure 15 It shows the process of growing the dielectric layer, bit line and source line of the multi-layer stack again;

[0049] Figure 16 The cross-sectional view of the structure obtained after repeating the above process steps several times;

[0050] Figure 17 It indicates that a vertical deep hole structure is formed after photolithography etching;

[0051] Figure 18 Represents the process of growing and preparing transistor gate materials;

[0052] Figure 19 for Figures 7 to 18 Legend for .

[0053] Specific implementation cases

[0054] The present invention is further described below with reference to specific embodiments and accompanying drawings.

[0055] Figure 1 This is a schematic diagram of the architecture of the present invention. Figure 1As shown, in the high-density memory array based on 2T2S2R cells proposed by the present invention, a vertical column of vertical transistors is formed. A word line WL is connected to the gate of each vertical column of transistors, controlling the switching state of the column of transistors. A functional layer of 1S1R cells connected to a bit line BL is provided horizontally to the vertical transistors. The bit line BL is connected to the vertical column of transistors through the 1S1R cells. A source line SL layer is provided between the functional layers of two vertical transistors connected in series, one above and one below. The SL is directly connected to the vertical column of transistors. Each 1S1R cell connected to the vertical transistors is connected to a separate BL. Two adjacent 1S1R cells share a single SL, forming a de facto 2T2S2R cell. This cell is expanded in both the vertical and horizontal directions to form an n(2T2S2R) array. When operating the array, the transistors in the column of the selected device are turned on, while the remaining columns are turned off. An operating voltage is applied between the source line SL and the bit line BL corresponding to the selected device, and the voltages of the remaining SL and BL are set using a 1 / 2 bias method. For example, to set a device (SET), the corresponding SL and BL voltages are set to 0 and V, respectively. SET , the voltages of the other SL and BL are set to V SET The above operation method can access any memory cell in the array while suppressing crosstalk current between different cells. In addition, multiple BLs or SLs can be enabled simultaneously to achieve parallel access to multiple devices. Figure 2 Schematic diagram of the expanded n(2T2S2R) array of the present invention, which is formed by expanding the 2T2S2R units in the horizontal X direction, vertical direction and horizontal Y direction respectively.

[0056] Figure 3 This is a schematic cross-sectional view of the structure of the present invention: The 1S1R unit consists of a gate transistor connected in series with a novel memory device. The novel memory device is vertically connected to the vertical transistor channel at one end and to the horizontal bit line at the other. Counting from bottom to top, the functional layer of the 1S1R unit connected to the bit line BL consists of a resistive material, a gate material, and a horizontally connected bit line material. The resistive material is connected to the vertical transistor channel. An additional source line is located between the 2n-1 and 2n bit lines, forming a "bit line-source line-bit line" sandwich block. Only an isolation dielectric layer exists between the 2n and 2n+1 bit lines. The gate of the vertical transistor is enclosed by the channel behind the dielectric layer and is located in the center of the vertical structure.

[0057] Figure 4 This is a top view of the structure of the present invention. The 2T2S2R multi-layer vertical structure can achieve high-density arrangement on the horizontal area. Figure 5 The vertical transistor central gate WL performs overall gating control on the vertical transistor channel, and each layer of the novel memory can be accessed by its layer BL and block SL.

[0058] Figure 6 This is the operational strategy used by the present invention to implement TCAM. In TCAM, each 2T2S2R cell in the three-dimensional memory array is used to store one bit of data. A '0' is represented by the upper memory being in a high-impedance state and the lower memory being in a low-impedance state; a '1' is represented by the upper memory being in a low-impedance state and the lower memory being in a high-impedance state; and an 'X' is represented by both memories being in a high-impedance state. An n-bit of data is stored by n 2T2S2R cells along the horizontal Y direction, with different data arranged along the horizontal X direction and the vertical direction. When performing a query, a group of vertical transistors controlled by the same WL is turned on each time, and the query data is represented by the voltages on BL and BL', V BL =Vread, V BL’ = GND means searching for '0', V BL =GND, V BL’ =Vread means searching for '1', V BL =GND, V BL’ = GND indicates a search for 'X'. When the stored data matches the query data, the total current on SL is 0; otherwise, there is a mismatch. This method allows for addressing query data in the memory with a high degree of parallelism.

[0059] The novel memory in the embodiment uses a 2T2S2R device based on vanadium oxide VOx stacked with hafnium oxide HfOx. The preparation method is as follows:

[0060] 1) Silicon oxide SiO2, metal vanadium V, silicon oxide SiO2, metal nitride TiN, silicon oxide SiO2, and metal vanadium V are alternately prepared on the substrate, corresponding to the isolation dielectric layer, bit line, isolation dielectric layer, source line, and bit line, respectively. SiO2 is prepared by plasma enhanced chemical vapor deposition (PECVD) process, and V and TiN are prepared by PVD sputtering process, such as Figure 7 As shown;

[0061] 2) Using photolithography and reactive ion etching (RIE) to form a first vertical through hole, such as Figure 8 As shown;

[0062] 3) Use thermal oxidation process to oxidize the metal V on the side wall of the deep hole to form a vanadium oxide VOx layer, such as Figure 9 As shown;

[0063] 4) Remove the excessively grown VOx layer by wet etching and etch its edge, such as Figure 10 As shown;

[0064] 5) ALD is used to prepare the HfOx resistive switching layer, such as Figure 11 As shown;

[0065] 6) Remove the excessively grown HfOx resistive layer by wet etching to make the sidewall smoother and form a second vertical through hole, such as Figure 12 As shown;

[0066] 7) Prepare IGAO channel in the second vertical through hole by atomic layer deposition ALD, as shown in FIG. Figure 13 As shown;

[0067] 8) Using atomic layer deposition (ALD) to deposit a gate dielectric layer of hafnium oxide HfOx to fill the second through hole. Figure 14 As shown;

[0068] 9) Alternately prepare silicon oxide SiO2, metal vanadium V, silicon oxide SiO2, metal nitride TiN, silicon oxide SiO2, and metal vanadium V stacks, corresponding to the isolation dielectric layer, bit line, isolation dielectric layer, source line, and bit line, respectively, wherein SiO2 is prepared by plasma enhanced chemical vapor deposition PECVD process, and V and TiN are prepared by sputtering process, such as Figure 15 As shown;

[0069] 10) Repeat 2) to 9) several times, such as Figure 16 As shown;

[0070] 11) Forming a third vertical through hole by alternately stacking transistor gate dielectric layer materials using photolithography and reactive ion etching (RIE), such as Figure 17 As shown;

[0071] 12) Using PECVD to deposit polysilicon gate in the third through hole, finally forming a 2T2S2R high-density storage array such as Figure 18 shown.

[0072] The memory array of the present invention can be formed on a semiconductor substrate, wherein the semiconductor substrate material is, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. Alternatively, in some cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP).

[0073] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Those skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be based on the claims.

Claims

1. A CMOS back-end process compatible memory array architecture, characterized in that: The invention comprises a plurality of columns of vertical transistors, wherein in each column of vertical transistors, two vertical transistors connected in series above and below each other are a unit, an isolation dielectric layer is provided between each unit, the gates of all vertical transistors are connected to the word line WL, and a 1S1R unit and a bit line BL are connected in the horizontal direction of each vertical transistor. The 1S1R unit is composed of a gate tube and a memory in series, and the 1S1R unit and the bit line BL constitute a functional layer. The functional layer is composed of a resistive material, a gate material and a bit line material connected to each other, or the functional layer is composed of a phase change material, a gate material and a bit line material connected to each other, wherein the resistive material or the phase change material is connected to the channel of the vertical transistor, and the gate material is made of vanadium oxide VOx, niobium oxide NbOx, germanium telluride GeTe x, germanium telluride GeTex, germanium selenide GeSex materials and their alloys, a source line SL layer is provided between the functional layers of the upper and lower adjacent vertical transistors, the source line SL is directly connected to the channel of the vertical transistor, an isolation dielectric layer is provided between the functional layer and the source line SL layer, the upper and lower adjacent 1S1R units share a source line SL to form a 2T2S2R unit, which is expanded in the vertical and horizontal directions to form a 2T2S2R array. When operating the array, the vertical transistor of the column where the selected device is located is turned on and the remaining vertical transistor columns are turned off, an operating voltage is applied between the source line SL and the bit line BL corresponding to the selected device, and the voltage of the remaining source lines SL and bit lines BL is set to half of the operating voltage.

2. The array architecture according to claim 1, wherein: The memory is a resistive memory, a phase change memory, a magnetoresistive memory or a ferroelectric memory.

3. A method for implementing TCAM using the array architecture of claim 1, characterized in that: Each 2T2S2R cell in the array architecture is used to store one bit of data. In the 2T2S2R cell, if the upper 1S1R cell is in a high-impedance state and the lower 1S1R cell is in a low-impedance state, it represents '0'; if the upper 1S1R cell is in a low-impedance state and the lower memory is in a high-impedance state, it represents '1'; if both the upper and lower 1S1R cells are in a high-impedance state, it represents 'X'. When querying, a group of column vertical transistors controlled by the same WL is turned on each time, and the query data is represented by the voltage on BL and BL', V BL =Vread, V BL’ = GND means searching for '0', V BL =GND, V BL’ =Vread means searching for '1', V BL =GND, V BL’ =GND means searching for 'X'. When the stored data matches the query data, the total current on SL is 0; otherwise, it indicates a mismatch.

4. A method for preparing the array architecture according to claim 1, characterized in that: The functional layer formed by the 1S1R unit and the bit line BL is composed of a resistive material, a gate material, and a bit line material connected to each other, or the functional layer is composed of a phase change material, a gate material, and a bit line material connected to each other, wherein the resistive material or the phase change material is connected to the channel of the vertical transistor, comprising the following steps: 1) preparing an isolation dielectric layer, a bit line, an isolation dielectric layer, a source line, an isolation dielectric layer, and a bit line alternately stacked on a substrate; 2) photolithographically etching all the alternating stacks prepared in step 1) to form a first vertical through hole; 3) preparing a gate material, or obtaining the gate material by chemical reaction of the bit line material, removing the excess gate material by wet etching, and etching its edge; 4) preparing a resistive material or phase change material; removing excess resistive material or phase change material by wet etching, so that the resistive material or phase change material, the gate material, and the bit line together form a functional layer; etching away redundant connection portions in the functional layer to make the sidewall smoother, thereby forming a second through hole; 5) depositing a vertical transistor channel material layer in the second vertical through hole; 6) growing a gate dielectric layer material on the vertical transistor channel material layer and filling the second vertical through hole; 7) preparing an alternately stacked isolation dielectric layer, a bit line, an isolation dielectric layer, a source line, and a bit line based on the existing structure; 8) Repeat steps 2) to 7) several times; 9) Photolithographically etching the alternately stacked gate dielectric layer materials to form a third vertical through hole; 10) A transistor gate material is prepared in the third vertical through hole, and finally a 2T2S2R high-density memory array is formed.

5. The preparation method according to claim 4, wherein In step 1), the isolation dielectric layer is made of silicon oxide SiO2, porous SiO2 or porous SiCOH material, and the preparation process is chemical vapor deposition CVD or plasma enhanced chemical vapor deposition PECVD. The thickness of the isolation dielectric layer ranges from 10 to 1000 nm.

6. The preparation method according to claim 4, wherein In step 1), the materials of the bit line and the source line are selected from one or more of vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), platinum (Pt), palladium (Pd), copper (Cu), and alloys thereof, or doped polysilicon material with a thickness ranging from 10 to 1000 nm. The bit line and source line are made of materials with different reducing properties and etching selectivities, respectively.

7. The preparation method according to claim 4, wherein In step 4), the gate material is selected from one or more of vanadium oxide VOx, niobium oxide NbOx, germanium telluride GeTex, germanium telluride GeTex, germanium selenide GeSex, and alloys thereof. The preparation process adopts physical vapor deposition PVD, oxidation or atomic layer deposition ALD, or thermal oxidation of bit line material to prepare the gate material.

8. The preparation method according to claim 4, wherein In step 4), the resistive switching material is selected from one or more of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide and alloys thereof. The preparation process adopts physical vapor deposition (PVD), oxidation or atomic layer deposition (ALD), and the memory formed is a resistive switching memory.

9. The preparation method according to claim 4, wherein In step 4), the phase change material is selected from germanium antimony telluride alloy, scandium antimony telluride alloy, InAgSbTe alloy, GeSb alloy, GeTe alloy, and SbTe alloy. The preparation process adopts atomic layer deposition ALD or physical vapor deposition PVD, and the memory formed is a phase change memory material.

10. The preparation method according to claim 4, characterized in that In step 4), the resistive material is selected from aluminum borate, magnesium oxide MgO or aluminum oxide AlOx, and the preparation process adopts atomic layer deposition ALD. The memory formed is a magnetoresistive memory.

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