Packaging structure and preparation method thereof, semiconductor device, and electronic device

Abstract

The present disclosure relates to a packaging layer and a preparation method thereof, a semiconductor device, and an electronic device, comprising: a substrate; a target metal layer, located on the substrate, the target metal layer comprising a bottom edge and two side edges inclined upward, the bottom edge is attached to the substrate, and the two side edges form a preset angle with the substrate respectively; a packaging layer, located on the target metal layer, the top size of the packaging layer is larger than the bottom size of the target metal layer. The present disclosure can at least prevent the packaging layer from forming a trapezoid with a small top and a large bottom, thereby improving the electrical data of the packaging layer.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a packaging structure and a preparation method thereof, a semiconductor device, and an electronic device. Background Art

[0002] The redistribution layer (RDL), also known as the packaging layer, plays an important role in semiconductor packaging by rewiring the circuits on the chip to match the external connection points. The importance of RDL in semiconductor packaging is reflected in its ability to improve the electrical performance and reliability of the package. Through rewiring and optimized design, the chip can better connect to the outside world, thereby improving the performance and stability of the overall system.

[0003] However, if the RDL has an inclination angle, it will affect the flow capacity, thereby causing the attenuation of the product's electrical performance. That is, ideally, the RDL needs to be a cylinder with equal width at the top and bottom. In the prior art, after removing the photoresist layer, the metal dielectric layer needs to be removed by corrosion. During this process, the upper part of the RDL will first come into contact with the corrosive liquid, resulting in a longer corrosion time for the upper part of the RDL relative to the lower part, resulting in the final RDL being a trapezoidal shape with a small top and a large bottom, resulting in poor RDL electrical data. Summary of the invention

[0004] Based on this, it is necessary to provide a packaging structure and its preparation method, a semiconductor device, and an electronic device to address the above technical problems, which can at least avoid the packaging layer from forming a trapezoidal shape with a small top and a large bottom, and improve the electrical data of the packaging layer.

[0005] In order to achieve the above-mentioned purpose and other purposes, in the first aspect, the present disclosure provides a packaging layer, including: a bottom metal layer; a substrate; a metal dielectric layer, located on the substrate, the metal dielectric layer including a bottom edge and two side edges inclined upward, the bottom edge is attached to the substrate, and the two side edges form a preset angle with the substrate respectively; a packaging layer, located on the metal dielectric layer, the top size of the packaging layer is larger than the bottom size of the metal dielectric layer.

[0006] In the encapsulation layer in the above embodiment, the encapsulation layer is formed on a metal dielectric layer including a bottom edge and two side edges inclined upward so that the top size of the encapsulation layer is larger than the bottom size of the metal dielectric layer. In this way, during the process of removing the metal dielectric layer by etching, the upper part of the encapsulation layer that first contacts the etching liquid will be corroded for a longer time than the lower part. However, since the top size of the encapsulation layer is larger than the bottom size of the metal dielectric layer, the encapsulation layer is prevented from forming a trapezoid with a small top and a large bottom, thereby improving the electrical data of the encapsulation layer.

[0007] In one embodiment, the two sides have target lengths, and the preset angle has a target angle.

[0008] In the encapsulation layer in the above embodiment, by setting the target angle and the target length, a redundant corrosion portion is formed on the top of the encapsulation layer formed on the metal dielectric layer, thereby avoiding the encapsulation layer from forming a trapezoid with a small top and a large bottom, thereby improving the electrical data of the encapsulation layer.

[0009] In one embodiment, the difference between the top dimension of the encapsulation layer and the bottom dimension of the metal dielectric layer is a first target value, and the first target value is a preset redundant corrosion value.

[0010] In the encapsulation layer in the above embodiment, by setting the first target value as a redundant corrosion value, a redundant corrosion portion is formed on the top of the encapsulation layer formed on the metal dielectric layer, and by setting the size of the redundant corrosion portion, while avoiding the encapsulation layer from forming a trapezoid with a small top and a large bottom, the encapsulation layer can be formed into a encapsulation layer with the same width at the top and the bottom, thereby further improving the electrical data of the encapsulation layer.

[0011] In a second aspect, the embodiments of the present disclosure further provide a semiconductor device, including: the packaging layer in any of the above embodiments, which can at least prevent the packaging layer from forming a trapezoidal shape that is small at the top and large at the bottom, thereby improving the electrical data of the packaging layer.

[0012] In a third aspect, the embodiments of the present disclosure further provide an electronic device, including: the semiconductor device in any of the above embodiments, which can at least prevent the packaging layer from forming a trapezoidal shape that is small at the top and large at the bottom, thereby improving the electrical data of the packaging layer.

[0013] In a fourth aspect, an embodiment of the present disclosure also provides a method for preparing a packaging layer, comprising: forming a substrate; forming a metal dielectric layer on the substrate, the metal dielectric layer comprising a bottom edge and two side edges inclined upward, the bottom edge is attached to the substrate, and the two side edges form an angle with the substrate respectively; forming a packaging layer on the metal dielectric layer.

[0014] In the method for preparing the encapsulation layer in the above embodiment, the encapsulation layer is formed on a metal dielectric layer including a bottom edge and two side edges inclined upward so that the top size of the encapsulation layer is larger than the bottom size of the metal dielectric layer. In this way, during the process of removing the metal dielectric layer by etching, the upper part of the encapsulation layer that first contacts the etching liquid will be corroded for a longer time than the lower part. However, since the top size of the encapsulation layer is larger than the bottom size of the metal dielectric layer, the encapsulation layer is prevented from forming a trapezoid with a small top and a large bottom, thereby improving the electrical data of the encapsulation layer.

[0015] In one embodiment, a metal dielectric layer is formed on a substrate, comprising: forming a photoresist layer on the substrate, the photoresist layer having a target notch, the target notch comprising a bottom edge and two side edges inclined upward, the bottom edge of the target notch being in contact with the substrate, and the two side edges forming angles with the substrate respectively; forming the metal dielectric layer on the photoresist layer; forming a sacrificial layer on the metal dielectric layer; patterning the sacrificial layer to form an opening on the sacrificial layer, the opening being used to expose the target notch; using the patterned sacrificial layer as a mask and the photoresist layer as an etching end point, etching and removing the metal dielectric layer except the target notch to form the metal dielectric layer on the substrate.

[0016] In the method for preparing the encapsulation layer of the above embodiment, a metal dielectric layer is formed to provide a formation position for the encapsulation layer, so that the structural shape and size of the encapsulation layer meet the subsequent etching requirements.

[0017] In one embodiment, forming a packaging layer on a metal dielectric layer includes: forming a sacrificial layer on the metal dielectric layer and then forming a packaging layer in a target gap; etching and removing the metal dielectric layer except for the target gap, and then etching and stripping the photoresist layer to form a packaging layer on the metal dielectric layer.

[0018] In one embodiment, the difference between the width of the top of the packaging layer and the width of the bottom of the metal dielectric layer is a first target value, and the first target value is a preset redundant corrosion value.

[0019] In the preparation method of the encapsulation layer of the above embodiment, a encapsulation layer is formed in which the difference between the width of the top of the encapsulation layer and the width of the bottom edge of the metal dielectric layer is a first target value, and a redundant size is formed on the top of the encapsulation layer before etching, so that the encapsulation layer after etching forms an encapsulation layer with equal widths at the top and bottom.

[0020] In one embodiment, the method further includes: etching the encapsulation layer to form a target encapsulation layer, wherein a top width of the target encapsulation layer is the same as a bottom width of the target encapsulation layer.

[0021] In the method for preparing the encapsulation layer of the above embodiment, the encapsulation layer with equal width at the top and bottom is formed by etching, thereby improving the electrical data of the encapsulation layer.

[0022] The packaging structure and preparation method thereof, the semiconductor device, and the electronic device of the above-mentioned embodiments can at least prevent the packaging layer from forming a trapezoidal shape with a small top and a large bottom, thereby improving the electrical data of the packaging layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 This is a schematic diagram of the structure of the encapsulation layer provided in one embodiment of the present application;

[0025] Figure 2 A schematic diagram of the structure of an encapsulation layer provided in another embodiment of the present application;

[0026] Figure 3 This is a schematic diagram of the structure of an encapsulation layer provided in yet another embodiment of the present application;

[0027] Figure 4 The present invention is a schematic diagram of a process for preparing a solar cell provided in another embodiment of the present application.

[0028] Description of reference numerals:

[0029] 101, substrate; 102, metal dielectric layer; 103, packaging layer; 201, photoresist layer; 301, sacrificial layer. DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0032] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0036] See also Figure 1 , Figure 1 The structure of the encapsulation layer 103 in the prior art is shown. In the conventional encapsulation layer 103 manufacturing process, refer to Figure 1 In FIG. (a), first, a substrate 101 is provided; secondly, refer to Figure 1 In FIG. (b), a metal dielectric layer is formed on the substrate 101; again, refer to Figure 1 In FIG. 2( c ), a photoresist layer 201 is formed on the substrate 101 , and the photoresist layer 201 can be patterned as required; again, refer to Figure 1 In (d), a packaging layer 103 is formed between the patterned photoresist layers 201; finally, see Figure 1 In Figure (e), the metal dielectric layer is corroded. Since the upper part will contact the corrosive liquid first, the upper part of the packaging layer 103 will corrode for a longer time than the lower part, resulting in the final packaging layer 103 being a trapezoidal shape with a small top and a large bottom, resulting in poor RDL electrical data.

[0037] See also Figure 2-Figure 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0038] Please continue reading Figure 2As an example, one aspect of the present application provides a packaging structure, including: a substrate 101; a metal dielectric layer 102, located on the substrate 101, the metal dielectric layer 102 including a bottom edge and two side edges inclined upward, the bottom edge is attached to the substrate 101, and the two side edges form a preset angle with the substrate 101 respectively; a packaging layer 103, located on the metal dielectric layer 102, the top size of the packaging layer 103 is larger than the bottom size of the metal dielectric layer 102. The packaging layer 103 can be formed on the metal dielectric layer including the bottom edge and the two side edges inclined upward, so that the top size of the packaging layer 103 is larger than the bottom size of the metal dielectric layer. Although, in the process of etching away the metal dielectric layer 102, the upper part of the packaging layer 103 that first contacts the etching liquid is etched by the etching liquid for a longer time than the lower part, but because the top size of the packaging layer 103 is larger than the bottom size of the metal dielectric layer, the packaging layer 103 is prevented from forming a trapezoid with a small top and a large bottom, thereby improving the electrical data of the packaging layer 103.

[0039] Wherein, the substrate 101 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 101 can be a single-layer structure or a multi-layer structure. For example, the substrate 101 can be a silicon substrate 101, a silicon germanium substrate 101, a silicon germanium carbon substrate 101, a silicon carbide substrate 101, a gallium arsenide substrate 101, an indium arsenide substrate 101, an indium phosphide substrate 101 or other III / V semiconductor substrates 101 or II / VI semiconductor substrates 101. Alternatively, for example, the substrate 101 can be a layered substrate 101 including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate 101 should not limit the scope of protection of the present disclosure.

[0040] The metal dielectric layer may be the metal dielectric layer 102, which may be made of silicon dioxide, silicon nitride, aluminum oxide, or other dielectric materials. Therefore, the type of the metal dielectric layer should not limit the protection scope of the present disclosure.

[0041] In the encapsulation layer 103 in the above embodiment, the two sides have target lengths, and the preset angle has a target angle. By setting the target angle and the target length, a redundant corrosion portion is formed on the top of the encapsulation layer 103 formed on the metal dielectric layer, thereby preventing the encapsulation layer 103 from forming a trapezoidal shape with a small top and a large bottom, thereby improving the electrical data of the encapsulation layer 103.

[0042] In the encapsulation layer 103 in the above embodiment, the difference between the top size of the encapsulation layer 103 and the bottom size of the metal dielectric layer is a first target value, and the first target value is a pre-set redundant corrosion value. By setting the first target value as the redundant corrosion value, a redundant corrosion portion is formed on the top of the encapsulation layer 103 formed on the metal dielectric layer, and by setting the size of the redundant corrosion portion, while avoiding the encapsulation layer 103 from forming a trapezoid with a small top and a large bottom, the encapsulation layer 103 can be formed into an encapsulation layer 103 with the same width at the top and the bottom, thereby further improving the electrical data of the encapsulation layer 103.

[0043] Please refer to Figure 2-Figure 4 As an example, the present disclosure provides a method for preparing the encapsulation layer 103, comprising the following steps:

[0044] Step S1000: forming a substrate 101.

[0045] Step S2000 : forming a metal dielectric layer on the substrate 101 .

[0046] The metal dielectric layer includes a bottom edge and two side edges inclined upward, the bottom edge is in contact with the substrate 101 , and the two side edges form angles with the substrate 101 .

[0047] Step S3000: forming a packaging layer 103 on the metal dielectric layer.

[0048] In the preparation method of the encapsulation layer 103 in the above embodiment, the encapsulation layer 103 is formed on a metal dielectric layer including a bottom edge and two side edges inclined upward, so that the top size of the encapsulation layer 103 is larger than the bottom size of the metal dielectric layer. In this way, during the process of removing the metal dielectric layer 102 by etching, the upper part of the encapsulation layer 103 that is first in contact with the etching solution will be corroded for a longer time than the lower part. However, since the top size of the encapsulation layer 103 is larger than the bottom size of the metal dielectric layer, the encapsulation layer 103 is prevented from forming a trapezoid with a small top and a large bottom, thereby improving the electrical data of the encapsulation layer 103.

[0049] In step S1000, refer to Figure 3 and Figure 4 ,in, Figure 3 Figure (a) is a schematic structural diagram corresponding to step S1000.

[0050] Wherein, the substrate 101 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 101 can be a single-layer structure or a multi-layer structure. For example, the substrate 101 can be a silicon substrate 101, a silicon germanium substrate 101, a silicon germanium carbon substrate 101, a silicon carbide substrate 101, a gallium arsenide substrate 101, an indium arsenide substrate 101, an indium phosphide substrate 101 or other III / V semiconductor substrates 101 or II / VI semiconductor substrates 101. Alternatively, for example, the substrate 101 can be a layered substrate 101 including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate 101 should not limit the scope of protection of the present disclosure.

[0051] In one embodiment, a metal dielectric layer is formed on a substrate 101, comprising: forming a photoresist layer 201 on the substrate 101, wherein the photoresist layer 201 has a target notch, wherein the target notch includes a bottom edge and two side edges inclined upward, wherein the bottom edge of the target notch is in contact with the substrate 101, and the two side edges respectively form an angle with the substrate 101; forming a metal dielectric layer 102 on the photoresist layer 201; forming a sacrificial layer 301 on the metal dielectric layer 102; patterning the sacrificial layer 301 to form an opening on the sacrificial layer 301, wherein the opening is used to expose the target notch; using the patterned sacrificial layer 301 as a mask and the photoresist layer 201 as an etching end point, etching and removing the metal dielectric layer 102 except the target notch, so as to form a metal dielectric layer on the substrate 101.

[0052] In the method for preparing the encapsulation layer 103 of the above embodiment, a metal dielectric layer is formed to provide a formation position for the encapsulation layer 103 so that the structural shape and size of the encapsulation layer 103 meet the subsequent etching requirements.

[0053] As an example, see Figure 3 and Figure 4 , Figure 3 Figures (b) to (c) are schematic diagrams of the structures corresponding to step S2000.

[0054] Specifically, first, a photoresist layer 201 needs to be formed on the substrate 101, wherein the photoresist layer 201 has a target notch, the target notch includes a bottom edge and two side edges inclined upward, the bottom edge of the target notch is in contact with the substrate 101, and the two side edges form an angle with the substrate 101, thus forming Figure 3The structure corresponding to the middle (b) figure; then, it is necessary to form a metal dielectric layer 102 on the photoresist layer 201; form a sacrificial layer 301 on the metal dielectric layer 102; pattern the sacrificial layer 301 to form an opening on the sacrificial layer 301, and the opening is used to expose the target gap; use the patterned sacrificial layer 301 as a mask and the photoresist layer 201 as an etching end point to etch and remove the metal dielectric layer 102 except the target gap, so that Figure 3 The structure corresponding to Figure (c).

[0055] Here, a deposition process can be used to form a metal dielectric layer 102 on the photoresist layer 201, and the deposition process may include but is not limited to at least one of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) and a spin-on dielectric layer (Spin-on Dielectric, SOD) process.

[0056] Preferably, a sputtering process can deposit thin film materials on the surface of the substrate 101. The sputtering process has the advantages of high uniformity, high adhesion and diversity. Different sputtering types can be selected and process parameters can be adjusted to meet the requirements of thin film materials in different situations.

[0057] In one embodiment, forming a packaging layer 103 on a metal dielectric layer includes: forming a sacrificial layer 301 on the metal dielectric layer 102, and then forming the packaging layer 103 in a target gap; after etching and removing the metal dielectric layer 102 except for the target gap, etching and stripping the photoresist layer 201 to form a packaging layer 103 on the metal dielectric layer.

[0058] As an example, see Figure 3 and Figure 4 , Figure 3 Figures (d) to (i) are schematic diagrams of the structures corresponding to step S3000.

[0059] Specifically, first, a sacrificial layer 301 needs to be formed on the metal dielectric layer 102, that is, Figure 3 The structure shown in Figure (d) needs to be explained. Figure 3 As shown in FIG. (d), the sacrificial layer 301 has a target gap. Next, after the sacrificial layer 301 is formed on the metal dielectric layer 102, the encapsulation layer 103 is formed in the target gap. Figure 3 The structure shown in Figure (e); again, the sacrificial layer 301 needs to be removed, that is, Figure 3 The structure shown in Figure (f); again, the metal dielectric layer 102 except the target gap needs to be removed, that is, Figure 3 The structure shown in FIG. (g); again, the photoresist layer 201 needs to be etched and stripped, and the photoresist layer 201 needs to be etched and stripped to form a packaging layer 103 on the metal dielectric layer, that is, Figure 3 The structures shown in Figures (g) to (i).

[0060] It should be understood that although Figure 3 The steps in the schematic diagram are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0061] Among them, in the step of etching and stripping the photoresist layer 201, the RDL at the bottom is protected due to the existence of the photoresist layer 201. At the same time, the redundant packaging layer 103 on the top also protects the packaging layer 103 inside it, further avoiding the packaging layer 103 from forming a trapezoidal shape with a small top and a large bottom.

[0062] In one embodiment, the difference between the width of the top of the packaging layer 103 and the width of the bottom of the metal dielectric layer is a first target value.

[0063] The first target value is a preset redundant corrosion value.

[0064] Here, the redundant corrosion value may be calculated based on the etching speed of the etching solution on the encapsulation layer 103 and the time required for etching, or may be set based on experience of etching the encapsulation layer 103 multiple times.

[0065] It should be noted that the present application uses a specific chemical solution (such as hydrofluoric acid, nitric acid, etc.) to etch the encapsulation layer 103. In the process of etching or corroding the encapsulation layer 103. Etching rate, selective anisotropy, uniformity, etc. are all key factors in determining the redundant corrosion value. Among them, the etching rate refers to the amount of material removed per unit time. It is necessary to select a suitable etching rate according to the process requirements to ensure etching accuracy and uniformity; etching selectivity refers to the etching rate ratio between the target material and the mask material or the substrate 101 material. High selectivity helps to protect the mask and substrate and avoid unnecessary material loss; anisotropic etching refers to different etching rates in the vertical and horizontal directions. High anisotropic etching can form a more vertical sidewall structure and improve the resolution and accuracy of the pattern; etching uniformity refers to the consistency of the etching rate on the entire substrate surface. Good uniformity ensures the consistency and reliability of device performance.

[0066] As an example, the selectivity among the packaging layer 103 material, the metal dielectric material, the substrate 101 material, etc. can be considered, and the selectivity can be improved by optimizing the etching gas and process parameters; the etching uniformity can be improved by optimizing the etching equipment and process parameters (such as gas flow distribution, plasma density, etc.).

[0067] In some etching processes, the etching or corrosion process may cause damage to the material surface, which can be reduced by selecting appropriate etching processes and post-processing steps (such as cleaning, annealing, etc.).

[0068] In this way, by forming a packaging layer 103 with a width difference between the top of the packaging layer 103 and the bottom of the metal dielectric layer being the first target value, a redundant size is formed on the top of the packaging layer 103 before etching, so that a packaging layer 103 with equal width at the top and bottom is formed after etching.

[0069] In one embodiment, the preparation method of the encapsulation layer 103 also includes: etching the encapsulation layer 103 to form a target encapsulation layer 103, the top width of the target encapsulation layer 103 is the same as the bottom width of the target encapsulation layer 103, and the encapsulation layer 103 with equal width at the top and bottom formed by etching improves the electrical data of the encapsulation layer 103.

[0070] In the preparation method of the encapsulation layer of the above embodiment, by forming an encapsulation layer with a top size larger than a bottom size, the top portion that is in contact with the corrosive liquid for a longer time when the encapsulation layer is corroded forms a corrosion redundancy, which at least avoids the encapsulation layer from forming a trapezoid with a small top and a large bottom, thereby improving the electrical data of the encapsulation layer.

[0071] The disclosed embodiments further provide a semiconductor device, including: the packaging layer in any of the above embodiments, which can at least prevent the packaging layer from forming a trapezoidal shape that is small at the top and large at the bottom, thereby improving the electrical properties of the packaging layer.

[0072] The disclosed embodiments further provide an electronic device, including: the semiconductor device in any of the above embodiments, which can at least prevent the packaging layer from forming a trapezoidal shape that is small at the top and large at the bottom, thereby improving the electrical data of the packaging layer.

[0073] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features of the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above embodiments only express several implementation methods of the present disclosure, and their descriptions are relatively specific and detailed, but they cannot be understood as limitations on the scope of the patent application. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present disclosure, several variations and improvements can be made, which all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed in this disclosure shall be based on the attached claims.

Claims

1. A packaging structure, characterized in that: include: substrate; A metal dielectric layer is located on the substrate, the metal dielectric layer comprises a bottom edge and two side edges inclined upward, the bottom edge is in contact with the substrate, and the two side edges respectively form a preset angle with the substrate; A packaging layer, located on the metal dielectric layer, wherein the top dimension of the packaging layer is larger than the bottom dimension of the metal dielectric layer; The difference between the top size of the encapsulation layer and the bottom size of the metal dielectric layer is a first target value, and the first target value is the top size of the portion of the encapsulation layer that is removed by corrosion.

2. The packaging structure according to claim 1, characterized in that: The two sides have a target length, and the preset angle has a target angle.

3. The packaging structure according to claim 1, characterized in that: The metal dielectric layer is made of at least one of silicon dioxide, silicon nitride and aluminum oxide.

4. A semiconductor device, characterized in that: include: The packaging structure according to any one of claims 1 to 3.

5. An electronic device, characterized in that: include: The semiconductor device according to claim 4.

6. A method for preparing a packaging structure, comprising: forming a substrate; forming a metal dielectric layer on the substrate, wherein the metal dielectric layer comprises a bottom edge and two side edges inclined upward, wherein the bottom edge is in contact with the substrate, and the two side edges respectively form an angle with the substrate; A packaging layer is formed on the metal dielectric layer; the top size of the packaging layer is larger than the bottom size of the metal dielectric layer; the difference between the top size of the packaging layer and the bottom size of the metal dielectric layer is a first target value, and the first target value is the top size of the portion of the packaging layer that is corroded and removed.

7. The method according to claim 6, characterized in that Forming a metal dielectric layer on the substrate, comprising: A photoresist layer is formed on the substrate, wherein the photoresist layer has a target notch, wherein the target notch includes a bottom edge and two side edges inclined upward, wherein the bottom edge of the target notch is in contact with the substrate, and the two side edges form angles with the substrate respectively; forming a metal dielectric layer on the photoresist layer; forming a sacrificial layer on the metal dielectric layer; Patterning the sacrificial layer to form an opening on the sacrificial layer, wherein the opening is used to expose the target notch; The patterned sacrificial layer is used as a mask, and the photoresist layer is used as an etching end point to etch and remove the metal dielectric layer except for the target gap, so as to form a metal dielectric layer on the substrate.

8. The method according to claim 7, characterized in that Forming a packaging layer on the metal dielectric layer, comprising: After forming a sacrificial layer on the metal dielectric layer, forming a packaging layer in the target gap; After etching and removing the metal dielectric layer except the target gap, etching and stripping the photoresist layer to form a packaging layer on the metal dielectric layer.

9. The method according to claim 8, characterized in that The metal dielectric layer is made of at least one of silicon dioxide, silicon nitride and aluminum oxide.

10. The method according to claim 6 or 9, characterized in that: Also includes: The encapsulation layer is etched to form a target encapsulation layer, wherein a top width of the target encapsulation layer is the same as a bottom width of the target encapsulation layer.

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