A semiconductor structure and its manufacturing method

Abstract

This disclosure relates to the semiconductor field and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a gate structure, a channel region, an isolation structure, and a charge-discharge structure. The gate structure is located on the substrate and extends along a first direction perpendicular to a vertical direction. The channel region surrounds the sidewalls of the gate structure perpendicular to the first direction. A portion of the isolation structure is located between the channel region and the substrate. One side of the charge-discharge structure contacts the channel region, and the other side of the charge-discharge structure at least partially contacts the isolation structure, and the charge-discharge structure is grounded.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] In semiconductor devices, because the transistor structure is located on the insulating layer, charge tends to accumulate in the channel region of the transistor structure and cannot be discharged through the substrate, resulting in a floating body effect in the transistor structure. This causes a decrease in transistor performance and, in turn, adversely affects the electrical performance and reliability of the device. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, including:

[0004] Substrate;

[0005] A gate structure is located on the substrate and extends along a first direction; the first direction is perpendicular to the vertical direction.

[0006] The channel region surrounds the sidewall of the gate structure perpendicular to the first direction;

[0007] An isolation structure, wherein a portion of the isolation structure is located between the channel region and the substrate;

[0008] A charge-discharging structure, wherein one side of the charge-discharging structure contacts the channel region; wherein the other side of the charge-discharging structure at least partially contacts the isolation structure; and the charge-discharging structure is grounded.

[0009] In some embodiments, the charge-derived structure includes a first sub-region and a second sub-region; the first sub-region and the second sub-region extend along the first direction;

[0010] The first sub-region and the second sub-region are located on opposite sides of the charge-out structure along the vertical direction, respectively.

[0011] Along a second direction, multiple second sub-regions are arranged at intervals; the second direction is perpendicular to the vertical direction.

[0012] In some embodiments, the doping type of the channel region is the same as the doping type of the charge-derived structure, and the doping concentration of the channel region is less than the doping concentration of the charge-derived structure.

[0013] In some embodiments, the semiconductor structure further includes: a source electrode and a drain electrode that are distributed opposite to each other along a second direction; the second direction is perpendicular to the vertical direction;

[0014] The source electrode and the drain electrode are respectively electrically connected to the two opposite ends of the channel region along the second direction.

[0015] In some embodiments, the cross-sections of the source electrode and the drain electrode perpendicular to the first direction are L-shaped;

[0016] The source electrode and the drain electrode each cover a portion of the upper surface of the channel region, and the source electrode and the drain electrode also cover two opposite sides of the channel region along the second direction.

[0017] In some embodiments, the material of the channel region includes indium gallium zinc oxide.

[0018] In some embodiments, the isolation structure includes a first trench, and the charge-discharging structure, the channel region, and the gate structure are located within the first trench.

[0019] In some embodiments, the semiconductor structure further includes: a gate dielectric layer;

[0020] The gate dielectric layer is located between the gate structure and the channel region, and surrounds the sidewall of the gate structure.

[0021] This disclosure also provides a method for manufacturing a semiconductor structure, including:

[0022] Provide substrate;

[0023] An isolation structure is formed on the substrate;

[0024] A charge-discharging structure is formed, one side of which is at least partially in contact with the isolation structure, and the charge-discharging structure is grounded;

[0025] A channel region and a gate structure are formed; wherein the gate structure extends along a first direction, which is perpendicular to the vertical direction; the channel region surrounds the sidewall of the gate structure perpendicular to the first direction; and the channel region contacts the other side of the charge-out structure.

[0026] In some embodiments, the method of forming the charge-derived structure includes:

[0027] An insulating material is deposited on the substrate;

[0028] The insulating material is etched to form a first trench; the remaining insulating material forms the isolation structure.

[0029] The charge-deriving structure is formed within the first trench.

[0030] In some embodiments, forming the charge-derived structure within the first trench includes:

[0031] Deposit channel material within the first trench;

[0032] The channel material is etched to form a second trench;

[0033] Ion implantation is performed on the channel material located at the bottom of the first trench to form the charge-exporting structure; wherein the charge-exporting structure includes a first sub-region and a second sub-region; the first sub-region and the second sub-region extend along the first direction.

[0034] In some embodiments, a method of forming the channel region and the gate structure includes:

[0035] A gate dielectric layer and the gate structure are formed within the second trench;

[0036] The channel material is deposited on the gate dielectric layer to form the channel region surrounding the gate structure.

[0037] In some embodiments, the gate dielectric layer and the gate structure are formed within the second trench, including:

[0038] Deposit the gate dielectric layer material in the second trench;

[0039] The gate dielectric layer material is etched to form a third trench;

[0040] The gate structure is formed within the third trench;

[0041] The gate dielectric layer material is deposited on the upper surface of the gate structure to form the gate dielectric layer surrounding the gate structure.

[0042] In some embodiments, before forming the second trench, the method further includes:

[0043] The channel material is etched to form a fourth trench and a fifth trench; the fourth trench and the fifth trench are distributed opposite to each other along a second direction; the second direction is perpendicular to the vertical direction;

[0044] Electrode material is deposited in the fourth and fifth trenches to form a portion of the source electrode and a portion of the drain electrode.

[0045] In some embodiments, after forming the channel region surrounding the gate structure, the method further includes:

[0046] On a portion of the upper surface of the channel region, the electrode material is deposited to form a source electrode and a drain electrode that are distributed opposite to each other along the second direction; the source electrode and the drain electrode are respectively electrically connected to the two opposite ends of the channel region along the second direction.

[0047] This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a gate structure, a channel region, an isolation structure, and a charge-discharging structure. The gate structure is located on the substrate and extends along a first direction perpendicular to the vertical direction. The channel region surrounds the sidewalls of the gate structure perpendicular to the first direction. The isolation structure is located between the channel region and the substrate. One side of the charge-discharging structure contacts the channel region, and the other side of the charge-discharging structure at least partially contacts the isolation structure, and the charge-discharging structure is grounded.

[0048] In this embodiment, by providing a grounded charge-discharging structure, with one sidewall of the charge-discharging structure contacting the channel region of the transistor structure and the other sidewall at least partially contacting the isolation structure, a discharge channel can be provided for the charge accumulated in the channel region. Releasing the accumulated charge in the channel region through the charge-discharging structure can improve the floating body effect of the transistor structure, thereby enhancing the electrical performance and reliability of the semiconductor structure. Furthermore, by providing a channel region surrounding the gate structure, the coverage area of ​​the gate structure over the channel region can be increased, thereby enhancing the gate structure's control over the channel region and further improving the electrical performance of the semiconductor structure.

[0049] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of a vertical cross-section of a semiconductor structure related to the technology.

[0052] Figure 2 This is a schematic vertical cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 3 A graph showing the gate-source voltage and drain-source current of a semiconductor structure provided in an embodiment of this disclosure;

[0054] Figure 4 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0055] Figures 5a to 8d This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the manufacturing process. Detailed Implementation

[0056] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0057] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0058] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. All numerical ranges herein include endpoint values.

[0062] The floating body effect (FBE) generally refers to the effect present in transistor structures located above an insulating layer. Because the transistor structure is situated above the insulating layer, it forms a capacitor on the insulating layer. The charge accumulated on this capacitor (i.e., the charge accumulated in the channel region of the transistor structure) can have negative effects, and this accumulated charge cannot be discharged through the substrate, leading to the floating body effect. In traditional semiconductor memory devices, the floating body effect of the built-in transistor structure can cause warpage, parasitic bipolar transistor effects, anomalous subthreshold slope, and device threshold voltage drift, severely impacting the performance of the semiconductor structure.

[0063] Appendix Figure 1This is a vertical cross-sectional diagram of a conductor structure developed for IMEC (Interuniversity Microelectronics Centre). It shows that the transistor structure is located on an isolation structure, but the semiconductor structure lacks a structure to dissipate the charge accumulated in the channel region. This results in a floating body effect in the transistor structure, leading to a large off-state leakage current. Furthermore, as semiconductor dimensions shrink, the channel region narrows, causing an increase in operating resistance and a decrease in electrical performance.

[0064] Based on this, the present disclosure proposes the following technical solutions:

[0065] This disclosure provides a semiconductor structure, with attached... Figure 2 This is a schematic vertical cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure, see attached diagram. Figure 2 The semiconductor structure includes: a substrate 10, a gate structure 31, a channel region 33, an isolation structure 11, and a charge extraction structure 20.

[0066] A gate structure 31 is located on the substrate 10 and extends along a first direction. The first direction is perpendicular to the vertical direction. A channel region 33 surrounds the sidewall of the gate structure 31 perpendicular to the first direction. A partial isolation structure 11 is located between the channel region 33 and the substrate 10. One side of the charge-discharging structure 20 contacts the channel region 33, and the other side of the charge-discharging structure 20 at least partially contacts the isolation structure 11, and the charge-discharging structure 20 is grounded.

[0067] It should be noted that the appendix Figure 2 The second direction shown is the direction perpendicular to the paper. Figure 2 Taking the example where the first and second directions are perpendicular to each other. In some embodiments, the first and second directions may not be perpendicular to each other, but merely intersect. This will not be elaborated further below.

[0068] In this embodiment of the disclosure, see Appendix Figure 2 The substrate 10 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, etc., or it can be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), or it can be a stacked structure, such as Si / SiGe, etc.

[0069] In this embodiment of the disclosure, the material of the gate structure 31 may include titanium nitride or polysilicon. The gate structure 31 may be a single structure or multiple structures stacked together in a vertical direction.

[0070] In some embodiments of this disclosure, the material of the channel region 33 may include indium gallium zinc oxide (IGZO).

[0071] It should be noted that in indium gallium zinc oxide (IGaZO), the conduction band is composed of the ns orbitals of metal ions. Since the s orbitals are spherical, both crystalline and amorphous IGaZO can achieve electron cloud overlap, resulting in good electron transport. Therefore, IGaZO has advantages such as high mobility, a large bandgap, and very low leakage current. Furthermore, because the valence band of IGaZO is composed of the 2p orbitals of oxygen ions, the hole mobility of amorphous IGaZO is much lower than its electron mobility; therefore, IGaZO exhibits the characteristics of an n-type semiconductor. In summary, using IGaZO as the channel region can further improve the electrical performance of the semiconductor structure.

[0072] Appendix Figure 3 The diagram shows the drain-source current (IDS) curves of a semiconductor structure and an IMEC semiconductor structure under different gate-source voltages (VGS) according to embodiments of this disclosure. Curve 1 represents the semiconductor structure provided in this disclosure, and curve 2 represents the IMEC semiconductor structure. See attached diagram. Figure 3 As can be seen, under the same gate-source voltage (VGS) condition in the off-state of the semiconductor structure, the drain-source current (IDS) of the semiconductor structure provided in this embodiment is less than that of the IMEC semiconductor structure. This is because the charge-discharging structure 20 discharges the charge accumulated in the channel region 33 to the ground, improving the floating body effect, thereby reducing the off-state leakage current of the semiconductor structure and improving the electrical performance of the semiconductor structure.

[0073] Understandably, by providing a grounded charge-discharging structure 20, with one sidewall of the charge-discharging structure 20 contacting the channel region 33 of the transistor structure and the other sidewall at least partially contacting the isolation structure 11, a discharge channel can be provided for the charge accumulated in the channel region 33. Releasing the accumulated charge in the channel region 33 through the charge-discharging structure 20 can improve the floating body effect of the transistor structure, thereby enhancing the electrical performance and reliability of the semiconductor structure. Furthermore, by arranging the channel region 33 around the gate structure 31, the coverage area of ​​the gate structure 31 over the channel region 33 can be increased, thereby enhancing the control capability of the gate structure 31 over the channel region 33.

[0074] In some embodiments of this disclosure, see the appendix. Figure 2 The isolation structure 11 includes a first trench H1, and the charge discharge structure 20, the channel region 33, and the gate structure 31 are located within the first trench H1. That is, the cross-section of the isolation structure 11 perpendicular to the first direction is concave. Thus, by setting the concave isolation structure 11, the transistor structure can be located on the insulating layer, thereby reducing the parasitic capacitance of the transistor structure; simultaneously, the isolation structures 11 located on opposite sides of the channel region 33 along the second direction can also isolate adjacent transistor structures.

[0075] In this embodiment of the disclosure, the material of the isolation structure 11 may include silicon oxide.

[0076] It should be noted that the isolation structures 11 located on opposite sides of the channel region 33 along the second direction can also adopt an ONO structure (silicon oxide-silicon nitride-silicon oxide), and no specific limitation is made here.

[0077] In some embodiments of this disclosure, see the appendix. Figure 2 The charge extraction structure 20 includes a first sub-region 21 and a second sub-region 22, which extend along a first direction. The first sub-region 21 and the second sub-region 22 are located on opposite sides of the charge extraction structure 20 along the vertical direction. A plurality of second sub-regions 22 are arranged at intervals along a second direction, which is perpendicular to the vertical direction.

[0078] In this embodiment, the second sub-region 22 is located on the first sub-region 21. Thus, the second sub-regions 22 are spaced apart and contact the channel region 33, increasing the contact area between the charge-exporting structure 20 and the channel region 33, thereby improving the charge-exporting effect of the charge-exporting structure 20 and further enhancing the buoyancy effect.

[0079] In some embodiments of this disclosure, see the appendix. Figure 2 The charge-derived structure 20 has the same doping type as the channel region 33, but the doping concentration of the channel region 33 is lower than that of the charge-derived structure 20. For example, the charge-derived structure 20 is a heavily doped region.

[0080] It should be noted that the doping concentrations of the first sub-region 21 and the second sub-region 22 can be the same or different, but both can be greater than the doping concentration of the channel region 33. No specific limitation is made here.

[0081] In this embodiment of the disclosure, see Appendix Figure 2 The charge-derived structure 20 is made of the same material as the channel region 33.

[0082] Understandably, since the charge extraction structure 20 and the channel region 33 are made of the same material, by setting the dopant ion type of the channel region 33 to be the same as that of the charge extraction structure 20, the charge extraction structure 20 can be considered an extension of the channel region 33. Thus, the charge moving towards the channel region 33 will also move towards the charge extraction structure 20, allowing the charge extraction structure 20 to bear a portion of the moving charge and improving the accumulation of charge in the channel region 33. Therefore, setting the dopant ion type of the charge extraction structure 20 to be the same as that of the channel region 33 makes it easier for charge to be transferred to the charge extraction structure 20 and then extracted to the ground, which helps to further alleviate the floating body effect. Simultaneously, since the doping concentration of the channel region 33 is lower than that of the second sub-region 22, the second sub-region 22 is arranged alternately on the first sub-region 21, which allows for alternating high and low doping concentration regions in the second direction, further alleviating charge accumulation in the channel region 33 and thus better mitigating the floating body effect. Therefore, the embodiments of this disclosure can improve the buoyancy effect of semiconductor structures, thereby improving the electrical performance and reliability of semiconductor structures.

[0083] In this embodiment of the disclosure, the semiconductor structure further includes: a grounding post ( Figure 1 (Not shown), the grounding post is electrically connected to the charge-discharging structure 20 extending along the first direction. The grounding post is used for coupling with ground. In this way, problems such as the charge-discharging structure 20 failing to ground properly due to the small size of the semiconductor structure and excessive integration can be prevented.

[0084] In some embodiments of this disclosure, see the appendix. Figure 2 The semiconductor structure also includes a gate dielectric layer 32. The gate dielectric layer 32 is located between the gate structure 31 and the channel region 33, and surrounds the sidewalls of the gate structure 31.

[0085] In this embodiment of the disclosure, see Appendix Figure 2 Along the second direction, the length of the gate dielectric layer 32 is greater than the length of the gate structure 31, and the length of the gate dielectric layer 32 is less than the length of the channel region 33, so that the gate structure 31 can be surrounded and covered by the gate dielectric layer 32, and the gate dielectric layer 32 can be surrounded and covered by the channel region 33. For example, along the second direction, the length D1 of the gate structure 31 is 40 nm, the length D2 of the gate dielectric layer 32 is 60 nm, and the length D3 of the channel region 33 is 100 nm.

[0086] In this embodiment of the disclosure, see Appendix Figure 2The material of the gate dielectric layer 32 may include silicon oxide, silicon nitride, or other high-k dielectric materials. Here, high-k dielectric materials generally refer to materials with a dielectric constant higher than 3.9, such as alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), etc.

[0087] In this embodiment of the disclosure, see Appendix Figure 3 Curve 1 represents the semiconductor structure provided in this embodiment, and curve 2 represents the IMEC semiconductor structure. It can be seen that, under the same gate-source voltage (VGS) condition, the drain-source current (IDS) of the semiconductor structure provided in this embodiment is greater than that of the IMEC semiconductor structure. This is because the channel region 33 surrounds the gate structure 31, forming a transistor structure with a dual-channel region 33, which reduces the operating resistance of the semiconductor structure and thus improves its electrical performance.

[0088] Understandably, by setting the gate dielectric layer 32 to surround the sidewalls of the gate structure 31, the channel region 33 can also surround the sidewalls of the gate structure 31. This effectively increases the coverage area of ​​the channel region 33 by the gate structure 31, improves the control capability of the gate structure 31 over the channel region 33, and maintains a large channel length within a small device size. This can mitigate the effects of the short-channel effect and improve the electrical performance of the semiconductor structure. Furthermore, the channel region 33 surrounding the gate structure 31 can also form a dual-channel transistor structure, thereby reducing the operating resistance of the semiconductor structure and further improving its performance.

[0089] In some embodiments of this disclosure, see the appendix. Figure 2 The semiconductor structure also includes a source electrode 41 and a drain electrode 42 that are distributed opposite to each other along the second direction. The source electrode 41 and the drain electrode 42 are electrically connected to the two opposite ends of the channel region 33 along the second direction, respectively.

[0090] In this embodiment, the source electrode 41 and the drain electrode 42 are also located within the first trench H1 and are isolated by the insulating structure 43. The materials of the source electrode 41 and the drain electrode 42 may include conductive materials such as tungsten (W) or titanium nitride (TiN). The material of the insulating structure 43 may be the same as or different from the material of the isolation structure 11; for example, the material of the insulating structure 43 may include silicon oxide.

[0091] In some embodiments of this disclosure, the source electrode 41 and the drain electrode 42 have L-shaped cross-sections perpendicular to the first direction. The source electrode 41 and the drain electrode 42 respectively cover a portion of the upper surface of the channel region 33, and the source electrode 41 and the drain electrode 42 also respectively cover two opposite sides of the channel region 33 along the second direction.

[0092] It should be noted that the source electrode 41 and the drain electrode 42 may also only cover the side of the channel region 33, and no specific limitation is made here.

[0093] It is understandable that by setting the L-shaped source electrode 41 and drain electrode 42, the source electrode 41 and drain electrode 42 not only cover the sides of the channel region 33, but also cover part of the upper surface of the channel region 33. On the one hand, this effectively increases the contact area between the source electrode 41 and drain electrode 42 and the channel region 33, thereby improving the driving capability and response speed of the transistor structure. It is understandable that the larger the contact area between the source electrode 41 and drain electrode 42 and the channel region 33, the smaller the contact resistance. The smaller the total resistance of the semiconductor structure, the larger the current will be under the same voltage, thereby effectively improving the driving capability and response speed of the semiconductor structure. On the other hand, it can also improve the capacitive coupling between the source / drain electrode 42 and the gate structure 31.

[0094] It should be noted that the semiconductor structure provided in this disclosure can be applied to a 1T1C (one transistor, one capacitor) architecture. In the 1T1C architecture, the gate structure 31 is stacked vertically, and the source electrode 41 and drain electrode 42 are electrically connected to the bit line structure and the capacitor, respectively. The semiconductor structure provided in this disclosure can also be applied to a 2T0C (two transistors, no capacitor) architecture. Since 2T0C-based memories do not use capacitors as data storage devices, the device size can be greatly reduced, the integration density of the memory can be improved, and the yield of the memory can be further improved. No specific limitations are made here.

[0095] This disclosure also provides a method for manufacturing a semiconductor structure, with appended... Figure 4 A schematic flowchart of a semiconductor structure manufacturing method provided in this disclosure is attached. Figure 4 As shown, the method includes the following steps:

[0096] Step S101: Provide substrate 10.

[0097] Step S102: Form an isolation structure 11 on the substrate 10.

[0098] Step S103: Form a charge-discharging structure 20, one side of the charge-discharging structure 20 is at least partially in contact with the isolation structure 11, and the charge-discharging structure 20 is grounded.

[0099] Step S104: Forming a channel region 33 and a gate structure 31; wherein, the gate structure 31 extends along a first direction, which is perpendicular to the vertical direction; the channel region 33 surrounds the sidewall of the gate structure 31 perpendicular to the first direction; the channel region 33 contacts the other side of the charge discharge structure 20.

[0100] Appendix Figure 5a To be continued Figure 8d This is a schematic diagram illustrating the semiconductor structure provided in the embodiments of this disclosure during the manufacturing process. The following is in conjunction with the accompanying drawings. Figure 5a To be continued Figure 8d The method for preparing the semiconductor structure provided in the embodiments of this disclosure will be further described.

[0101] First, see appendix Figure 5a Step S101: Provide substrate 10.

[0102] In this embodiment of the disclosure, the substrate 10 may be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, etc., or it may be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), or it may be a stacked structure, such as Si / SiGe, etc.

[0103] Next, see Appendix Figure 5b and attached Figure 5c Step S102: Form an isolation structure 11 on the substrate 10.

[0104] In some embodiments of this disclosure, the specific steps of forming the isolation structure 11 on the substrate 10 include: depositing an insulating material 51 on the substrate 10; etching the insulating material 51 to form a first trench H1; and forming the remaining insulating material 51 into the isolation structure 11.

[0105] In this embodiment of the disclosure, one or more of the following processes may be used to deposit the insulating material 51: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma-enhanced chemical vapor deposition (PECVD). The insulating material 51 may be etched using a wet etching process or a dry etching process. The insulating material 51 may include silicon oxide.

[0106] It is understandable that by forming an isolation structure 11 on the substrate 10, the subsequently formed transistor structure can be located on the insulating layer, thereby reducing the parasitic capacitance of the transistor structure.

[0107] Next, step S103 is performed: a charge-deriving structure 20 is formed, one side of the charge-deriving structure 20 is at least partially in contact with the isolation structure 11, and the charge-deriving structure 20 is grounded.

[0108] In some embodiments of this disclosure, in conjunction with the appendix Figure 6a and attached Figure 6dThe specific steps for forming the charge-discharging structure 20 include: First, depositing a channel material 52 within a first trench H1. Then, etching the channel material 52 to form a second trench H2; and in the vertical direction, the depth of the second trench H2 is less than the depth of the first trench H1. Finally, performing ion implantation (IMP) on the channel material 52 located at the bottom of the first trench H1 to form the charge-discharging structure 20. The charge-discharging structure 20 includes a first sub-region 21 and a second sub-region 22; the first sub-region 21 and the second sub-region 22 extend along a first direction.

[0109] It should be noted that the charge-exporting structure 20 can also be formed by ion implantation of the channel material 52 located at the bottom of the first trench H1 before forming the second trench H2; no specific limitation is made here.

[0110] In this embodiment of the disclosure, in conjunction with the appendix Figure 6a and attached Figure 6d The channel material 52 can be deposited using processes such as atomic layer deposition (ALD) or sputtering. The channel material 52 can be etched using either dry or wet etching processes. The charge-discharge structure 20 can be formed by controlling parameters such as the type of dopant ions, the ion implantation dose, and the ion implantation energy during ion implantation. The ion implantation direction can be vertical or at a certain angle.

[0111] In this embodiment of the disclosure, after ion implantation, an annealing process is required to repair the lattice damage caused by ion implantation.

[0112] It is understandable that by forming a grounded charge-discharging structure 20, a charge-discharging channel can be provided for the subsequently formed channel region 33 to release the accumulated charge in the channel region 33, which can reduce the impact of the floating body effect on the transistor structure, stabilize the transistor structure performance, and thus effectively improve the electrical performance and reliability of the semiconductor structure.

[0113] In this embodiment of the disclosure, see Appendix Figure 6d The charge-derived structure 20 has the same doping type as the subsequently formed channel region 33, but the doping concentration of the charge-derived structure 20 is greater than that of the channel region 33. For example, the charge-derived structure 20 is a heavily doped region.

[0114] It should be noted that the deposited channel material 52 is used not only to form the charge-exit structure 20 but also to form the subsequent channel region 33. Therefore, the doping type of the subsequently formed channel region 33 is set to be the same as that of the charge-exit structure 20, so that the charge-exit structure 20 can be regarded as an extension of the channel region 33. In this way, the charge moving towards the channel region 33 will also move into the charge-exit structure 20, allowing the charge-exit structure 20 to bear a portion of the moving charge and improving the phenomenon of charge accumulation in the channel region 33. Thus, setting the dopant ion type of the charge-exit structure 20 to be the same as that of the subsequently formed channel region 33 makes it easier for the charge to be transported to the charge-exit structure 20 and thus exported to the ground, which is beneficial for further suppressing the floating body effect.

[0115] In this embodiment of the disclosure, see Appendix Figure 6d The first sub-region 21 and the second sub-region 22 are located on opposite sides of the charge output structure 20 along the vertical direction, and the second sub-region 22 is located on the first sub-region 21; along the second direction, a plurality of second sub-regions 22 are arranged at intervals; the second direction is perpendicular to the vertical direction.

[0116] Understandably, the spaced arrangement of the second sub-regions 22 in contact with the channel region 33 increases the contact area between the charge extraction structure 20 and the channel region 33, thereby improving the charge extraction effect of the charge extraction structure 20 and further mitigating the floating body effect. Simultaneously, since the doping concentration of the channel region 33 is lower than that of the second sub-regions 22, the spaced arrangement of the second sub-regions 22 on the first sub-region 21 allows for alternating high and low doping concentration regions in the second direction, further alleviating charge accumulation in the channel region 33 and thus better mitigating the floating body effect.

[0117] Finally, see appendix. Figure 7a To be continued Figure 7g Step S104 is executed: a channel region 33 and a gate structure 31 are formed; wherein the gate structure 31 extends along a first direction, which is perpendicular to the vertical direction; the channel region 33 surrounds the sidewall of the gate structure 31 perpendicular to the first direction; the channel region 33 is in contact with the other side of the charge discharge structure 20.

[0118] In some embodiments of this disclosure, see the appendix. Figure 7a To be continued Figure 7g The method for forming the channel region 33 and the gate structure 31 includes: first, forming a gate dielectric layer 32 and a gate structure 31 within a second trench H2; then, depositing a channel material 52 on the gate dielectric layer 32 to form a channel region 33 surrounding the gate structure 31 (as shown in the attached figure). Figure 7f and attached Figure 7g (As shown).

[0119] In some embodiments of this disclosure, see the appendix. Figure 7a To be continued Figure 7e The gate dielectric layer 32 and gate structure 31 are formed within the second trench H2. Specific steps include: depositing a gate dielectric layer material 53 within the second trench H2; etching the gate dielectric layer material 53 to form a third trench H3; the depth of the third trench H3 being less than the depth of the second trench H2 in the vertical direction; depositing a gate material 54 within the third trench H3; and etching a portion of the gate material 54 to form the gate structure 31; and depositing the gate dielectric layer material 53 on the upper surface of the gate structure 31 to form a gate dielectric layer 32 surrounding the gate structure 31.

[0120] It should be noted that the steps of forming the gate structure 31 and the gate dielectric layer 32 and the channel region 33 surrounding the gate structure 31 can also be as follows: first, a channel region 33 with a first gap is formed. Then, a gate dielectric layer 32 covering the surface of the channel region 33 is formed in the first gap, and finally, a gate structure 31 covering the surface of the gate dielectric layer 32 is formed in the first gap.

[0121] In this embodiment of the disclosure, in conjunction with the appendix Figure 7a Appendix Figure 7c and attached Figure 7f The gate dielectric material 53, gate material 54 and channel material 52 can be deposited using one or more processes such as atomic layer deposition (ALD) or sputtering, and the gate dielectric material 53, gate material 54 and channel material 52 can be etched using dry etching or wet etching processes.

[0122] In this embodiment, the gate material 54 may include materials such as titanium nitride and polysilicon, and the gate dielectric layer material 53 may include silicon oxide, silicon nitride, or other high-k dielectric materials. Specifically, high-k dielectric materials generally refer to materials with a dielectric constant higher than 3.9, such as alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), and strontium titanate (SrTiO3).

[0123] In this embodiment of the disclosure, see Appendix Figure 7f The channel material 52 can be an oxide semiconductor material. Oxide semiconductor materials can be converted between conductors and insulators. Using an oxide semiconductor material to form the channel region 33 eliminates the need for complex doping processes, thus simplifying the semiconductor structure formation process. The oxide semiconductor material can be any one or a combination of two or more of In₂O₃ (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), and ZnON (zinc oxynitride). In this embodiment, the channel region 33 is described using IGZO (indium gallium zinc oxide) as an example.

[0124] In this embodiment, the channel material 52 is indium gallium zinc oxide (IGZO). The device constructed using the IGZO-formed channel region 33 can be a junctionless transistor, meaning the dopant ions in the source, channel, and drain regions are of the same type. Furthermore, the dopant ions in the source, channel, and drain regions can be identical. Here, "junctionless" refers to the absence of a PN junction; the transistor structure does not have a PN junction. This eliminates the need for additional doping, thus avoiding the difficulty in controlling the doping process in the source and drain regions. Especially as transistor sizes shrink further, controlling the doping concentration becomes even more challenging if additional doping is applied to the source and drain regions. It is understood that the additional doping here refers to doping performed to differentiate the dopant ion types in the source and drain regions from those in the channel region.

[0125] Understandably, by setting one sidewall of the charge-discharging structure 20 to contact the channel region 33 of the transistor structure, a discharge channel is provided for the accumulated charge, releasing the accumulated charge in the channel region 33. This reduces the impact of the floating body effect on the transistor structure, stabilizes the transistor structure performance, and effectively improves the electrical performance and reliability of the semiconductor structure. Furthermore, the channel region 33 surrounding the gate structure 31 effectively increases the coverage area of ​​the gate structure 31 over the channel region 33, improving the control capability of the gate structure 31 over the channel region 33. This allows for maintaining a larger channel length within a smaller device size, mitigating the effects of the short-channel effect and improving the electrical performance of the semiconductor structure. Additionally, the channel region 33 surrounding the gate structure 31 can also form a dual-channel transistor structure, thereby reducing the operating resistance of the semiconductor structure and further improving its performance.

[0126] In this embodiment of the disclosure, in conjunction with the appendix Figure 6b Appendix Figure 6c Appendix Figure 8a To be continued Figure 8c The method further includes: forming a source electrode 41 and a drain electrode 42, wherein the source electrode 41 and the drain electrode 42 are electrically connected to opposite ends of the channel region 33 along the second direction.

[0127] In some embodiments of this disclosure, the specific steps for forming the source electrode 41 and the drain electrode 42 include:

[0128] First, see appendix Figure 6b and attached Figure 6cBefore forming the second trench H2, the channel material 52 is etched to form the fourth trench H4 and the fifth trench H5; the fourth trench H4 and the fifth trench H5 are distributed relative to each other along the second direction; the bottom of the fourth trench H4 and the fifth trench H5 are flush with the bottom of the first trench H1. Electrode material 55 is deposited in the fourth trench H4 and the fifth trench H5 to form a portion of the source electrode 41 and a portion of the drain electrode 42.

[0129] Next, see Appendix Figure 8a To be continued Figure 8c After forming the channel region 33 surrounding the gate structure 31, electrode material 55 is deposited on a portion of the source electrode 41, a portion of the drain electrode 42, and the upper surface of the channel region 33; the electrode material 55 on a portion of the upper surface of the channel region 33 is etched to form a source electrode 41 and a drain electrode 42 that are relatively distributed along the second direction; the source electrode 41 and the drain electrode 42 are respectively electrically connected to the two ends of the channel region 33 that are relatively opposite to each other along the second direction.

[0130] It should be noted that the source electrode 41 and the drain electrode 42 can also be formed after the gate dielectric layer 32 is formed by depositing channel material 52 on the gate dielectric layer 32, then etching part of the channel material 52 to form the channel region 33 and the fourth trench H4 and the fifth trench H5 located on both sides of the channel region 33 in one step, and finally depositing electrode material 55 in the fourth trench H4 and the fifth trench H5 and part of the upper surface of the channel region 33.

[0131] In this embodiment of the disclosure, see Appendix Figure 8a The electrode material 55 can be deposited using a sputtering process or etched using a wet etching process.

[0132] In this embodiment of the disclosure, see Appendix Figure 8c The source electrode 41 and the drain electrode 42 respectively cover a portion of the upper surface of the channel region 33, and the source electrode 41 and the drain electrode 42 also respectively cover two opposite sides of the channel region 33 along the second direction. The upper surface of the insulating structure 43 is flush with the upper surfaces of the source electrode 41 and the drain electrode 42.

[0133] It is understandable that the formed source electrode 41 and drain electrode 42 not only cover the side of the channel region 33, but also cover part of the upper surface of the channel region 33, which can increase the contact area between the source electrode 41 and drain electrode 42 and the channel region 33, thereby improving the driving capability and response speed of the transistor structure.

[0134] In this embodiment of the disclosure, see Appendix Figure 8d The method further includes: after forming the source electrode 41 and the drain electrode 42, depositing an insulating material 51 on a portion of the upper surface of the channel region 33 to form an insulating structure 43.

[0135] In summary, in this embodiment, by providing a grounded charge-discharging structure 20, with one sidewall of the charge-discharging structure 20 contacting the channel region 33 of the transistor structure and the other sidewall at least partially contacting the isolation structure 11, a discharge channel can be provided for the charge accumulated in the channel region 33. Releasing the accumulated charge in the channel region 33 through the charge-discharging structure 20 can improve the floating body effect of the transistor structure, thereby improving the electrical performance and reliability of the semiconductor structure. Furthermore, by arranging the channel region 33 around the gate structure 31, the coverage area of ​​the gate structure 31 over the channel region 33 can be increased, thereby enhancing the control capability of the gate structure 31 over the channel region 33 and further improving the electrical performance of the semiconductor structure.

[0136] It should be noted that the semiconductor structure and manufacturing method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and are not limited thereto. The embodiments of the semiconductor structure and the embodiments of the semiconductor structure manufacturing method provided in this disclosure belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0137] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A gate structure is located on the substrate and extends along a first direction; The first direction is perpendicular to the vertical direction; The channel region surrounds the sidewall of the gate structure perpendicular to the first direction; An isolation structure located on and in contact with the substrate, wherein a portion of the isolation structure is located between the channel region and the substrate; A charge-discharging structure is provided, wherein one side of the charge-discharging structure contacts the channel region, the charge-discharging structure is located at the bottom of the channel region, and the material of the charge-discharging structure is the same as the material of the channel region; wherein the other side of the charge-discharging structure at least partially contacts the isolation structure. The charge extraction structure is grounded.

2. The structure according to claim 1, characterized in that, The charge extraction structure includes a first sub-region and a second sub-region; the first sub-region and the second sub-region extend along the first direction; The first sub-region and the second sub-region are located on opposite sides of the charge-out structure along the vertical direction, respectively. Along a second direction, multiple second sub-regions are arranged at intervals; the second direction is perpendicular to the vertical direction.

3. The structure according to claim 1, characterized in that, The doping type of the channel region is the same as that of the charge-derived structure, and the doping concentration of the channel region is less than that of the charge-derived structure.

4. The structure according to claim 1, characterized in that, The semiconductor structure further includes: a source electrode and a drain electrode that are distributed opposite to each other along a second direction; the second direction is perpendicular to the vertical direction; The source electrode and the drain electrode are respectively electrically connected to the two opposite ends of the channel region along the second direction.

5. The structure according to claim 4, characterized in that, The cross-sections of the source electrode and the drain electrode perpendicular to the first direction are L-shaped; The source electrode and the drain electrode each cover a portion of the upper surface of the channel region, and the source electrode and the drain electrode also cover two opposite sides of the channel region along the second direction.

6. The structure according to claim 1, characterized in that, The material of the channel region includes indium gallium zinc oxide.

7. The structure according to claim 1, characterized in that, The isolation structure includes a first trench, and the charge discharge structure, the channel region, and the gate structure are located within the first trench.

8. The structure according to claim 1, characterized in that, The semiconductor structure further includes: a gate dielectric layer; The gate dielectric layer is located between the gate structure and the channel region, and surrounds the sidewall of the gate structure.

9. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; An isolation structure is formed on the substrate; A charge-discharging structure is formed, one side of which is at least partially in contact with the isolation structure, and the charge-discharging structure is grounded; The method for forming the charge-discharging structure includes: depositing an insulating material on the substrate; etching the insulating material to form a first trench; forming the remaining insulating material as the isolation structure; depositing a channel material in the first trench; etching the channel material to form a second trench; and ion implanting the channel material located at the bottom of the first trench to form the charge-discharging structure. A channel region and a gate structure are formed; wherein the gate structure extends along a first direction, which is perpendicular to the vertical direction; the channel region surrounds the sidewall of the gate structure perpendicular to the first direction; and the channel region contacts the other side of the charge-out structure.

10. The method according to claim 9, characterized in that, The charge-derived structure includes a first sub-region and a second sub-region; the first sub-region and the second sub-region extend along the first direction.

11. The method according to claim 9, characterized in that, The method of forming the channel region and the gate structure includes: A gate dielectric layer and the gate structure are formed within the second trench; The channel material is deposited on the gate dielectric layer to form the channel region surrounding the gate structure.

12. The method according to claim 11, characterized in that, Forming the gate dielectric layer and the gate structure within the second trench includes: Deposit the gate dielectric layer material in the second trench; The gate dielectric layer material is etched to form a third trench; The gate structure is formed within the third trench; The gate dielectric layer material is deposited on the upper surface of the gate structure to form the gate dielectric layer surrounding the gate structure.

13. The method according to claim 11, characterized in that, Before forming the second trench, the method further includes: The channel material is etched to form a fourth trench and a fifth trench; the fourth trench and the fifth trench are distributed opposite to each other along a second direction; the second direction is perpendicular to the vertical direction; Electrode material is deposited in the fourth and fifth trenches to form a portion of the source electrode and a portion of the drain electrode.

14. The method according to claim 13, characterized in that, After forming the channel region surrounding the gate structure, the method further includes: On a portion of the upper surface of the channel region, the electrode material is deposited to form a source electrode and a drain electrode that are distributed opposite to each other along the second direction; the source electrode and the drain electrode are respectively electrically connected to the two opposite ends of the channel region along the second direction.

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