Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same. The method comprises: forming a stacked structure on a semiconductor substrate, comprising a plurality of linear semiconductor patterns extending in a first direction and arranged in an array in a second and vertical directions, the stacked structure sequentially comprising a transistor region and a capacitor region along the first direction; removing a sacrificial layer in the capacitor region to form a cavity; forming a first spacer layer extending in the first direction, at least partially suspended, within the cavity; forming a first electrode layer on a horizontal surface of the first spacer layer, on a vertical inner wall of the cavity, and on a horizontal surface of the linear semiconductor patterns between the cavities; forming a dielectric layer on a surface of the first electrode layer and on a vertical surface of the first spacer layer; and forming a second electrode layer on a surface of the dielectric layer, the second electrode layer filling the remaining cavity. This method improves the storage density of DRAM.

Description

Technical Field

[0001] The present disclosure relates to the field of memory, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. The voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0003] To improve integration, existing 3D DRAM manufacturing processes typically use a multi-layer stacked lateral transistor structure. However, the capacitors in existing DRAMs occupy a large area, leaving DRAM storage density to be improved. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, comprising:

[0005] providing a semiconductor substrate;

[0006] forming a stacked structure on the semiconductor substrate, the stacked structure comprising a plurality of linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction, a sacrificial layer being filled between adjacent linear semiconductor patterns in the vertical direction, and an insulating layer being filled between adjacent linear semiconductor patterns in the second direction, the stacked structure sequentially comprising a transistor region and a capacitor region along the first direction, the vertical direction being perpendicular to a surface of the semiconductor substrate, and the first and second directions being parallel to the surface of the semiconductor substrate;

[0007] removing the sacrificial layer in the capacitor region to form a cavity between adjacent linear semiconductor patterns;

[0008] forming a first separation layer in the cavity that is at least partially suspended and extends along a first direction;

[0009] forming a first electrode layer on the horizontal surface of the first separation layer, on the vertical inner walls of the cavities, and on the vertical and horizontal surfaces of the linear semiconductor patterns between the cavities;

[0010] forming a dielectric layer on a surface of the first electrode layer and a vertical surface of the first separator layer;

[0011] A second electrode layer is formed on the surface of the dielectric layer, and the second electrode layer fills the remaining cavity.

[0012] In some embodiments, the stacked structure forming process includes: forming an initial stacked structure on the semiconductor substrate, the initial stacked structure including an initial sacrificial layer and an initial semiconductor layer alternately stacked along a vertical direction, the initial stacked structure including a transistor region and a capacitor region in sequence along a first direction;

[0013] In some embodiments, a plurality of trenches extending along a first direction and penetrating the initial stacked structure along a vertical direction are formed in the initial stacked structure, and the initial semiconductor layer is divided into a plurality of linear semiconductor patterns by the plurality of trenches;

[0014] The trench is filled with an insulating layer.

[0015] In some embodiments, the forming process of the first spacer layer includes: forming a first sidewall material layer on the vertical sidewall surface and the horizontal sidewall surface of the cavity;

[0016] forming a first separation layer filling the remaining cavity on the surface of the first sidewall material layer;

[0017] A portion of the first sidewall material layer is removed along a first direction to expose a portion of the horizontal sidewall surface of the cavity and to allow a portion of the first separation layer to be suspended.

[0018] In some embodiments, the method further includes: removing a portion of the length of the linear semiconductor pattern along the first direction, so that the vertical surface of the first separation layer protrudes from the vertical surface of the remaining linear semiconductor pattern along the first direction; the length of the linear semiconductor pattern removed is less than the length of the first sidewall material layer removed.

[0019] In some embodiments, the forming process of the first electrode layer includes: forming a first electrode material layer on the vertical surface and the horizontal surface of the first separation layer, on the vertical inner wall of the cavity, and on the vertical surface and the horizontal surface of the linear semiconductor pattern between the cavities;

[0020] forming a first filling material layer filling the cavities on the surface of the first electrode material layer;

[0021] removing a portion of the first filling material layer to expose a surface of the first electrode material layer on a vertical surface of the first separator layer;

[0022] removing the exposed first electrode material layer to disconnect the first electrode material layer;

[0023] The first filling material layer is removed.

[0024] In some embodiments, after forming the first separation layer, the method further includes: forming a suspended second separation layer extending along the first direction between the first separation layer and the linear semiconductor pattern; and the formed first electrode layer also covers the vertical surface and horizontal surface of the second separation layer.

[0025] In some embodiments, the forming process of the second spacer layer includes: forming a second sidewall material layer on vertical sidewall surfaces and horizontal sidewall surfaces of the cavity remaining between the first spacer layer and the linear semiconductor pattern;

[0026] forming a second separation layer filling the remaining cavity on the surface of the second sidewall material layer;

[0027] Removing a portion of the linear semiconductor pattern and the second separation layer along a first direction so that a vertical surface of the first separation layer protrudes from a remaining vertical surface of the linear semiconductor pattern and the remaining vertical surface of the second separation layer along the first direction;

[0028] A portion of the second sidewall material layer is removed along a first direction to expose a portion of the horizontal sidewall surface of the cavity, so that the first separation layer and the second separation layer are at least partially suspended.

[0029] Some embodiments of the present disclosure further provide a semiconductor structure, including:

[0030] semiconductor substrates;

[0031] a stacked structure located on the semiconductor substrate, the stacked structure comprising a plurality of linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction, the stacked structure sequentially comprising a transistor region and a capacitor region along the first direction, a first space being defined between adjacent linear semiconductor patterns along the vertical direction in the capacitor region, and an insulating layer being filled between adjacent linear semiconductor patterns along the second direction, the vertical direction being perpendicular to a surface of the semiconductor substrate, and the first and second directions being parallel to the surface of the semiconductor substrate;

[0032] a first separation layer located in the first space and extending along a first direction;

[0033] a first electrode layer located on a horizontal sidewall surface of the first separation layer and extending to a surface of the linear semiconductor pattern;

[0034] a dielectric layer located on a surface of the first electrode layer and on a vertical surface of the first separator layer;

[0035] A second electrode layer is located on a surface of the dielectric layer.

[0036] In some embodiments, a vertical surface of the first separation layer protrudes from a vertical surface of the linear semiconductor pattern along a first direction.

[0037] In some embodiments, the invention further comprises: a second separation layer extending along the first direction between the first separation layer and the linear semiconductor pattern, wherein a vertical surface of the first separation layer protrudes from a vertical surface of the second separation layer along the first direction; and the first electrode layer further covers the vertical surface and horizontal surface of the second separation layer.

[0038] The method for forming the semiconductor structure in the aforementioned embodiment of the present disclosure forms a stacked structure on a semiconductor substrate, the stacked structure including a plurality of linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction, a sacrificial layer being filled between adjacent linear semiconductor patterns along the vertical direction, and an insulating layer being filled between adjacent linear semiconductor patterns along the second direction, the stacked structure sequentially including a transistor region and a capacitor region along the first direction; removing the sacrificial layer in the capacitor region to form a cavity between adjacent linear semiconductor patterns; forming a first separation layer extending along the first direction that is at least partially suspended in the cavity; forming a dielectric layer on the horizontal surface of the first separation layer, on the vertical inner wall of the cavity, and on the vertical and horizontal surfaces of the linear semiconductor patterns between the cavities; forming a dielectric layer on the surface of the first electrode layer and on the vertical surface of the first separation layer; and forming a second electrode layer on the surface of the dielectric layer, the second electrode layer filling the remaining cavity. The present disclosure forms a first spacer layer extending in a first direction that is at least partially suspended within a cavity in a capacitor region. The suspended first spacer layer cooperates with a linear semiconductor pattern to form a first electrode layer on the horizontal surface of the first spacer layer, on the vertical inner wall of the cavity, and on the horizontal surface of the linear semiconductor pattern between the cavities. This increases the surface area of ​​the first electrode layer, and accordingly, increases the surface area of ​​the dielectric layer formed on the first electrode layer and the surface area of ​​the second electrode layer formed on the dielectric layer. Consequently, with the same storage capacitance, the area occupied by the vertical projection of the formed capacitor on the semiconductor substrate surface is reduced, thereby improving the storage density of the DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figures 1-19 A schematic structural diagram of a semiconductor structure forming process in some embodiments of the present disclosure;

[0040] Figure 20-25 Schematic diagram of the formation process of the semiconductor structure in some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The following detailed description of the specific embodiments of the present disclosure is provided with reference to the accompanying figures. When describing the embodiments of the present disclosure, the schematic diagrams may be partially enlarged to a different scale for ease of explanation. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of the present disclosure. Furthermore, in actual production, the three-dimensional dimensions of length, width, and depth should be included.

[0042] Some embodiments of the present disclosure first provide a method for forming a semiconductor structure, and the forming method is described in detail below with reference to the figures.

[0043] refer to Figure 5 and Figure 6 ,in Figure 6 The four figures in the upper left, upper right, lower left and lower right are Figure 5 A semiconductor substrate 200 is provided, including a schematic diagram of the cross-sectional structure along the cutting line AA1, a schematic diagram of the cross-sectional structure along the cutting line BB1, a schematic diagram of the cross-sectional structure along the cutting line CC1, and a schematic diagram of the cross-sectional structure along the cutting line DD1; a stacking structure 203 is formed on the semiconductor substrate 200, and the stacking structure 203 includes a plurality of linear semiconductor patterns 202 extending along a first direction and arranged in an array in a second direction and a vertical direction, a sacrificial layer 201 is filled between adjacent linear semiconductor patterns 202 along the vertical direction, and an insulating layer 242 is filled between adjacent linear semiconductor patterns 202 along the second direction, and the stacking structure 203 includes a transistor region 21 and a capacitor region 22 in sequence along the first direction, the vertical direction is perpendicular to the surface of the semiconductor substrate 200, and the first direction and the second direction are parallel to the surface of the semiconductor substrate 200.

[0044] The material of the semiconductor substrate 200 can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon (Si).

[0045] In some embodiments, the stacked structure 203 includes a transistor region 21 along a first direction and a capacitor region 22 located to one side of the transistor region 21. The transistor region 21 is used to form a lateral transistor, and the capacitor region 22 is used to form a capacitor. In some embodiments, the transistor region 21 may further include a first active region, a channel region, and a second active region sequentially arranged along the first direction. In some embodiments, the linear semiconductor pattern 202 in the first active region is used to form one of the drain region or the source region of the lateral transistor, the linear semiconductor pattern 202 in the channel region is used to form the channel region of the lateral transistor, and the linear semiconductor pattern 202 in the second active region is used to form the other of the drain region or the source region of the lateral transistor.

[0046] The sacrificial layer 201 is made of a different material than the linear semiconductor pattern 202 and the insulating layer 241. In some embodiments, the sacrificial layer 201 is made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, polycrystalline silicon, or silicon germanium. The linear semiconductor pattern 202 is made of single crystal silicon, polycrystalline silicon, silicon germanium, or a metal oxide semiconductor, wherein the metal oxide semiconductor is made of zinc tin oxide (ZnxSnyO, commonly known as "ZTO"), indium zinc oxide (InxZnyO, commonly known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly known as "IGZO"), indium gallium silicon oxide (InxGaySizO, commonly known as "IGSO"), or indium tungsten oxide (InxWyO, commonly known as "IWO"). The insulating layer 241 is made of one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride. In this embodiment, the material of the sacrificial layer 201 is silicon germanium, the material of the linear semiconductor pattern 202 is single crystal silicon, and the material of the insulating layer 241 is silicon nitride.

[0047] In some embodiments, the first direction and the second direction are perpendicular to each other and parallel to the surface of the semiconductor substrate 200 .

[0048] In some embodiments, the following Figures 1-6 The formation process of the stacked structure 203 is described in detail.

[0049] First reference Figure 1-Figure 2 ,in Figure 2 The four figures in the upper left, upper right, lower left and lower right are Figure 1 The cross-sectional structure diagram along the cutting line AA1, the cross-sectional structure diagram along the cutting line BB1, the cross-sectional structure diagram along the cutting line CC1 and the cross-sectional structure diagram along the cutting line DD1 are shown in FIG. Figure 1 and Figure 2An initial stacking structure 230 is formed on the semiconductor substrate 200. The initial stacking structure 230 includes an initial sacrificial layer 231 and an initial semiconductor layer 232 alternately stacked along a vertical direction. The initial stacking structure 230 includes a transistor region 21 and a capacitor region 22 in sequence along a first direction.

[0050] The initial stack structure 230 is subsequently used to form a stack structure, the initial sacrificial layer 231 is subsequently used to form a sacrificial layer, and the initial semiconductor layer 232 is subsequently used to form a linear semiconductor pattern.

[0051] The initial stacked structure 230 includes an initial sacrificial layer 231 and an initial semiconductor layer 232 alternately stacked in a vertical direction. The alternating stacking of the initial sacrificial layer 231 and the initial semiconductor layer 232 means that after forming an initial sacrificial layer 231 on the semiconductor substrate 200, an initial semiconductor layer 232 is formed on the surface of the initial sacrificial layer 231, and then the steps of forming the initial sacrificial layer 231 and the initial semiconductor layer 232 located on the initial sacrificial layer 231 are repeated in sequence. The number of layers of the initial sacrificial layer 231 and the initial semiconductor layer 232 can be determined according to actual needs. In this embodiment, the example of the initial sacrificial layer 231 and the initial semiconductor layer 232 being two layers is used for explanation. In other embodiments, the number of layers of the initial sacrificial layer 231 and the initial semiconductor layer 232 can be other numbers.

[0052] In some embodiments, the initial stacking structure 230 includes a transistor region 21 and a capacitor region 22 located on one side of the transistor region 21 along the first direction. In some embodiments, the transistor region 21 may also include a first active region, a channel region, and a second active region arranged in sequence along the first direction.

[0053] refer to Figure 3 and Figure 4 ,in Figure 4 The four figures in the upper left, upper right, lower left and lower right are Figure 3 A schematic diagram of the cross-sectional structure along the cutting line AA1, a schematic diagram of the cross-sectional structure along the cutting line BB1, a schematic diagram of the cross-sectional structure along the cutting line CC1, and a schematic diagram of the cross-sectional structure along the cutting line DD1 are provided. A plurality of grooves 241 extending along the first direction and penetrating the initial stacking structure along the vertical direction are formed in the initial stacking structure. The initial semiconductor layer is divided into a plurality of linear semiconductor patterns 202 by the plurality of grooves 241, and the remaining initial sacrificial layer serves as a sacrificial layer 201.

[0054] The initial stacked structure is etched by an anisotropic dry etching process to form a plurality of trenches 241 extending along a first direction and vertically penetrating the initial stacked structure. In some embodiments, the plurality of trenches 241 are parallel to each other.

[0055] refer to Figure 5 and Figure 6 , the trench 241 is filled with the insulating layer 242 , and thus the stacked structure 203 is formed.

[0056] refer to Figure 7 and Figure 8 , Figure 7 exist Figure 5 Based on Figure 8 The two figures on the left and right are Figure 7 The cross-sectional structural diagram along the cutting line AA1 and the cross-sectional structural diagram along the cutting line BB1 ​​show that the sacrificial layer 201 in the capacitor region 22 is removed to form a cavity 205 between adjacent linear semiconductor patterns 202 .

[0057] The purpose of forming the cavity 205 is to facilitate the subsequent formation of a first separation layer extending along the first direction and at least partially suspended in the cavity 205 .

[0058] An isotropic wet etching process may be used to remove the sacrificial layer 201 in the capacitor region 22 .

[0059] In some embodiments, before removing the sacrificial layer 201, an etching hole 204 is formed on the side of the capacitor region 22 away from the transistor region 21, passing through the linear semiconductor pattern 202 and the sacrificial layer 201, and the sacrificial layer 201 in the capacitor region 22 is removed along the etching hole 204 to form a cavity 205.

[0060] In some embodiments, the cross-sectional shape of the cavity 205 along the second direction is rectangular.

[0061] After forming the cavity 205, it is necessary to form a first separation layer 207 (refer to FIG. Figure 12 ), in some embodiments below combined Figures 9-12 The formation process of the first separation layer 207 is described in detail.

[0062] First, refer to Figure 9 and Figure 10 ,in Figure 10 The two figures on the left and right are Figure 9 Schematic diagram of the cross-sectional structure along the cutting line AA1 and the schematic diagram of the cross-sectional structure along the cutting line BB1, a first sidewall material layer 206 is formed on the vertical sidewall surface and the horizontal sidewall surface of the cavity 205; a first separation layer 207 filling the remaining cavity is formed on the surface of the first sidewall material layer 206.

[0063] The formed first sidewall material layer 206 is used to define the position and thickness of the first separation layer 207. The formed first sidewall material layer 206 does not completely fill the cavity 205, and the first separation layer 207 is formed in the remaining cavity between the first sidewall material layers 206.

[0064] The function of the formed first separation layer 207 is: when a portion of the length of the first sidewall material layer is subsequently removed along the first direction so that the first separation layer 207 is partially suspended, the suspended first separation layer 201 cooperates with the linear semiconductor pattern 202 to define the positions of the first electrode layer, dielectric layer, and second electrode layer of different capacitors in the subsequent vertical direction, and is used to increase the surface area of ​​the first electrode layer, dielectric layer, and second electrode layer in the capacitor.

[0065] The material of the first sidewall material layer 206 is different from the materials of the first separation layer 207 and the linear semiconductor pattern 202. When a portion of the first sidewall material layer is subsequently removed along the first direction so that the first separation layer 207 is partially suspended, the etching selectivity of the first sidewall material layer 206 relative to the first separation layer 207 and the linear semiconductor pattern 202 is improved. When the first sidewall material layer 206 is removed, the first separation layer 207 and the linear semiconductor pattern 202 will not be etched or will be etched to a very small extent.

[0066] In some embodiments, the material of the first sidewall material layer 206 is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The first sidewall material layer 206 is formed by a chemical vapor deposition process, which includes an atomic layer deposition process. In this embodiment, the material of the first sidewall material layer 206 is silicon oxide.

[0067] In some embodiments, the material of first spacer layer 207 is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The first spacer layer 207 is formed by a chemical vapor deposition process, which includes an atomic layer deposition process. In this embodiment, the material of first spacer layer 207 is silicon nitride.

[0068] In some embodiments, when the first sidewall material layer 206 and the first separation layer 207 are formed, the first sidewall material layer 206 and the first separation layer 207 are also formed on the surface of the top linear semiconductor pattern 202 .

[0069] In some embodiments, when forming the first sidewall material layer 206 and the first separation layer 207, the first sidewall material layer and the first separation layer formed on the surface of the top linear semiconductor pattern 202 and the first sidewall material layer and the first separation layer formed on the inner wall and bottom surface of the etched hole 204 will be removed, leaving the first sidewall material layer 206 and the first separation layer 207 in the cavity.

[0070] In some embodiments, reference Figure 11 , Figure 11 exist Figure 10 The method further includes: removing a portion of the linear semiconductor pattern 202 along the first direction, so that the vertical surface of the first separation layer 207 protrudes from the vertical surface of the remaining linear semiconductor pattern 202 along the first direction.

[0071] An isotropic wet etching process is used to remove a portion of the linear semiconductor pattern 202 along the first direction. When removing the linear semiconductor pattern 202, the first sidewall material layer 206 is not etched or is over-etched to remove a portion of its length.

[0072] By removing a portion of the linear semiconductor pattern 202 along the first direction, the vertical surface of the first separation layer 207 protrudes from the vertical surface of the remaining linear semiconductor pattern 202 along the first direction. After the first electrode material layer is subsequently formed, the protruding first separation layer 207 causes a portion of the first electrode material layer to also protrude, thereby making it easy to disconnect the first electrode material layer from the protruding first separation layer 201, thereby forming multiple first electrode layers arranged discretely in the vertical direction, and ultimately forming multiple individually controlled capacitors in the vertical direction.

[0073] In one embodiment, the length of the linear semiconductor pattern 202 removed along the first direction is smaller than the length of the first sidewall material layer subsequently removed along the first direction.

[0074] refer to Figure 12 , a portion of the first sidewall material layer 206 is removed along the first direction, exposing a portion of the horizontal sidewall surface of the cavity 205 and causing a portion of the first separation layer 207 to be suspended.

[0075] An isotropic wet etching process is used to remove a portion of the first sidewall material layer 206 along the first direction. When the first sidewall material layer 206 is removed, the linear semiconductor pattern 202 and the first separation layer 207 are not etched or are etched to a very small extent.

[0076] After a portion of the first sidewall material layer 206 is removed along the first direction, a portion of the cavity 205 is exposed again, causing the first spacer layer 207 to be partially suspended. Simultaneously, the linear semiconductor pattern 202 is also partially suspended. Thus, a first spacer layer 207 extending along the first direction, which is at least partially suspended, is formed within the cavity 205. Through the coordination of the suspended first spacer layer 207 and the linear semiconductor pattern 202, the surface area of ​​the first electrode layer is increased when a first electrode layer is subsequently formed on the horizontal surface of the first spacer layer, on the vertical inner wall of the cavity, and on the horizontal surface of the linear semiconductor pattern between the cavities. Correspondingly, the surface areas of the dielectric layer formed on the first electrode layer and the second electrode layer formed on the dielectric layer are also increased. Consequently, with the same storage capacitance, the area occupied by the vertical projection of the formed capacitor on the semiconductor substrate surface is reduced, thereby improving the storage density of the DRAM.

[0077] In some embodiments, the following Figure 13-16 The formation process of the first electrode layer 210 is described in detail.

[0078] refer to Figure 13 A first electrode material layer 208 is formed on the vertical and horizontal surfaces of the first separation layer 207, on the vertical surface of the first sidewall material layer 206 (i.e., the vertical inner wall within the cavity 205), and on the vertical and horizontal surfaces of the linear semiconductor pattern 202 between the cavities 205.

[0079] The first electrode material layer 208 is subsequently used to form a first electrode layer.

[0080] In some embodiments, the first electrode material layer 208 can be a single-layer structure formed by one of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, or WSi, or a stacked-layer structure formed by two or more materials from the group consisting of the foregoing materials. In this embodiment, the first electrode material layer 208 is a TiN layer.

[0081] In some embodiments, the first electrode material layer 208 may be formed by chemical vapor deposition, physical vapor deposition, electroplating, or chemical plating.

[0082] refer to Figure 14 , forming a first filling material layer 209 filling the cavity on the surface of the first electrode material layer 208; Figure 15 , a portion of the first filling material layer 209 is removed to expose the surface of the first electrode material layer 208 on the vertical surface of the first separation layer 27 .

[0083] The material of the first filling material layer 209 is different from that of the first electrode material layer 208 and the first separator layer 207. In some embodiments, the first filling material layer 209 can be an organic material, such as photoresist, or other materials, such as amorphous carbon.

[0084] When forming the first electrode material layer 208, since the first separation layer 207 protrudes from the linear semiconductor pattern 202 and the first sidewall material layer 206 along the first direction, the first electrode material layer 208 on the vertical sidewall surface of the first separation layer 207 also protrudes from the linear semiconductor pattern 202 and the vertical sidewall surface of the first sidewall material layer 206 along the first direction. After forming the first filling material layer 209, by removing part of the first filling material layer 209, the first electrode material layer 209 located on the vertical sidewall surface of the first separation layer 207 can be easily exposed. Subsequently, by removing the exposed first electrode material layer 209, the first electrode material layer 209 is disconnected, so that a plurality of first electrode layers arranged separately along the vertical direction can be easily and accurately formed.

[0085] refer to Figure 16 , remove the exposed first electrode material layer, disconnect the first electrode material layer 209, and form a plurality of first electrode layers 210 arranged separately in a vertical direction.

[0086] The exposed first electrode material layer may be removed by an isotropic dry etching or wet etching process.

[0087] refer to Figure 17 , remove the first filling material layer 209 (refer to Figure 16 ).

[0088] The first filling material layer 209 is removed by dry etching or wet etching. At this point, the first electrode layer 210 is formed.

[0089] refer to Figure 18 A dielectric layer 211 is formed on the surface of the first electrode layer 210 and on the vertical surface of the first separation layer 207 .

[0090] In some embodiments, the material of dielectric layer 211 is a high-K dielectric material (K greater than 2.8) to increase the capacitance of the capacitor per unit area. In specific embodiments, dielectric layer 211 can be a single-layer structure formed by one of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO, or a stacked structure formed by two or more materials from the group consisting of the above materials. In this embodiment, dielectric layer 211 is an HfO2 layer, and the formation process includes a deposition process, and the deposition process includes atomic layer deposition. In other embodiments, the material of dielectric layer 211 can also be silicon oxide.

[0091] refer to Figure 19 , a second electrode layer 212 is formed on the surface of the dielectric layer 211 , and the second electrode layer 212 fills the remaining cavity.

[0092] The second electrode layer 212 can be a single-layer structure formed of one material selected from the group consisting of polysilicon, silicon germanium, W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked-layer structure formed of two or more materials selected from the group consisting of the foregoing materials. In this embodiment, the second electrode layer 212 is a TiN layer.

[0093] In some embodiments, the second electrode layer 212 may be formed by chemical vapor deposition, physical vapor deposition, electroplating, or chemical plating.

[0094] In other embodiments, the present invention further includes: removing the sacrificial layer in the channel region of the transistor region 21, so that the linear semiconductor layer in the channel region is suspended; forming a word line structure extending along the second direction on the surface of each suspended linear semiconductor layer, the word line structure including a word line dielectric layer and a metal word line located on the surface of the word line dielectric layer; and forming a bit line connecting the vertical multi-layer linear semiconductor pattern 202 in the first active region of the transistor region 21 (the side of the transistor region 21 away from the capacitor region 22).

[0095] Some other embodiments of the present disclosure (see Figure 20-25 ) also provides a method for forming a semiconductor structure. The difference between this embodiment and the aforementioned embodiment is that a suspended second separation layer 217 extending along the first direction is further formed between the first separation layer 207 and the linear semiconductor pattern 202, so that the surface area of ​​the formed first electrode layer 210 can be further increased. Therefore, under the same storage capacitance, the area occupied by the vertical projection of the formed capacitor on the surface of the semiconductor substrate will be further reduced, thereby further improving the storage density of the DRAM.

[0096] First, refer to Figure 20 , Figure 20 exist Figure 10 On the basis of the first sidewall material layer 206 and the first separation layer 207, a portion of the first sidewall material layer 206 is removed along the first direction to expose a portion of the cavity 205 again, so that the first separation layer 207 is partially suspended.

[0097] refer to Figure 21 A second sidewall material layer 216 is formed on the vertical sidewall surfaces and the horizontal sidewall surfaces of the cavity remaining between the first separation layer 207 and the linear semiconductor pattern 202; and a second separation layer 217 filling the remaining cavity is formed on the surface of the second sidewall material layer 216.

[0098] In some embodiments, the second spacer layer 217 is made of a different material than the first spacer layer 207. The second spacer layer 217 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride. In this embodiment, the second spacer layer 217 is made of silicon carbide nitride.

[0099] In some embodiments, the second sidewall material layer 216 may be made of the same material as the first sidewall material layer 206 .

[0100] In some embodiments, reference Figure 22 , a portion of the linear semiconductor pattern 202 and the second separation layer 217 is removed along the first direction, so that the vertical surface of the first separation layer 207 protrudes from the vertical surfaces of the remaining linear semiconductor pattern 202 and the remaining second separation layer 217 along the first direction.

[0101] refer to Figure 23 , a portion of the second sidewall material layer 216 is removed along the first direction to expose a portion of the horizontal sidewall surface of the cavity 205, so that the first separation layer 207 and the second separation layer 217 are at least partially suspended.

[0102] refer to Figure 24 A first electrode layer 210 is formed on the horizontal surface of the first separation layer 207, the vertical surface and horizontal surface of the second separation layer 217, the vertical surface of the second sidewall material layer 216, and the vertical surface and horizontal surface of the linear semiconductor pattern 202 between the cavities 205.

[0103] refer to Figure 25 A dielectric layer 211 is formed on the surface of the first electrode layer 210 and the vertical surface of the first separation layer 207 ; a second electrode layer 212 is formed on the surface of the dielectric layer 211 , and the second electrode layer 212 fills the remaining cavity.

[0104] Some embodiments of the present disclosure further provide a semiconductor structure, referring to Figure 19 or Figure 25 ,include:

[0105] a semiconductor substrate 200;

[0106] A stacked structure 203 located on a semiconductor substrate 200 includes a plurality of linear semiconductor patterns 202 extending along a first direction and arranged in an array in a second direction and a vertical direction. The stacked structure 203 includes a transistor region 21 and a capacitor region 22 in sequence along the first direction. A first space is defined between adjacent linear semiconductor patterns 202 in the vertical direction in the capacitor region 22. An insulating layer 242 is filled between adjacent linear semiconductor patterns in the second direction. The vertical direction is perpendicular to the surface of the semiconductor substrate 200, and the first and second directions are parallel to the surface of the semiconductor substrate 200.

[0107] a first separation layer 207 located in the first space and extending along the first direction;

[0108] a first electrode layer 210 located on a horizontal sidewall surface of the first separation layer 207 and extending to a surface of the linear semiconductor pattern 202;

[0109] a dielectric layer 211 located on the surface of the first electrode layer 210 and on the vertical surface of the first separator layer 207;

[0110] The second electrode layer 212 is located on the surface of the dielectric layer 211 .

[0111] In some embodiments, a vertical surface of the first separation layer 207 protrudes from a vertical surface of the linear semiconductor pattern 202 along the first direction.

[0112] In some embodiments, reference Figure 25 , further comprising: a second spacer layer 217 extending along the first direction between the first spacer layer 207 and the linear semiconductor pattern 202; a vertical surface of the first spacer layer 207 protruding from a vertical surface of the second spacer layer 217 along the first direction; and the first electrode layer 210 further covering the vertical and horizontal surfaces of the second spacer layer. The first spacer layer 207 and the second spacer layer 217 are located only in the capacitor region 22.

[0113] It should be noted that the definitions or descriptions of the same or similar parts in some embodiments of the aforementioned semiconductor structure and some embodiments of the aforementioned semiconductor structure forming method will not be repeated here. Please refer to the definitions or descriptions of the corresponding parts in some embodiments of the aforementioned semiconductor structure forming method for details.

[0114] Although the present disclosure has been disclosed as above in terms of preferred embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present disclosure by using the methods and technical contents disclosed above without departing from the spirit and scope of the present disclosure. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solutions of the present disclosure shall fall within the scope of protection of the technical solutions of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a semiconductor substrate; forming a stacked structure on the semiconductor substrate, the stacked structure comprising a plurality of linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction, a sacrificial layer being filled between adjacent linear semiconductor patterns in the vertical direction, and an insulating layer being filled between adjacent linear semiconductor patterns in the second direction, the stacked structure sequentially comprising a transistor region and a capacitor region along the first direction, the vertical direction being perpendicular to a surface of the semiconductor substrate, and the first and second directions being parallel to the surface of the semiconductor substrate; removing the sacrificial layer in the capacitor region to form a cavity between adjacent linear semiconductor patterns; forming a first separation layer in the cavity that is at least partially suspended and extends along a first direction; forming a first electrode layer on the horizontal surface of the first separation layer, on the vertical inner walls of the cavities, and on the vertical and horizontal surfaces of the linear semiconductor patterns between the cavities; forming a dielectric layer on a surface of the first electrode layer and a vertical surface of the first separator layer; A second electrode layer is formed on the surface of the dielectric layer, and the second electrode layer fills the remaining cavity.

2. The method for forming a semiconductor structure according to claim 1, wherein: The stacking structure forming process includes: forming an initial stacking structure on the semiconductor substrate, the initial stacking structure including an initial sacrificial layer and an initial semiconductor layer alternately stacked in a vertical direction, and the initial stacking structure including a transistor region and a capacitor region in sequence along a first direction; forming a plurality of trenches extending along a first direction and penetrating the initial stacked structure in a vertical direction in the initial stacked structure, wherein the initial semiconductor layer is divided into a plurality of linear semiconductor patterns by the plurality of trenches; The trench is filled with an insulating layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The forming process of the first separation layer includes: forming a first sidewall material layer on the vertical sidewall surface and the horizontal sidewall surface of the cavity; forming a first separation layer filling the remaining cavity on the surface of the first sidewall material layer; A portion of the first sidewall material layer is removed along a first direction to expose a portion of the horizontal sidewall surface of the cavity and to allow a portion of the first separation layer to be suspended.

4. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: Removing a portion of the length of the linear semiconductor pattern along a first direction, so that a vertical surface of the first separation layer protrudes from a vertical surface of the remaining linear semiconductor pattern along the first direction; The length of the linear semiconductor pattern removed is shorter than the length of the first sidewall material layer removed.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process of forming the first electrode layer includes: forming a first electrode material layer on the vertical surface and the horizontal surface of the first separation layer, on the vertical inner wall of the cavity, and on the vertical surface and the horizontal surface of the linear semiconductor pattern between the cavities; forming a first filling material layer filling the cavities on the surface of the first electrode material layer; removing a portion of the first filling material layer to expose a surface of the first electrode material layer on a vertical surface of the first separator layer; removing the exposed first electrode material layer to disconnect the first electrode material layer; The first filling material layer is removed.

6. The method for forming a semiconductor structure according to claim 3, wherein: After forming the first separation layer, the method further includes: forming a suspended second separation layer extending along the first direction between the first separation layer and the linear semiconductor pattern; and the formed first electrode layer also covers the vertical surface and the horizontal surface of the second separation layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The forming process of the second separation layer includes: forming a second sidewall material layer on the vertical sidewall surface and the horizontal sidewall surface of the cavity remaining between the first separation layer and the linear semiconductor pattern; forming a second separation layer filling the remaining cavity on the surface of the second sidewall material layer; Removing a portion of the linear semiconductor pattern and the second separation layer along a first direction, so that a vertical surface of the first separation layer protrudes from a remaining vertical surface of the linear semiconductor pattern and the remaining vertical surface of the second separation layer along the first direction; A portion of the second sidewall material layer is removed along a first direction to expose a portion of the horizontal sidewall surface of the cavity, so that the first separation layer and the second separation layer are at least partially suspended.

8. A semiconductor structure, characterized in that include: semiconductor substrates; a stacked structure located on the semiconductor substrate, the stacked structure comprising a plurality of linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction, the stacked structure sequentially comprising a transistor region and a capacitor region along the first direction, a first space being defined between adjacent linear semiconductor patterns along the vertical direction in the capacitor region, and an insulating layer being filled between adjacent linear semiconductor patterns along the second direction, the vertical direction being perpendicular to a surface of the semiconductor substrate, and the first and second directions being parallel to the surface of the semiconductor substrate; a first separation layer located in the first space and extending along a first direction; a first electrode layer located on a horizontal sidewall surface of the first separation layer and extending to a surface of the linear semiconductor pattern; a dielectric layer located on a surface of the first electrode layer and on a vertical surface of the first separator layer; A second electrode layer is located on a surface of the dielectric layer.

9. The semiconductor structure according to claim 8, wherein: A vertical surface of the first separation layer protrudes from a vertical surface of the linear semiconductor pattern along a first direction.

10. The semiconductor structure according to claim 8, wherein: Also includes: A second separation layer is located between the first separation layer and the linear semiconductor pattern and extends along the first direction. The vertical surface of the first separation layer protrudes from the vertical surface of the second separation layer along the first direction. The first electrode layer also covers the vertical and horizontal surfaces of the second separation layer.

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