Semiconductor structure and preparation method thereof

Abstract

The present invention relates to a semiconductor structure and a method for fabricating the same. The method comprises: providing a substrate; forming a sacrificial layer and a capacitor support layer on the substrate; etching the sacrificial layer and the capacitor support layer to the substrate to form a plurality of capacitor holes; forming a first electrode within the capacitor holes, and removing the sacrificial layer by ashing. In the semiconductor structure fabrication method of the present invention, ashing to remove the sacrificial layer reduces damage to the first electrode, thereby protecting the first electrode and extending the service life of the capacitor.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Capacitor structures are common in semiconductor memory devices. To fabricate a capacitor structure, multiple layers of sacrificial layers and capacitor support layers are typically placed alternately on a substrate. Capacitor holes are then etched to form the holes, which are then filled to form electrodes. The sacrificial layers are then removed, leaving the capacitor support layers and electrodes.

[0003] The electrodes of capacitors are easily damaged during the manufacturing process, which affects the use of the capacitors and reduces the life of the capacitors. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problem that the electrodes of capacitors in the prior art are easily damaged.

[0005] In order to achieve the above objectives, the present invention provides, in one aspect, a method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming a sacrificial layer and a capacitor support layer on the substrate;

[0008] Etching the sacrificial layer and the capacitor support layer to the substrate to form a plurality of capacitor holes;

[0009] A first electrode is formed in the capacitor hole, and the sacrificial layer is removed by ashing.

[0010] In one embodiment, the sacrificial layer comprises a carbon layer.

[0011] In one embodiment, the capacitor support layer includes an oxide support layer.

[0012] In one embodiment, forming a sacrificial layer and a capacitor support layer on the substrate includes:

[0013] A plurality of alternating sacrificial layers and oxide support layers are formed on the substrate.

[0014] In one embodiment, the hardness of the material of the multiple sacrificial layers decreases from the top layer to the bottom layer.

[0015] In one embodiment, forming multiple layers of alternating sacrificial layers and oxide support layers on the substrate includes:

[0016] The oxide support layer is formed by using a sub-atmospheric pressure chemical vapor deposition method. The material of the oxide support layer includes borophosphosilicate glass.

[0017] In one embodiment, before forming multiple layers of the sacrificial layer and the oxide support layer alternately arranged on the substrate, the method includes:

[0018] forming a nitride supporting layer on the substrate;

[0019] Etching the sacrificial layer and the capacitor support layer to the substrate to form a plurality of capacitor holes, comprising:

[0020] The sacrificial layer, the oxide support layer, and the nitride support layer are removed to the substrate to form a plurality of capacitor holes.

[0021] In one embodiment, forming a first electrode in the capacitor hole and removing the sacrificial layer by ashing includes:

[0022] Filling the first electrode in the capacitor hole;

[0023] forming a support enhancement layer on the upper surface of the oxide support layer located at the top layer and the upper surface of the first electrode;

[0024] Openings are formed in the support enhancement layer and each of the oxide support layers, and the sacrificial layer is removed from the openings.

[0025] In one embodiment, the material of the support enhancement layer is the same as that of the oxide support layer.

[0026] In one embodiment, forming a sacrificial layer and a capacitor support layer on the substrate includes:

[0027] forming a first sacrificial layer, a first oxide supporting layer, a second sacrificial layer, a second oxide supporting layer, a third sacrificial layer and a third oxide supporting layer in sequence on the substrate;

[0028] Forming openings in the support enhancement layer and each of the oxide support layers, and removing the sacrificial layer from the openings, comprising:

[0029] Etching the support enhancement layer, the third oxide support layer, the third sacrificial layer, and the second oxide support layer to form a first opening;

[0030] Based on the first opening, removing the third sacrificial layer and the second sacrificial layer;

[0031] etching the first oxide supporting layer to form a second opening;

[0032] Based on the second opening, the first sacrificial layer is removed.

[0033] In one embodiment, after forming the first electrode in the capacitor hole and removing the sacrificial layer by ashing, the method further includes:

[0034] forming a capacitor dielectric layer on the surface of the first electrode;

[0035] A second electrode is formed on the surface of the capacitor dielectric layer.

[0036] In another aspect, the present invention further provides a semiconductor structure comprising:

[0037] substrate;

[0038] a capacitor support layer, located on the substrate;

[0039] The first electrode penetrates the capacitor support layer and extends to the substrate. The first electrode is attached to the capacitor support layer, and a plurality of the first electrodes are arranged in parallel and at equal intervals. The capacitor support layer includes multiple oxide support layers arranged at intervals.

[0040] In one embodiment, the capacitor support layer further comprises:

[0041] A nitride supporting layer is located on the substrate, the nitride supporting layer and the oxide supporting layer are spaced apart, and the first electrode penetrates the oxide supporting layer and the nitride supporting layer.

[0042] In one embodiment, the semiconductor structure includes:

[0043] A support enhancement layer is located on the upper surface of the top oxide support layer and the upper surface of the first electrode.

[0044] In one embodiment, the material of the support enhancement layer is the same as that of the oxide support layer.

[0045] The semiconductor structure and the preparation method thereof of the present invention have the following beneficial effects:

[0046] In the semiconductor structure and preparation method thereof of the present invention, the sacrificial layer is removed by ashing to reduce damage to the first electrode, so that the first electrode can be bonded to the capacitor support layer, and multiple first electrodes are arranged in parallel and at equal intervals, thereby protecting the first electrodes and extending the service life of the capacitor prepared by the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figures 1A to 1L A flowchart of a prior art semiconductor structure preparation process provided in one embodiment;

[0049] Figure 2 A schematic diagram of a bending first electrode provided in an embodiment;

[0050] Figure 3 A schematic diagram of oxidation of a capacitor support layer provided in one embodiment;

[0051] Figure 4 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0052] Figures 5A to 5K is a flow chart for preparing a semiconductor structure provided in one embodiment;

[0053] Figures 6A to 6K A flowchart of preparing a semiconductor structure provided in another embodiment.

[0054] Explanation of the accompanying drawings: 100-semiconductor structure; 110-base; 111-substrate; 112-capacitor contact structure; 1121-capacitor contact pad; 1122-capacitor plug; 120-sacrificial layer; 121-first sacrificial layer; 122-second sacrificial layer; 123-third sacrificial layer; 130-capacitor support layer; 131-first oxide support layer; 132-second oxide support layer; 133-third oxide support layer; 140-capacitor hole; 150-first electrode; 151-first electrode material layer; 160-capacitor mask layer; 161-opening mask material layer; 170-nitride support layer; 180-support enhancement layer; 190-opening; 191-first opening; 192-second opening. DETAILED DESCRIPTION

[0055] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0057] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it can be directly on, adjacent to, or connected to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, and layers, these elements, components, regions, and layers should not be limited by these terms. These terms are merely used to distinguish one element, component, region, or layer from another element, component, region, or layer. Thus, a first element, component, region, or layer discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0058] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0059] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the invention.

[0061] As mentioned in the background art, the electrodes of a capacitor are easily damaged during the manufacturing process, which affects the use of the capacitor and reduces the life of the capacitor.

[0062] See also Figures 1A to 1L When forming the capacitor hole 140, the sacrificial layer 120 needs to be removed. In the prior art, wet etching is often used to remove the sacrificial layer 120. Specifically, the material of the sacrificial layer 120 is usually a compound such as silicon oxide, and the wet etching liquid is usually a high concentration of hydrofluoric acid.

[0063] See also Figure 2 The inventors discovered that when wet etching removes the sacrificial layer 120, the curvature of the liquid surface generates capillary forces. This capillary force, combined with the material stress of the first electrode 150 itself, causes the first electrode 150 to bend. This warping of the first electrode 150 affects the normal operation of the capacitor and shortens its lifespan.

[0064] Also, see Figure 3 The capacitor support layer 130 may also be oxidized, and the oxidized portion may be removed when the sacrificial layer 120 (such as silicon oxide) is wet-etched to remove the sacrificial layer 120, resulting in the capacitor support layer 130 not supporting the first electrode 150 firmly, the first electrode 150 may become loose, and the first electrode 150 may be damaged.

[0065] Based on the above situation, the inventors propose the following solution.

[0066] In one embodiment, see Figure 4 , a method for preparing a semiconductor structure 100 is provided, comprising the following steps:

[0067] Step S100: providing a substrate 110 .

[0068] Step S200 : forming a sacrificial layer 120 and a capacitor support layer 130 on the substrate 110 .

[0069] Step S300 : etching the sacrificial layer 120 and the capacitor support layer 130 to the substrate 110 to form a plurality of capacitor holes 140 .

[0070] Step S400 : forming the first electrode 150 in the capacitor hole 140 , and removing the sacrificial layer 120 by ashing.

[0071] In step S100, refer to Figures 5A to 5K , the base 110 may include a substrate 111 and a capacitor contact structure 112 provided in the substrate 111. The substrate 111 may be a single-layer structure or a multi-layer structure. As an example, the substrate 111 may include a silicon substrate, a silicon-germanium substrate, a silicon-germanium-carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, the substrate 111 may include a substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon-germanium on insulator. The type of substrate 111 should not limit the scope of protection of the present disclosure.

[0072] See also Figure 2 , the capacitor contact structure 112 may include a capacitor contact pad 1121 and a capacitor plug 1122. The substrate 110 may also be provided with a transistor structure and a bit line structure. The first electrode 150 formed in a subsequent step may be connected to the capacitor contact pad 1121. As an example, the drain of the transistor is connected to the bit line, and the source is connected to a capacitor formed subsequently. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage. Specifically, the semiconductor structure 100 can be prepared as a dynamic random access memory.

[0073] In step S200, sacrificial layer 120 and capacitor support layer 130 may comprise multiple layers. Sacrificial layer 120 may be removed in a subsequent step. Capacitor support layer 130 may be used to support the capacitor. For example, sacrificial layer 120 and capacitor support layer 130 may be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0074] In step S300, the capacitor hole 140 may extend from the surface of the capacitor support layer 130 through the sacrificial layer 120 to the capacitor contact structure 112 in the substrate 110. The capacitor hole 140 may be filled to form the first electrode 150 in a subsequent step.

[0075] See also Figure 5AAs an example, before forming multiple capacitor holes 140, a capacitor mask layer material layer can be formed on the top capacitor support layer 130. The capacitor mask layer material layer can be a single-layer structure or a multi-layer stacked structure. Then, a photoresist is coated on the capacitor mask layer material layer, and a series of steps such as exposure and development are performed to form a first patterned photoresist layer. Then, based on the first patterned photoresist layer, the capacitor mask material layer is etched to form a capacitor mask layer 160. The patterned capacitor mask layer 160 can define the specific location of the capacitor hole 140. As an example, the capacitor mask layer 160 can include at least one or more layers of an oxide layer, a silicon nitride layer, etc.

[0076] In step S400 , the material of the first electrode 150 may include a conductive metal. For example, the material of the first electrode 150 may include titanium nitride, cobalt, nickel, tungsten, tantalum, etc. The first electrode 150 is electrically connected to the capacitor contact pad 1121 in the substrate 110 .

[0077] After forming the first electrode 150 within the capacitor hole 140, the sacrificial layer 120 needs to be removed. Ashing can be used to remove the sacrificial layer 120. Specifically, an oxygen plasma can be generated within the process chamber to combust the sacrificial layer 120. For example, the ashing gas can include oxygen, hydrogen, or a mixture of oxygen and hydrogen with nitrogen.

[0078] In the above embodiment, a sacrificial layer 120 and a capacitor support layer 130 are first formed on the substrate 110, and then the sacrificial layer 120 and the capacitor support layer 130 are etched to the substrate 110 to form a plurality of capacitor holes 140. Finally, a first electrode 150 is formed in the capacitor hole 140, and the sacrificial layer 120 is removed by ashing. Since the ashing method is used when removing the sacrificial layer 120 instead of the conventional wet etching method, the first electrode 150 will not come into contact with the liquid, and will not bend under the action of capillary force. At the same time, even if the capacitor support layer 130 is partially oxidized, the oxide formed is not easily removed during the ashing process. Therefore, the stability of the first electrode 150 can also be enhanced at this time, thereby enhancing the performance of the capacitor and extending the service life of the capacitor.

[0079] In one embodiment, the sacrificial layer 120 may include a carbon layer.

[0080] The semiconductor structure 100 may include multiple sacrificial layers 120. The multiple sacrificial layers 120 may be entirely or partially carbon layers. For example, the carbon layer material may include a carbon-containing compound such as a diamond-like carbon material, an advanced patterning film (APF), or a first amorphous carbon layer (ACL). For example, the diamond-like carbon material may include Kodiak.

[0081] During the ashing process to remove the sacrificial layer 120, the carbon layer is more easily removed. Specifically, during ashing, the ashing gas reacts with the sacrificial layer 120 material and burns. The carbon layer reacts more easily with ashing gases such as oxygen, and the resulting carbon oxide gases (e.g., carbon monoxide, carbon dioxide, etc.) are also easier to remove.

[0082] Of course, in other embodiments, the sacrificial layer 120 may include other material layers, which is not limited here.

[0083] In one embodiment, the capacitor support layer 130 may include an oxide support layer.

[0084] Similarly, the semiconductor structure 100 may include a multilayer capacitor support layer 130. In the multilayer capacitor support layer 130, all of it may be an oxide support layer, or part of it may be an oxide support layer. Since the capacitor support layer 130 is used to support the first electrode 150, when the sacrificial layer 120 is removed, the capacitor support layer 130 should not easily react with the ashing gas. When an oxide support layer is used as the capacitor support layer 130, the oxide support layer is not easy to react with ashing gases such as oxygen and hydrogen, so the oxide support layer can be retained intact, providing better support for the first electrode 150.

[0085] See also Figure 5K After removing the sacrificial layer 120, the capacitor support layer 130 serves as a support frame for the semiconductor structure 100. In this embodiment, the capacitor support layer 130 may include an oxide support layer. The oxide support layer, which is not easily oxidized, not only improves the mechanical strength of the semiconductor structure 100 during subsequent capacitor fabrication, but also prevents damage to the capacitor during subsequent processes.

[0086] In one embodiment, step S200 includes:

[0087] Step S220 : forming multiple layers of alternating sacrificial layers 120 and oxide support layers on the substrate 110 .

[0088] See also Figure 5A, a sacrificial layer 120 may be formed on the substrate 110 first, and then an oxide support layer may be formed on the sacrificial layer 120. As an example, the sacrificial layer 120 and the oxide support layer may have two layers, three layers, or other numbers of layers.

[0089] Since the sacrificial layer 120 is removed and the oxide support layer is retained, multiple oxide support layers are spaced apart in the final semiconductor structure 100. The multiple oxide support layers provide support for different parts of the first electrode 150, thereby better fixing the first electrode 150 and reducing damage to the first electrode 150.

[0090] In one embodiment, the hardness of the material of the multi-layer sacrificial layer 120 decreases from the top layer to the bottom layer.

[0091] When forming the capacitor hole 140, each sacrificial layer 120 needs to be etched sequentially from the top layer to the bottom layer. The material hardness of the multiple sacrificial layers 120 decreases from the top layer to the bottom layer, which helps control the morphology of the capacitor hole 140, thereby producing a capacitor hole 140 with more vertical sidewalls, and subsequently forming the first electrode 150 with higher verticality.

[0092] As an example, the materials of the multi-layer sacrificial layer 120 can be Kodiak, APF, and ACL, from top to bottom. The hardness of Kodiak, APF, and ACL decreases in this order. The formation temperature of Kodiak is approximately 600-700°C. The formation temperature of APF is approximately 500-600°C. The formation temperature of ACL is approximately 300-500°C.

[0093] In one embodiment, step S220 includes:

[0094] Step S221 : forming an oxide support layer by using a sub-atmospheric pressure chemical vapor deposition method.

[0095] The oxide support layer material includes borophosphosilicate glass. For example, the borophosphosilicate glass in the underlying oxide support layer material can be doped with P2O5 or B2O3. Doping with P2O5 or B2O3 can increase the reflowability of the oxide support layer, making it more uniform and facilitating the fabrication of other structures on the oxide support layer.

[0096] As an example, the hardness of each oxide support layer may also decrease from the top layer to the bottom layer, thereby facilitating subsequent etching to produce capacitor holes 140 with higher sidewall verticality.

[0097] In one embodiment, before step S220, the following steps are included:

[0098] Step S210 : forming a nitride supporting layer 170 on the substrate 110 .

[0099] Step S300 includes:

[0100] Step S310 : etching the sacrificial layer 120 , the oxide supporting layer, and the nitride supporting layer 170 to the substrate 110 to form a plurality of capacitor holes 140 .

[0101] In step S210, refer to Figure 5A The nitride support layer 170 is located between the capacitor contact structure 112 and the sacrificial layer 120. The material of the nitride support layer 170 may include silicon nitride or silicon carbonitride.

[0102] In step S310, in order to connect the first electrode 150 to the capacitor contact structure 112, the capacitor contact structure 112 needs to be exposed when forming the capacitor hole 140. Therefore, the sacrificial layer 120, the oxide support layer, and the nitride support layer 170 need to be etched in sequence.

[0103] In one embodiment, step S400 includes:

[0104] Step S410 : filling the capacitor hole 140 with the first electrode 150 .

[0105] Step S420 : forming a support enhancement layer 180 on the upper surface of the oxide support layer located at the top layer and the upper surface of the first electrode 150 .

[0106] Step S430 : forming an opening 190 in the support enhancement layer 180 and each oxide support layer, and removing the sacrificial layer 120 from the opening 190 .

[0107] In step S410 , electrode metal is filled into the capacitor hole 140 to form the first electrode 150 .

[0108] Of course, the first electrode 150 can be located not only in the capacitor hole 140. In the actual process, please refer to Figure 5D When the first electrode 150 is filled in the capacitor hole 140, a first electrode material layer 151 may be formed first. The first electrode material layer 151 covers the capacitor hole 140 and the upper surface of the semiconductor structure 100. Figure 5E The first electrode material layer 151 on the upper surface of the semiconductor structure 100 is removed by chemical mechanical polishing or the like, leaving only the first electrode material layer 151 in the capacitor hole 140 to form the first electrode 150 .

[0109] In step S420, refer to Figure 5F The support enhancement layer 180 covers the upper surface of the first electrode 150 and the top oxide support layer. The support enhancement layer 180 is used to enhance the support effect of the semiconductor structure 100 on the first electrode 150.

[0110] In step S430, opening 190 is used to remove sacrificial layer 120. Specifically, sacrificial layer 120 can be removed by ashing, that is, ashing gas is introduced into opening 190, and the process chamber temperature is increased. The ashing gas reacts with sacrificial layer 120 and removes sacrificial layer 120, leaving a cavity.

[0111] When forming openings 190 in the support reinforcement layer 180 and each oxide support layer, only a small number of openings 190 may be formed. That is, the middle region including multiple first electrodes 150 may have only one opening 190. Of course, the first electrodes 150 and the openings 190 may also be provided in a one-to-one correspondence. This embodiment does not impose any specific limitation on this.

[0112] As an example, in order to more accurately control the position of the opening 190, an opening mask material layer 161 may be provided on the support reinforcement layer 180. Figure 5G The opening mask material layer 161 can be a single-layer structure or a multi-layer stacked structure. A photoresist is then coated on the opening mask material layer 161 and subjected to a series of steps such as exposure and development to form a second patterned photoresist layer. The opening mask material layer 161 is etched based on the second patterned photoresist layer to form an opening 190. The opening in the second patterned photoresist layer can define the specific location of the opening 190. As an example, the opening 190 can be located between adjacent first electrodes 150.

[0113] During the process of forming the opening 190 , the top oxide support layer may be damaged. In this case, the support enhancement layer 180 can play a role in strengthening the support.

[0114] In one embodiment, the material of the support enhancement layer 180 is the same as that of the oxide support layer.

[0115] As an example, the material of the support and reinforcement layer 180 may also include compounds such as oxides. In this case, when the sacrificial layer 120 is removed by ashing, the support and reinforcement layer 180 is less affected.

[0116] As an example, the material of the support enhancement layer 180 is the same as the material of the top oxide support layer. Using the same material for the support enhancement layer 180 and the top oxide support layer can also improve contact between the support enhancement layer 180 and the top oxide support layer, reducing the impact of lattice mismatch and other issues on the stability of the semiconductor structure 100 caused by different materials.

[0117] In one embodiment, step S200 includes:

[0118] Step S230 : sequentially forming a first sacrificial layer 121 , a first oxide supporting layer 131 , a second sacrificial layer 122 , a second oxide supporting layer 132 , a third sacrificial layer 123 and a third oxide supporting layer 133 on the substrate 110 .

[0119] Step S430 includes:

[0120] Step S431 : etching the support enhancement layer 180 , the third oxide support layer 133 , the third sacrificial layer 123 and the second oxide support layer 132 to form a first opening 191 .

[0121] Step S432 : removing the third sacrificial layer 123 and the second sacrificial layer 122 based on the first opening 191 .

[0122] Step S433 : etching the first oxide supporting layer 131 to form a second opening 192 .

[0123] Step S434 : removing the first sacrificial layer 121 based on the second opening 192 .

[0124] In step S230, refer to Figure 5A , the sacrificial layer 120 and the oxide support layer each have three layers. In this case, the sacrificial layer 120 can be a carbon layer. Since the carbon layer is relatively soft, the sacrificial layer 120 and the oxide support layer each have three layers, which can better support the first electrode 150 without causing the negative impact of the bending of the first electrode 150. Of course, the sacrificial layer 120 and the oxide support layer can also have two layers each, or other number of layers. This embodiment only exemplifies the number of layers of the sacrificial layer 120 and the oxide support layer. Please refer to Figures 6A to 6K , the figure shows the preparation process when the sacrificial layer 120 and the oxide support layer each have two layers.

[0125] As an example, the thickness of the third sacrificial layer 123 can be less than that of the second sacrificial layer 122, making the semiconductor structure 100 more stable. The thickness of the second sacrificial layer 122 can be the same as that of the first sacrificial layer 121. Of course, this embodiment does not impose any specific restrictions on the thickness of the first sacrificial layer 121, the second sacrificial layer 122, and the third sacrificial layer 123. At the same time, this embodiment does not impose any specific restrictions on the materials of the first sacrificial layer 121, the second sacrificial layer 122, and the third sacrificial layer 123, that is, the materials of the first sacrificial layer 121, the second sacrificial layer 122, and the third sacrificial layer 123 can be the same or different.

[0126] Likewise, this embodiment does not impose any specific restrictions on the materials and thicknesses of the first oxide supporting layer 131 , the second oxide supporting layer 132 , and the third oxide supporting layer 133 .

[0127] The three-layer capacitor support layer 130 can well support the first electrode 150 , and also increase the effective height of the capacitor, thereby increasing the capacitance value of the memory.

[0128] Of course, the deposition process for each film layer may include, but is not limited to, one or more of chemical vapor deposition, atomic layer deposition, high-density plasma deposition, plasma-enhanced deposition, and spin-on dielectric layer deposition. After each film layer is formed, each film layer may be planarized to facilitate subsequent formation of a new film layer. As an example, a chemical mechanical polishing process may be used to further flatten the top surface of each film layer.

[0129] In step S431, refer to Figure 5H The first opening 191 can extend from the upper surface of the support reinforcement layer 180 into the second sacrificial layer 122 , that is, the first opening 191 can simultaneously expose the third sacrificial layer 123 and the second sacrificial layer 122 . Similarly, there can be only a small number of first openings 191 in the plurality of first electrodes 150 .

[0130] In step S432, refer to Figure 5I Based on the first opening 191 , the third sacrificial layer 123 and the second sacrificial layer 122 may be removed by using an ashing method.

[0131] Because the first opening 191 exposes the third sacrificial layer 123 and the second sacrificial layer 122, ashing gases such as oxygen and hydrogen can contact the third sacrificial layer 123 and the second sacrificial layer 122. The third sacrificial layer 123 and the second sacrificial layer 122 may include a carbon layer, which can be reversed upon contact with ashing gases such as oxygen and hydrogen, thereby being removed. After the third sacrificial layer 123 and the second sacrificial layer 122 are removed, a cavity is formed within the semiconductor structure 100. Directly etching the support enhancement layer 180, the third oxide support layer 133, the third sacrificial layer 123, and the second oxide support layer 132 to form the first opening 191 can improve the efficiency of removing the sacrificial layer 120 and reduce the number of process steps.

[0132] Of course, in other embodiments, the support and reinforcement layer 180 and the third oxide support layer 133 may be etched to form the ashing opening 190. In this case, the third sacrificial layer 123 may be removed based on the ashing opening 190. The ashing opening 190 may then be deepened to extend into the second sacrificial layer 122, and the second sacrificial layer 122 may be removed based on the deepened ashing opening 190.

[0133] In step S433, refer to Figure 5J The first oxide supporting layer 131 may be etched to deepen the first opening 191 and form a second opening 192 . The second opening 192 exposes the first sacrificial layer 121 .

[0134] In step S434, refer to Figure 5K , the first sacrificial layer 121 can be removed using the same method.

[0135] After the first sacrificial layer 121 , the second sacrificial layer 122 and the third sacrificial layer 123 are removed, the interior of the semiconductor includes the first electrode 150 and the capacitor support layer 130 , and there is a cavity between adjacent capacitor support layers 130 .

[0136] In the above embodiment, a first sacrificial layer 121120, a first oxide supporting layer 131, a second sacrificial layer 122, a second oxide supporting layer 132, a third sacrificial layer 123, and a third oxide supporting layer 133 are sequentially formed on the substrate 110. The first sacrificial layer 121, the second sacrificial layer 122, and the third sacrificial layer 123 are removed in sequence to form a cavity in the semiconductor structure 100. The cavity can be used to subsequently form other capacitor structures. When the first sacrificial layer 121, the second sacrificial layer 122, and the third sacrificial layer 123 include a carbon layer, it is easier to remove the first sacrificial layer 121, the second sacrificial layer 122, and the third sacrificial layer 123 by ashing. Moreover, the materials of the first oxide supporting layer 131, the second oxide supporting layer 132, and the third oxide supporting layer 133 are not easily oxidized and are not easily damaged during the ashing process, thereby improving the stability of the semiconductor structure 100.

[0137] In one embodiment, after step S400, the following steps are included:

[0138] Step S500 : forming a capacitor dielectric layer on the surface of the first electrode 150 .

[0139] Step S510: forming a second electrode on the surface of the capacitor dielectric layer.

[0140] In step S500, the capacitor dielectric layer can be used to isolate the first electrode 150 from the subsequently formed second electrode, so the capacitor dielectric layer can be made of a non-conductive material. For example, the capacitor dielectric layer can include silicon dioxide, silicon nitride, aluminum oxide, or silicon oxynitride.

[0141] Those skilled in the art should know that the capacitor dielectric layer is located in the cavity formed after the sacrificial layer 120 is removed in the above step.

[0142] In step S510, the cavity formed in the previous step can be filled to form a second electrode. The second electrode, the capacitor dielectric layer, and the first electrode 150 constitute a capacitor. The material of the second electrode can be the same as or different from that of the first electrode 150.

[0143] As an example, the second electrode may include an electrode layer and a filling layer. The electrode layer may be located on the surface of the capacitor dielectric layer and may be made of titanium nitride, for example. The filling layer may fill the remaining space in the cavity and cover the upper surface of the support reinforcement layer 180. The filling layer may be made of silicon germanium or polycrystalline silicon, for example.

[0144] The second electrode may be connected to a logic circuit in the peripheral region, for example, a source region or a drain region of a CMOS transistor.

[0145] It should be understood that although Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 4 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0146] Based on the same invention concept, please continue to refer to Figures 5A to 5K , see also 6A to Figure 6K , an embodiment of a semiconductor structure 100 is also provided. The semiconductor structure 100 includes: a substrate 110 , a capacitor support layer 130 and a first electrode 150 .

[0147] The substrate 110 may include a substrate 111 and a capacitor contact structure 112 disposed within the substrate 111. The capacitor contact structure 112 may include a capacitor contact pad 1121 and a capacitor plug 1122. The substrate 110 may also include a transistor structure and a bit line structure. For example, the first electrode 150 may be connected to the capacitor contact pad 1121. As an example, the drain of the transistor is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor through the bit line for storage.

[0148] The capacitor support layer 130 is located on the substrate 110. The capacitor support layer 130 can be used to support the capacitor structure.

[0149] The first electrode 150 extends through the capacitor support layer 130 and to the substrate 110. The material of the first electrode 150 may include a conductive metal. As an example, the material of the first electrode 150 may include a metal material such as titanium nitride, cobalt, nickel, tungsten, or tantalum. The first electrode 150 is electrically connected to the capacitor contact pad 1121 in the substrate 110.

[0150] There may be a plurality of first electrodes 150 , and the plurality of first electrodes 150 are attached to the capacitor support layer 130 . The plurality of first electrodes 150 are vertically parallel and equally spaced in the semiconductor structure 100 .

[0151] In the above embodiment, during the process of preparing the semiconductor structure 100 , the sacrificial layer 120 may be removed by ashing to obtain a relatively straight first electrode 150 .

[0152] Conventional techniques often use wet etching to remove the sacrificial layer 10. In actual processes, the capillary force of the etching liquid can cause the first electrode 150 to bend. This affects the normal operation of the semiconductor structure 100 after it is fabricated into a capacitor. Furthermore, the capacitor support layer 130 may also be oxidized, and the oxidized portion may be etched away during the wet etching of the sacrificial layer, resulting in a weak support provided by the capacitor support layer 130 to the first electrode 150.

[0153] When the sacrificial layer 120 is removed by ashing, the first electrodes 150 are protected and prevented from bending, thereby allowing the plurality of first electrodes 150 to be arranged vertically, parallel, and evenly spaced within the semiconductor structure 100. Furthermore, when the sacrificial layer 120 is removed by ashing, even if the capacitor support layer 130 is partially oxidized, the resulting oxide is not easily removed during the ashing process, thereby protecting the capacitor support layer 130 and allowing the first electrodes 150 to adhere to the capacitor support layer 130.

[0154] In one embodiment, the capacitor support layer 130 includes multiple oxide support layers spaced apart from each other.

[0155] The capacitor support layer 130 includes an oxide support layer. The oxide support layer prevents the capacitor support layer 130 from being oxidized during the fabrication process of the semiconductor structure 100. This allows the capacitor support layer 130 to better support the first electrode 150, thereby improving the stability of the first electrode 150 and enhancing the performance of the capacitor fabricated using the semiconductor structure 100.

[0156] The capacitor support layer 130 may have multiple layers. The multiple capacitor support layers 130 are spaced apart, i.e., there is a cavity between adjacent capacitor support layers 130. As an example, the capacitor support layer 130 may have two or three layers. For example, when the capacitor support layer 130 has three layers, the three-layer capacitor support layer 130 can effectively support the first electrode 150, while also increasing the effective height of the capacitor, thereby increasing the capacitance value of the memory.

[0157] The oxide support layer is made of borophosphosilicate glass. For example, the borophosphosilicate glass in the bottom oxide support layer can be doped with P2O5 or B2O3. Doping with P2O5 or B2O3 can improve the reflowability of the oxide support layer, making it more uniform and facilitating the fabrication of other structures on the oxide support layer. The bottom oxide support layer can be less hard than the remaining oxide support layers.

[0158] Of course, the multilayer capacitor support layer 130 may be entirely or partially made of oxide support layers. As an example, some capacitor support layers 130 may be made of non-oxide materials such as silicon nitride or silicon carbonitride.

[0159] In one embodiment, the capacitor support layer 130 further includes a nitride support layer 170 .

[0160] The nitride supporting layer 170 is located on the substrate 110 . The nitride supporting layer 170 and the oxide supporting layer are spaced apart from each other. The first electrode 150 penetrates the oxide supporting layer and the nitride supporting layer 170 .

[0161] The nitride support layer 170 is used for capacitor contact, that is, the nitride support layer 170 is located between the capacitor contact structure 112 and the sacrificial layer 120. The material of the nitride support layer 170 may include silicon nitride or silicon carbonitride.

[0162] In one embodiment, the semiconductor structure 100 further includes a support enhancement layer 180 .

[0163] See also Figure 5F The support enhancement layer 180 is located on the upper surface of the top oxide support layer and the upper surface of the first electrode 150. The support enhancement layer 180 is used to enhance the support effect of the semiconductor structure 100 on the first electrode 150.

[0164] In one embodiment, the material of the support enhancement layer 180 is the same as that of the oxide support layer, that is, the material of the support enhancement layer 180 may also include compounds such as oxides.

[0165] During the process of manufacturing the semiconductor structure 100, the material of the support enhancement layer 180 includes compounds such as oxides. The oxides can reduce the impact of ashing and other manufacturing steps on the support enhancement layer 180. For example, the material of the support enhancement layer 180 can be the same as that of the top oxide support layer, which can improve the contact performance between the support enhancement layer 180 and the top oxide support layer and reduce the impact of lattice mismatch and other problems caused by different materials on the stability of the semiconductor structure 100.

[0166] In one embodiment, the semiconductor structure 100 further includes a capacitor dielectric layer and a second electrode.

[0167] The capacitor dielectric layer is located on the surface of the first electrode 150. The capacitor dielectric layer can be used to isolate the first electrode 150 from the second electrode. As an example, the material of the capacitor dielectric layer can include silicon dioxide, silicon nitride, aluminum oxide, or silicon oxynitride.

[0168] The second electrode is located on the surface of the capacitor dielectric layer. The material of the second electrode can be the same as or different from that of the first electrode 150. As an example, the material of the second electrode can include metal materials such as titanium nitride, cobalt, nickel, tungsten, and tantalum. The second electrode can be electrically connected to the capacitor contact structure 112. The second electrode can also include an electrode layer and a filling layer, which will not be described in detail here.

[0169] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0170] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a sacrificial layer and a capacitor support layer on the substrate; Etching the sacrificial layer and the capacitor support layer to the substrate to form a plurality of capacitor holes; forming a first electrode in the capacitor hole and removing the sacrificial layer by ashing; The capacitor support layer includes an oxide support layer; Forming a first electrode in the capacitor hole and removing the sacrificial layer by ashing, comprising: Filling the first electrode in the capacitor hole; forming a support enhancement layer on the upper surface of the oxide support layer located at the top layer and the upper surface of the first electrode; Openings are formed in the support enhancement layer and each of the oxide support layers, and the sacrificial layer is removed from the openings.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The sacrificial layer includes a carbon layer.

3. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a sacrificial layer and a capacitor support layer on the substrate, comprising: A plurality of alternating sacrificial layers and oxide supporting layers are formed on the substrate.

4. The method for preparing a semiconductor structure according to claim 3, wherein: The hardness of the material of the multiple layers of sacrificial layers decreases from the top layer to the bottom layer.

5. The method for preparing a semiconductor structure according to claim 3, wherein: Forming multiple layers of the sacrificial layer and the oxide support layer alternately arranged on the substrate, comprising: The oxide support layer is formed by using a sub-atmospheric pressure chemical vapor deposition method. The material of the oxide support layer includes borophosphosilicate glass.

6. The method for preparing a semiconductor structure according to claim 3, wherein: Before forming multiple layers of the sacrificial layer and the oxide support layer alternately arranged on the substrate, the method includes: forming a nitride supporting layer on the substrate; Etching the sacrificial layer and the capacitor support layer to the substrate to form a plurality of capacitor holes, comprising: The sacrificial layer, the oxide support layer, and the nitride support layer are etched to the substrate to form a plurality of capacitor holes.

7. The method for preparing a semiconductor structure according to claim 1, wherein: The material of the support enhancement layer is the same as that of the oxide support layer.

8. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a sacrificial layer and a capacitor support layer on the substrate, comprising: forming a first sacrificial layer, a first oxide supporting layer, a second sacrificial layer, a second oxide supporting layer, a third sacrificial layer and a third oxide supporting layer in sequence on the substrate; Forming openings in the support enhancement layer and each of the oxide support layers, and removing the sacrificial layer from the openings, comprising: Etching the support enhancement layer, the third oxide support layer, the third sacrificial layer, and the second oxide support layer to form a first opening; Based on the first opening, removing the third sacrificial layer and the second sacrificial layer; etching the first oxide supporting layer to form a second opening; Based on the second opening, the first sacrificial layer is removed.

9. The method for preparing a semiconductor structure according to claim 1, wherein: After forming a first electrode in the capacitor hole and removing the sacrificial layer by ashing, the method includes: forming a capacitor dielectric layer on the surface of the first electrode; A second electrode is formed on the surface of the capacitor dielectric layer.

10. A semiconductor structure, characterized in that include: substrate; a capacitor support layer, located on the substrate; a first electrode, penetrating the capacitor support layer and extending to the substrate, the first electrode being in contact with the capacitor support layer, and a plurality of the first electrodes being arranged in parallel and at equal intervals; The capacitor support layer includes multiple layers of oxide support layers spaced apart; A support enhancement layer is located on the upper surface of the top oxide support layer and the upper surface of the first electrode.

11. The semiconductor structure according to claim 10, wherein: The capacitor support layer further includes: A nitride supporting layer is located on the substrate, the nitride supporting layer and the oxide supporting layer are spaced apart, and the first electrode penetrates the oxide supporting layer and the nitride supporting layer.

12. The semiconductor structure according to claim 10, wherein: The material of the support enhancement layer is the same as that of the oxide support layer.

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