Method for preparing semiconductor structure

Abstract

The present disclosure provides a method for preparing a semiconductor structure, which relates to the field of semiconductor technology. The method includes: providing a substrate; forming a first mask layer on the substrate, the first mask layer having a plurality of first patterns arranged at intervals; forming a gap layer to form grooves between adjacent first patterns; forming a second mask layer to at least fill the grooves; performing a first back-etch on the second mask layer and the top gap layer, with the remaining second mask layer in the groove serving as the second pattern, the first pattern and the second pattern having a height difference; performing a second back-etch on the first pattern and the second pattern; forming a third mask layer; flattening the third mask layer so that its top surface is flush with the top surface of the sidewall gap layer; etching away the sidewall gap layer to form a gap, using the remaining first pattern, the remaining second pattern and the third mask layer as a common mask and etching the substrate along the gap. The present disclosure improves the uniformity of pattern size and control accuracy in semiconductor manufacturing processes.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, photolithography and etching processes are typically used to form specific patterns, thereby producing the desired device structure. With increasing integration, precise control of pattern dimensions is required to achieve high-precision, high-quality semiconductor devices. However, the accuracy of pattern size control in related technologies is limited, resulting in the inability to achieve uniform and ideal patterns and semiconductor structures, which in turn affects semiconductor performance. Summary of the Invention

[0003] The present disclosure provides a method for fabricating a semiconductor structure, which can improve the uniformity and control accuracy of pattern size at least to a certain extent.

[0004] According to one aspect of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: providing a substrate; forming a first mask layer on the substrate, the first mask layer having a plurality of first patterns arranged at intervals; forming a gap layer, the gap layer comprising at least a top gap layer covering a top surface of the first mask layer and a sidewall gap layer covering a sidewall of the first mask layer, so as to form a groove between adjacent first patterns; forming a second mask layer, the second mask layer at least filling the groove; performing a first back etching on the second mask layer and the top gap layer until the top surface of the first pattern is exposed, and the remaining second mask layer in the groove serves as a second pattern, and the second mask layer is used as a second pattern. There is a height difference between the top surface of a graphic and the top surface of the second graphic; the first graphic and the second graphic are etched back for a second time so that the top surface of the sidewall spacer layer is higher than the top surface of the remaining first graphic and the top surface of the remaining second graphic; a third mask layer is formed, and the third mask layer covers the remaining first graphic and the remaining second graphic; the third mask layer is planarized so that the top surface of the third mask layer is flush with the top surface of the sidewall spacer layer; the sidewall spacer layer is etched away to form a gap, and the substrate is etched along the gap using the remaining first graphic, the remaining second graphic and the third mask layer as a common mask.

[0005] Optionally, the first graphics and the second graphics are arranged alternately along a first direction, and a first size of the first graphics along the first direction is the same as a second size of the second graphics along the first direction.

[0006] Optionally, forming a first mask layer on the substrate includes: depositing a first initial mask layer on the substrate; forming a plurality of photoresist patterns arranged along the first direction on the first initial mask layer, wherein the size of the photoresist patterns along the first direction is the same as the first size, and the spacing between adjacent photoresist patterns along the first direction is a third size, and the third size is larger than the first size; etching the first initial mask layer using the photoresist patterns as a mask to obtain the first mask layer, wherein the first mask layer has a plurality of the first patterns arranged at intervals along the first direction.

[0007] Optionally, after depositing the first initial mask layer on the substrate, the method further includes: forming an initial cover layer covering the top surface of the first initial mask layer; the photoresist pattern is formed on the top surface of the initial cover layer; when etching the first initial mask layer using the photoresist pattern as a mask, the initial cover layer is also etched using the photoresist pattern as a mask to form a cover layer, and the first mask layer and the cover layer together have a plurality of first patterns arranged at intervals along the first direction; the first back-etching of the second mask layer and the top gap layer until the top surface of the first pattern is exposed includes: performing a first back-etching of the second mask layer, the top gap layer and the cover layer until the top surface of the first pattern is exposed.

[0008] Optionally, a gap layer is formed on the substrate, including: forming the top gap layer covering the top surface of the first mask layer and the sidewall gap layer covering the side wall of the first mask layer, and controlling the single-layer thickness of the sidewall gap layer along the first direction to be 1 / 2 of the difference between the third size and the first size.

[0009] Optionally, forming a second mask layer on the substrate includes: forming the second mask layer to fill the groove and cover the top surface of the top gap layer.

[0010] Optionally, after the second back etching, the top surface of the sidewall spacer layer is higher than the top surface of the remaining first pattern and the top surface of the remaining second pattern; the material of the third mask layer is different from the material of the first mask layer and the material of the second mask layer.

[0011] Optionally, an etch stop layer and a film layer to be etched located above the etch stop layer are formed in the substrate; the remaining first pattern, the remaining second pattern and the third mask layer are used as a common mask and the substrate is etched along the gap, including: using the remaining first pattern, the remaining second pattern and the third mask layer as a common mask, taking the etch stop layer as the etching end point, and etching the film layer to be etched in the substrate along the gap.

[0012] Optionally, the film layer to be etched is etched to form a fourth mask layer or a plurality of bit lines.

[0013] Optionally, when etching the substrate, the substrate area exposed by the gap forms a first trench, and the first trench is used to form a shallow trench isolation structure; the substrate area covered by the common mask forms an active area; or when etching the substrate, the substrate area exposed by the gap forms a second trench, and the second trench is used to form a buried word line.

[0014] The technical solution disclosed in this disclosure has the following beneficial effects:

[0015] On the one hand, a third mask layer is formed above the first figure and the second figure which originally have a height difference. Through flattening treatment, the top surface of the third mask layer is made to be consistent in height and flush with the top surface of the sidewall spacer, thereby eliminating the height difference between the first figure and the second figure. In this way, during the process of etching the sidewall spacer and etching downward into the substrate, the gap between the first figure and the second figure can be reduced from shifting or expanding to either side. On the other hand, in the first graphic part, the first mask layer and the third mask layer form a composite mask layer, and in the second graphic part, the second mask layer and the third mask layer also form a composite mask layer. This is beneficial to improving the etching selectivity of the sidewall spacer layer to the composite mask layers on both sides during etching of the sidewall spacer layer, realizing an etching process with a high aspect ratio, and also improving the problem of the gap shifting or expanding to either side. Furthermore, before forming the third mask layer, the first graphic and the second graphic are subjected to a second back etching, so that the top surface of the sidewall spacer layer is higher than the top surface of the remaining first graphic and the top surface of the remaining second graphic, which can increase the proportion of the third mask layer in the first graphic part and the second graphic part, so as to obtain a more ideal composite mask layer, which is beneficial to more precise control of the etching of the sidewall spacer layer. Taking the above factors into consideration, this solution can more accurately transfer the first graphic and the second graphic downward, and improve the accuracy of the control of the size of the first graphic and the second graphic. In particular, it can improve the problem of inconsistent size between the core area and the spacing area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1E The process flow of forming core area and spacer area patterns in the related art is shown;

[0017] Figure 2 Shown Figure 1B to Figure 1C Electron microscope images of the process;

[0018] Figure 3 A flow chart showing a method for preparing a semiconductor structure in this exemplary embodiment is shown;

[0019] Figure 4shows a top view of a semiconductor structure in this exemplary embodiment;

[0020] Figures 5 to 12B A process schematic diagram of a method for preparing a semiconductor structure in this exemplary embodiment is shown;

[0021] Figure 13 、 Figure 14 shows a schematic diagram of a process for forming a capping layer in this exemplary embodiment;

[0022] Figures 15 to 26 A schematic diagram showing a process of a method for preparing a semiconductor structure in this exemplary embodiment is shown;

[0023] Figure 27 A schematic diagram of a semiconductor structure in this exemplary embodiment is shown.

[0024] The reference numerals are as follows:

[0025] 101: substrate; 102: first mask layer; 102': first initial mask layer; 103: gap layer; 1031: top gap layer; 1032: sidewall gap layer; 104: groove; 105: second mask layer; 106: third mask layer; 107: gap; 108: cap layer; 108': initial cap layer; 109: etch stop layer; 110: film layer to be etched; 110a: carbon layer; 110b: silicon oxynitride layer; 111: photoresist area; 112: pattern layer; 112a: core area; 112b: spacer area. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

[0027] The accompanying drawings are schematic illustrations of the present disclosure and are not necessarily drawn to scale. The technical solutions of the present disclosure can be implemented in various forms and should not be construed as being limited to the examples set forth herein. The features, structures, or characteristics described in the present disclosure may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full description of the embodiments of the present disclosure. However, those skilled in the art will appreciate that one or more specific details may be omitted when implementing the technical solutions of the present disclosure, or that other methods, components, structures, etc. may be used to replace one or more specific details.

[0028] In the related technologies of semiconductor manufacturing processes, the accuracy of pattern size control needs to be improved, resulting in the inability to obtain a uniform and ideal device structure.

[0029] Figures 1A to 1E The process flow of forming core and gap patterns on a substrate in the related art is shown. Figure 1A As shown, a mask layer A and a mask layer B are formed on the substrate, and a gap material is filled between the mask layers B. Generally, the gap material needs to be etched away, and the pattern of the core area and the spacer area is defined by the gap formed. Then, the pattern is transferred from the mask layer B to the mask layer A to obtain the desired pattern structure. However, due to the height difference between the structures distributed in different areas of the mask layer B and the difficulty in accurately controlling the etching selection results, the etched gap may expand laterally toward the core area (or spacer area), resulting in a reduction in the size of the core area (or spacer area). For example, if the etching rate of the gap material is greater than the etching rate of the mask layer B, the following will be formed: Figure 1B As shown in Figure 2, the gap tends to expand toward the core area, which leads to the core area size being smaller than the spacer area size during the pattern transfer process, i.e. Figure 1C If the etching rate of the gap material is lower than the etching rate of the mask layer B, the following situation will be formed: Figure 1D As shown in Figure 2, the gap tends to expand toward the spacer area, which leads to the core area size being larger than the spacer area size during the pattern transfer process, i.e. Figure 1E The situation shown.

[0030] Figure 2 Shown Figure 1B to Figure 1C The electron microscope image of the process shows that due to the different heights of the mask layer B above the core area and the spacer area, the following will be produced during the etching of the gap material: Figure 2 As shown in the left figure, if we continue to etch the mask layer A, the pattern will be transferred down and the result will be as follows: Figure 2 The structure shown in the figure on the right.

[0031] These issues can affect subsequent device structures and the performance and quality of the final semiconductor product. In particular, in device structures that require the core and spacer regions to be of identical dimensions, these issues can lead to inconsistent core and spacer dimensions, significantly impacting the performance and quality of the semiconductor product.

[0032] In view of the above problems, the exemplary embodiments of the present disclosure first provide a method for preparing a semiconductor structure. The semiconductor structure can be a local structure in a semiconductor device, and the semiconductor device can be a memory device such as DRAM (Dynamic Random Access Memory), or a logic device. The prepared semiconductor structure has a first graphic and a second graphic, one of the first graphic and the second graphic is used to define the core area, and the other is used to define the spacer area. For example, the core area and the spacer area can be used as an active area (Active Area, AA), and the gap between the core area and the spacer area can be used as a shallow trench isolation structure (STI) or a buried word line (BWL), etc. The first graphic and the second graphic can also be used to form various structures distributed in an intermittent manner in a semiconductor device, that is, the structures formed by the core area and the spacer area are different.

[0033] Figure 3 An exemplary process of a method for preparing a semiconductor structure is shown, which may include the following steps S310 to S390:

[0034] Step S310, providing a substrate 101;

[0035] Step S320, forming a first mask layer 102 on the substrate 101, wherein the first mask layer 102 has a plurality of first patterns arranged at intervals;

[0036] Step S330 , forming a gap layer 103 , the gap layer 103 at least including a top gap layer 1031 covering the top surface of the first mask layer 102 and a sidewall gap layer 1032 covering the sidewalls of the first mask layer 102 , so as to form a groove 104 between adjacent first patterns;

[0037] Step S340 , forming a second mask layer 105 , wherein the second mask layer 105 at least fills the groove 104 ;

[0038] Step S350 , performing a first back etching on the second mask layer 105 and the top gap layer 1031 until the top surface of the first pattern is exposed, and the remaining second mask layer 105 in the groove 104 serves as the second pattern, and there is a height difference between the top surface of the first pattern and the top surface of the second pattern;

[0039] Step S360 , performing a second etching back on the first pattern and the second pattern, so that the top surface of the sidewall spacer 1032 is higher than the top surface of the remaining first pattern and the top surface of the remaining second pattern;

[0040] Step S370: forming a third mask layer 106, where the third mask layer 106 covers the remaining first pattern and the remaining second pattern;

[0041] Step S380 , performing a planarization process on the third mask layer 106 so that the top surface of the third mask layer 106 is flush with the top surface of the sidewall spacer layer 1032 ;

[0042] In step S390 , the sidewall spacer layer 1032 is removed by etching to form a gap 107 , and the substrate 101 is etched along the gap 107 using the remaining first pattern, the remaining second pattern, and the third mask layer 106 as a common mask.

[0043] Based on the above method, on the one hand, a third mask layer 106 is formed above the first figure and the second figure that originally have a height difference. Through flattening treatment, the top surface of the third mask layer 106 is made to be consistent in height and flush with the top surface of the sidewall spacer 1032, thereby eliminating the height difference between the first figure and the second figure. In this way, during the process of etching the sidewall spacer 1032 and etching downward into the substrate 101, the gap 107 between the first figure and the second figure can be reduced from shifting or expanding to either side. On the other hand, in the first pattern portion, the first mask layer 102 and the third mask layer 106 form a composite mask layer, and in the second pattern portion, the second mask layer 105 and the third mask layer 106 also form a composite mask layer. This helps improve the etching selectivity of the sidewall spacer layer 1032 to the composite mask layers on both sides during etching of the sidewall spacer layer 1032, achieving a high aspect ratio etching process, and also improving the problem of the gap 107 shifting or expanding to either side. Furthermore, before forming the third mask layer 106, the first and second patterns are subjected to a second back etching, so that the top surface of the sidewall spacer layer 1032 is higher than the top surface of the remaining first pattern and the top surface of the remaining second pattern. This can increase the proportion of the third mask layer 106 in the first and second pattern portions, thereby obtaining a more ideal composite mask layer, which is conducive to more precise control of the etching of the sidewall spacer layer 1032. Taking into account the above factors, this solution can more accurately transfer the first and second patterns downward, improving the accuracy of the dimensional control of the first and second patterns. In particular, the problem of inconsistent sizes between the core region and the spacer region can be improved.

[0044] The following combination Figures 4 to 8B ,right Figure 3 Each step is described in detail.

[0045] refer to Figure 3 In step S310 , a substrate 101 is provided.

[0046] The substrate 101 may be located at the bottom of the semiconductor structure and may be a substrate of materials such as silicon (e.g., single crystal silicon, polycrystalline silicon, amorphous silicon), germanium, silicon-germanium compounds, or Group III-V compounds (e.g., gallium arsenide). The substrate 101 may have an epitaxial layer or may be a silicon-on-insulator substrate (i.e., an SOI substrate). The present disclosure does not limit the specific structure of the substrate 101. For example, a p-type well (p-well) or an n-type well (n-well) may be formed in the substrate 101 for subsequent formation of an active region.

[0047] Continue to refer Figure 3 In step S320, a first mask layer 102 is formed on the substrate 101, and the first mask layer 102 has a plurality of first patterns arranged at intervals.

[0048] Figure 4 FIG shows a top view of the substrate 101 and the first mask layer 102. Figure 4 As shown, in a semiconductor device, the first direction can be perpendicular to the active area, the second direction can be parallel to the active area, the third direction can be the word line (WL) direction, and the fourth direction can be the bit line (BL) direction. The first direction and the second direction can be perpendicular, the third direction and the fourth direction can be perpendicular, and both the first and second directions intersect with the third and fourth directions. For example, if the first and second graphics both define the active area, and the gap between the first and second graphics defines a shallow trench isolation structure, then the first and second graphics can also be staggered along the first direction. It should be understood that if the first and second graphics define other structures in the semiconductor device, then the first and second graphics can be staggered along other directions. For example, if the first and second graphics define a bit line structure, then the first and second graphics can be staggered along the third direction; if the gap between the first and second graphics defines a word line trench, then the first and second graphics can be staggered along the fourth direction.

[0049] Semiconductor memory devices typically include an array area and a peripheral area. The array area includes an array of memory cells, each of which is primarily composed of a transistor and a capacitor. The active area defined by the first pattern, or the active area defined by the first and second patterns, can be the active area of ​​a memory cell, and can, for example, be used to form the source, drain, and channel regions of transistors in a DRAM memory cell. A bit line can connect the source or drain regions of multiple transistors in the fourth direction, and a word line (or buried word line) can span the channel regions of multiple transistors in the third direction.

[0050] Figure 5 Shown from Figure 4The II' cross-sectional view taken along the first direction is a cross-sectional view taken along the first direction. The first mask layer 102 is located on the substrate 101 and has a plurality of first patterns arranged at intervals. Each first pattern can define a cross-sectional pattern of each active region.

[0051] In one embodiment, a first preliminary mask layer 102' may be deposited first, and then a reticle having a first pattern may be used to pattern the first preliminary mask layer 102' through photolithography and etching processes to form a first mask layer 102 having the first pattern.

[0052] It should be understood that the first mask layer 102 may be located on the top surface of the substrate 101 and in direct contact with the substrate 101, or may be located on other film layers on the substrate 101 and not in direct contact with the substrate 101. For example, other film layers, such as a dielectric layer, other mask layers, etc., may be formed on the substrate 101 first, and then the first mask layer 102 may be formed on the other film layers.

[0053] Continue to refer Figure 3 In step S330, a gap layer 103 is formed. The gap layer 103 includes at least a top gap layer 1031 covering the top surface of the first mask layer 102 and a sidewall gap layer 1032 covering the sidewall of the first mask layer 102 to form a groove 104 between adjacent first patterns.

[0054] refer to Figure 6 As shown, a gap layer 103 can be deposited on the top surface of the entire semiconductor structure. The portion of the gap layer 103 covering the top surface of the first mask layer 102 forms a top gap layer 1031, and the portion covering the sidewalls of the first mask layer 102 forms a sidewall gap layer 1032. Furthermore, the gap layer 103 can also cover areas on the substrate 101 not covered by the first mask layer 102. The gap layer 103 in this area can be referred to as a bottom gap layer. Recesses 104 are formed between adjacent first patterns. Specifically, the recesses 104 can be enclosed by the sidewall gap layers 1032 on the adjacent sidewalls of the first mask layer 102.

[0055] Continue to refer Figure 3 In step S340 , a second mask layer 105 is formed so that the second mask layer 105 fills the groove 104 .

[0056] The present disclosure does not limit the filling height of the second mask layer 105 in the groove 104 . The second mask layer 105 may completely fill the groove 104 or partially fill the groove 104 . Figure 7A The situation in which the second mask layer 105 completely fills the groove 104 is shown.

[0057] In one embodiment, the second mask layer 105 may also be located in other areas outside the groove 104. Specifically, the above-mentioned formation of the second mask layer 105 may include the following steps:

[0058] A second mask layer 105 is formed to fill the groove 104 and cover the top surface of the top spacer layer 1031 .

[0059] refer to Figure 7B As shown, the second mask layer 105 can be deposited on the top surface of the entire semiconductor structure without requiring special control over the deposition area of ​​the second mask layer 105, thereby simplifying the process. In one embodiment, the second mask layer 105 can also be planarized to make the top surface of the entire structure flat, which facilitates control of the subsequent etch-back.

[0060] Continue to refer Figure 3 In step S350, the second mask layer 105 and the top gap layer 1031 are etched back for the first time until the top surface of the first pattern is exposed. The remaining second mask layer 105 in the groove 104 serves as the second pattern. The top surface of the first pattern and the top surface of the second pattern have a height difference.

[0061] Herein, in order to distinguish the etch-back processes adopted in different stages, the etch-back in step S350 and the etch-back in step S360 are respectively referred to as the first etch-back and the second etch-back.

[0062] As can be seen from the above, the top surface of the first pattern is covered by the top gap layer 1031 and may also be covered by the second mask layer 105. In order to expose the top surface of the first pattern, the second mask layer 105 and the top gap layer 1031 are first etched back. The first etch back consumes a portion of the second mask layer 105 in the groove 104, and the remaining second mask layer 105 in the groove 104 is used as the second pattern. Figure 8A or Figure 8B As shown, during the first back-etching process, due to the inconsistent etching rates of the top gap layer 1031 on the top surface of the first pattern and the second mask layer 105 in the groove 104, the top surface of the first pattern and the top surface of the second pattern will be inconsistent in height, and there will be a height difference H1 or H2 between the two. For example, in the first back-etching, if the etching rate of the top gap layer 1031 is greater than the etching rate of the second mask layer 105, then when the top gap layer 1031 is completely etched away, the height of the second mask layer 105 etched away in the groove 104 is lower than the height of the top gap layer 1031, so that the top surface of the second pattern is higher than the top surface of the first pattern, as shown in FIG. Figure 8AIn the case shown, the top surface of the second pattern is higher than the top surface of the first pattern by H1; if the etching rate of the top gap layer 1031 is lower than the etching rate of the second mask layer 105, when the top gap layer 1031 is completely etched away, the height of the second mask layer 105 etched away in the groove 104 is higher than the height of the top gap layer 1031, so that the top surface of the second pattern is lower than the top surface of the first pattern, as shown in FIG. Figure 8B In the illustrated case, the top surface of the first figure is higher than the top surface of the second figure by an amount H2.

[0063] Continue to refer Figure 3 In step S360, the first pattern and the second pattern are etched back for the second time, so that the top surface of the sidewall spacer 1032 is higher than the top surface of the remaining first pattern and the top surface of the remaining second pattern.

[0064] based on Figure 8A After the second etching, the structure shown in FIG. Figure 9A The structure shown. Based on Figure 8B After the second etching, the structure shown in FIG. Figure 9B The second etching can play the following two roles:

[0065] On the one hand, by the second back etching, the height of the first figure and the second figure is reduced, so that the top surface of the sidewall spacer 1032 can be ensured to be higher than the top surface of the remaining first figure and the top surface of the remaining second figure. In this way, after the third mask layer 106 is subsequently formed, the first mask layer 102 / third mask layer 106 interface and the second mask layer 105 / third mask layer 106 interface are both lower than the top surface of the sidewall spacer 1032, which makes the two sides of the sidewall spacer 1032 completely composite mask layers. In particular, when the third mask layer 106 is flattened to be flush with the sidewall spacer 1032, the composite mask layer can be retained on both sides of the sidewall spacer 1032, which facilitates the precise control of the etching process of the sidewall spacer 1032.

[0066] Secondly, through the second back etching, the height of the first and second graphics can be controlled within a suitable range, thereby leaving a space of appropriate size above the first and second graphics, facilitating the subsequent formation of a third mask layer 106 with a relatively ideal height, especially making the ratio of the first mask layer 102 to the third mask layer 106 in the first graphic portion appropriate, and making the ratio of the second mask layer 105 to the third mask layer 106 in the second graphic portion appropriate. For example, the top surface of the sidewall spacer 1032 can be higher than the preset height of the top surface of the remaining first graphics, or higher than the preset height of the top surface of the remaining second graphics. Figure 9A or Figure 9BIn the figure, H3 represents a preset height, which can be the height difference between the top surface of the higher one of the first and second graphics and the top surface of the sidewall spacer 1032 ( Figure 9A and Figure 9B H3 is shown as the height difference between the top surface of the higher one and the top surface of the sidewall spacer 1032, or it can be the height difference between the top surface of the lower one of the first pattern and the second pattern and the top surface of the sidewall spacer 1032. The preset height is also the height of the subsequently formed third mask layer 106 in the first pattern portion or the second pattern portion. Therefore, the preset height can be determined based on the desired height of the third mask layer 106, and the process parameters such as the etching time of the second back etch can be controlled to ensure that the second back etch can form a height difference of the preset height, thereby indirectly controlling the height of the third mask layer 106.

[0067] Continue to refer Figure 3 In step S370, a third mask layer 106 is formed, and the third mask layer 106 covers the remaining first pattern and the remaining second pattern.

[0068] based on Figure 9A After forming the third mask layer 106, the structure shown in FIG. Figure 10A The structure shown. Based on Figure 9B After forming the third mask layer 106, the structure shown in FIG. Figure 10B The structure shown.

[0069] Continue to refer Figure 3 In step S380 , the third mask layer 106 is planarized so that the top surface of the third mask layer 106 is flush with the top surface of the sidewall spacer 1032 .

[0070] based on Figure 10A The structure shown in FIG. 1 is flattened to obtain Figure 11A The structure shown. Based on Figure 10B The structure shown in FIG. 1 is flattened to obtain Figure 11B The structure shown.

[0071] It can be seen that by forming the third mask layer 106 and performing a planarization process, the first pattern and the second pattern, which originally had a height difference, are made to be of the same height. This can reduce the lateral offset or expansion of the gap 107 during the subsequent etching process. In addition, the top surface of the third mask layer 106 is made flush with the top surface of the sidewall spacer layer 1032, which actually avoids the problem of the third mask layer 106 covering the top surface of the sidewall spacer layer 1032 and causing the sidewall spacer layer 1032 to be unable to be selectively etched (if the third mask layer 106 covers the top surface of the sidewall spacer layer 1032, then when the sidewall spacer layer 1032 is subsequently etched, the third mask layer 106 needs to be etched first, which will etch away the third mask layer 106 in the first pattern portion and the second pattern portion, affecting the dimensional accuracy of the first and second patterns).

[0072] Continue to refer Figure 3 In step S390 , the sidewall spacer 1032 is removed by etching to form a gap 107 , and the substrate 101 is etched along the gap 107 using the remaining first pattern, the remaining second pattern, and the third mask layer 106 as a common mask.

[0073] The etching of the sidewall spacer 1032 is preferably performed mainly in the longitudinal direction, so as to have less influence on the first pattern and the second pattern structures on both sides of the sidewall spacer 1032, otherwise it may cause Figure 1C or Figure 1E In this exemplary embodiment, since the top surfaces of the first and second patterns on both sides of the sidewall spacer layer 1032 are at the same height, the tendency of the formed gap 107 to shift or expand laterally to one side during the etching process of the sidewall spacer layer 1032 can be reduced, so that the gap 107 can better retain the pattern and size of the sidewall spacer layer 1032 itself. In this way, the sizes of the first and second patterns retained on both sides can also be consistent with the originally defined sizes (such as the size of the first mask layer 102 and the size of the second mask layer 105), thereby ensuring the uniformity of the pattern size and the accuracy of control.

[0074] In addition, since the two sides of the sidewall spacer 1032 are respectively the composite mask layer of the first mask layer 102 / the third mask layer 106, and the composite mask layer of the second mask layer 105 / the third mask layer 106, during the etching process of the sidewall spacer 1032, due to the different etching selectivities for different materials in the composite mask layer, it is beneficial to improve the etching selectivity of the sidewall spacer 1032 to the composite mask layers on both sides, further improve the lateral offset or expansion of the gap 107, and can also improve the uniformity of the pattern size and the accuracy of control.

[0075] based on Figure 11A The structure shown in FIG. 1 is obtained after removing the sidewall spacer 1032. Figure 12A The structure shown. Based on Figure 11B The structure shown in FIG. 1 is obtained after removing the sidewall spacer 1032. Figure 12B The structure shown.

[0076] After removing the sidewall spacer 1032 to form the gap 107, the remaining first pattern, the remaining second pattern, and the third mask layer 106 serve as a common mask, and the substrate 101 is etched downward along the gap 107 to transfer the first pattern and the second pattern downward. For example, by transferring the first pattern and the second pattern into the substrate 101, an active area can be further formed in the first pattern portion, and shallow trench isolation can be formed in the second pattern portion.

[0077] The first mask layer 102, the second mask layer 105, and the third mask layer 106 can all be made of easily etchable materials, such as spin-on hardmask (SOH) materials, silicon oxynitride (SiON), silicon nitride (SiN), silicon oxide (such as SiO2), carbon, etc. In one embodiment, the material of the third mask layer 106 can be different from the material of the first mask layer 102 and the material of the second mask layer 105. This allows the first mask layer 102 and the third mask layer 105 to form a composite mask layer, and the second mask layer 105 and the third mask layer 106 to also form a composite mask layer. This helps to improve the etching selectivity of the sidewall spacer layer 1032 to the composite mask layers on both sides during the etching of the sidewall spacer layer 1032, thereby achieving a high aspect ratio etching process, further improving the problem of lateral offset or expansion of the gap 107, and improving the accuracy of pattern size control.

[0078] In one embodiment, one or more of the first mask layer 102, the second mask layer 105, and the third mask layer 106 can be prepared using a material having a significantly different etching selectivity from the gap layer 103. For example, the material of the gap layer 103 can be silicon oxide, and the gas used to etch the gap layer 103 includes one or more of tetrafluoromethane (CF4), trifluoromethane (CHF3), and oxygen (O2). These gases have a higher etching selectivity for silicon oxide than for spin-on hard mask materials and silicon nitride. Therefore, the first mask layer 102 and the second mask layer 105 can be made of a spin-on hard mask material, and the third mask layer 106 can be made of silicon nitride. This can further improve the accuracy of etching the sidewall gap layer 1032 and enhance the dimensional accuracy and consistency of the first and second patterns.

[0079] In one embodiment, the first pattern and the second pattern may be arranged alternately along the first direction, and a first dimension w1 of the first pattern along the first direction and a second dimension w2 of the second pattern along the first direction may be the same. By controlling the size of the first mask layer 102, the spacing between the first mask layer 102, the size of the sidewall spacer 1032, etc., the first dimension and the second dimension may be made equal.

[0080] In semiconductor manufacturing, the non-uniformity of the etching process can be defined as follows:

[0081] IMB=|Core-Gap|;

[0082] Here, "Core" represents the size of the core region, and "Gap" represents the size of the gap region, which are w1 and w2 respectively (w1 being "Core" or "Gap" depends on whether the first graphic defines a core region or a gap region). As can be seen, the closer w1 and w2 are, the lower the non-uniformity of the etching process, i.e., the higher the uniformity. Because this solution can more accurately control the first and second dimensions, it can achieve consistent or very small differences in the sizes of the core region and the gap region, improving the problem of poor uniformity and consistency of critical dimensions (CDs) in semiconductor manufacturing processes, especially in etching processes.

[0083] In one embodiment, the forming of the first mask layer 102 on the substrate 101 may include the following steps:

[0084] Depositing a first initial mask layer 102 ′ on the substrate 101 ;

[0085] A plurality of photoresist patterns are formed on the first preliminary mask layer 102' along a first direction. The size of the photoresist patterns along the first direction is the same as the first size. The size of the intervals between adjacent photoresist patterns along the first direction is a third size, which is larger than the first size.

[0086] The first initial mask layer 102 ′ is etched using the photoresist pattern as a mask to obtain a first mask layer 102 . The first mask layer 102 has a plurality of first patterns arranged at intervals along a first direction.

[0087] The first initial mask layer 102' is an unpatterned first mask layer 102, which can be a continuous film layer formed on the substrate 101. After the first initial mask layer 102' is deposited on the substrate 101, the first initial mask layer 102' can cover the entire top surface of the substrate 101. A plurality of photoresist patterns are formed on the first initial mask layer 102', and the photoresist patterns are the same as the patterns of the first patterns. Specifically, a photoresist (PR) material can be first coated on the first initial mask layer 102', and a mask having the first pattern is used for exposure to form the photoresist pattern. The size of the photoresist pattern along the first direction is a first size w1, and the spacing size is a third size w3. The third size w3 is the size of the second pattern (i.e., the second size w2, which is equal to the first size w1) plus twice the size of the gap between the first pattern and the second pattern. Therefore, the third size w3 is larger than the first size w1. The first initial mask layer 102' can be dry-etched under the masking effect of the photoresist pattern to remove the portion of the first initial mask layer 102' not covered by the photoresist pattern, and then the photoresist pattern is removed by a cleaning process to form a first mask layer 102 having a first pattern. Figure 5 Thus, the position and size of the photoresist pattern can be strictly controlled based on the photolithography process and transferred to the first mask layer 102, so that the first mask layer 102 forms a precise first pattern.

[0088] In one embodiment, after depositing the first initial mask layer 102' on the substrate 101, the method for preparing the semiconductor structure may further include the following steps:

[0089] forming an initial capping layer 108' covering a top surface of the first initial mask layer 102';

[0090] The photoresist pattern is formed on the top surface of the initial cap layer 108 '; when the first initial mask layer 102 'is etched using the photoresist pattern as a mask, the initial cap layer 108 'is also etched using the photoresist pattern as a mask to form the cap layer 108, reference Figure 13 As shown, the first mask layer 102 and the cap layer 108 together have a plurality of first patterns arranged at intervals along a first direction.

[0091] Accordingly, the first etching back of the second mask layer 102 and the top gap layer 1031 until the top surface of the first pattern is exposed may include the following steps:

[0092] The second mask layer 102 , the top gap layer 1031 and the capping layer 108 are first etched back until the top surface of the first pattern is exposed.

[0093] After the gap layer 103 is formed, the depth of the groove 104 is increased due to the presence of the cap layer 108. After the second mask layer 105 is formed, Figure 14 As shown, the first mask layer 102 is covered with three film layers, namely the cap layer 108, the top gap layer 1031, and the second mask layer 105. These three film layers can be etched to expose the top surface of the first pattern. By adding the cap layer 108, on the one hand, the etching selectivity of the first back etch can be optimized, making the first back etch more complete, eliminating the inclined rounded corners that may be generated at the top of the sidewall gap layer 1032, and reducing structural defects. On the other hand, the height difference between the top surfaces of the first pattern and the second pattern is made more controllable. If the cap layer 108 is not present, the height difference is generated only based on the different etching selectivities of the top gap layer 1031 and the second mask layer 102 in the first back etch. The height difference in different areas may be uneven. The addition of the cap layer 108 makes the height difference more uniform and controllable. In addition, the cap layer 108 also increases the depth of the groove 104, increasing the height difference between the top surface of the first pattern and the top surface of the second pattern, which is conducive to the subsequent control of the height of the third mask layer 106 of the first pattern portion and the second pattern portion.

[0094] The material and thickness of the cap layer 108 can be determined according to specific requirements. For example, the cap layer 108 can be made of silicon oxide, which can be the same material as the gap layer 103 .

[0095] In one embodiment, the forming of the gap layer 103 may include the following steps:

[0096] A top spacer 1031 covering the top surface of the first mask layer 102 and a sidewall spacer 1032 covering the sidewall of the first mask layer 102 are formed, and the thickness of the sidewall spacer 1032 along the first direction is controlled to be 1 / 2 of the difference between the third dimension and the first dimension.

[0097] Among them, the thickness of the single layer of the sidewall spacer 1032 along the first direction, that is, the thickness of the sidewall spacer 1032 on the side wall of one side of the first mask layer 102, is equal to (w3-w1) / 2, and w1 is equal to w2. In this way, the width of the groove 104 surrounded by the sidewall spacer 1032 on the side wall of the adjacent first mask layer 102 is w2 along the first direction, which is the size of the second pattern. It can be seen that by controlling the thickness of the sidewall spacer 1032, the size of the groove 104 and the second mask layer 105 can be indirectly controlled, thereby defining the size of the desired second pattern. For example, the sidewall spacer 10323 can be formed by physical vapor deposition. By controlling the process parameters of physical vapor deposition, such as deposition time, power, chamber temperature, etc., the sidewall spacer 1032 of the desired thickness can be obtained.

[0098] In one embodiment, an etch stop layer 109 and a film layer 110 to be etched located above the etch stop layer 109 are formed in the substrate 101. Accordingly, etching the substrate 101 along the gap 107 using the remaining first pattern, the remaining second pattern, and the third mask layer 106 as a common mask may include the following steps:

[0099] The remaining first pattern, the remaining second pattern and the third mask layer 106 are used as a common mask, and the etching stop layer 109 is used as an etching end point to etch the film layer 110 to be etched in the substrate 101 along the gap 107 .

[0100] The etch stop layer 109 can serve as the etching endpoint during the downward transfer of the first and second patterns, and a dielectric such as silicon oxide can be used. The film layer 110 to be etched can be a mask layer different from the first mask layer 102, the second mask layer 105, and the third mask layer 106, or can be a film layer used to form a specific functional structure. The etch stop layer 109 and the film layer to be etched 110 can be located below the first mask layer 102. When forming the gap 107 and etching downward the substrate 101, the first and second patterns can be transferred to the film layer 110 to be etched, with the etch stop layer 109 as the endpoint. This can increase the structural depth of the first and second patterns, which is conducive to achieving precise pattern transfer. In one embodiment, the film layer 110 to be etched can include multiple film layers. For example, the film layer 110 to be etched can be a composite layer of carbon and silicon oxynitride. The composite layer is beneficial for increasing the aspect ratio of etching and improving the accuracy of pattern transfer when performing pattern transfer of the first and second patterns.

[0101] In one embodiment, after etching the film layer 110 to be etched in the substrate 101 along the gap 107, the remaining film layer 110 to be etched forms a fourth mask layer or a plurality of bit lines. Specifically, if the film layer 110 to be etched is a film layer or a composite film layer of a mask material, after etching the film layer 110 along the gap 107, it forms a fourth mask layer, which can be used to further transfer the first pattern and the second pattern downward. For example, an active region can be further formed in the region of the substrate 101 below the film layer 110 to be etched, thereby improving the dimensional accuracy of the relevant structure. If the film layer 110 to be etched is a film layer of a bit line material (such as metal, doped polysilicon, conductive metal oxide, conductive metal silicide, conductive metal nitride, or a combination thereof), after etching the film layer 110 along the gap 107, it forms a plurality of bit lines, thereby improving the dimensional accuracy of the bit lines and ensuring the consistency of the bit line dimensions.

[0102] In one embodiment, the etching selectivity between the common mask and the fourth mask layer can be greater than the etching selectivity between the common mask and the substrate 101, and / or the etching selectivity between the fourth mask layer and the substrate 101 can be greater than the etching selectivity between the common mask and the substrate 101. Therefore, compared to a structure without a fourth mask layer (e.g., a structure in which the common mask is directly located on the substrate 101), in a structure with a fourth mask layer, the transfer accuracy of the first pattern and the second pattern can be further improved during the process of etching the film layer 110 to be etched along the common mask to form the fourth mask layer, and etching the substrate 101 along the fourth mask layer.

[0103] In one embodiment, after etching the film layer 110 to be etched in the substrate 101 along the gap 107 , the method for preparing the semiconductor structure may further include the following steps:

[0104] All film layers above the film layer 110 to be etched are removed.

[0105] The film layers above the film layer to be etched 110 may include a first mask layer 102, a second mask layer 105, a third mask layer 106, and may also include a residual gap layer 103 located at the bottom of the second mask layer 105. These film layers can be removed by etching to completely expose the film layer to be etched 110. This can simplify the complexity of the semiconductor structure and reduce the adverse effects of the complex film layer structure on subsequent processes.

[0106] In one embodiment, in the presence of the film layer 110 to be etched, the etching to remove the sidewall spacer layer 1032 to form the gap 107 may include the following steps:

[0107] The etching end point is the film layer 110 to be etched, and the sidewall spacer layer 1032 is removed by etching to form a gap 107 .

[0108] That is to say, when etching the sidewall spacer layer 1032, the film layer above the film layer to be etched 110 in the gap 107 (mainly the sidewall spacer layer 1032) can be completely removed, and the etching end point is determined by the film layer to be etched 110 below the sidewall spacer layer 1032, which makes the etching process of the sidewall spacer layer 1032 easier to control.

[0109] In one embodiment, when etching the substrate 101, the region of the substrate 101 exposed by the gap 107 forms a first trench. The first trench is used to form a shallow trench isolation structure, and the region of the substrate 101 covered by the common mask forms an active area. For example, the region of the substrate 101 exposed by the gap 107 can be etched along the common mask to form a first trench. The first trench is then filled with an isolation material (e.g., an insulating material such as silicon oxide) to form a shallow trench isolation structure. The common mask has a first pattern and a second pattern. The region of the substrate 101 covered by the common mask can form an active area. This active area can be the active area of ​​a memory cell, for example, the source, drain, and channel regions of a transistor in a DRAM memory cell. The active area has a first pattern and a second pattern. Exemplarily, the common mask can be removed, and the exposed region of the substrate 101 (i.e., the region of the substrate 101 outside the shallow trench isolation structure) can be used to form an active area. For example, the active area can be formed by doping using a process such as ion implantation, or the substrate 101 may have already been doped. This can improve the dimensional accuracy of the active area and the shallow trench isolation structure, and ensure the dimensional consistency of the active area.

[0110] In one embodiment, when etching the substrate 101, a second trench is formed in the region of the substrate 101 exposed by the gap 107, and the second trench is used to form a buried word line. Among them, a buried word line can be arranged across the channel region of multiple transistors in the third direction. Exemplarily, the region of the substrate 101 exposed by the gap 107 can be etched along a common mask to form a second trench, and a word line material (such as metal, doped polysilicon, conductive metal oxide, conductive metal silicide, conductive metal nitride or a combination thereof) is filled in the first trench to form a buried word line. This can improve the dimensional accuracy of the buried word line and ensure the dimensional consistency of the buried word line.

[0111] In one embodiment, the method for preparing the semiconductor structure can refer to Figures 15 to 26 As shown, it includes the following processes:

[0112] refer to Figure 15 As shown, a substrate 101 is provided. An etch stop layer 109, a film layer to be etched 110 (including a carbon layer 110a and a silicon oxynitride layer 110b), a first initial mask layer 102', an initial cap layer 108', and a photoresist region 111 are sequentially formed on the substrate 101. The etch stop layer 109 can be made of SiN, SiO2, or the like. The first initial mask layer 102' can be made of SOH material, and the initial cap layer 108' can be made of silicon oxide.

[0113] refer to Figure 16 As shown, a photoresist pattern having a first pattern is formed in the photoresist region 111 by photolithography.

[0114] refer to Figure 17 As shown, the initial capping layer 108' and the first initial mask layer 102' are dry-etched to form the capping layer 108 and the first mask layer 102, thereby transferring the photoresist pattern into the capping layer 108 and the first mask layer 102 to form a first pattern.

[0115] refer to Figure 18 As shown, a spacer layer 103 is deposited, including a sidewall spacer layer 1032 covering the sidewalls of the first mask layer 102 and a top spacer layer 1031 covering the top surface of the cap layer 108. The spacer layer 103 may also cover the portion of the top of the silicon oxynitride layer 110b not blocked by the first mask layer 102. The spacer layer 103 may be made of silicon oxide, the same as the cap layer 108. Between adjacent first patterns, the area enclosed by the sidewall spacer layer 1032 forms a groove 104.

[0116] refer to Figure 19 As shown, a second mask layer 105 is deposited to fill the grooves 104 between adjacent gap layers 103 and cover the tops of the gap layers 103. The second mask layer 105 may also be planarized to make the upper surface of the entire structure flat, which facilitates control of the subsequent etch-back. The second mask layer 105 may be made of SOH material, the same as the first mask layer 102.

[0117] refer to Figure 20A or Figure 20B As shown, the second mask layer 105, the top gap layer 1031 and the cap layer 108 are first etched back until the top surface of the first pattern is exposed, and the second mask layer 105 remaining in the groove 104 is used as the second pattern. Due to the different selectivity of the etching gas to the top gap layer 1031, the cap layer 108 and the second mask layer 105 during the etching process, a height difference will be caused. Specifically, if the etching rate of the top gap layer 1031 and the cap layer 108 is greater than the etching rate of the second mask layer 105, a height difference will be formed. Figure 20A The top surface of the second pattern is higher than the top surface of the first pattern. If the etching rate of the second mask layer 105 is greater than the etching rate of the top gap layer 1031 and the cap layer 108, a Figure 20B The top surface of the first figure is higher than the top surface of the second figure.

[0118] refer to Figure 21A or Figure 21B As shown, O2 can be used as the main etching gas to perform a second back etching on the first and second patterns. By controlling the etching time, the top surface of the sidewall spacer 1032 is higher than the top surface of the remaining first pattern and the top surface of the remaining second pattern. Figure 20A The structure shown is formed after the second etching Figure 21A The structure shown, Figure 20B The structure shown is formed after the second etching Figure 21B The structure shown.

[0119] refer to Figure 22A or Figure 22B As shown, a third mask layer 106 is formed, such as SiN, to cover the top of the first mask layer 102 , the top of the second mask layer 105 , and the top of the sidewall spacer 1032 . Figure 21A After forming the third mask layer 106, the structure shown in FIG. Figure 22A The structure shown, Figure 21B After forming the third mask layer 106, the structure shown in FIG. Figure 22B The structure shown.

[0120] refer to Figure 23A or Figure 23B As shown, the third mask layer 106 is planarized by etching, chemical mechanical polishing, etc., so that the third mask layer 106 is flush with the top surface of the sidewall spacer 1032. In this way, there is no height difference between the first pattern and the second pattern on both sides of the sidewall spacer 1032. Figure 22A The structure shown in FIG. 1 is obtained after the third mask layer 106 is planarized. Figure 23A The structure shown, Figure 22B The structure shown in FIG. 1 is obtained after the third mask layer 106 is planarized. Figure 23B The structure shown.

[0121] refer to Figure 24A or Figure 24B As shown, SiN and SOH materials are used as etching stops to remove the sidewall spacer layer 1032 and form a gap 107. Figure 23A The structure shown in FIG1 is obtained after etching the sidewall spacer 1032. Figure 24A The structure shown, Figure 23B The structure shown in FIG1 is obtained after etching the sidewall spacer 1032. Figure 24B The structure shown.

[0122] refer to Figure 25A or Figure 25B As shown, the carbon layer 110a and the silicon oxynitride layer 110b are etched using the etch stop layer 109 as an etching barrier to transfer the first pattern and the second pattern downward. Figure 24A The structure shown in FIG. 1 is obtained by etching the carbon layer 110a and the silicon oxynitride layer 110b. Figure 25A The structure shown, Figure 24B The structure shown in FIG. 1 is obtained by etching the carbon layer 110a and the silicon oxynitride layer 110b. Figure 25B The structure shown.

[0123] It should be understood that during the aforementioned etching of the sidewall spacer layer 1032 and the etching of the carbon layer 110a and the silicon oxynitride layer 110b, the third mask layer 106 located on top may also be etched and thinned. Although this will reduce the depth of the gap 107, it will not affect the shape and width of the gap 107. In fact, it is precisely because of the etching barrier effect of the third mask layer 106 with the same height on both sides of the sidewall spacer layer 1032 that the shape and size of the gap 107 are maintained.

[0124] Finally, the remaining first mask layer 102, second mask layer 105, third mask layer 106, and gap layer 103 on the carbon layer 110a and silicon oxynitride layer 110b are removed to obtain the following: Figure 26 In the structure shown, the carbon layer 110a and the silicon oxynitride layer 110b have a first pattern and a second pattern.

[0125] The process ends. Subsequently, the carbon layer 110a and the silicon oxynitride layer 110b can be used as masks to further transfer the first pattern and the second pattern downward to form a desired device structure.

[0126] The thickness of the above-mentioned various film layers can be between 5-500 nm, which can be determined according to the process requirements.

[0127] Exemplary embodiments of the present disclosure also provide a semiconductor structure. Figure 27 As shown, the semiconductor structure may include: a substrate 101 and a pattern layer 112. The pattern layer 112 is formed on the substrate 101 and includes core regions 112a and spacer regions 112b arranged alternately along a preset direction. The size of the core region 112a along the preset direction is the same as the size of the spacer region 112b along the preset direction. The pattern layer 112 may be any mask layer after etching the substrate 101, such as Figure 26 The film layer 110 to be etched (including the carbon layer 110a and the silicon oxynitride layer 110b) is etched in the core region 112a. The size of the core region 112a along the first direction may be a first size w1, and the size of the spacer region 112b along the first direction may be a second size w2. This exemplary embodiment allows for precise control of w1 and w2 to ensure consistency. This allows for consistency or minimal difference in the size of the core region 112a and the spacer region 112b, which is beneficial for improving the dimensional uniformity and consistency of subsequently formed device structures and enhancing semiconductor performance.

[0128] The exemplary embodiments of the present disclosure further provide a memory, which may include the semiconductor structure of the exemplary embodiment. The memory may be a volatile memory such as DRAM, or a non-volatile memory such as NAND Flash.

[0129] It should be understood that the present disclosure is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and variations can be made without departing from the scope thereof. This application is intended to cover any variation, use, or adaptation of the technical solution that follows the general principles of this disclosure and includes common knowledge or customary technical means in the art that are not disclosed herein. The contents of this specification are to be regarded as exemplary only, and the scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first mask layer on the substrate, wherein the first mask layer has a plurality of first patterns arranged at intervals; forming a gap layer, the gap layer comprising at least a top gap layer covering a top surface of the first mask layer and a sidewall gap layer covering a sidewall of the first mask layer, so as to form a groove between adjacent first patterns; forming a second mask layer, wherein the second mask layer at least fills the groove; Performing a first etching back on the second mask layer and the top gap layer until the top surface of the first pattern is exposed, and the remaining second mask layer in the groove serves as the second pattern, and a height difference exists between the top surface of the first pattern and the top surface of the second pattern; Performing a second etching back on the first pattern and the second pattern, so that the top surface of the sidewall spacer layer is higher than the top surface of the remaining first pattern and the top surface of the remaining second pattern; forming a third mask layer, wherein the third mask layer covers the remaining first pattern and the remaining second pattern; performing a planarization process on the third mask layer so that a top surface of the third mask layer is flush with a top surface of the sidewall spacer layer; The sidewall spacer layer is removed by etching to form a gap, and the substrate is etched along the gap using the remaining first pattern, the remaining second pattern, and the third mask layer as a common mask.

2. The method according to claim 1, characterized in that The first graphics and the second graphics are arranged alternately along a first direction, and a first size of the first graphics along the first direction is the same as a second size of the second graphics along the first direction.

3. The method according to claim 2, characterized in that The step of forming a first mask layer on the substrate comprises: depositing a first initial mask layer on the substrate; forming a plurality of photoresist patterns arranged along the first direction on the first initial mask layer, wherein a size of the photoresist patterns along the first direction is the same as the first size, and a size of intervals between adjacent photoresist patterns along the first direction is a third size, and the third size is larger than the first size; The first initial mask layer is etched using the photoresist pattern as a mask to obtain the first mask layer, wherein the first mask layer has a plurality of the first patterns arranged at intervals along the first direction.

4. The method according to claim 3, characterized in that After depositing the first initial mask layer on the substrate, the method further includes: forming an initial capping layer covering a top surface of the first initial mask layer; The photoresist pattern is formed on the top surface of the initial cover layer; when etching the first initial mask layer using the photoresist pattern as a mask, the initial cover layer is also etched using the photoresist pattern as a mask to form a cover layer, and the first mask layer and the cover layer together have a plurality of first patterns spaced apart along the first direction; The performing a first etching back on the second mask layer and the top gap layer until the top surface of the first pattern is exposed includes: The second mask layer, the top gap layer and the cap layer are first etched back until the top surface of the first pattern is exposed.

5. The method according to claim 3, characterized in that The forming of the gap layer comprises: The top spacer covering the top surface of the first mask layer and the sidewall spacer covering the sidewall of the first mask layer are formed, and the single layer thickness of the sidewall spacer along the first direction is controlled to be 1 / 2 of the difference between the third size and the first size.

6. The method according to claim 1, characterized in that The forming of the second mask layer includes: The second mask layer is formed to fill the groove and cover the top surface of the top gap layer.

7. The method according to claim 1, characterized in that The material of the third mask layer is different from the material of the first mask layer and the material of the second mask layer.

8. The method according to claim 1, characterized in that An etch stop layer and a film layer to be etched located above the etch stop layer are formed in the substrate; Using the remaining first pattern, the remaining second pattern, and the third mask layer as a common mask and etching the substrate along the gap, comprising: The remaining first pattern, the remaining second pattern and the third mask layer are used as a common mask, the etching stop layer is used as an etching end point, and the film layer to be etched in the substrate is etched along the gap.

9. The method according to claim 8, characterized in that The film layer to be etched is etched to form a fourth mask layer or a plurality of bit lines.

10. The method according to claim 1, characterized in that When etching the substrate, the substrate region exposed by the gap forms a first trench, and the first trench is used to form a shallow trench isolation structure; the substrate region covered by the common mask forms an active area; Or when etching the substrate, the substrate region exposed by the gap forms a second trench, and the second trench is used to form a buried word line.

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