Antifuse storage structure and array structure thereof and respective operation methods, memory

Abstract

The present disclosure provides an antifuse storage structure and an operating method thereof, an antifuse storage array structure and an operating method thereof, and a memory. The antifuse storage structure includes: an active area including a first portion, a second portion, a third portion, a fourth portion, and a fifth portion arranged in sequence along a first direction; a first antifuse structure, a second antifuse structure, and a selection transistor disposed on the active area, the first antifuse structure including a first antifuse gate overlapping with the first portion, the second antifuse structure including a second antifuse gate overlapping with the fifth portion, and the selection transistor including a selection gate overlapping with the third portion; a first bit line and a second bit line arranged at intervals along a second direction, the first bit line being electrically connected to the fourth portion, and the second bit line being electrically connected to the second portion. The embodiments of the present disclosure are at least beneficial in reducing the layout area of ​​the antifuse storage structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to an anti-fuse storage structure, an array structure thereof, respective operation methods, and a memory. Background Art

[0002] OTP memory can be divided into fuse-type memory and antifuse-type memory based on its characteristics. Before programming, the memory cell of a fuse-type memory is in a low-resistance storage state; after programming, the memory cell has a high-resistance storage state. Before programming, the memory cell of an antifuse-type memory has a high-resistance storage state; after programming, the memory cell has a low-resistance storage state.

[0003] With the continuous development of semiconductor technology, there is a need to improve the storage unit in the anti-fuse type memory so as to reduce the area of ​​the anti-fuse type memory and save valuable space for other circuits. Summary of the Invention

[0004] The embodiments of the present disclosure provide an antifuse storage structure and an operation method thereof, an antifuse storage array structure and an operation method thereof, and a memory, which are at least beneficial in reducing the layout area of ​​the antifuse storage structure and improving the electrical performance of the antifuse storage structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides an anti-fuse storage structure, comprising: an active area, wherein the active area includes a first part, a second part, a third part, a fourth part and a fifth part arranged in sequence along a first direction; a first anti-fuse structure, a second anti-fuse structure and a selection transistor arranged on the active area, wherein the first anti-fuse structure includes a first anti-fuse gate overlapping with the first part, the second anti-fuse structure includes a second anti-fuse gate overlapping with the fifth part, the selection transistor includes a selection gate overlapping with the third part, the first anti-fuse gate, the selection gate and the second anti-fuse gate are arranged at intervals along the first direction; a first bit line and a second bit line are arranged at intervals along the second direction, the first bit line is electrically connected to the fourth part, the second bit line is electrically connected to the second part, and the first direction and the second direction intersect.

[0006] In some embodiments, in the second direction, the width of the third portion is greater than the width of the first portion, and the width of the third portion is greater than the width of the fifth portion.

[0007] In some embodiments, in the second direction, the width of the first portion is the first width, the width of the second portion is the second width, the width of the third portion is the third width, the width of the fourth portion is the fourth width, and the width of the fifth portion is the fifth width; wherein, the second width is greater than or equal to the first width and less than or equal to the third width, and the fourth width is greater than or equal to the fifth width and less than or equal to the third width.

[0008] In some embodiments, the first portion and the fifth portion are offset in the second direction.

[0009] In some embodiments, the first bit line and the second bit line both extend along the first direction, and the anti-fuse storage structure further includes: a first conductive plug located above the fourth portion, and the first bit line is electrically connected to the fourth portion through the first conductive plug; a second conductive plug located above the second portion, and the second bit line is electrically connected to the second portion through the second conductive plug.

[0010] In some embodiments, the first conductive plug and the second conductive plug are staggered in the second direction.

[0011] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides an operating method for an anti-fuse storage structure, comprising: providing an anti-fuse storage structure as described in any one of the above items; and performing a programming operation or a reading operation on the anti-fuse storage structure.

[0012] In some embodiments, performing the programming operation on the anti-fuse storage structure includes: providing a first voltage to the selection gate, providing a second voltage to the first anti-fuse gate, and providing a third voltage to the first bit line, so as to perform the programming operation on the first anti-fuse structure; or, providing the first voltage to the selection gate, providing the second voltage to the second anti-fuse gate, and providing the third voltage to the second bit line, so as to perform the programming operation on the second anti-fuse structure; wherein the first voltage is the turn-on voltage of the selection transistor, and the level difference between the second voltage and the third voltage is not less than the breakdown voltage of the first anti-fuse structure, and is not less than the breakdown voltage of the second anti-fuse structure.

[0013] In some embodiments, during the programming operation on the first anti-fuse structure, a voltage signal is not provided to the second bit line, and a voltage signal is not provided to the second anti-fuse gate, or the third voltage is provided to the second anti-fuse gate; during the programming operation on the second anti-fuse structure, a voltage signal is not provided to the first bit line, and a voltage signal is not provided to the first anti-fuse gate, or the third voltage is provided to the first anti-fuse gate.

[0014] In some embodiments, performing the read operation on the anti-fuse storage structure includes: providing the first voltage to the selection gate, providing the fourth voltage to the first anti-fuse gate, providing the fifth voltage to the first bit line, detecting the current size in the first anti-fuse structure through the first anti-fuse gate to determine the data information stored in the first anti-fuse structure, so as to perform the read operation on the first anti-fuse structure; or, providing the first voltage to the selection gate, providing the fourth voltage to the second anti-fuse gate, providing the fifth voltage to the second bit line, detecting the current size in the second anti-fuse structure through the second anti-fuse gate to determine the data information stored in the second anti-fuse structure, so as to perform the read operation on the second anti-fuse structure; wherein the level value of the fifth voltage is greater than the level value of the fourth voltage and less than the level value of the first voltage.

[0015] In some embodiments, during the read operation on the first anti-fuse structure, a voltage signal is not provided to the second bit line, and a voltage signal is not provided to the second anti-fuse gate, or the fifth voltage is provided to the second anti-fuse gate; during the read operation on the second anti-fuse structure, a voltage signal is not provided to the first bit line, and a voltage signal is not provided to the first anti-fuse gate, or the fifth voltage is provided to the first anti-fuse gate.

[0016] According to some embodiments of the present disclosure, on another aspect, an anti-fuse storage array structure is further provided, comprising a plurality of anti-fuse storage structures arranged in an array along a first direction and a second direction, each of the anti-fuse storage structures comprising an anti-fuse storage structure as described in any one of the above items; wherein the anti-fuse storage structures in the same column in the first direction share the first bit line and the second bit line; the anti-fuse storage structures in the same row in the second direction share the first programming line, the second programming line and the selection control line, the first programming line comprising the first anti-fuse gate of each of the anti-fuse storage structures in the same row, the second programming line comprising the second anti-fuse gate of each of the anti-fuse storage structures in the same row, and the selection control line comprising the selection gate of each of the anti-fuse storage structures in the same row.

[0017] According to some embodiments of the present disclosure, on the other hand, an operating method of an anti-fuse storage array structure is further provided, comprising: providing an anti-fuse storage array structure as described above; performing programming operations or reading operations on the anti-fuse storage structures in the same row of the anti-fuse storage array structure.

[0018] In some embodiments, the programming operation on the antifuse storage structures in the same row in the antifuse storage array structure includes: providing a first voltage to the selection control line corresponding to the antifuse storage structure in the row, providing a second voltage to the first programming line corresponding to the antifuse storage structure in the row, providing a third voltage to the first bit line corresponding to the first antifuse structure that needs to be programmed in the antifuse storage structure in the row, and providing a sixth voltage to the first bit line corresponding to the first antifuse structure that does not need to be programmed in the antifuse storage structure in the row, so as to perform the programming operation on the first antifuse structure in the antifuse storage structure in the row; or providing the first voltage to the selection control line corresponding to the antifuse storage structure in the row, providing a sixth voltage to the first bit line corresponding to the first antifuse structure that does not need to be programmed in the antifuse storage structure in the row. The second programming line provides the second voltage, provides the third voltage to the second bit line corresponding to the second anti-fuse structure that needs to be programmed in the anti-fuse storage structure in this row, and provides the sixth voltage to the second bit line corresponding to the second anti-fuse structure that does not need to be programmed in the anti-fuse storage structure in this row, so as to perform the programming operation on the second anti-fuse structure in the anti-fuse storage structure in this row; wherein, the first voltage is the turn-on voltage of the selection transistor, the level difference between the second voltage and the third voltage is not less than the breakdown voltage of the first anti-fuse structure, and not less than the breakdown voltage of the second anti-fuse structure, and the level difference between the second voltage and the sixth voltage is less than the breakdown voltage of the first anti-fuse structure, and less than the breakdown voltage of the second anti-fuse structure.

[0019] In some embodiments, in the step of performing the programming operation, a voltage signal is not provided to the selection control line corresponding to other rows of anti-fuse storage structures, a voltage signal is not provided to the first programming line and the second programming line corresponding to other rows of anti-fuse storage structures, or the third voltage is provided to both the first programming line and the second programming line corresponding to other rows of anti-fuse storage structures; in the process of performing the programming operation on the first anti-fuse structure in the row of anti-fuse storage structures, a voltage signal is not provided to all the second bit lines, a voltage signal is not provided to the second programming line corresponding to the anti-fuse storage structure in the row, or the third voltage is provided to the second programming line corresponding to the anti-fuse storage structure in the row; in the process of performing the programming operation on the second anti-fuse structure in the row of anti-fuse storage structures, a voltage signal is not provided to all the first bit lines, a voltage signal is not provided to the first programming line corresponding to the anti-fuse storage structure in the row, or the third voltage is provided to the first programming line corresponding to the anti-fuse storage structure in the row.

[0020] In some embodiments, performing a read operation on the antifuse storage structures in the same row in the antifuse storage array structure includes: providing the first voltage to the selection control line corresponding to the antifuse storage structure in the row, providing the fourth voltage to the first programming line corresponding to the antifuse storage structure in the row, providing the fifth voltage to the first bit line corresponding to the first antifuse structure in the antifuse storage structure in the row that needs to be read, and providing the seventh voltage to the first bit line corresponding to the first antifuse structure in the antifuse storage structure in the row that does not need to be read, so as to perform the read operation on the first antifuse structure in the antifuse storage structure in the row; or providing the seventh voltage to the first bit line corresponding to the antifuse structure in the antifuse storage structure in the row. The first voltage is provided to the selection control line corresponding to the row anti-fuse storage structure, the fourth voltage is provided to the second programming line corresponding to the row anti-fuse storage structure, the fifth voltage is provided to the second bit line corresponding to the second anti-fuse structure that needs to be read in the row anti-fuse storage structure, and the seventh voltage is provided to the second bit line corresponding to the second anti-fuse structure that does not need to be read in the row anti-fuse storage structure, so as to perform the reading operation on the second anti-fuse structure in the row anti-fuse storage structure; wherein the level value of the fifth voltage is greater than the level value of the fourth voltage and less than the level value of the first voltage, and the level value of the seventh voltage is not greater than the level value of the fifth voltage.

[0021] In some embodiments, in the step of performing the read operation, a voltage signal is not provided to the selection control lines corresponding to other rows of anti-fuse storage structures, or the fourth voltage is provided to the selection control lines corresponding to other rows of anti-fuse storage structures; in the process of performing the read operation on the first anti-fuse structure in the row of anti-fuse storage structures, a voltage signal is not provided to all the second bit lines, a voltage signal is not provided to the first programming lines corresponding to other rows of anti-fuse storage structures, and the fifth voltage or the seventh voltage is provided to all the second programming lines; in the process of performing the read operation on the second anti-fuse structure in the row of anti-fuse storage structures, a voltage signal is not provided to all the first bit lines, a voltage signal is not provided to the second programming lines corresponding to other rows of anti-fuse storage structures, and the fifth voltage or the seventh voltage is provided to all the first programming lines.

[0022] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a memory, comprising the anti-fuse storage structure as described in any one of the above items, or comprising the anti-fuse storage array structure as described in the above items.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0024] In one aspect, a novel layout of an antifuse memory structure is provided. Two bit lines, namely a first bit line and a second bit line, and a select transistor are used to control both a first antifuse structure and a second antifuse structure, for example, to program or read the first antifuse structure and / or the second antifuse structure. It will be appreciated that an antifuse memory structure includes two memory cells, namely a first antifuse structure and a second antifuse structure, and control of the two memory cells is achieved with the assistance of a select transistor and two bit lines.

[0025] On the other hand, only one select transistor needs to be arranged, which helps reduce the overall length of the anti-fuse storage structure in the first direction, thereby helping to reduce the overall layout area of ​​the anti-fuse storage structure. In addition, two bit lines are arranged in a spaced relationship in the second direction, with the first bit line electrically connected to the fourth portion, the second bit line electrically connected to the second portion, and the third portion, the second portion, and the fourth portion all in contact with each other. Therefore, the third portion is at least directly opposite to the first bit line and the second bit line, that is, the width of the third portion in the second direction is greater than or equal to the sum of the widths of the first bit line and the second bit line in the second direction. This helps to increase the width of the third portion in the second direction, that is, increase the width of the channel region in the select transistor, thereby increasing the current driving capability of the select transistor and thus improving the electrical performance of the anti-fuse storage structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 1a is a schematic diagram of a partial top view of an antifuse storage structure provided by an embodiment of the present disclosure;

[0028] Figure 1 1b is a schematic top view of an active area in an antifuse storage structure provided by an embodiment of the present disclosure;

[0029] Figure 2 Two partial top-view structural diagrams of an antifuse storage structure provided in one embodiment of the present disclosure;

[0030] Figure 3 Two other partial top-view structural diagrams of the antifuse storage structure provided in one embodiment of the present disclosure;

[0031] Figure 4 Two more partial top-view structural schematic diagrams of the antifuse storage structure provided in one embodiment of the present disclosure;

[0032] Figure 5 A schematic top view of an antifuse storage structure provided in one embodiment of the present disclosure;

[0033] Figure 6 Two simplified circuit diagrams for performing programming operations on an anti-fuse storage structure according to another embodiment of the present disclosure;

[0034] Figure 7 Two simplified circuit diagrams for performing a read operation on an antifuse storage structure according to another embodiment of the present disclosure;

[0035] Figure 8 A schematic top view of an antifuse memory array structure provided in yet another embodiment of the present disclosure;

[0036] Figure 9 A simplified circuit diagram of a programming operation performed on an anti-fuse memory array structure according to another embodiment of the present disclosure;

[0037] Figure 10Another circuit diagram for performing a programming operation on an anti-fuse memory array structure according to another embodiment of the present disclosure;

[0038] Figure 11 A simplified circuit diagram of a read operation performed on an antifuse memory array structure according to another embodiment of the present disclosure;

[0039] Figure 12 Another circuit diagram of performing a read operation on an antifuse memory array structure is provided in accordance with another embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] As known from the background art, the memory cells in the anti-fuse type memory need to be improved, and the electrical performance of the anti-fuse type memory needs to be improved.

[0041] The present disclosure provides an antifuse memory structure, an array structure thereof, and respective operating methods and a memory. The antifuse memory structure, on the one hand, provides a novel layout for the antifuse memory structure. Two bit lines, namely a first bit line and a second bit line, and a single select transistor can be used to control both the first antifuse structure and the second antifuse structure, for example, to implement programming or reading operations on the first antifuse structure and / or the second antifuse structure. Furthermore, the need for only one select transistor facilitates reducing the overall length of the antifuse memory structure in the first direction, thereby reducing the overall layout area of ​​the antifuse memory structure.

[0042] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0043] An embodiment of the present disclosure provides an anti-fuse storage structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 1a is a schematic diagram of a partial top view of an antifuse storage structure provided by an embodiment of the present disclosure; Figure 1 1b is a schematic top view of an active area in an antifuse storage structure provided by an embodiment of the present disclosure; Figure 2 Two partial top-view structural diagrams of an antifuse storage structure provided in one embodiment of the present disclosure; Figure 3 Two other partial top-view structural diagrams of the antifuse storage structure provided in one embodiment of the present disclosure; Figure 4 Two more partial top-view structural schematic diagrams of the antifuse storage structure provided in one embodiment of the present disclosure; Figure 5A schematic top view of an antifuse storage structure provided in one embodiment of the present disclosure.

[0044] refer to Figures 1 to 5 The anti-fuse storage structure includes: an active area 100, wherein the active area 100 includes a first portion 110, a second portion 120, a third portion 130, a fourth portion 140 and a fifth portion 150 arranged in sequence along the first direction X; a first anti-fuse structure 101, a second anti-fuse structure 102 and a selection transistor 103 arranged on the active area 100, wherein the first anti-fuse structure 101 includes a first anti-fuse gate 111 overlapping with the first portion 110, and the second anti-fuse structure 102 ... The first portion 140 and the second portion 120 are electrically connected to each other, and the first direction X and the second direction Y intersect.

[0045] It is understood that the plane defined by the first direction X and the second direction Y is a reference plane. The first antifuse gate 111 overlapping the first portion 110 means that the orthographic projection of the first portion 110 on the reference plane is located within the orthographic projection of the first antifuse gate 111 on the reference plane. The second antifuse gate 112 overlapping the fifth portion 150 means that the orthographic projection of the fifth portion 150 on the reference plane is located within the orthographic projection of the second antifuse gate 112 on the reference plane. The select gate 113 overlapping the third portion 130 means that the orthographic projection of the third portion 130 on the reference plane is located within the orthographic projection of the select gate 113 on the reference plane.

[0046] It should be noted that, in order to clearly illustrate the relative positional relationship between the active region 100, the first anti-fuse structure 101, the second anti-fuse structure 102 and the selection transistor 103, Figure 1 1a does not illustrate the first bit line 104 and the second bit line 105 in the antifuse storage structure; in order to clearly illustrate the shape of the active area 100, Figure 1 1b is a separate diagram of the active area in 1a. Figures 1 to 4 The first anti-fuse structure 101, the second anti-fuse structure 102 and the selection transistor 103 are framed by dotted lines. Figures 2 to 4 The first bit line 104 and the second bit line 105 framed by the dotted line do not belong to the components of the above three structures. Figures 3 and 4 The first conductive plug 114 and the second conductive plug 115 framed by the dotted line are not components of the above three structures.

[0047] It is understood that the first anti-fuse structure 101 and the selection transistor 103 share the second portion 120. Figures 1 to 4 The first antifuse structure 101 and the selection transistor 103 are schematically shown in FIG. 2 . The two dashed boxes representing the first antifuse structure 101 and the selection transistor 103 divide the second portion 120 . In practical applications, the second portion 120 is both a part of the first antifuse structure 101 and a part of the selection transistor 103 . The second antifuse structure 102 and the selection transistor 103 share the fourth portion 140 . Figures 1 to 4 The second anti-fuse structure 102 and the selection transistor 103 are schematically shown in the figure. The two dotted boxes representing the second anti-fuse structure 102 and the selection transistor 103 divide the fourth part 140. In actual application, the fourth part 140 is both a part of the second anti-fuse structure 1021 and a part of the selection transistor 103.

[0048] also, Figures 1 to 5 In order to clearly illustrate the relative positional relationship between the active region 100, the first anti-fuse structure 101, the second anti-fuse structure 102 and the selection transistor 103, the first anti-fuse gate 111, the selection gate 113 and the second anti-fuse gate 112 are all drawn in perspective. Figures 2 to 5 In the figure, the first bit line 104 and the second bit line 105 are also drawn in perspective. It can be understood that any of the first anti-fuse gate 111, the selection gate 113, and the second anti-fuse gate 112 extending along the second direction Y will not be cross-connected with the first bit line 104 and the second bit line 105 extending along the first direction X, that is, they will not be located in the same layer.

[0049] In one example, the first anti-fuse gate 111, the selection gate 113, and the second anti-fuse gate 112 can be set in the same layer, for example, all in the first metal layer; the first bit line 104 and the second bit line 105 can also be set in the same layer, for example, in the second metal layer, and the first metal layer and the second metal layer are different layers.

[0050] It should be noted that, for the clarity of the illustration, the first anti-fuse gate 111, the selection gate 113 and the second anti-fuse gate 112 are filled in the same way, and the first bit line 104 and the second bit line 105 are also filled in the same way. In actual applications, the materials of the first anti-fuse gate 111, the selection gate 113 and the second anti-fuse gate 112 can be the same or different, and the materials of the first bit line 104 and the second bit line 105 can be the same or different.

[0051] refer to Figures 1 to 5As can be seen, on the one hand, an embodiment of the present disclosure provides a novel layout of an antifuse memory structure, which can realize control of both the first antifuse structure 101 and the second antifuse structure 102 through two bit lines, namely the first bit line 104 and the second bit line 105, and a select transistor 103, for example, to realize programming or reading operations on the first antifuse structure 101 and / or the second antifuse structure 102. It can be understood that an antifuse memory structure includes two memory cells, namely the first antifuse structure 101 and the second antifuse structure 102, and the control of the two memory cells can be realized with the help of the cooperation of the select transistor 103 and the two bit lines.

[0052] On the other hand, only one selection transistor 103 needs to be arranged, which is beneficial to reducing the length of the entire anti-fuse storage structure in the first direction X, thereby facilitating reducing the layout area of ​​the entire anti-fuse storage structure.

[0053] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0054] In some embodiments, the anti-fuse storage structure further includes: a first anti-fuse layer (not shown in the figure), located between the first anti-fuse gate 111 and the first part 110; a second anti-fuse layer (not shown in the figure), located between the second anti-fuse gate 112 and the fifth part 150; and a gate dielectric layer (not shown in the figure), located between the selection gate 113 and the third part 130.

[0055] It can be understood that when the difference between the potential at the first anti-fuse gate 111 and the potential at the first part 110 is large, the first anti-fuse layer will be broken down, thereby realizing programming of the first anti-fuse structure 101; when the difference between the potential at the second anti-fuse gate 112 and the potential at the fifth part 150 is large, the second anti-fuse layer will be broken down, thereby realizing programming of the second anti-fuse structure 102; the selection gate 113, the gate dielectric layer, the third part 130, the second part 120 and the fourth part 140 together constitute the selection transistor 103.

[0056] In some embodiments, along the third direction, the thickness of the first antifuse layer may be less than the thickness of the gate dielectric layer, and the thickness of the second antifuse layer may also be less than the thickness of the gate dielectric layer. The third direction is perpendicular to the first direction X and the second direction Y. This facilitates breakdown of the first antifuse layer by a smaller potential difference between the first antifuse gate 111 and the first portion 110 , and breakdown of the second antifuse layer by a smaller potential difference between the second antifuse gate 112 and the fifth portion 150 , thereby increasing the probability of successful programming of the first antifuse structure 101 and the second antifuse structure 102 .

[0057] In some embodiments, reference Figures 1 to 3 ,as well as Figure 5 In the second direction Y, the width of the third portion 130 is greater than the width of the first portion 110, and the width of the third portion 130 is greater than the width of the fifth portion 150. It can be understood that the third portion 130 is used to form a channel region when the select transistor 103 is turned on. Among the first portion 110, the third portion 130, and the fifth portion 150, the third portion 130 has the largest width in the second direction Y. This helps ensure that the layout area of ​​the first portion 110 and the fifth portion 150 is small while making the width of the channel region larger when the select transistor 103 is turned on, thereby increasing the current driving capability of the select transistor 103 and improving the electrical performance of the antifuse memory structure.

[0058] In some embodiments, reference Figures 1 to 3 ,as well as Figure 5 In the second direction Y, the width of the first part 110 is the first width, the width of the second part 120 is the second width, the width of the third part 130 is the third width, the width of the fourth part 140 is the fourth width, and the width of the fifth part 150 is the fifth width; wherein the second width is greater than or equal to the first width and less than or equal to the third width, and the fourth width is greater than or equal to the fifth width and less than or equal to the third width.

[0059] Thus, among the first portion 110 , the second portion 120 , the third portion 130 , the fourth portion 140 and the fifth portion 150 , the third portion 130 has the largest width, the second portion 120 and the third portion 130 have moderate widths, and the first portion 110 and the fifth portion 150 have smaller widths. Therefore, along the first direction X, the second portion 120 serves as a buffer zone between the first portion 110 and the third portion 130, that is, the width of the active area 100 in the second direction Y increases from the first width to the second width, and then increases to the third width, rather than directly increasing from the first width to the third width. When current exists in the active area 100, this helps to avoid the current transmission path from being too curved, thereby reducing losses during current transmission. Similarly, along the first direction X, the fourth portion 140 serves as a buffer zone between the fifth portion 150 and the third portion 130, that is, the width of the active area 100 in the second direction Y increases from the fifth width to the fourth width, and then increases to the third width, rather than directly increasing from the fifth width to the third width. When current exists in the active area 100, this helps to avoid the current transmission path from being too curved, thereby reducing losses during current transmission. In addition, by reducing the width of the first part 110, the second part 120, the fourth part 140 and / or the fifth part 150 in the second direction Y, the width of the channel region can be larger when the selection transistor 103 is turned on, so that the selection transistor 103 has a larger current driving capability, while helping to reduce the overall layout area of ​​the active area 100.

[0060] It should be noted that Figures 1 to 3 as well as Figure 5 In the figure, the widths of the first portion 110 , the second portion 120 , the third portion 130 , the fourth portion 140 and the fifth portion 150 in the second direction Y refer to the maximum values ​​of their respective widths in the second direction Y. Figures 1 to 3 In the second direction Y, different regions of the second portion 120 have different widths. For example, the width of the portion of the second portion 120 that is in contact with the first portion 110 is equal to the width of the first portion 110, while the width of the remaining portion of the second portion 120 that is in contact with the third portion 130 is equal to the width of the third portion 130. The second width refers to the width of the second portion 120 that is equal to the width of the third portion 130. Similarly, different regions of the fourth portion 140 have different widths in the second direction Y. For example, the width of the portion of the fourth portion 140 that is in contact with the fifth portion 150 is equal to the width of the fifth portion 150, while the width of the remaining portion of the fourth portion 140 that is in contact with the third portion 130 is equal to the width of the third portion 130. The fourth width refers to the width of the fourth portion 140 that is equal to the width of the third portion 130.

[0061] It is understood that the embodiment of the present disclosure does not limit the change in the width of the second portion 120 and the fourth portion 140 in the second direction Y. Figures 1 to 3 This is just an exemplary description. In actual applications, it is only necessary that the second width is greater than or equal to the first width and less than or equal to the third width, and the fourth width is greater than or equal to the fifth width and less than or equal to the third width.

[0062] In some embodiments, continue to refer to Figures 1 to 3 ,as well as Figure 5 The first portion 110 and the fifth portion 150 are staggered in the second direction Y. This helps to reduce the widths of the first portion 110 and the fifth portion 150 in the second direction Y while ensuring that the width of the third portion 130 in the second direction Y is large, thereby reducing the overall layout area of ​​the active area 100.

[0063] It should be noted that the first part 110 and the fifth part 150 are staggered in the second direction Y, which means that, with a plane perpendicular to the first direction X as the projection plane, the orthographic projection of the first part 110 and the orthographic projection of the fifth part 150 on the projection plane do not overlap.

[0064] In some embodiments, reference Figure 4 The widths of the first portion 110 , the second portion 120 , the third portion 130 , the fourth portion 140 and the fifth portion 150 in the second direction Y may also be equal.

[0065] It is understandable that Figure 1 、 Figure 2 2a in Figure 3 3a in , and Figure 4 One of the two opposite end portions of the active region 100 along the first direction X, as shown in FIG. 4 a , is located directly below the first anti-fuse gate 111 , and the other is located directly below the second anti-fuse gate 112 .

[0066] In other embodiments, reference Figure 2 2b in Figure 3 3b in Figure 4 4b in, and Figure 5 The active region 100 may further include a first extending portion 160 located on a side of the first portion 110 away from the second portion 120 .

[0067] In other embodiments, continue to refer to Figure 2 2b in Figure 3 3b in Figure 4 4b in, and Figure 5 The active region 100 may further include a second extending portion 170 located on a side of the fifth portion 150 away from the fourth portion 140 .

[0068] In some embodiments, reference Figures 3 to 5 The first bit line 104 and the second bit line 105 both extend along the first direction X. The antifuse memory structure may further include: a first conductive plug 114 located above (for example, directly above, but not limited to) the fourth portion 140, and the first bit line 104 is electrically connected to the fourth portion 140 via the first conductive plug 114; a second conductive plug 115 located above (for example, directly above, but not limited to) the second portion 120, and the second bit line 105 is electrically connected to the second portion 120 via the second conductive plug 115. In this way, the first bit line 104 can control the potential of the fourth portion 140 via the first conductive plug 114, and the second bit line 105 can control the potential of the second portion 120 via the second conductive plug 115.

[0069] In some embodiments, continue to refer to Figures 3 to 5 The first conductive plug 114 and the second conductive plug 115 are staggered in the second direction Y. In this way, the first bit line 104 and the second bit line 105 are arranged in the same layer and spaced apart from each other.

[0070] It should be noted that the first conductive plug 114 and the second conductive plug 115 are staggered in the second direction Y, which means that, with a plane perpendicular to the first direction X as the projection plane, the orthographic projection of the first conductive plug 114 and the orthographic projection of the second conductive plug 115 on the projection plane do not overlap.

[0071] In some embodiments, reference Figure 5 The antifuse storage structure may further include a third conductive plug 121 and a first antifuse conductive layer 131. The third conductive plug 121 is located above one end of the first antifuse gate 111, and the first antifuse conductive layer 131 is electrically connected to the first antifuse gate 111 through the third conductive plug 121. Thus, the first antifuse conductive layer 131 can control the potential of the first antifuse gate 111 through the third conductive plug 121.

[0072] In some embodiments, continue to refer to Figure 5 The antifuse storage structure may further include: a fourth conductive plug 122 and a second antifuse conductive layer 132. The fourth conductive plug 122 is located above one end of the second antifuse gate 112, and the second antifuse conductive layer 132 is electrically connected to the second antifuse gate 112 via the fourth conductive plug 122. In this way, the second antifuse conductive layer 132 can control the potential of the second antifuse gate 112 via the fourth conductive plug 122.

[0073] In some embodiments, continue to refer to Figure 5 The antifuse memory structure may further include a fifth conductive plug 123 and a selection conductive layer 133. The fifth conductive plug 123 is located above one end of the selection gate 113, and the selection conductive layer 133 is electrically connected to the selection gate 113 through the fifth conductive plug 123. In this way, the selection conductive layer 133 can control the potential of the selection gate 113 through the fifth conductive plug 123.

[0074] It should be noted that Figure 5 The diagram only illustrates a layout of how to control the potentials of the first anti-fuse gate 111 , the second anti-fuse gate 112 and the selection gate 113 through the conductive plugs and the conductive layer. In actual applications, the layout positions of the conductive plugs and the conductive layer can be adjusted according to actual needs.

[0075] In summary, the first bit line 104, the second bit line 105, and the select transistor 103 can be used to control both the first antifuse structure 101 and the second antifuse structure 102, for example, to implement programming or reading operations on the first antifuse structure 101 and / or the second antifuse structure 102. Furthermore, only one select transistor 103 is required, which helps reduce the overall length of the antifuse storage structure in the first direction X, thereby helping to reduce the overall layout area of ​​the antifuse storage structure.

[0076] Another embodiment of the present disclosure further provides an operation method of an anti-fuse storage structure, which is used to operate the anti-fuse storage structure provided by an embodiment of the present disclosure. Figures 5 to 7An operating method of an antifuse storage structure provided by another embodiment of the present disclosure is described in detail. Figure 6 Two simplified circuit diagrams for performing programming operations on an anti-fuse storage structure according to another embodiment of the present disclosure; Figure 7 Two circuit diagrams are provided for performing a read operation on an antifuse storage structure according to another embodiment of the present disclosure.

[0077] Combined with reference Figures 5 to 7 The operating method of the anti-fuse storage structure includes: providing the anti-fuse storage structure as described in an embodiment of the present disclosure; and performing a programming operation or a reading operation on the anti-fuse storage structure.

[0078] In some embodiments, in conjunction with reference Figure 5 and Figure 6 , the programming operation of the anti-fuse storage structure includes at least the following two situations:

[0079] First, in some embodiments, reference Figure 5 and Figure 6 In step 6a, a first voltage V1 is provided to the select gate 113, a second voltage V2 is provided to the first antifuse gate 111, and a third voltage V3 is provided to the first bit line 104 to perform a programming operation on the first antifuse structure 101. The first voltage V1 is a turn-on voltage of the select transistor 103, and the difference between the second voltage V2 and the third voltage V3 is not less than the breakdown voltage of the first antifuse structure 101.

[0080] In some embodiments, during the programming operation on the first anti-fuse structure 101 , no voltage signal is provided to the second bit line 105 , and no voltage signal is provided to the second anti-fuse gate 112 , or a third voltage V3 is provided to the second anti-fuse gate 112 .

[0081] It can be understood that when the third voltage V3 is provided to the first bit line 104, the potential of the fourth part 140 approaches the third voltage V3, and when the first voltage V1 is provided to the selection gate 113 so that the selection transistor 103 is turned on, so that the second part 120 and the fourth part 140 are electrically connected, the potential of the second part 120 approaches the potential of the fourth part 140, that is, approaches the third voltage V3, and the difference between the potential of the first anti-fuse gate 111 and the potential of the second part 120 is equivalent to the level difference between the second voltage V2 and the third voltage V3, so that the first anti-fuse layer is broken down, thereby realizing the programming operation of the first anti-fuse structure 101.

[0082] Second, in other embodiments, reference Figure 5 and Figure 6In step 6b, a first voltage V1 is provided to the select gate 113, a second voltage V2 is provided to the second anti-fuse gate 112, and a third voltage V3 is provided to the second bit line 105 to perform a programming operation on the second anti-fuse structure 102. The first voltage V1 is a turn-on voltage of the select transistor, and the difference between the second voltage V2 and the third voltage V3 is not less than the breakdown voltage of the second anti-fuse structure 102.

[0083] In some embodiments, during the programming operation on the second anti-fuse structure 102 , no voltage signal is provided to the first bit line 104 , and no voltage signal is provided to the first anti-fuse gate 111 , or a third voltage V3 is provided to the first anti-fuse gate 111 .

[0084] It can be understood that when the third voltage V3 is provided to the second bit line 105, the potential of the second part 120 approaches the third voltage V3, and when the first voltage V1 is provided to the selection gate 113 so that the selection transistor 103 is turned on, so that the second part 120 and the fourth part 140 are electrically connected, the potential of the fourth part 140 approaches the potential of the second part 120, that is, approaches the third voltage V3, and the difference between the potential of the second anti-fuse gate 112 and the potential of the fourth part 140 is equivalent to the level difference between the second voltage V2 and the third voltage V3, so that the second anti-fuse layer is broken down, thereby realizing the programming operation of the second anti-fuse structure 102.

[0085] In some examples, the first voltage V1 may be 3V, the second voltage V2 may be 5V, and the third voltage V3 may be 0V.

[0086] In some embodiments, in conjunction with reference Figure 5 and Figure 7 , the read operation on the antifuse storage structure includes at least the following two situations:

[0087] First, in some embodiments, reference Figure 5 and Figure 7 In step 7a, a first voltage V1 is provided to the select gate 113, a fourth voltage V4 is provided to the first antifuse gate 111, and a fifth voltage V5 is provided to the first bit line 104. The first antifuse gate 111 detects the current in the first antifuse structure 101 to determine the data stored in the first antifuse structure 101, thereby performing a read operation on the first antifuse structure 101. The level of the fifth voltage V5 is greater than the level of the fourth voltage V4 and less than the level of the first voltage V1.

[0088] In some embodiments, during a read operation on the first anti-fuse structure 101 , no voltage signal is provided to the second bit line 105 , and no voltage signal is provided to the second anti-fuse gate 112 , or a fifth voltage V5 is provided to the second anti-fuse gate 112 .

[0089] It can be understood that when the fifth voltage V5 is provided to the first bit line 104, the potential of the fourth portion 140 approaches the fifth voltage V5. When the first voltage V1 is provided to the select gate 113, the select transistor 103 is turned on, and the second portion 120 and the fourth portion 140 are electrically connected. The potential of the second portion 120 approaches the potential of the fourth portion 140, that is, approaches the fifth voltage V5. The difference between the potential of the first antifuse gate 111 and the potential of the second portion 120 is equivalent to the level difference between the fourth voltage V4 and the fifth voltage V5. At this time, if the first antifuse structure 101 has been programmed, the first antifuse layer has been broken down, and the first antifuse gate 111 and the second portion 120 are electrically connected. Due to the potential difference between the first antifuse gate 111 and the second portion 120, there is a potential difference between the first antifuse gate 111 and the second portion 120. Figure 7 7a, the current value detected in the first antifuse structure 101 is large; if the first antifuse structure 101 is not programmed, the first antifuse layer is not broken down, and there is no electrical connection between the first antifuse gate 111 and the second portion 120, then the current value detected in the first antifuse structure 101 is close to 0.

[0090] Second, in some other embodiments, reference Figure 5 and Figure 7 7b, a first voltage V1 is provided to the selection gate 113, a fourth voltage V4 is provided to the second anti-fuse gate 112, and a fifth voltage V5 is provided to the second bit line 105, and the current in the second anti-fuse structure 102 is detected by the second anti-fuse gate 112 to determine the data information stored in the second anti-fuse structure 102, so as to perform the read operation on the second anti-fuse structure 102; wherein the level value of the fifth voltage V5 is greater than the level value of the fourth voltage V4 and less than the level value of the first voltage V1.

[0091] In some embodiments, during the read operation on the second antifuse structure 102 , no voltage signal is provided to the first bit line 104 , and no voltage signal is provided to the first antifuse gate 111 . Alternatively, a fifth voltage V5 is provided to the first antifuse gate 111 .

[0092] It can be understood that when the fifth voltage V5 is provided to the second bit line 105, the potential of the second portion 120 approaches the fifth voltage V5. When the first voltage V1 is provided to the select gate 113, the select transistor 103 is turned on, thereby achieving electrical connection between the second portion 120 and the fourth portion 140. The potential of the fourth portion 140 approaches the potential of the second portion 120, that is, approaches the fifth voltage V5. The difference between the potential of the second anti-fuse gate 112 and the fourth portion 140 is equivalent to the level difference between the fourth voltage V4 and the fifth voltage V5. At this time, if the second anti-fuse structure 102 has been programmed, the second anti-fuse layer has been broken down, and the second anti-fuse gate 112 and the fourth portion 140 are electrically connected. Due to the potential difference between the second anti-fuse gate 112 and the fourth portion 140, there is a potential difference between the second anti-fuse gate 112 and the fourth portion 140. Figure 7 7b, the current value detected in the second anti-fuse structure 102 is larger; if the second anti-fuse structure 102 is not programmed, the second anti-fuse layer is not broken down, and there is no electrical connection between the second anti-fuse gate 112 and the fourth portion 140, then the current value detected in the second anti-fuse structure 102 is close to 0.

[0093] In some examples, the fourth voltage V4 may be 0V, and the fifth voltage V5 may be 1V.

[0094] In summary, the first antifuse structure 101 and the second antifuse structure 102 can be controlled by two bit lines, namely the first bit line 104 and the second bit line 105, and a selection transistor 103, for example, programming or reading operations on the first antifuse structure 101 and / or the second antifuse structure 102 can be implemented.

[0095] Another embodiment of the present disclosure further provides an antifuse storage array structure, comprising a plurality of antifuse storage structures arranged in an array along a first direction X and a second direction Y, each antifuse storage structure comprising the antifuse storage structure as described in an embodiment of the present disclosure. Figure 5 and Figure 8 An anti-fuse memory array structure provided by another embodiment of the present disclosure is described in detail. Figure 8 A schematic top view of an antifuse memory array structure provided in yet another embodiment of the present disclosure.

[0096] It should be noted that the parts that are the same as or corresponding to an embodiment of the present disclosure are not repeated here.

[0097] Combined with reference Figure 5 and Figure 8The anti-fuse memory array structure includes a plurality of anti-fuse memory structures arranged in an array along a first direction X and a second direction Y; wherein, the anti-fuse memory structures in the same column in the first direction X share a first bit line 104 and a second bit line 105; and the anti-fuse memory structures in the same row in the second direction Y share a first programming line FG1, a second programming line FG2 and a selection control line XG, wherein the first programming line FG1 includes a first anti-fuse gate 111 of each anti-fuse memory structure in the same row, the second programming line FG2 includes a second anti-fuse gate 112 of each anti-fuse memory structure in the same row, and the selection control line XG includes a selection gate 113 of each anti-fuse memory structure in the same row.

[0098] It should be noted that Figure 8 In the example, two antifuse storage structures are arranged along the first direction X and two antifuse storage structures are arranged along the second direction Y. In actual applications, there is no limitation on the number of antifuse storage structures arranged along the first direction X and the number of antifuse storage structures arranged along the second direction Y. In addition, since the first programming line FG1 includes the first antifuse gates 111 of each antifuse storage structure in the same row, the second programming line FG2 includes the second antifuse gates 112 of each antifuse storage structure in the same row, and the selection control line XG includes the selection gates 113 of each antifuse storage structure in the same row, Figure 8 Only the first programming line FG1, the second programming line FG2 and the selection control line XG are shown, and the first anti-fuse gate 111 of each anti-fuse storage structure is not shown (refer to Figure 5 ), the second anti-fuse gate 112 (reference Figure 5 ) and select gate 113 (reference Figure 5 ).

[0099] In addition, in order to clearly illustrate the relative positional relationship between the active area 100, the first programming line FG1, the second programming line FG2, the selection control line XG, the first bit line 104, and the second bit line 105, Figure 8 In the figure, the first programming line FG1, the second programming line FG2, the selection control line XG, the first bit line 104, and the second bit line 105 are all drawn in a perspective manner.

[0100] It can be understood that antifuse memory structures in the same column in the first direction X share the first bit line 104 and the second bit line 105; and antifuse memory structures in the same row in the second direction Y share the first programming line FG1, the second programming line FG2, and the select control line XG. The first bit line 104, the second bit line 105, the first programming line FG1, the second programming line FG2, and the select control line XG are data lines that control the potentials of different regions of the antifuse memory structure. The antifuse memory array structure provided in another embodiment of the present disclosure facilitates programming and reading operations for multiple antifuse memory structures using a small number of regularly arranged data lines, thereby simplifying the overall layout area of ​​the antifuse memory array structure and reducing the complexity of wiring within the antifuse memory array structure.

[0101] Another embodiment of the present disclosure further provides an operation method of an anti-fuse memory array structure, which is used to operate the anti-fuse memory array structure provided by another embodiment of the present disclosure. Figures 8 to 12 An operating method of an antifuse storage structure provided by another embodiment of the present disclosure is described in detail. Figure 9 A simplified circuit diagram of a programming operation performed on an anti-fuse memory array structure according to another embodiment of the present disclosure; Figure 10 Another circuit diagram for performing a programming operation on an anti-fuse memory array structure according to another embodiment of the present disclosure; Figure 11 A simplified circuit diagram of a read operation performed on an antifuse memory array structure according to another embodiment of the present disclosure; Figure 12 Another circuit diagram of performing a read operation on an antifuse memory array structure is provided in accordance with another embodiment of the present disclosure.

[0102] It should be noted that the parts that are the same or corresponding to another embodiment of the present disclosure will not be repeated here. Figures 9 to 12 In the figure, different antifuse structures are marked with cell1, cell2, cell3, cell4, cell5, cell6, cell7 and cell8, different first programming lines are marked with FG11 and FG21, different second programming lines are marked with FG12 and FG22, different first bit lines are marked with BL1 and BL3, and different second bit lines are marked with BL2 and BL4.

[0103] Combined with reference Figures 8 to 12 The operating method of the anti-fuse memory array structure includes: providing the aforementioned anti-fuse memory array structure; performing a programming operation or a reading operation on the anti-fuse memory structures in the same row in the anti-fuse memory array structure.

[0104] In some embodiments, reference Figure 9 and Figure 10The programming operation on the anti-fuse storage structures in the same row in the anti-fuse storage array structure includes at least the following two methods:

[0105] It should be noted that Figure 9 and Figure 10 The antifuse memory structures in the same row of the antifuse memory array structure that need to be programmed are labeled as 106 in the following text, and the antifuse memory structures in other rows of the antifuse memory array structure except the antifuse memory structure 106 are labeled as 107. First, in some embodiments, a first voltage V1 is provided to the selection control line XG1 corresponding to the antifuse memory structure 106 in the row, a second voltage V2 is provided to the first programming line FG11 corresponding to the antifuse memory structure 106 in the row, a third voltage V3 is provided to the first bit line BL1 corresponding to the first antifuse structure 101 in the antifuse memory structure 106 that needs to be programmed, and a sixth voltage V6 is provided to the first bit line BL3 corresponding to the first antifuse structure 101 in the antifuse memory structure 106 that does not need to be programmed, so as to perform a programming operation on the first antifuse structure 101 in the antifuse memory structure 106 in the row.

[0106] In some embodiments, during the step of performing the programming operation, no voltage signal is provided to the selection control line XG2 corresponding to other rows of anti-fuse storage structures 107, no voltage signal is provided to the first programming line FG21 and the second programming line FG22 corresponding to other rows of anti-fuse storage structures 107, or a third voltage V3 is provided to both the first programming line FG21 and the second programming line FG22 corresponding to other rows of anti-fuse storage structures 107. Moreover, during the programming operation of the first anti-fuse structure 101 in the row of anti-fuse storage structures 106, no voltage signal is provided to all second bit lines BL2 and BL4, no voltage signal is provided to the second programming line FG12 corresponding to the row of anti-fuse storage structures 106, or a third voltage V3 is provided to the second programming line FG12 corresponding to the row of anti-fuse storage structures 106; wherein, the first voltage V1 is the turn-on voltage of the selection transistor 103, the level difference between the second voltage V2 and the third voltage V3 is not less than the breakdown voltage of the first anti-fuse structure 101, and is not less than the breakdown voltage of the second anti-fuse structure 102, and the level difference between the second voltage V2 and the sixth voltage V6 is less than the breakdown voltage of the first anti-fuse structure 101, and less than the breakdown voltage of the second anti-fuse structure 102.

[0107] In one example, continue with reference Figure 9In the case where the first antifuse structure in the row of antifuse storage structures 106 that needs to be programmed is cell1, and the first antifuse structure in the row of antifuse storage structures 106 that does not need to be programmed is cell5, a third voltage V3 is applied to the first bit line BL1 corresponding to the first antifuse structure cell1, and a sixth voltage V6 is applied to the first bit line BL3 corresponding to the first antifuse structure cell5. This causes the first antifuse layer in the first antifuse structure cell1 to be broken down, while the first antifuse layer in the first antifuse structure cell5 is not broken down. Furthermore, if no voltage signal is supplied to any of the second bit lines BL2 and BL4, no voltage signal is supplied to the second programming line FG12 corresponding to the anti-fuse storage structure 106 in that row, or the third voltage V3 is supplied to the second programming line FG12 corresponding to the anti-fuse storage structure 106 in that row, the second anti-fuse structures cell2 and cell6 will not be broken down. If no voltage signal is supplied to the selection control line XG2 corresponding to the anti-fuse storage structure 107 in other rows, no voltage signal is supplied to the first programming line FG21 and the second programming line FG22 corresponding to the anti-fuse storage structure 107 in other rows, or the third voltage V3 is supplied to both the first programming line FG21 and the second programming line FG22 corresponding to the anti-fuse storage structure 107 in other rows, the first anti-fuse structures cell3 and cell7, and the second anti-fuse structures cell4 and cell8 will not be broken down. Therefore, programming of only the first anti-fuse structure cell1 can be achieved.

[0108] In another example, the number of first anti-fuse structures that need to be programmed in the row of anti-fuse storage structures 106 can be 2, such as cell1 and cell5, and the third voltage V3 is provided to the first bit lines BL1 and BL3 corresponding to the first anti-fuse structures cell1 and cell5, and the sixth voltage V6 is provided to the first bit line (not shown in the figure) corresponding to the first anti-fuse structure (not shown in the figure) that does not need to be programmed in the row of anti-fuse storage structures 106.

[0109] In other embodiments, reference Figure 10, providing a first voltage V1 to the selection control line XG1 corresponding to the anti-fuse storage structure 106 in the row, providing a second voltage V2 to the second programming line FG12 corresponding to the anti-fuse storage structure 106 in the row, providing a third voltage V3 to the second bit line BL2 corresponding to the second anti-fuse structure 102 that needs to be programmed in the anti-fuse storage structure 106 in the row, and providing a sixth voltage V6 to the second bit line BL4 corresponding to the second anti-fuse structure 102 that does not need to be programmed in the anti-fuse storage structure 106 in the row, so as to A programming operation is performed on the second anti-fuse structure 102 in the anti-fuse storage structure 106 of the row; wherein the first voltage V1 is the turn-on voltage of the selection transistor 103, the level difference between the second voltage V2 and the third voltage V3 is not less than the breakdown voltage of the first anti-fuse structure 101, and is not less than the breakdown voltage of the second anti-fuse structure 102, and the level difference between the second voltage V2 and the sixth voltage V6 is less than the breakdown voltage of the first anti-fuse structure 101, and less than the breakdown voltage of the second anti-fuse structure 102.

[0110] In some embodiments, during the programming operation, no voltage signal is provided to the select control line XG2 corresponding to the anti-fuse storage structure 107 in other rows, no voltage signal is provided to the first programming line FG21 and the second programming line FG22 corresponding to the anti-fuse storage structure 107 in other rows, or the third voltage V3 is provided to both the first programming line FG21 and the second programming line FG22 corresponding to the anti-fuse storage structure 107 in other rows. Furthermore, during the programming operation of the second anti-fuse structure 102 in the anti-fuse storage structure 106 in the row, no voltage signal is provided to any of the first bit lines BL1 and BL3, no voltage signal is provided to the first programming line FG11 corresponding to the anti-fuse storage structure 106 in the row, or the third voltage V3 is provided to the first programming line FG11 corresponding to the anti-fuse storage structure 106 in the row.

[0111] In one example, continue with reference Figure 10If the second antifuse structure in the row of antifuse storage structures 106 that requires programming is cell2, and the second antifuse structure in the row of antifuse storage structures 106 that does not require programming is cell6, then a third voltage V3 is applied to the second bit line BL2 corresponding to the second antifuse structure cell2, and a sixth voltage V6 is applied to the second bit line BL4 corresponding to the second antifuse structure cell6. This causes the second antifuse layer in the second antifuse structure cell2 to break down, while the second antifuse layer in the second antifuse structure cell6 does not break down. Furthermore, if voltage signals are not applied to all first bit lines BL1 and BL3, and if a voltage signal is not applied to the first programming line FG11 corresponding to the row of antifuse storage structures 106, or if the third voltage V3 is applied to the first programming line FG11 corresponding to the row of antifuse storage structures 106, then neither the first antifuse structures cell1 nor cell5 will break down. Therefore, programming of only the second antifuse structure cell2 can be achieved.

[0112] In another example, the number of second anti-fuse structures that need to be programmed in the row of anti-fuse storage structures 106 can be 2, such as cell2 and cell6, and the third voltage V3 is provided to the first bit lines BL1 and BL3 corresponding to the first anti-fuse structures cell2 and cell6, and the sixth voltage V6 is provided to the first bit line (not shown in the figure) corresponding to the second anti-fuse structure (not shown in the figure) that does not need to be programmed in the row of anti-fuse storage structures 106.

[0113] In some examples, the first voltage V1 may be 3V, the second voltage V2 may be 5V, the third voltage V3 may be 0V, and the sixth voltage V6 may be 0V or a voltage with a level lower than that of the second voltage V2.

[0114] In some embodiments, reference Figure 11 and Figure 12 The read operation on the anti-fuse storage structures in the same row in the anti-fuse storage array structure includes at least the following two methods:

[0115] First, in some embodiments, reference Figure 11, providing a first voltage V1 to the selection control line XG1 corresponding to the anti-fuse storage structure 106 in this row, providing a fourth voltage V4 to the first programming line FG11 corresponding to the anti-fuse storage structure 106 in this row, providing a fifth voltage V5 to the first bit line BL1 corresponding to the first anti-fuse structure 101 that needs to be read in the anti-fuse storage structure 106 in this row, and providing a seventh voltage V7 to the first bit line BL3 corresponding to the first anti-fuse structure 101 that does not need to be read in the anti-fuse storage structure 106 in this row, so as to perform a read operation on the first anti-fuse structure 101 in the anti-fuse storage structure 106 in this row; wherein, the level value of the fifth voltage V5 is greater than the level value of the fourth voltage V4 and less than the level value of the first voltage V1, and the level value of the seventh voltage V7 is not greater than the level value of the fifth voltage V5.

[0116] In some embodiments, during the step of performing a read operation, a voltage signal is not provided to the selection control line XG2 corresponding to other rows of anti-fuse storage structures 107, or the fourth voltage V4 is provided to the selection control line XG2 corresponding to other rows of anti-fuse storage structures; during the process of performing a read operation on the first anti-fuse structure 101 in the anti-fuse storage structure 106 in this row, a voltage signal is not provided to all second bit lines BL2 and BL4, and a voltage signal is not provided to the first programming line FG21 corresponding to other rows of anti-fuse storage structures 107, and the fifth voltage V5 or the seventh voltage V7 is provided to all second programming lines FG12 and FG22.

[0117] In one example, continue with reference Figure 11 , the first anti-fuse structure to be read in the row of anti-fuse storage structures 106 is cell1, and the first anti-fuse structure not to be read in the row of anti-fuse storage structures 106 is cell5, then the fifth voltage V5 is provided to the first bit line BL1 corresponding to the first anti-fuse structure cell1, and the seventh voltage V7 is provided to the first bit line BL3 corresponding to the first anti-fuse structure cell5. If the first anti-fuse structure cell1 has been programmed, the first anti-fuse gate 111 (refer to Figure 5 ) and the second portion 120 (reference Figure 5 ) are electrically connected, and since there is a potential difference between the first anti-fuse gate 111 and the second portion 120, that is, the potential difference between the fifth voltage V5 and the seventh voltage V7, there is a potential difference between the first anti-fuse gate 111 and the second portion 120. Figure 11 If the current is as shown in , the current value detected in the first anti-fuse structure cell1 is larger; if the first anti-fuse structure cell1 is not programmed, the first anti-fuse gate 111 and the second portion 120 are not electrically connected, and the current value detected in the first anti-fuse structure cell1 is close to 0.

[0118] In addition, if a voltage signal is not provided to the selection control line XG2 corresponding to the anti-fuse storage structure 107 in other rows, or the fourth voltage V4 is provided to the selection control line XG2 corresponding to the anti-fuse storage structure in other rows, the selection transistor 103 in the anti-fuse storage structure 107 in other rows will not be turned on, and the first anti-fuse structures cell3 and cell7 corresponding to the anti-fuse storage structure 107 in other rows will not be read; if a voltage signal is not provided to all second bit lines BL2 and BL4, and if a voltage signal is not provided to the first programming line FG21 corresponding to the anti-fuse storage structure in other rows, and the fifth voltage V5 or the seventh voltage V7 is provided to all second programming lines FG12 and FG22, then no matter whether the second anti-fuse structures cell2, cell4, cell6, and cell8 are in a programmed or unprogrammed state, no additional current will be generated and superimposed on the first bit lines BL1 and BL3.

[0119] Second, in other embodiments, reference Figure 12 , providing a first voltage V1 to the selection control line XG1 corresponding to the row of anti-fuse storage structure 106, providing a fourth voltage V4 to the second programming line FG12 corresponding to the row of anti-fuse storage structure 106, providing a fifth voltage V5 to the second bit line BL2 corresponding to the second anti-fuse structure 102 that needs to be read in the row of anti-fuse storage structure 106, and providing a seventh voltage V7 to the second bit line BL4 corresponding to the second anti-fuse structure 102 that does not need to be read in the row of anti-fuse storage structure 106, so as to perform a read operation on the second anti-fuse structure 102 in the row of anti-fuse storage structure 106; wherein, the level value of the fifth voltage V5 is greater than the level value of the fourth voltage V4 and less than the level value of the first voltage V1, and the level value of the seventh voltage V7 is not greater than the level value of the fifth voltage V5.

[0120] In some embodiments, during the step of performing a read operation, a voltage signal is not provided to the selection control line XG2 corresponding to other rows of anti-fuse storage structures 107, or the fourth voltage V4 is provided to the selection control line XG2 corresponding to other rows of anti-fuse storage structures 107; during the process of performing a read operation on the second anti-fuse structure 102 in the anti-fuse storage structure 106 in this row, a voltage signal is not provided to all first bit lines BL1 and BL3, and a voltage signal is not provided to the second programming line FG22 corresponding to other rows of anti-fuse storage structures 107, and the fifth voltage V5 or the seventh voltage V7 is provided to all first programming lines FG11 and FG21.

[0121] In one example, continue with reference Figure 12, the second anti-fuse structure to be read in the row of anti-fuse storage structures 106 is cell2, and the second anti-fuse structure not to be read in the row of anti-fuse storage structures 106 is cell6, then the fifth voltage V5 is provided to the second bit line BL2 corresponding to the second anti-fuse structure cell2, and the seventh voltage V7 is provided to the second bit line BL4 corresponding to the second anti-fuse structure cell6. If the second anti-fuse structure cell2 has been programmed, the second anti-fuse gate 112 (refer to Figure 5 ) and Section 4.140 (reference Figure 5 ) are electrically connected, since there is a potential difference between the second anti-fuse gate 112 and the fourth portion 140, that is, the potential difference between the fifth voltage V5 and the seventh voltage V7, the second anti-fuse gate 112 and the fourth portion 140 are connected as follows: Figure 12 If the current is as shown in , the current value detected in the second anti-fuse structure cell2 is larger; if the second anti-fuse structure cell2 is not programmed, the second anti-fuse gate 112 and the fourth portion 140 are not electrically connected, and the current value detected in the second anti-fuse structure cell2 is close to 0.

[0122] In addition, if a voltage signal is not provided to the selection control line XG2 corresponding to the anti-fuse storage structure 107 in other rows, or the fourth voltage V4 is provided to the selection control line XG2 corresponding to the anti-fuse storage structure in other rows, the selection transistor 103 in the anti-fuse storage structure 107 in other rows will not be turned on, and the second anti-fuse structures cell4 and cell8 corresponding to the anti-fuse storage structure 107 in other rows will not be read; if a voltage signal is not provided to all first bit lines BL1 and BL3, and a voltage signal is not provided to the second programming line FG22 corresponding to the anti-fuse storage structure in other rows 107, and the fifth voltage V5 or the seventh voltage V7 is provided to all first programming lines FG11 and FG21, then no matter whether the first anti-fuse structures cell1, cell3, cell5, and cell7 are in a programmed or unprogrammed state, no additional current will be generated and superimposed on the second bit lines BL2 and BL4.

[0123] In some examples, the fourth voltage V4 may be 0V, the fifth voltage V5 may be 1V, and the seventh voltage V7 may be 0V or 1V.

[0124] It should be noted that, in actual applications, after programming the multiple first antifuse structures 101 in a certain row one by one, the multiple second antifuse structures 102 in the same row may be programmed one by one, and then after programming the multiple first antifuse structures 101 in another row one by one, the multiple second antifuse structures 102 in the other row may be programmed one by one. Alternatively, after reading the multiple first antifuse structures 101 in a certain row one by one, the multiple second antifuse structures 102 in the same row may be read one by one, and then after reading the multiple first antifuse structures 101 in another row one by one, the multiple second antifuse structures 102 in the other row may be read one by one.

[0125] To sum up, by respectively controlling the potentials of different first programming lines FG1, different second programming lines FG2, different selection control lines XG, different first bit lines 104 and different second bit lines 105, it is beneficial to achieve flexible control of multiple first anti-fuse structures 101 and multiple second anti-fuse structures 102 in the anti-fuse storage array structure.

[0126] Another embodiment of the present disclosure further provides a memory, comprising the antifuse memory structure provided in one embodiment of the present disclosure, or comprising the antifuse memory array structure provided in yet another embodiment of the present disclosure. Thus, when the layout area of ​​the antifuse memory structure is reduced and the electrical performance is improved, or when the layout area of ​​the antifuse memory array structure is reduced and the electrical performance is improved, the size of the memory can be reduced and the electrical performance of the memory can be improved.

[0127] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. An antifuse storage structure, characterized in that: include: An active area, wherein the active area includes a first portion, a second portion, a third portion, a fourth portion, and a fifth portion sequentially arranged along a first direction; a first antifuse structure, a second antifuse structure, and a selection transistor disposed on the active region, wherein the first antifuse structure includes a first antifuse gate overlapping with the first portion, the second antifuse structure includes a second antifuse gate overlapping with the fifth portion, and the selection transistor includes a selection gate overlapping with the third portion, and the first antifuse gate, the selection gate, and the second antifuse gate are spaced apart and arranged along the first direction; A first bit line and a second bit line are arranged at intervals along a second direction, the first bit line is electrically connected to the fourth portion, the second bit line is electrically connected to the second portion, and the first direction and the second direction intersect.

2. The antifuse storage structure according to claim 1, wherein: In the second direction, the width of the third portion is greater than that of the first portion, and the width of the third portion is greater than that of the fifth portion.

3. The antifuse storage structure according to claim 1, wherein: In the second direction, the width of the first portion is a first width, the width of the second portion is a second width, and the width of the third portion is a third width. The width of the fourth portion is the fourth width, and the width of the fifth portion is the fifth width; The second width is greater than or equal to the first width and less than or equal to the third width, and the fourth width is greater than or equal to the fifth width and less than or equal to the third width.

4. The antifuse storage structure according to claim 1, wherein: The first portion and the fifth portion are staggered in the second direction.

5. The antifuse storage structure according to any one of claims 1 to 4, wherein: The first bit line and the second bit line both extend along the first direction, and the antifuse storage structure further includes: a first conductive plug located above the fourth portion, and the first bit line electrically connected to the fourth portion through the first conductive plug; The second conductive plug is located above the second portion, and the second bit line is electrically connected to the second portion through the second conductive plug.

6. The antifuse storage structure according to claim 5, wherein: The first conductive plug and the second conductive plug are staggered in the second direction.

7. A method for operating an antifuse storage structure, characterized in that: include: Providing an antifuse storage structure according to any one of claims 1 to 6; A programming operation or a reading operation is performed on the anti-fuse storage structure.

8. The method for operating the antifuse storage structure according to claim 7, wherein: Performing the programming operation on the antifuse storage structure includes: providing a first voltage to the select gate, providing a second voltage to the first anti-fuse gate, and providing a third voltage to the first bit line to perform the programming operation on the first anti-fuse structure; or, providing the first voltage to the select gate, providing the second voltage to the second anti-fuse gate, and providing the third voltage to the second bit line to perform the programming operation on the second anti-fuse structure; The first voltage is a turn-on voltage of the selection transistor, and a level difference between the second voltage and the third voltage is not less than a breakdown voltage of the first anti-fuse structure and is not less than a breakdown voltage of the second anti-fuse structure.

9. The method for operating the antifuse storage structure according to claim 8, wherein: During the programming operation on the first anti-fuse structure, no voltage signal is provided to the second bit line, no voltage signal is provided to the second anti-fuse gate, or the third voltage is provided to the second anti-fuse gate; During a programming operation on the second anti-fuse structure, no voltage signal is provided to the first bit line, no voltage signal is provided to the first anti-fuse gate, or the third voltage is provided to the first anti-fuse gate.

10. The method for operating the antifuse storage structure according to claim 8, wherein: Performing the reading operation on the antifuse storage structure includes: providing the first voltage to the select gate, providing a fourth voltage to the first anti-fuse gate, and providing a fifth voltage to the first bit line, detecting a current in the first anti-fuse structure through the first anti-fuse gate to determine data information stored in the first anti-fuse structure, and performing the read operation on the first anti-fuse structure; or, providing the first voltage to the select gate, providing the fourth voltage to the second anti-fuse gate, and providing the fifth voltage to the second bit line, detecting a current in the second anti-fuse structure through the second anti-fuse gate to determine data information stored in the second anti-fuse structure, and performing the read operation on the second anti-fuse structure; The level of the fifth voltage is greater than the level of the fourth voltage and less than the level of the first voltage.

11. The method for operating the antifuse storage structure according to claim 10, wherein: During the read operation on the first anti-fuse structure, no voltage signal is provided to the second bit line, no voltage signal is provided to the second anti-fuse gate, or the fifth voltage is provided to the second anti-fuse gate; During the read operation on the second anti-fuse structure, no voltage signal is provided to the first bit line, no voltage signal is provided to the first anti-fuse gate, or the fifth voltage is provided to the first anti-fuse gate.

12. An antifuse memory array structure, characterized in that: A plurality of anti-fuse storage structures are arrayed along a first direction and a second direction, each of the anti-fuse storage structures comprising the anti-fuse storage structure according to any one of claims 1 to 6; The anti-fuse storage structures in the same column in the first direction share the first bit line and the second bit line; The anti-fuse storage structures in the same row in the second direction share a first programming line, a second programming line and a selection control line, the first programming line includes the first anti-fuse gates of the anti-fuse storage structures in the same row, the second programming line includes the second anti-fuse gates of the anti-fuse storage structures in the same row, and the selection control line includes the selection gates of the anti-fuse storage structures in the same row.

13. A method for operating an antifuse memory array structure, characterized in that: include: Providing an antifuse memory array structure as claimed in claim 12; A programming operation or a reading operation is performed on the anti-fuse memory structures in the same row of the anti-fuse memory array structure.

14. The method for operating the antifuse memory array structure according to claim 13, wherein: The performing a programming operation on the anti-fuse storage structures in the same row in the anti-fuse storage array structure includes: providing a first voltage to the selection control line corresponding to the row of anti-fuse storage structures, providing a second voltage to the first programming line corresponding to the row of anti-fuse storage structures, providing a third voltage to the first bit lines corresponding to the first anti-fuse structures in the row of anti-fuse storage structures that need to be programmed, and providing a sixth voltage to the first bit lines corresponding to the first anti-fuse structures in the row of anti-fuse storage structures that do not need to be programmed, so as to perform the programming operation on the first anti-fuse structures in the row of anti-fuse storage structures; or, providing the first voltage to the selection control line corresponding to the row of anti-fuse storage structures, providing the second voltage to the second programming line corresponding to the row of anti-fuse storage structures, providing the third voltage to the second bit line corresponding to the second anti-fuse structure in the row of anti-fuse storage structures that needs to be programmed, and providing the sixth voltage to the second bit line corresponding to the second anti-fuse structure in the row of anti-fuse storage structures that does not need to be programmed, so as to perform the programming operation on the second anti-fuse structure in the row of anti-fuse storage structures; Among them, the first voltage is the turn-on voltage of the selection transistor, the level difference between the second voltage and the third voltage is not less than the breakdown voltage of the first anti-fuse structure, and is not less than the breakdown voltage of the second anti-fuse structure, and the level difference between the second voltage and the sixth voltage is less than the breakdown voltage of the first anti-fuse structure, and less than the breakdown voltage of the second anti-fuse structure.

15. The method for operating the antifuse memory array structure according to claim 14, wherein: In the step of performing the programming operation, no voltage signal is provided to the selection control line corresponding to the anti-fuse storage structure in other rows, no voltage signal is provided to the first programming line and the second programming line corresponding to the anti-fuse storage structure in other rows, or the third voltage is provided to both the first programming line and the second programming line corresponding to the anti-fuse storage structure in other rows; During the programming operation on the first anti-fuse structure in the row of anti-fuse storage structures, not providing a voltage signal to all of the second bit lines, not providing a voltage signal to the second programming lines corresponding to the anti-fuse storage structures in the row, or providing the third voltage to the second programming lines corresponding to the anti-fuse storage structures in the row; During the programming operation on the second anti-fuse structure in the row of anti-fuse storage structures, no voltage signal is provided to all of the first bit lines, no voltage signal is provided to the first programming line corresponding to the anti-fuse storage structure in the row, or the third voltage is provided to the first programming line corresponding to the anti-fuse storage structure in the row.

16. The method for operating the antifuse memory array structure according to claim 14, wherein: Performing a read operation on the anti-fuse storage structures in the same row of the anti-fuse storage array structure includes: providing the first voltage to the selection control line corresponding to the row of anti-fuse storage structures, providing the fourth voltage to the first programming line corresponding to the row of anti-fuse storage structures, providing the fifth voltage to the first bit line corresponding to the first anti-fuse structure that needs to be read in the row of anti-fuse storage structures, and providing the seventh voltage to the first bit line corresponding to the first anti-fuse structure that does not need to be read in the row of anti-fuse storage structures, so as to perform the read operation on the first anti-fuse structure in the row of anti-fuse storage structures; or, providing the first voltage to the selection control line corresponding to the row of anti-fuse storage structures, providing the fourth voltage to the second programming line corresponding to the row of anti-fuse storage structures, providing the fifth voltage to the second bit line corresponding to the second anti-fuse structure to be read in the row of anti-fuse storage structures, and providing the seventh voltage to the second bit line corresponding to the second anti-fuse structure not to be read in the row of anti-fuse storage structures, so as to perform the read operation on the second anti-fuse structure in the row of anti-fuse storage structures; The level of the fifth voltage is greater than the level of the fourth voltage and less than the level of the first voltage, and the level of the seventh voltage is not greater than the level of the fifth voltage.

17. The method for operating the antifuse memory array structure according to claim 16, wherein: In the step of performing the reading operation, no voltage signal is provided to the selection control lines corresponding to the anti-fuse storage structures in other rows, or the fourth voltage is provided to the selection control lines corresponding to the anti-fuse storage structures in other rows; During the read operation of the first anti-fuse structure in the row of anti-fuse storage structures, no voltage signal is provided to all the second bit lines, no voltage signal is provided to the first programming lines corresponding to the anti-fuse storage structures in other rows, and the fifth voltage or the seventh voltage is provided to all the second programming lines; During the reading operation on the second anti-fuse structure in the row of anti-fuse storage structures, no voltage signal is provided to all the first bit lines, no voltage signal is provided to the second programming lines corresponding to other rows of anti-fuse storage structures, and the fifth voltage or the seventh voltage is provided to all the first programming lines.

18. A memory, characterized in that: The antifuse storage structure comprises the antifuse storage structure according to any one of claims 1 to 6, or the antifuse storage array structure according to claim 12.

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