Diamond / single-crystalline silicon composite three-dimensional substrate, preparation method and application thereof

Abstract

The present invention discloses a diamond / single-crystalline silicon composite three-dimensional substrate, a preparation method thereof and an application. The diamond / single-crystalline silicon composite three-dimensional substrate includes a single-crystalline silicon substrate and a diamond layer disposed on the single-crystalline silicon substrate. A micro-nano structure is formed on a surface of the diamond layer away from the single-crystalline silicon substrate, and the micro-nano structure includes a plurality of protruding portions distributed at intervals. The diamond / single-crystalline silicon composite three-dimensional substrate provided by the present invention forms a composite three-dimensional substrate by combining the diamond layer and the single-crystalline silicon substrate. The diamond layer is used to achieve high-efficiency heat dissipation, and the single-crystalline silicon substrate is used to fabricate silicon-based devices. Moreover, a micro-nano structure formed by a plurality of protruding portions is disposed on the surface of the diamond layer, further improving the heat dissipation efficiency, thereby greatly improving the heat dissipation performance for high-heat-generation-rate devices such as GPUs, improving the computing performance and lifespan of the devices, and reducing the cost per unit computing power.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to a diamond / single crystal silicon composite three-dimensional substrate, and a preparation method and application thereof. Background Art

[0002] A graphics processing unit (GPU), also known as a display core, visual processor, or display chip, is a microprocessor that is specialized in performing image and graphics-related calculations on personal computers, workstations, game consoles, and some mobile devices (such as tablets, smart phones, etc.). Not only in the field of image processing, but also with the development of AI technology, the demand for GPU chips in the field of AI is also growing.

[0003] Existing GPU chips have the problem of high heat generation, increasing computing power hardware power, and increasing chip heat flux density. In the chip field, when the chip temperature is high, long-term high-temperature operation will result in a short GPU life and low performance, leading to increased economic and time costs. Moreover, long-term operation of the chip at high temperatures will lead to reduced performance. According to the "Ten-degree Rule", starting from room temperature, the failure rate of electronic components doubles for every ten degrees increase in temperature, and the life span will also decrease. The failure rate of GPU spare parts will increase, which will lead to an increase in computing power costs throughout the life cycle. The development trend in the chip field over the past few decades has been increasing power and increasing heat flux, and this will also be the case in the foreseeable future.

[0004] Some existing technologies have proposed various solutions to achieve efficient heat dissipation of GPUs. For example, some existing technologies have mentioned using the high thermal conductivity of diamond as part of the chip substrate to enhance heat dissipation. However, the existing technologies have not yet fully utilized the best performance of diamond heat dissipation. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention aims to provide a diamond / single crystal silicon composite three-dimensional substrate, a preparation method and application thereof, and to improve the heat dissipation effect of the diamond composite substrate on high heat generation devices such as GPUs.

[0006] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0007] In a first aspect, the present invention provides a diamond / single crystal silicon composite three-dimensional substrate, which includes a single crystal silicon base and a diamond layer arranged on the single crystal silicon base, wherein a micro-nano structure is formed on a surface of the diamond layer on a side away from the single crystal silicon base, and the micro-nano structure includes a plurality of protrusions distributed at intervals.

[0008] In a second aspect, the present invention further provides a method for preparing the above diamond / single-crystalline silicon composite three-dimensional substrate, which includes:

[0009] Providing a first silicon wafer, the first silicon wafer including a first surface and a second surface facing away from each other;

[0010] In-situ growing a diamond layer on the first surface;

[0011] Performing a thinning process on the second surface to form a first silicon layer with a thinned surface;

[0012] Providing a second silicon wafer and bonding the second silicon wafer to the thinned surface by silicon-silicon bonding as the second silicon layer to obtain a diamond / single-crystalline silicon composite three-dimensional substrate.

[0013] In a third aspect, the present invention further provides a semiconductor chip heat dissipation structure, which is characterized by including:

[0014] A semiconductor chip and the above diamond / single-crystalline silicon composite three-dimensional substrate, the semiconductor chip being disposed on a surface of the single-crystalline silicon substrate in the diamond / single-crystalline silicon composite three-dimensional substrate away from the diamond layer.

[0015] Based on the above technical solutions, compared with the prior art, the beneficial effects of the present invention at least include:

[0016] The diamond / single-crystalline silicon composite three-dimensional substrate provided by the present invention forms a composite three-dimensional substrate by combining a diamond layer and a single-crystalline silicon substrate. The diamond layer is used to achieve high-efficiency heat dissipation, and the single-crystalline silicon substrate is used to fabricate silicon-based devices. Moreover, a micro-nano structure formed by a plurality of protrusions is provided on the surface of the diamond layer, further improving the heat dissipation efficiency, thereby greatly improving the heat dissipation performance for high-heat-generation devices such as GPUs, improving the computing performance and lifespan of the devices, and reducing the cost per unit of computing power.

[0017] The above description is only an overview of the technical solutions of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement it in accordance with the content of the specification, the following is a detailed description with reference to the preferred embodiments of the present invention and accompanying drawings. Description of the Drawings

[0018] Figure 1 is an electron microscope photograph of the micro-nano structure on the surface of the diamond layer of the diamond / single-crystalline silicon composite three-dimensional substrate provided by a typical embodiment of the present invention;

[0019] Figure 2 is a schematic flow chart of the method for preparing the diamond / single-crystalline silicon composite three-dimensional substrate provided by a typical embodiment of the present invention. Detailed Embodiments

[0020] In view of the deficiencies in the prior art, through long-term research and a large number of practices, the inventors of this case have been able to propose the technical solution of the present invention. The following will further explain the technical solution, its implementation process, principles, etc.

[0021] In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited by the specific embodiments disclosed below.

[0022] Moreover, relational terms such as "first" and "second" are only used to distinguish one component or method step with the same name from another, and do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0023] An embodiment of the present invention provides a diamond / single-crystalline silicon composite three-dimensional substrate, which includes a single-crystalline silicon substrate and a diamond layer provided on the single-crystalline silicon substrate. A micro-nano structure is formed on a surface of the diamond layer away from the single-crystalline silicon substrate. The micro-nano structure includes a plurality of protruding portions distributed at intervals, and the morphology of these protruding portions is, for example Figure 1 as shown, but is not limited to the state shown in this image (such as spacing, shape, height, diameter, etc.).

[0024] Regarding the specific dimensions and structural characteristics of the above composite three-dimensional substrate, in some embodiments, the height of the protruding portion is 5%-50% of the thickness of the diamond layer, and the diameter is 1-100 μm.

[0025] In some embodiments, along a first direction pointing from the center of the diamond layer to the center of the single-crystalline silicon substrate, the single-crystalline silicon substrate sequentially includes a first silicon layer and a second silicon layer. The first silicon layer has a first surface and a second surface facing away from each other. The diamond layer is formed in-situ on the first surface, and the second surface is silicon-silicon bonded to the second silicon layer.

[0026] In some embodiments, the first silicon layer is formed by thinning a silicon wafer, and the thickness is 20-30 μm; the second silicon layer includes at least one complete silicon wafer, and this silicon wafer is directly bonded to the first silicon layer.

[0027] In some embodiments, the thickness of the diamond layer is 100 μm-2 mm.

[0028] In addition, regarding the surface structure of the diamond layer, the conventional processing method usually processes it into a conventional solution where each convex portion is evenly distributed at equal intervals and each convex portion is the same. This is because this processing method is simpler and easier to implement. However, the inventors of the present invention have found that for devices with a relatively high power density such as GPUs, their heat and thermal stress actually have the characteristic of regional distribution. Heat energy is usually concentrated in the central region, and the degree of heat energy concentration in the peripheral region is less than that in the central region. As a result, it is easy to cause a temperature difference between the inner and outer regions, leading to the problem of local failure.

[0029] Therefore, in some embodiments, along a second direction pointing from the center of the diamond layer to the edge, the heights of the plurality of convex portions are equal, the diameters gradually decrease, and the spacing between adjacent convex portions gradually increases.

[0030] The above-mentioned gradually changing trend can usually be in a linear change manner. However, the present invention also proposes a more optimized distribution method. That is, in some embodiments, in the first direction, if it is defined that among any two adjacent convex portions, the diameter of the convex portion relatively closer to the center of the diamond layer is R x , the diameter of the convex portion relatively farther from the center of the diamond layer is Ry, and the spacing between the two convex portions is D, then:

[0031] R y = R x ×α×L 2 / (L + D) 2 ;

[0032] D = D 1 +β×L;

[0033] Among them, α represents the diameter proportionality coefficient, and the usual value range is 0.8 ≤ a < 1; β represents the spacing proportionality coefficient; D 1 represents the spacing between the previous two adjacent convex portions; L represents the distance between the center of the convex portion relatively closer to the center of the diamond layer and the center of the diamond layer.

[0034] In some embodiments:

[0035] α = exp(-(H Si1 -H Si2 ) / H Si2 ×H b / (H d +H b ));

[0036] Among them, H d is the thickness of the diamond layer, H b is the height of the convex portion, H Si1 is the thickness of the first silicon layer before thinning, which is the in-situ growth substrate of the diamond layer.Si1 is the thickness of the first silicon layer after thinning; β is a fixed value, and its value range is 0.01 - 0.05.

[0037] By setting the size and spacing of the protrusions forming the micro-nano structure to satisfy the above mathematical relationship, the following technical effects can be achieved:

[0038] Firstly, during the process of thinning the first silicon layer, the stress in the diamond layer will not be released concentratedly, preventing cracks from appearing in the diamond layer or causing the diamond layer to break, and also ensuring that the diamond layer remains flat, avoiding the detachment of local areas of the diamond layer from the first silicon layer.

[0039] Secondly, the thermal conductivity of the diamond layer can be gradientized in the planar direction. That is, when dissipating heat from the GPU bonded to it, the heat in the central area of the GPU with the highest temperature can be transferred out at a very fast speed, while the heat in the peripheral area of the GPU with a relatively lower temperature can be transferred out at a relatively slower speed (but still much higher than the heat dissipation speed of the prior art), avoiding a large temperature difference between the central area and the peripheral area of the GPU, making the temperatures of these areas basically the same, that is, achieving the temperature equalization effect, avoiding damage to the GPU chip, ensuring its normal working performance, and extending its service life.

[0040] In addition to the gradient setting of the protrusions, the present invention also proposes to further reduce the problem of thermal expansion mismatch between silicon and diamond by setting annular grooves. That is, in some embodiments, on the surface of the diamond layer away from the single-crystal silicon substrate, a plurality of concentrically arranged annular grooves are also provided, and the center of the annular grooves coincides with the center of the diamond layer. The depth of the annular grooves is 5 - 50% of the thickness of the diamond layer.

[0041] For these grooves, they are also preferably distributed in a regionalized manner. One is to block pressure conduction and reduce the stress effect; the other is to cooperate with the micro-nano structure to adjust the thermal conductivity of each area of the diamond layer.

[0042] That is, in some embodiments, the surface of the diamond layer is divided into a central area and a peripheral area. The diameter of the central area is 30 - 60% of the outer diameter of the diamond layer. The depth of the annular grooves in the central area is 30 - 50% of the thickness of the diamond layer, and the width is 10 - 25 μm. The depth of the annular grooves in the peripheral area is 1 / 8 - 1 / 6 of the depth of the annular grooves in the central area, and the width is 30 - 70 μm. And the total planar area of all the annular grooves in the central area is lower than the total planar area of all the annular grooves in the peripheral area.

[0043] The main reason for the above preferred settings is that the inventor believes that the grooves near the central region of the diamond layer should be long, narrow, and relatively deep, but the area ratio on the surface of the diamond layer should be small. This is because the central region of the diamond layer is in contact with the central region of the GPU. The GPU is silicon-based, and the central region of the GPU generates heat fastest and has the highest temperature, so its thermal expansion degree is the largest, and the pressure generated on the central region of the diamond layer is the largest. Through the grooves in these central regions, most of the pressure received by the central region of the diamond layer can be quickly released at the grooves, and the conduction of this pressure along the plane direction to the peripheral region of the diamond layer can be blocked; however, the area occupied by the grooves in the central region cannot be too large, otherwise the impact on heat conduction is relatively obvious, which will reduce the heat dissipation performance of the central region and bring adverse effects.

[0044] Similarly, conversely, the grooves farther away from the central region of the diamond layer are wider and shallower, and the area ratio on the surface of the diamond layer is getting larger and larger.

[0045] As Figure 2 shown, corresponding to the structural features of the above diamond / single-crystalline silicon composite three-dimensional substrate, an embodiment of the present invention also provides a preparation method, which includes the following steps:

[0046] Provide a first silicon wafer, and the first silicon wafer includes a first surface and a second surface facing each other;

[0047] In-situ grow a diamond layer on the first surface;

[0048] Perform a thinning process on the second surface to form a first silicon layer with a thinned surface;

[0049] Provide a second silicon wafer, and bond the second silicon wafer to the thinned surface as the second silicon layer to obtain a diamond / single-crystalline silicon composite three-dimensional substrate.

[0050] In some embodiments, the above preparation method may specifically include the following process:

[0051] After growing a diamond material layer with a preset thickness, perform a grinding process on the obtained diamond material layer to make the surface roughness Ra value less than 1 nm to obtain the diamond layer;

[0052] Perform a first annealing process on the first combination body composed of the diamond layer and the first silicon wafer;

[0053] Then, construct a micro-nano structure on the surface of the diamond layer.

[0054] In some embodiments, it may further include the following process:

[0055] After constructing the micro-nano structure, process grooves on the surface of the diamond layer through micro-nano processing.

[0056] In some embodiments, with regard to subsequent processing steps, the following processes may specifically be further included:

[0057] Through the thinning process, the Ra value of the formed thinned surface is below 1 nm;

[0058] Perform a second annealing treatment on the second combination formed by the diamond layer and the first silicon layer;

[0059] After surface cleaning the thinned surface, make it contact with the surface of the second silicon wafer under pressure to perform pre-bonding;

[0060] Perform a third annealing treatment on the third combination obtained by pre-bonding to obtain the diamond / single-crystalline silicon composite three-dimensional substrate.

[0061] The main technical concept of the above technical solution lies in the preparation, processing, surface treatment of the diamond substrate, and the bonding with the chip during subsequent applications. This structure can bring better heat dissipation, reduce the junction temperature, quickly export the heat of the chip, thereby improving the chip life and chip efficiency. When the value of a single chip exceeds a certain value, the value brought by the increased life and working efficiency will exceed the increase in the substrate cost, thus forming an improvement in the comprehensive cost and cost efficiency. Reduce the cost per unit of computing power.

[0062] As an application of the above technical solution, an embodiment of the present invention further provides a semiconductor chip heat dissipation structure, which includes:

[0063] A semiconductor chip;

[0064] The diamond / single-crystalline silicon composite three-dimensional substrate provided or prepared by any of the above embodiments, and the semiconductor chip is disposed on one side of the single-crystalline silicon substrate in the diamond / single-crystalline silicon composite three-dimensional substrate away from the diamond layer.

[0065] Specifically, in some embodiments, the semiconductor chip includes a GPU chip.

[0066] In some embodiments, the semiconductor chip is directly constructed based on the single-crystalline silicon matrix.

[0067] As some typical examples, a complete device preparation process includes: growing a diamond layer on a single-crystalline silicon substrate → processing the diamond by grinding and polishing, etc. → thinning and polishing the underlying substrate single-crystalline silicon to 20 - 30 μm → performing silicon-silicon bonding with another single-crystalline silicon wafer → and then preparing a chip on the other side.

[0068] Specifically as a typical example of the above technical solution, the above preparation process is:

[0069] 1. Clean the substrate for growing polycrystalline diamond films, i.e., a single-crystalline silicon wafer. The cleaning can be carried out by ultrasonic cleaning with acetone, alcohol, and water: Immerse the substrate in the solution so that the liquid level is more than 5 mm above the substrate, and use ultrasonic waves for cleaning.

[0070] 2. After cleaning, the substrate is dried with an inert gas.

[0071] 3. After drying, seed crystals are deposited on the substrate to facilitate the subsequent growth of diamond on the substrate: Use diamond nanocrystals with a particle size of 5 - 10 nm to deposit diamond seeds on the silicon substrate, which is beneficial for the subsequent growth of diamond.

[0072] 4. Place the substrate in an MPCVD device to grow polycrystalline diamond films: Use hydrogen and methane to grow diamond in the temperature range of 800 - 1000 °C. The growth conditions are, for example, a hydrogen flow rate of 100 - 1000 sccm and a methane flow rate of 1 - 50 sccm; however, it should be noted that the specific growth conditions are not the key of the present invention, and those skilled in the art can replace them with other conditions or other growth methods, which all belong to equivalent replacements.

[0073] 5. After completion of growth, take it out to obtain a silicon / diamond material, and the thickness of the formed diamond layer is between 100 microns and 2 millimeters.

[0074] 6. Grind and polish the diamond: For example, use CMP to process the diamond surface until the Ra value is less than 1 nm. The function of polishing is, on the one hand, to make the diamond surface flat, which is beneficial for ensuring higher controllability of the morphology of the formed micro-nano structures in the subsequent micro-nano structure processing procedures, and on the other hand, to partially eliminate the stress accumulated in the diamond layer and facilitate better release of the stress inside the diamond layer during subsequent vacuum cyclic annealing.

[0075] 7. Perform vacuum cyclic annealing on the diamond and silicon to reduce the internal stress of the material. The temperature range is 0 - 600 °C. The specific conditions of the vacuum cyclic annealing may not be specifically limited, as long as the substrate structure is not damaged and the stress can be reduced. One can refer to various existing annealing processes or obtain appropriate process conditions through self-experimentation with conditions.

[0076] 8. Subsequently, use picosecond laser to perform micro-nano structure processing on the diamond surface to increase the surface area of the diamond, improve the contact area, and accelerate the heat exchange rate. Such micro-nano structures should meet the following two functions: 1. Increase the surface area; 2. Facilitate heat exchange. In addition to this processing method, such micro-structures can also be obtained by mask etching. The preferred micro-structure is an arc-shaped body, and of course, the cases of conical or square bodies are not excluded.

[0077] 9. Thinning and polishing the silicon wafer to 20 - 30 μm. At the same time, processing the surface Ra value to below 1 nm.

[0078] 10. During the silicon thinning process, cyclic annealing is also carried out. During the cyclic annealing process, a flattening pressure of 0 - 5 N is applied. The temperature range is 0 - 600 °C. As described above, the specific annealing conditions can be set by oneself, and it is advisable to be able to avoid damage and reduce stress.

[0079] 11. Put the processed sample into a vacuum environment for preservation (this step belongs to a transfer process and may be omitted in some cases, such as in a vacuum interconnection system).

[0080] 12. Perform silicon - silicon bonding: First, clean another new silicon wafer. Ultrasonically clean the surface impurities with acetone, alcohol, and water in turn for 15 min. Then soak the silicon wafer in HF for 15 min to remove the natural oxide layer on the surface. Put the cleaned silicon wafer into a bonding machine and bond the thinned surface mentioned above. When the pressure in the bonding machine drops to 1 mbar, apply a force of 0 - 5 N to the silicon wafer to complete the pre - bonding.

[0081] 13. Put the bonded silicon wafer into an annealing furnace for vacuum annealing at 800 °C for 2 hours. The heating rate and cooling rate are 5 °C / min.

[0082] 14. Obtain the structure of diamond / first silicon layer / second silicon layer after bonding. At this time, it can be used as a diamond / single - crystal silicon composite three - dimensional substrate.

[0083] 15. However, in order to further reduce the thermal mismatch between the diamond layer and the silicon layer, and further reduce the influence of thermal stress on the heat dissipation stability, a symmetric groove - like structure can also be processed on the surface of the diamond layer by micro - nano processing. The composite structure with this groove - like structure is used as another diamond / single - crystal silicon composite three - dimensional substrate.

[0084] 16. As a specific application of the above - mentioned diamond / single - crystal silicon composite three - dimensional substrate, GPU devices can be prepared on the surface of the second silicon layer as needed. The specific GPU preparation method and process are not the key of the present invention. Those skilled in the art can appropriately select existing solutions or set personalized preparation solutions. In addition, the heat dissipation structure provided by the present invention is not limited to GPU chips. Other chips with relatively large heat generation and concentrated heat energy can also adopt the technical idea provided by the present invention to achieve stable and efficient heat dissipation.

[0085] The technical solutions of the present invention will be further described in detail below through several embodiments in combination with the accompanying drawings. However, the selected embodiments are only used to illustrate the present invention and do not limit the scope of the present invention.

[0086] Example 1

[0087] This embodiment exemplifies the preparation process of a diamond / single-crystal silicon composite three-dimensional substrate and the process of fabricating a GPU device using this substrate, which is specifically as follows:

[0088] 1. Clean a 4-inch single-crystal silicon wafer with a thickness of 4 mm: Immerse the substrate in a mixed solution of acetone and alcohol, making the liquid level more than 5 mm above the substrate, and use ultrasound for cleaning.

[0089] 2. After cleaning, dry the single-crystal silicon wafer with an inert gas.

[0090] 3. After drying, seed the substrate to facilitate the subsequent growth of diamond on the substrate: Use diamond nanocrystals with a particle size distribution of 5 - 10 nm to seed the silicon substrate with diamond.

[0091] 4. Place the substrate in an MPCVD device for polycrystalline diamond film growth: Use hydrogen and methane to grow diamond at 900 °C. During growth, the hydrogen flow rate is 500 sccm and the methane flow rate is 20 sccm.

[0092] 5. After completion of growth, take it out to obtain a silicon / diamond material, and the thickness of the formed diamond layer is 300 μm.

[0093] 6. Grind and polish the diamond layer: Use CMP to process the diamond surface until the Ra value is less than 1 nm.

[0094] 7. Perform vacuum cyclic annealing on diamond and silicon to reduce the internal stress of the material. The heating rate is 5 °C per minute. The maximum temperature is 600, the time is 12 h, and it is cycled 4 times.

[0095] 8. Subsequently, use a picosecond laser to perform micro-nano structure processing on the diamond surface to form an arrayed arc-shaped convex micro-nano structure. Its height is 15% of the thickness of the diamond layer, and the distance between the innermost convex part and the center of the substrate is 30 μm, and the diameter is 10 μm. The diameters and distances of the remaining convex parts satisfy the following rules:

[0096] R y =R x ×α×L 2 / (L + D) 2 ;

[0097] D = β×L;

[0098] Wherein, the diameter of the convex part relatively close to the center of the diamond layer is R x , the diameter of the convex part relatively far from the center of the diamond layer is R y , the distance between the two convex parts is D, D 1denotes the spacing between two adjacent protrusions in the previous layer; α represents the diameter ratio coefficient, which is calculated according to the formula α = exp(-(H Si1 - H Si2 ) / H Si2 × H b / (H d + H b )) Here, H d is the thickness of the diamond layer, H b is the height of the protrusion, H Si1 is the thickness of the first silicon layer before thinning, which is the in-situ growth substrate of the diamond layer, and H Si1 is the thickness of the first silicon layer after thinning. The calculated value of α is 0.89; β represents the spacing ratio coefficient, which is a fixed value and takes 0.02 in this embodiment; L represents the distance between the center of the protrusion relatively close to the center of the diamond layer and the center of the diamond layer.

[0099] 9. Thinning and polishing the silicon wafer to 25 μm. At the same time, processing the surface ra value to less than 1 nm.

[0100] 10. Perform cyclic annealing during the silicon thinning process, and apply a flat pressure of 5 N during the cyclic annealing process. The heating rate is 5 °C per minute. The maximum temperature is 600, the time is 12 h, and the cycle is 4 times.

[0101] 11. Place the processed sample in a vacuum environment for storage.

[0102] 12. Perform silicon-silicon bonding: First, clean another new silicon wafer of the same size. Use acetone, alcohol, and water to ultrasonically clean the surface impurities for 15 minutes in sequence. Then soak the silicon wafer in HF for 15 minutes to remove the natural oxide layer on the surface. Put the cleaned silicon wafer into the bonding machine and bond the thinned surface mentioned above. When the pressure in the bonding machine drops to 1 mbar, apply a force of 5 N to the silicon wafer to complete the pre-bonding.

[0103] 13. Put the bonded silicon wafer into an annealing furnace for vacuum annealing at 800 °C for 2 hours. The heating rate and the cooling rate are 5 °C / min.

[0104] 14. Obtain the bonded diamond / first silicon layer / second silicon layer structure.

[0105] 15. In order to further reduce the thermal mismatch between the diamond layer and the silicon layer, and thus reduce the influence of thermal stress on the heat dissipation stability, continue to process a symmetric groove structure on the surface of the diamond layer by micro-nano processing. Use the composite structure with this groove structure as the diamond / single-crystalline silicon composite three-dimensional substrate obtained in this embodiment.

[0106] The grooved structure is regionalized, defining the central region as the region within 50% of the outer diameter of the substrate. The depth of the annular groove in the central region is 30% of the thickness of the diamond layer, and the width is 20 μm. The depth of the annular groove in the outer peripheral region is 1 / 6 of the depth of the annular groove in the central region, and the width is 60 μm. And the spacing of the annular grooves in the central region and the outer peripheral region is appropriately set so that the total planar area of all the annular grooves in the central region is 50% of the total planar area of all the annular grooves in the outer peripheral region.

[0107] Using traditional processes, the production of GPU chips is continued on the outermost silicon wafer to obtain a device with a complete heat dissipation structure.

[0108] Perform the operation test on this device. After maintaining full computing power operation for 20 minutes, use an infrared camera to test the temperature of the chip area. It can be found that there is no obvious high-temperature area on this chip, and the temperature at each place can be controlled at an ideal low temperature.

[0109] Example 2

[0110] This example is generally the same as Example 1, and the main difference is:

[0111] Change the diameter change of multiple protrusions to a linear change, and the maximum value and the minimum value remain unchanged.

[0112] Perform the same operation test on the obtained chip. It can be found that the temperature in the central region of this chip is slightly higher than that in the surrounding regions by about 2 °C.

[0113] Example 3

[0114] This example is generally the same as Example 1, and the main difference is:

[0115] Adjust the spacing of multiple protrusions to be equal to the average value in Example 1, so that the total number of protrusions remains unchanged.

[0116] Perform the same operation test on the obtained chip. It can be found that the temperature in the central region of this chip is slightly higher than that in the surrounding regions by about 5 °C.

[0117] Comparative Example 1

[0118] This comparative example is generally the same as Example 1, and the main difference is:

[0119] No micro-nano structure is processed on the surface of the diamond layer.

[0120] Perform the same operation test on the obtained chip. It can be found that the temperature in the central region of this chip is about 10 °C higher than that in Example 1, and the temperature in the surrounding regions is also about 6 °C higher than that in the surrounding regions of Example 1.

[0121] Example 4

[0122] This example demonstrates the preparation process of a diamond / single-crystalline silicon composite three-dimensional substrate and the process of fabricating a GPU device using this substrate, which is specifically as follows:

[0123] 1. Clean the single-crystalline silicon wafer: Immerse the substrate in a mixed solution of acetone and alcohol, ensuring that the liquid level is more than 5 mm above the substrate, and use ultrasonic waves for cleaning.

[0124] 2. Dry the cleaned single-crystalline silicon wafer using an inert gas.

[0125] 3. Seed the substrate after drying to facilitate the subsequent growth of diamond on the substrate: Use diamond nanocrystals with a particle size distribution of 5 - 10 nm to seed the silicon substrate with diamond.

[0126] 4. Place the substrate in an MPCVD device for the growth of polycrystalline diamond thin film: Use hydrogen and methane to grow diamond at 800 °C. During growth, the hydrogen flow rate is 100 sccm and the methane flow rate is 3 sccm.

[0127] 5. After completion of growth, take out the sample to obtain a silicon / diamond material, and the thickness of the formed diamond layer is 100 μm.

[0128] 6. Grind and polish the diamond layer: Use chemical mechanical polishing (CMP) to process the diamond surface until the Ra value is less than 1 nm.

[0129] 7. Perform vacuum cyclic annealing on diamond and silicon to reduce the internal stress of the material.

[0130] 8. Subsequently, use picosecond laser to perform micro-nano structure processing on the diamond surface to form an arrayed arc-shaped convex micro-nano structure. Its height is 50% of the thickness of the diamond layer, and the diameter of these micro-nano structures is 30 μm, with a spacing of 80 μm.

[0131] 9. Thin and polish the silicon wafer to 30 μm. At the same time, process the surface Ra value to less than 1 nm.

[0132] 10. Also perform cyclic annealing during the thinning of silicon, and apply a flat pressure of 2 N during the cyclic annealing process.

[0133] 11. Place the processed sample in a vacuum environment for storage.

[0134] 12. Perform silicon-silicon bonding: First, clean another new silicon wafer of the same size. Use acetone, alcohol, and water to ultrasonically clean the surface impurities for 15 minutes in sequence. Then, immerse the silicon wafer in HF for 15 minutes to remove the native oxide layer on the surface. Put the cleaned silicon wafer into a bonding machine and bond the thinned surface mentioned above. When the pressure in the bonding machine drops to 1 mbar, apply a force of 5 N to the silicon wafer to complete the pre-bonding.

[0135] 13. Put the bonded silicon wafer into an annealing furnace for vacuum annealing at 800 °C for 2 hours. The heating rate and cooling rate are 5 °C / min.

[0136] 14. Obtain the bonded diamond / first silicon layer / second silicon layer structure, which serves as the diamond / single-crystalline silicon composite three-dimensional substrate obtained in this embodiment.

[0137] Using the traditional process, continue to fabricate the GPU chip on the outermost silicon wafer to obtain a device with a complete heat dissipation structure.

[0138] Although the heat dissipation efficiency of the heat dissipation structure provided in this embodiment is not as good as that of Embodiments 1-3, and there is also a tendency that the temperature in the central region is significantly higher than that in the peripheral region, it still has achieved a significant improvement compared to Comparative Example 1.

[0139] Embodiment 5

[0140] This embodiment exemplifies the preparation process of a diamond / single-crystalline silicon composite three-dimensional substrate and the process of fabricating a GPU device using this substrate, which is specifically as follows:

[0141] 1. Clean the single-crystalline silicon wafer: Immerse the substrate in a mixed solution of acetone and alcohol, making the liquid level more than 5 mm above the substrate, and use ultrasonic waves for cleaning.

[0142] 2. After cleaning, use an inert gas to blow dry the single-crystalline silicon wafer to make it dry.

[0143] 3. After drying, perform seeding on the substrate to facilitate the subsequent growth of diamond on the substrate: Use diamond nanocrystals with a particle size distribution of 5-10 nm to perform diamond seeding on the silicon substrate.

[0144] 4. Put the substrate into an MPCVD device for polycrystalline diamond thin film growth: Use hydrogen and methane to grow diamond at 1000 °C. During growth, the hydrogen flow rate is 1000 sccm and the methane flow rate is 50 sccm.

[0145] 5. Take it out after completion of growth to obtain a silicon / diamond material, and the thickness of the formed diamond layer is 2 mm.

[0146] 6. Grind and polish the diamond layer: Use CMP to process the diamond surface until the Ra value is less than 1 nm.

[0147] 7. Perform vacuum cyclic annealing on the diamond and silicon to reduce the internal stress of the material..

[0148] 8. Subsequently, use picosecond laser to perform micro-nano structure processing on the diamond surface to form an arrayed arc-shaped convex micro-nano structure. Its height is 5% of the diamond layer thickness, and the diameter of these micro-nano structures is 50 μm, and the spacing is 100 μm.

[0149] 9. Thin and polish the silicon wafer to 20 μm. At the same time, process the surface Ra value to less than 1 nm.

[0150] 10. Also perform cyclic annealing during the silicon thinning process, and apply a flat pressure of 2 N during the cyclic annealing process..

[0151] 11. Place the processed sample in a vacuum environment for storage.

[0152] 12. Perform silicon-silicon bonding: First, clean another new silicon wafer of the same size. Use acetone, alcohol, and water to ultrasonically clean the surface impurities for 15 minutes in sequence. Then soak the silicon wafer in HF for 15 minutes to remove the natural oxide layer on the surface. Place the cleaned silicon wafer into the bonding machine and bond the thinned surface mentioned above. When the pressure in the bonding machine drops to 1 mbar, apply a force of 5 N to the silicon wafer to complete the pre-bonding.

[0153] 13. Place the bonded silicon wafer into an annealing furnace for vacuum annealing at 800 °C for 2 hours. The heating rate and cooling rate are 5 °C / min.

[0154] 14. Obtain the structure of the bonded diamond / first silicon layer / second silicon layer as the diamond / single-crystal silicon composite three-dimensional substrate obtained in this embodiment.

[0155] Adopt the traditional process to continue manufacturing the GPU chip on the outermost silicon wafer to obtain a device with a complete heat dissipation structure.

[0156] Although the heat dissipation efficiency of the heat dissipation structure provided in this embodiment is not as good as that of Embodiments 1-3, and there is also a tendency that the temperature in the central region is significantly higher than that in the peripheral region, it still has achieved a significant improvement compared to Comparative Example 1.

[0157] Based on the above embodiments and comparative examples, it can be clearly seen that the diamond / single-crystalline silicon composite three-dimensional substrate provided by the embodiments of the present invention forms a composite three-dimensional substrate by combining a diamond layer and a single-crystalline silicon substrate. The diamond layer is used to achieve high-efficiency heat dissipation, and the single-crystalline silicon substrate is used to fabricate silicon-based devices. Moreover, a micro-nano structure formed by a plurality of protrusions is provided on the surface of the diamond layer, further improving the heat dissipation efficiency. Thereby, the heat dissipation performance of high-heat-generation-rate devices such as GPUs is greatly improved, the computing performance and lifespan of the devices are enhanced, and the cost per unit of computing power is reduced.

[0158] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It should not be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A diamond / single crystal silicon composite three-dimensional substrate, characterized in that: It comprises a single crystal silicon substrate and a diamond layer arranged on the single crystal silicon substrate, wherein a micro-nano structure is formed on a surface of the diamond layer on a side away from the single crystal silicon substrate, and the micro-nano structure comprises a plurality of protrusions distributed at intervals; Along a first direction pointing from the center of the diamond layer to the center of the single crystal silicon substrate, the single crystal silicon substrate sequentially comprises a first silicon layer and a second silicon layer, the first silicon layer has a first surface and a second surface facing each other, the diamond layer is in-situ formed on the first surface, and the second surface generates silicon-silicon bonding with the second silicon layer; The first silicon layer is formed by thinning a silicon wafer, and has a thickness of 20 to 30 μm; the second silicon layer includes at least one complete silicon wafer, and the silicon wafer is directly bonded to the first silicon layer; the thickness of the diamond layer is 100 μm to 2 mm; the height of the protrusion is 5% to 50% of the thickness of the diamond layer, and the diameter is 1 to 100 μm; Along the second direction from the center to the edge of the diamond layer, the heights of the plurality of protrusions are equal, the diameters gradually decrease, and the spacing between adjacent protrusions gradually increases; in the first direction, if any two adjacent protrusions are defined, the diameter of the protrusion relatively close to the center of the diamond layer is R x The diameter of the protrusion relatively far from the center of the diamond layer is R y , the distance between the two protrusions is D, then: R y =R x ×α×L 2 / (L+D) 2 ; D = D1 + β × L; Wherein, α represents the diameter ratio coefficient; β represents the spacing ratio coefficient; D1 represents the spacing between the two adjacent protrusions; L represents the distance between the center of the protrusion relatively close to the center of the diamond layer and the center of the diamond layer; α=exp(-(H Si1 -H Si2 ) / H Si2 ×H b / (H d +H b )); Among them, H d is the thickness of the diamond layer, H b is the height of the protrusion, H Si1 is the thickness of the first silicon layer before thinning, which is the in-situ growth substrate of the diamond layer. Si1 is the thickness of the first silicon layer after thinning; β is a constant value ranging from 0.01 to 0.

05.

2. The diamond / single crystal silicon composite three-dimensional substrate according to claim 1, characterized in that: A plurality of concentrically arranged annular grooves are arranged on the surface of the diamond layer away from the single crystal silicon substrate, and the center of the annular grooves coincides with the center of the diamond layer. The depth of the annular grooves is 5-50% of the thickness of the diamond layer.

3. The diamond / single crystal silicon composite three-dimensional substrate according to claim 2, characterized in that: The surface of the diamond layer is divided into a central area and a peripheral area, and the diameter of the central area is 30-60% of the outer diameter of the diamond layer; The depth of the annular groove in the central area is 30-50% of the thickness of the diamond layer, and the width is 10-25 μm; the depth of the annular groove in the peripheral area is 1 / 8-1 / 6 of the depth of the annular groove in the central area, and the width is 30-70 μm; And the total plane area of ​​all the annular grooves in the central area is lower than the total plane area of ​​all the annular grooves in the peripheral area.

4. A method for preparing a diamond / single crystal silicon composite three-dimensional substrate according to any one of claims 1 to 3, characterized in that: include: Providing a first silicon wafer, wherein the first silicon wafer comprises a first surface and a second surface facing away from each other; In-situ growing a diamond layer on the first surface; Performing a thinning process on the second surface to form a first silicon layer having a thinned surface; A second silicon wafer is provided, and the second silicon wafer is silicon-silicon bonded with the thinned surface to form a second silicon layer, so as to obtain a diamond / single crystal silicon composite three-dimensional substrate.

5. The preparation method according to claim 4, characterized in that: Specifically include: After growing a diamond material layer of a preset thickness, grinding the obtained diamond material layer to make its surface roughness Ra value below 1 nm, thereby obtaining the diamond layer; Performing a first annealing treatment on a first assembly consisting of the diamond layer and the first silicon wafer; Then, a micro-nano structure is constructed on the surface of the diamond layer.

6. The preparation method according to claim 4, characterized in that: Also includes: After constructing the micro-nano structure, grooves are processed on the surface of the diamond layer by micro-nano processing.

7. The preparation method according to claim 4, characterized in that: It also specifically includes: Through the thinning process, the roughness Ra value of the formed thinned surface is less than 1nm; performing a second annealing treatment on a second assembly formed by the diamond layer and the first silicon layer; Afterwards, the thinned surface is cleaned and then brought into contact with the surface of the second silicon wafer under pressure to achieve pre-bonding; The third assembly obtained by pre-bonding is subjected to a third annealing treatment to obtain the diamond / single crystal silicon composite three-dimensional substrate.

8. A semiconductor chip heat dissipation structure, characterized in that: include: Semiconductor chips; The diamond / single crystal silicon composite three-dimensional substrate according to any one of claims 1 to 3, wherein the semiconductor chip is arranged on a side of the single crystal silicon base in the diamond / single crystal silicon composite three-dimensional substrate away from the diamond layer.

9. The semiconductor chip heat dissipation structure according to claim 8, characterized in that: The semiconductor chip comprises a GPU chip, and the semiconductor chip is directly constructed based on the single crystal silicon substrate.

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