Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises a substrate, a plurality of source lines, a plurality of channel material columns, a plurality of gate structures and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, the plurality of source lines extend along a first direction and are arranged at intervals along a second direction; the plurality of channel material columns are located on the plurality of source lines and connected with the source lines; the gate structure comprises a first part and a second part, the first part of the gate structure is arranged along the sidewall of the channel material column, and the second part of the gate structure extends across the plurality of source lines along the second direction and is connected with the first part; the plurality of drain structures are located on the channel material column and connected with the channel material column; and the application can avoid the influence of the non-central position of the channel, thereby improving the electrical performance of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Semiconductor transistors, such as metal oxide semiconductor transistors (MOS transistors), have been used in various applications, such as power supply, power converter, switch, etc. Conventional MOS transistors adopt a planar structure, and with the development of semiconductor integrated circuit technology over time, MOS transistors adopt a stacked structure to realize transistor miniaturization. In the design of the stacked structure, a plurality of strip-shaped gate structures are formed, a plurality of through holes are formed in the gate structures, and a channel structure is formed by filling a material in the through holes. However, the position of the through hole cannot be guaranteed to be on the center line of the gate structure when the through hole is prepared, which causes the channel position to be off-center, thereby affecting the electrical performance of the semiconductor device. SUMMARY

[0003] The present application aims to provide a semiconductor device and a preparation method thereof, and improve the electrical performance of the semiconductor device.

[0004] To achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising:

[0005] a substrate;

[0006] a plurality of source lines located on the substrate, the plurality of source lines extending along a first direction and being arranged apart from each other along a second direction;

[0007] a plurality of channel material columns located on the plurality of source lines and connected with the source lines;

[0008] a plurality of gate structures, the gate structure comprising a first part and a second part, the first part of the gate structure being arranged along the sidewall of the channel material column, and the second part of the gate structure extending across a plurality of the source lines along the second direction and connecting the first part;

[0009] a plurality of drain structures located on the channel material column and connected with the channel material column.

[0010] Optionally, along the first direction, the first part of the gate structure has a first size, the second part of the gate structure has a second size, the channel material column has a third size, and the first size is greater than the second size, and the second size is greater than or equal to the third size.

[0011] Optionally, the first part of the gate structure and the second part of the gate structure are integrally formed, and the center lines of the first part of the gate structure and the second part of the gate structure do not overlap along the second direction.

[0012] Optionally, the first part of the gate structure is annular, and the second part of the gate structure is strip-shaped.

[0013] Optionally, the plurality of channel material columns are arranged in a matrix array, and the plurality of channel material columns are arranged into a plurality of rows extending along the first direction and a plurality of columns extending along the second direction, and the second part of the gate structure is connected to the channel material columns in the same column.

[0014] Optionally, the drain structure is connected to a plurality of adjacent channel material columns in the same row.

[0015] Optionally, the source line is connected to a plurality of adjacent channel material columns in different rows.

[0016] Optionally, the plurality of channel material columns are arranged in a staggered array, and two adjacent columns of the channel material columns are staggered on different source lines along the second direction.

[0017] Optionally, the two adjacent columns of the channel material columns are staggered on two sides of the second part of the gate structure.

[0018] The application further provides a preparation method of a semiconductor device, comprising:

[0019] providing a substrate;

[0020] forming a plurality of source lines on the substrate, the plurality of source lines extending along a first direction and being arranged apart from each other along a second direction;

[0021] forming a plurality of channel material columns on the plurality of source lines and connected to the source lines;

[0022] forming a plurality of gate structures, the gate structure comprising a first part and a second part, the first part of the gate structure being arranged along the sidewall of the channel material column, and the second part of the gate structure extending across a plurality of source lines along the second direction and connecting the first part;

[0023] forming a plurality of drain structures on the channel material columns and connected to the channel material columns.

[0024] Optionally, the step of forming the gate structure comprises:

[0025] forming a sacrificial layer covering the sidewall of the channel material column;

[0026] forming a first isolation material layer filled between adjacent channel material columns;

[0027] forming a patterned mask layer covering part of the first isolation material layer, part of the sacrificial layer and the channel material column;

[0028] etching part of the first isolation material layer to form a plurality of first openings extending along the second direction, taking the patterned mask layer as a mask;

[0029] removing the patterned mask layer and removing the sacrificial layer, and forming a second opening in the position where the sacrificial layer is located after removing the sacrificial layer;

[0030] forming the gate structure in the first opening and the second opening, the gate structure in the first opening as the second part, and the gate structure in the second opening as the first part.

[0031] Optionally, the sacrificial layer is formed by a self-alignment process.

[0032] Optionally, the first part of the gate structure and the second part of the gate structure are integrally formed under the same process condition.

[0033] In the semiconductor device and the preparation method thereof provided by the present application, the semiconductor device comprises a substrate, a plurality of source lines, a plurality of channel material columns, a plurality of gate structures and a plurality of drain structures. The plurality of source lines are located on the substrate and extend along a first direction and are arranged at intervals along a second direction. The plurality of channel material columns are located on the plurality of source lines and are connected to the source lines. The gate structure comprises a first part and a second part. The first part of the gate structure is arranged along the side wall of the channel material column. The second part of the gate structure extends along the second direction and connects the first part across the plurality of source lines. The plurality of drain structures are located on the channel material column and are connected to the channel material column. In the present application, the gate structure comprises the first part and the second part. The first part of the gate structure is arranged along the side wall of the channel material column. The second part of the gate structure extends along the second direction and connects the first part across the plurality of source lines. The influence of the non-central position of the channel can be avoided, thereby improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The top view of the semiconductor device provided by the first embodiment of the present application.

[0035] Figure 2 The sectional view of the semiconductor device provided by the first embodiment of the present application.

[0036] Figures 3-23 The schematic diagram of the corresponding steps of the preparation method of the semiconductor device provided by the first embodiment of the present application.

[0037] Figure 24 The top view of the semiconductor device provided by the second embodiment of the present application.

[0038] Figure 25A cross-sectional view of a semiconductor device according to Embodiment 2 of the present application.

[0039] Figures 26-36 A cross-sectional view of a semiconductor device according to Embodiment 2 of the present application.

[0040] Figure 37 A top view of a semiconductor device according to Embodiment 3 of the present application.

[0041] Figure 38 A top view of a semiconductor device according to Embodiment 4 of the present application.

[0042] Figure 39 A top view of a semiconductor device according to Embodiment 5 of the present application.

[0043] Wherein, the reference signs are:

[0044] 10 - substrate; 20 - source line; 30 - channel material pillar; 41 - first oxide layer; 42 - second oxide layer; 51 - gate dielectric layer; 52 - barrier layer; 53 - sacrificial layer; 61 - first isolation material layer; 62 - second isolation material layer; 63 - third isolation material layer; 70 - patterned mask layer; 71 - first opening; 72 - second opening; 80 - gate structure; 81 - first portion; 82 - second portion; 90 - drain structure; 100 - side wall. DETAILED DESCRIPTION

[0045] In order to make the objects, advantages and features of the present application clearer, the following further describes the present application in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of describing the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0046] As used in the present application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of "and / or", the term "at least one" is generally used in the sense of "one or more", and the term "at least two" is generally used in the sense of "two or more", and in addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. The specific meaning of the above terms in the present application can be understood by those skilled in the art according to the specific circumstances.

[0047] Embodiment 1

[0048] Figure 1A top view of a semiconductor device provided in the present embodiment; Figure 2 A cross-sectional schematic view of a semiconductor device provided in the present embodiment, Figure 2 A cross-sectional schematic view of a semiconductor device provided in the present embodiment, Figure 1 A cross-sectional schematic view of a semiconductor device provided in the present embodiment, Figure 1 A cross-sectional schematic view of a semiconductor device provided in the present embodiment, Figure 1 A cross-sectional schematic view of a semiconductor device provided in the present embodiment, Figure 1 A cross-sectional schematic view of a semiconductor device provided in the present embodiment, Figure 2 The present embodiment provides a semiconductor device, comprising: a substrate 10, a plurality of source lines 20, a plurality of channel material columns 30, a plurality of gate structures 80 and a plurality of drain structures 90. The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, a fully-depleted silicon-on-insulator substrate, and the like. In the present embodiment, a dielectric layer (not shown in the figure) is further formed on the substrate 10, and an electrical connecting member is formed in the dielectric layer, which is electrically connected to the substrate 10 and the source lines 20.

[0049] The plurality of source lines 20 are located on the substrate 10 (specifically, on the dielectric layer), extend along a first direction D1 and are arranged at intervals along a second direction D2. An isolation material layer is filled between adjacent source lines 20. In the present embodiment, the source line 20 can include, from bottom to top, a first source barrier layer, a source metal layer, a second source barrier layer and a source semiconductor layer (not shown in the figure, respectively), wherein the materials of the first source barrier layer and the second source barrier layer can include TiN, the material of the source metal layer can include W, and the material of the source semiconductor layer can include polysilicon, but are not limited to the above-mentioned materials.

[0050] The plurality of channel material columns 30 are located on the plurality of source lines 20 and connected to the source lines 20. In the present embodiment, the plurality of channel material columns 30 are arranged in a matrix array, and the plurality of channel material columns 30 are arranged into a plurality of rows extending along the first direction D1 and a plurality of columns extending along the second direction D2. In the present embodiment, the material of the channel material column 30 can include polysilicon (with doped ions), and can further include one or more combinations of metal silicide material, ferroelectric material, high-k dielectric material and indium gallium zinc oxide (IGZO).

[0051] The gate structure 80 includes a first portion 81 and a second portion 82, the first portion 81 of the gate structure 80 is disposed along the sidewall of the channel material pillar 30, the second portion 82 of the gate structure 80 extends across the plurality of source lines 20 in the second direction D2 and connects the first portion 81, and the second portion 82 of the gate structure 80 connects the channel material pillars 30 in the same column. In the embodiment, the first portion 81 of the gate structure 80 and the second portion 82 of the gate structure 80 are integrally formed (simultaneously formed in the manufacturing process), and the center line S1 of the first portion 81 of the gate structure 80 and the center line S2 of the second portion 82 of the gate structure 80 do not overlap in the second direction D2. The first portion 81 of the gate structure 80 is annular, and the second portion 82 of the gate structure 80 is strip-shaped.

[0052] In the embodiment, in the first direction D1, the first portion 81 of the gate structure 80 has a first size CD1, the second portion 82 of the gate structure 80 has a second size CD2, the channel material pillar 30 has a third size CD3, and the first size CD1 is greater than the second size CD2, the second size CD2 is greater than or equal to the third size CD3, and the second size CD2 and the third size CD3 can be designed according to the minimum process size of the current process platform. In the embodiment, the gate structure 80 can be a metal stack, such as TiN, W, and is not limited to the above-mentioned materials.

[0053] Further, the first portion 81 of the gate structure 80 and the channel material pillar 30 have a gate dielectric layer 51 and a barrier layer 52 disposed in sequence along the sidewall of the channel material pillar 30, and the first portion 81 of the gate structure 80 is located on the gate dielectric layer 51 and the barrier layer 52; the material of the gate dielectric layer 51 can include at least one of silicon oxide, silicon nitride and silicon oxynitride, and the barrier layer 52 can include titanium nitride, and is not limited to the above-mentioned materials. Further, it also includes a first oxide layer 41, the first oxide layer 41 covers the source line 20, and the gate dielectric layer 51 and the barrier layer 52 are located on the first oxide layer 41.

[0054] Further, it also includes a first isolation material layer 61 and a second isolation material layer 62, the first isolation material layer 61 fills between adjacent gate structures 80, and the second portion 82 of the gate structure 80 is located on the first isolation material layer 61; the top of the gate structure 80 is lower than the top of the channel material pillar 30, the second isolation material layer 62 is located on the gate structure 80, and the tops of the channel material pillar 30, the first isolation material layer 61 and the second isolation material layer 62 are flush. In the embodiment, the materials of the first isolation material layer 61 and the second isolation material layer 62 can include one of low-k dielectric material, oxide, nitride, oxynitride and carbon silicon oxynitride, and are not limited to the above-mentioned materials.

[0055] A plurality of drain structures 90 are located on and connected with the channel material columns 30, one drain structure 90 is connected with one channel material column 30, and the size of the drain structure 90 along the first direction D1 and the second direction D2 can be similar to the size of the first part 81 of the gate structure 80. In the embodiment, the drain structure 90 includes a drain barrier layer and a drain metal layer (not shown in the figure) stacked in order from bottom to top, wherein the material of the drain barrier layer can include TiN, and the material of the drain metal layer can include W, which is not limited to the above-mentioned materials.

[0056] Further, the side wall 100 and the third isolation material layer 63 are further included, the side wall 100 covers the side surface of the drain structure 90; the third isolation material layer 63 is filled between adjacent drain structures 90; the material of the side wall 100 and the third isolation material layer 63 are different, the material of the side wall 100 can include silicon nitride, and the material of the third isolation material layer 63 can include one of low-k dielectric material, oxide, nitride, oxynitride and carbon silicon oxynitride, which is not limited to the above-mentioned materials.

[0057] In the embodiment, the gate structure 80 includes the first part 81 and the second part 82, the first part 81 of the gate structure 80 is arranged along the sidewall of the channel material column 30, and the second part 82 of the gate structure 80 extends across a plurality of source lines 20 along the second direction D2 and connects the first part 81, which can avoid the influence of the position of the channel (channel material column 30) not being centered, thereby improving the electrical performance of the semiconductor device.

[0058] The embodiment further provides a preparation method of a semiconductor device, which is used for preparing the semiconductor device and includes the following steps:

[0059] Step S1: providing a substrate;

[0060] Step S2: forming a plurality of source lines on the substrate, the plurality of source lines extend along a first direction and are arranged at intervals along a second direction;

[0061] Step S3: forming a plurality of channel material columns on the plurality of source lines and connected with the source lines;

[0062] Step S4: forming a plurality of gate structures, the gate structure includes a first part and a second part, the first part of the gate structure is arranged along the sidewall of the channel material column, and the second part of the gate structure extends across a plurality of source lines along the second direction and connects the first part;

[0063] Step S5: forming a plurality of drain structures on the channel material column and connected with the channel material column.

[0064] Figures 3-23 The preparation method of the semiconductor device provided in the embodiment is provided with a schematic diagram of the corresponding steps. The following will be described in combination with the semiconductor device provided in the embodiment. Figures 3-23The method for manufacturing the semiconductor device is described in detail.

[0065] Please refer to Figure 3 and Figure 4 , Figure 4 is Figure 3 A cross-sectional view along the cross-sectional line A1A2 in FIG. 1B is shown in FIG. 2B. Step S1 is performed: a substrate 10 is provided, which can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate, without limitation. In this embodiment, a dielectric layer (not shown in the figure) is also formed on the substrate 10, and an electrical connection is formed in the dielectric layer, which is electrically connected to the substrate 10 and the source line 20 through the dielectric layer.

[0066] Please refer to Figure 3 and Figure 4 Step S2 is performed: a plurality of source lines 20 are formed on the substrate 10 (specifically on the dielectric layer), the plurality of source lines 20 extend along a first direction D1 and are arranged apart from each other along a second direction D2, and an isolation material layer (not shown in the figure) is filled between adjacent source lines 20, and the material of the source line 20 is as described above.

[0067] Please refer to Figure 3 and Figure 4 Step S3 is performed: a plurality of channel material columns 30 are formed on the plurality of source lines 20 and connected to the source lines 20, the channel material columns 30 can be designed according to the minimum process size of the current process platform, and the material of the channel material column 30 is as described above. A first oxide layer 41 is formed on the source line 20, and the channel material column 30 is connected to the source line 20 through the first oxide layer 41; a second oxide layer 42 is formed on the top of the channel material column 30 as a protective layer. In this embodiment, the plurality of channel material columns 30 are arranged in a matrix array, and the plurality of channel material columns 30 are arranged into a plurality of rows extending along the first direction D1 and a plurality of columns extending along the second direction D2.

[0068] Step S4 is performed: the step of forming a gate structure includes:

[0069] Please refer to Figure 5 and Figure 6 , Figure 6 is Figure 5 A cross-sectional view along the cross-sectional line A1A2 in FIG. 1B is shown in FIG. 2B. Step S1 is performed: a substrate 10 is provided, which can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate, without limitation. In this embodiment, a dielectric layer (not shown in the figure) is also formed on the substrate 10, and an electrical connection is formed in the dielectric layer, which is electrically connected to the substrate 10 and the source line 20 through the dielectric layer. Figure 5 In order to clearly show the source line and part of the structure, Figure 5 In the top view, some structures are not completely shown, and in Figure 5The middle part structure is provided with transparency. The self-alignment process is used to form the sacrificial layer 53 covering the sidewall of the channel material column 30. Before forming the sacrificial layer 53, the gate dielectric layer 51 and the barrier layer 52 are sequentially formed to cover the sidewall of the channel material column 30, and the gate dielectric layer 51, the barrier layer 52 and the sacrificial layer 53 extend to cover the surface of the exposed first oxide layer 41 of the adjacent channel material column 30. The materials of the gate dielectric layer 51 and the barrier layer 52 are as described above, and the material of the sacrificial layer 53 can include silicon nitride, which is not limited to the above materials.

[0070] Please refer to Figure 7 and Figure 8 , Figure 8 for Figure 7 the cross-sectional view along the cross-sectional line A1A2. The first oxide layer 41 is not shown in Figure 7 . Part of the gate dielectric layer 51, the barrier layer 52 and the sacrificial layer 53 are etched to expose the first oxide layer 41 and the second oxide layer 42. After etching, the remaining gate dielectric layer 51, the barrier layer 52 and the sacrificial layer 53 are arranged along the sidewall of the channel material column 30. The remaining gate dielectric layer 51 is annularly arranged on the sidewall of the channel material column 30, and the remaining gate dielectric layer 51 is arranged on the remaining barrier layer 52 and the sacrificial layer 53.

[0071] Please refer to Figure 9 and Figure 10 , Figure 10 for Figure 9 the cross-sectional view along the cross-sectional line A1A2. The first isolation material layer 61 is formed to fill between the adjacent channel material columns 30, and the top of the first isolation material layer 61 is flush with the top of the second oxide layer 42. The material of the first isolation material layer 61 is as described above.

[0072] Please refer to Figure 11 and Figure 12 , Figure 12 for Figure 11 the cross-sectional view along the cross-sectional line A1A2. The patterned mask layer 70 is formed to cover part of the first isolation material layer 61, part of the sacrificial layer 53 and the channel material column 30. The material of the patterned mask layer 70 can be photoresist, which is not limited thereto.

[0073] Please refer to Figure 13 and Figure 14 , Figure 14 for Figure 13 the cross-sectional view along the cross-sectional line A1A2. In order to clearly show part of the structure, the top view is not completely shown in Figure 13 . Part of the first isolation material layer 61 is etched to form a plurality of first openings 71 extending along the second direction D2 by taking the patterned mask layer 70 as a mask. Then, the patterned mask layer 70 is removed.

[0074] Please refer toFigure 15 and Figure 16 , Figure 16 for Figure 15 A cross-sectional view along section line A1A2 is shown. To clearly illustrate some of the structures, [the following text is missing]. Figure 15 The top view is not fully shown. After removing the sacrificial layer 53, a second opening 72 is formed at the location of the sacrificial layer 53. The first opening 71 and the second opening 72 are connected.

[0075] Please refer to Figure 17 and Figure 18 , Figure 18 for Figure 17 A cross-sectional view along section line A1A2 is shown. A gate structure 80 is formed in the first opening 71 and the second opening 72. The gate structure 80 in the first opening 71 serves as the second portion 82, and the gate structure 80 in the second opening 72 serves as the first portion 81. The first portion 81 of the gate structure 80 is disposed along the sidewall of the channel material pillar 30, and the second portion 82 of the gate structure 80 extends along the second direction D2, crossing multiple source lines 20 and connecting to the first portion 81. In this embodiment, the first portion 81 and the second portion 82 of the gate structure 80 are integrally formed under the same process conditions.

[0076] Further, please refer to Figure 19 The gate structure 80 is etched so that the top of the gate structure 80 is lower than the top of the channel material pillar 30, and the barrier layer 52 is etched so that the top of the barrier layer 52 is flush with the top of the gate structure 80.

[0077] Please refer to Figure 20 and Figure 21 , Figure 21 for Figure 20 A cross-sectional view along section line A1A2. A second isolation material layer 62 is formed to cover the gate structure 80, the first isolation oxide layer 61, and the second oxide layer 42. The material of the second isolation material layer 62 is as described above.

[0078] Please refer to Figure 22 and Figure 23 , Figure 23 for Figure 22 A cross-sectional view along section line A1A2. Part of the second isolation material layer 62, part of the first isolation oxide layer 61, and the second oxide layer 42 are etched away, exposing the top of the channel material pillar 30. After etching, the top of the second isolation material layer 62, the first isolation oxide layer 61, and the channel material pillar 30 are flush.

[0079] Please refer to Figure 1 and Figure 2Step S5: Form several drain structures 90 located on and connected to the channel material pillars 30. The size of the drain structures 90 along the first direction D1 and the second direction D2 can be similar to the size of the first part 81 of the gate structure 80. The material of the drain structures 90 is as described above.

[0080] Furthermore, it also includes forming a sidewall 100 and a third insulating material layer 63, the sidewall 100 covering the side of the drain structure 90; the third insulating material layer 63 filling between adjacent drain structures 90; the materials of the sidewall 100 and the third insulating material layer 63 are as described above.

[0081] Example 2

[0082] Figure 24 This is a top view of the semiconductor device provided in this embodiment. Figure 25 This is a cross-sectional schematic diagram of the semiconductor device provided in this embodiment. Figure 25 for Figure 24 A schematic diagram of the cross-section along section line A1A2. Figure 24 In order to clearly illustrate the key structures, therefore in Figure 24 The structure is omitted and transparency is set. This embodiment differs from Embodiment 1 in that the second part 82 of the gate structure 80 is connected to the channel material pillars 30 located in two adjacent columns, and the drain structure 90 is connected to multiple adjacent channel material pillars 30 located in the same row. In this embodiment, the drain structure 90 is connected to two adjacent channel material pillars 30 located in the same row. Other structures in this embodiment are the same as in Embodiment 1; please refer to the description of Embodiment 1 for details.

[0083] The method for fabricating the semiconductor device provided in this embodiment differs from that in Embodiment 1 in that the structures of the first and second openings formed are different, as are the structures of the drain structure formed.

[0084] Figures 26-36 The diagram below illustrates the corresponding steps of the semiconductor device fabrication method provided in this embodiment. Figures 26-36 The differences between the semiconductor device fabrication method provided in this embodiment and that in Embodiment 1 will be described in detail.

[0085] Please refer to Figure 26 and Figure 27 , Figure 27 for Figure 26 A cross-sectional schematic diagram along section line A1A2. A patterned mask layer 70 is formed to cover part of the first isolation material layer 61, part of the sacrificial layer 53 and the channel material pillars 30. Unlike Embodiment 1, the patterned mask layer 70 exposes the first isolation material layer 61 between a portion of the adjacent channel material pillars 30 along the first direction D1.

[0086] Please refer toFigure 28 and Figure 29 , Figure 29 for Figure 28 A cross-sectional view along section line A1A2 is shown. To clearly illustrate some of the structures, [the following text is missing]. Figure 28 The top view is not fully shown. Using a patterned mask layer 70 as a mask, a portion of the first isolation material layer 61 is etched to form a plurality of first openings 71 extending along the second direction D2. Unlike Embodiment 1, the sacrificial layer 53 is exposed on both sides of the first openings 71. Then, the patterned mask layer 70 is removed.

[0087] Please refer to Figure 30 and Figure 31 , Figure 31 for Figure 30 A cross-sectional view along section line A1A2 is shown. To clearly illustrate some of the structures, [the following text is missing]. Figure 30 The top view is not fully shown. After removing the sacrificial layer 53, a second opening 72 is formed at the location of the sacrificial layer 53. The first opening 71 and the second opening 72 are connected.

[0088] Please refer to Figure 32 and Figure 33 , Figure 33 for Figure 32 A cross-sectional view along section line A1A2 is shown. A gate structure 80 is formed in the first opening 71 and the second opening 72. The gate structure 80 in the first opening 71 serves as the second part 82, and the gate structure 80 in the second opening 72 serves as the first part 81. The first part 81 of the gate structure 80 is disposed along the sidewall of the channel material pillar 30. The second part 82 of the gate structure 80 extends along the second direction D2, crossing multiple source lines 20 and connecting to the first part 81. The second part 82 of the gate structure 80 connects to two adjacent columns of channel material pillars 30. In this embodiment, the first part 81 and the second part 82 of the gate structure 80 are integrally formed under the same process conditions.

[0089] Further, please refer to Figure 34 The gate structure 80 is etched so that the top of the gate structure 80 is lower than the top of the channel material pillar 30, and the barrier layer 52 is etched so that the top of the barrier layer 52 is flush with the top of the gate structure 80.

[0090] Please refer to Figure 35 and Figure 36 , Figure 36 for Figure 35Fig. 6 is a cross-sectional view along the cross-sectional line A1A2. A second isolation material layer 62 is formed to cover the gate structure 80, the first isolation oxide layer 61 and the second oxide layer 42. Then, a portion of the second isolation material layer 62, a portion of the first isolation oxide layer 61 and the second oxide layer 42 are etched to expose the top of the channel material pillar 30. After etching, the second isolation material layer 62, the first isolation oxide layer 61 and the top of the channel material pillar 30 are flush.

[0091] Fig. 7 is a cross-sectional view along the cross-sectional line A1A2. A plurality of drain structures 90 are formed on and connected to the channel material pillars 30. The drain structure 90 connects to the adjacent plurality of channel material pillars 30 in the same row. In this embodiment, the drain structure 90 connects to the adjacent two channel material pillars 30 in the same row. Figure 24 Figure 25 Fig. 8 is a cross-sectional view along the cross-sectional line A1A2. A side wall 100 and a third isolation material layer 63 are further formed. The side wall 100 covers the side of the drain structure 90. The third isolation material layer 63 fills between the adjacent drain structures 90.

[0092] Embodiment Three

[0093] Fig. 9 is a cross-sectional view along the cross-sectional line A1A2. A plurality of source lines 20 are formed to connect to the channel material pillars 30. In this embodiment, the source line 20 connects to the adjacent two rows of channel material pillars 30. The drain structure 90 connects to the adjacent two channel material pillars 30 in the adjacent two rows. The other structures in this embodiment are the same as those in Embodiment Two.

[0094] Figure 37 Fig. 10 is a top view of a semiconductor device according to this embodiment. This embodiment is different from Embodiment Two in that the source line 20 connects to the adjacent three rows of channel material pillars 30. The drain structure 90 connects to the adjacent two channel material pillars 30 in the adjacent three rows. The other structures in this embodiment are the same as those in Embodiment Three.

[0095] Embodiment Four

[0096] Figure 38 Fig. 11 is a top view of a semiconductor device according to this embodiment. This embodiment is different from Embodiment Three in that the source line 20 connects to the adjacent three rows of channel material pillars 30. The drain structure 90 connects to the adjacent two channel material pillars 30 in the adjacent three rows. The other structures in this embodiment are the same as those in Embodiment Three.

[0097] Embodiment Five

[0098] Figure 39 Fig. 12 is a top view of a semiconductor device according to this embodiment. This embodiment is different from Embodiment One in that the plurality of channel material pillars 30 are arranged in a staggered array. The adjacent two columns of channel material pillars 30 are staggered on different source lines 20 along the second direction D2. The adjacent two columns of channel material pillars 30 are staggered on both sides of the second portion 82 of the gate structure 80. Similarly, the first portion 81 of the gate structure 80 is also staggered on both sides of the second portion 82 of the gate structure 80.

[0099] ​In summary, in the semiconductor device and the preparation method thereof provided by the application, the semiconductor device comprises a substrate, a plurality of source lines, a plurality of channel material columns, a plurality of gate structures and a plurality of drain structures, wherein the plurality of source lines are arranged on the substrate, the plurality of source lines extend along a first direction and are arranged at intervals along a second direction; the plurality of channel material columns are arranged on the plurality of source lines and connected with the source lines; the gate structure comprises a first part and a second part, the first part of the gate structure is arranged along the sidewall of the channel material column, and the second part of the gate structure extends along the second direction and connects the first part across the plurality of source lines; and the plurality of drain structures are arranged on the channel material column and connected with the channel material column. In the application, the gate structure comprises the first part and the second part, the first part of the gate structure is arranged along the sidewall of the channel material column, and the second part of the gate structure extends along the second direction and connects the first part across the plurality of source lines, so that the influence of the non-central position of the channel can be avoided, and the electrical performance of the semiconductor device is improved.

[0100] The above merely describes the preferred embodiments of the present application and does not limit the present application in any way. Any person skilled in the art can make any equivalent replacement, modification or change to the technical solutions and technical contents disclosed in the present application without departing from the scope of the technical solutions of the present application, and such changes still belong to the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A plurality of source lines are located on the substrate, and the plurality of source lines extend along a first direction and are spaced apart from each other along a second direction; Several channel material pillars are located on several of the source lines and connected to the source lines; A plurality of gate structures, the gate structure comprising a first portion and a second portion, the first portion of the gate structure being disposed along the sidewall of the channel material pillar, and the second portion of the gate structure extending along the second direction across multiple source lines and connecting to the first portion; Several drain structures are located on and connected to the channel material pillar; In this configuration, some of the channel material pillars are disposed on both sides of the same gate structure, and the drain structure simultaneously contacts the channel material pillars located on both sides of the gate structure.

2. The semiconductor device as claimed in claim 1, characterized in that, Along the first direction, a first portion of the gate structure has a first dimension, a second portion of the gate structure has a second dimension, and the channel material pillar has a third dimension, wherein the first dimension is greater than the second dimension, and the second dimension is greater than or equal to the third dimension.

3. The semiconductor device as described in claim 1, characterized in that, The first part and the second part of the gate structure are integrally formed, and the center lines of the first part and the second part of the gate structure do not overlap along the second direction.

4. The semiconductor device as claimed in claim 1, characterized in that, The first part of the gate structure is ring-shaped, and the second part of the gate structure is strip-shaped.

5. The semiconductor device as claimed in claim 1, characterized in that, The channel material pillars are arranged in a matrix array, and the channel material pillars are arranged in a plurality of rows extending along the first direction and a plurality of columns extending along the second direction, and the second part of the gate structure is connected to the channel material pillars located in the same column.

6. The semiconductor device as claimed in claim 5, characterized in that, The drain structure connects multiple adjacent channel material pillars located in the same row.

7. The semiconductor device as claimed in claim 5, characterized in that, The source line connects multiple adjacent rows of channel material columns.

8. The semiconductor device as claimed in claim 1, characterized in that, The channel material pillars are arranged in an alternating array, with adjacent columns of channel material pillars staggered along the second direction on different source lines.

9. The semiconductor device as claimed in claim 8, characterized in that, The adjacent columns of channel material pillars are staggered on both sides of the second part of the gate structure.

10. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A plurality of source lines are formed on the substrate, and the plurality of source lines extend along a first direction and are spaced apart from each other along a second direction; Several channel material pillars are formed located on several of the source lines and connected to the source lines; A plurality of gate structures are formed, the gate structure including a first part and a second part, the first part of the gate structure is disposed along the sidewall of the channel material pillar, and the second part of the gate structure extends along the second direction across multiple source lines and connects to the first part; Several drain structures are formed on the channel material pillar and connected to the channel material pillar; In this configuration, some of the channel material pillars are disposed on both sides of the same gate structure, and the drain structure simultaneously contacts the channel material pillars located on both sides of the gate structure.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The steps for forming the gate structure include: A sacrificial layer is formed to cover the sidewalls of the channel material column; A first insulating material layer is formed and filled between adjacent channel material columns; A patterned mask layer is formed to cover a portion of the first isolation material layer, a portion of the sacrificial layer, and the channel material pillars; Using the patterned mask layer as a mask, a portion of the first isolation material layer is etched to form a plurality of first openings extending along the second direction; Remove the patterned mask layer and the sacrificial layer, and after removing the sacrificial layer, form a second opening at the location of the sacrificial layer; The gate structure is formed in the first opening and the second opening, with the gate structure in the first opening serving as the second part and the gate structure in the second opening serving as the first part.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The sacrificial layer is formed using a self-aligned process.

13. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The first part of the gate structure and the second part of the gate structure are integrally formed under the same process conditions.

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