A slow-start power MOS transistor and its manufacturing method

Abstract

The invention provides a slow-start power MOS transistor and a preparation method thereof, comprising a first groove and a second groove spaced apart from the first groove arranged in an N-type epitaxial layer; a first oxide layer is deposited on the surface of the first groove, a groove formed by the first oxide layer is filled with gate polysilicon, a first N-type sublayer and a first P-type sublayer are sequentially arranged in the N-type epitaxial layer on the side of the first groove away from the second groove along the depth direction of the first groove, and the doping concentration of the first N-type sublayer is higher than that of the N-type epitaxial layer; a second oxide layer is deposited on the surface of the second groove, a groove formed by the second oxide layer is filled with capacitor polysilicon, and the capacitor polysilicon is sequentially arranged with a second N-type sublayer and a second P-type sublayer along the depth direction of the second groove, and the doping concentrations of the first N-type sublayer and the second N-type sublayer are the same; wherein the depth of the second groove is greater than that of the first groove, so as to increase its Miller capacitance and prolong the duration of the Miller platform.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device manufacturing, and in particular to a slow-start power MOS transistor and a preparation method thereof. Background Art

[0002] Miller platform is a phenomenon that occurs in electronic circuits, especially during the switching process of power switching tubes (such as MOSFET, IGBT, etc.).

[0003] During the process of the switch tube being turned on and off, there is a capacitor (called Miller capacitor) between the gate and drain of the switch tube. When the state of the switch tube changes, the charging and discharging process of the Miller capacitor will cause the gate voltage to remain relatively stable for a period of time, thus forming a Miller platform. For example, during the turn-on process of the MOSFET, when the gate voltage rises to a certain level, the drain current begins to increase and the drain voltage begins to drop. At this time, the Miller capacitor is charged through the gate drive source. Since the Miller capacitor is large, the charging current mainly flows to the Miller capacitor, causing the gate voltage to rise slowly, resulting in a relatively stable period, namely the Miller platform.

[0004] Although the Miller platform is disadvantageous in high-frequency applications, it is very useful in power supply slow start. Most of the drop interval of the drain-source voltage at both ends of the MOS transistor is completed between the Miller platforms. If the Miller capacitance is artificially increased and the duration of the Miller platform is extended, the drop time of the drain-source voltage can be extended. This can also be used to perform power supply slow start, which is beneficial in hot plugging, independent module power supply, and high-power equipment power-on.

[0005] Since Miller capacitance is parasitic in power MOS transistors, it cannot be regulated by existing processes. For applications where power supply slow startup is required, the Miller platform needs to last for a long time. Existing high-performance MOS transistors such as SGT and super junction have small Miller capacitance and fast switching speed due to their characteristics, which makes it difficult to meet the requirements. Circuit designers need to add additional electronic components, which increases the complexity of the drive circuit and the additional cost, and is not conducive to the integration of system circuits. Summary of the invention

[0006] Based on this, the purpose of the present invention is to provide a slow-start power MOS transistor and a preparation method thereof, which aims to be compatible with the existing advanced process platform, and can independently regulate the Miller capacitance of the power MOS transistor, increase its Miller capacitance, extend the duration of the Miller platform, and extend the switching time.

[0007] According to a MOS transistor in an embodiment of the present invention, when the MOS transistor is a Trench NMOS transistor, the MOS transistor includes a first trench disposed in an N-type epitaxial layer and a second trench spaced apart from the first trench;

[0008] A first oxide layer is deposited on the surface of the first trench, and a trench formed by the first oxide layer is filled with gate polysilicon. In the N-type epitaxial layer on the side of the first trench away from the second trench, a first N-type sublayer and a first P-type sublayer are sequentially arranged along the depth direction of the first trench, and the doping concentration of the first N-type sublayer is higher than the doping concentration of the N-type epitaxial layer;

[0009] A second oxide layer is deposited on the side of the second trench, the bottom surface of the second trench is partially exposed, the trench formed by the second oxide layer is filled with capacitor polysilicon, and the capacitor polysilicon is sequentially provided with a second N-type sublayer and a second P-type sublayer along the depth direction of the second trench, and the first N-type sublayer and the second N-type sublayer have the same doping concentration;

[0010] wherein the depth of the second groove is greater than the depth of the first groove;

[0011] When the MOS transistor is a Trench PMOS transistor, it is obtained by inverting all doping in the Trench NMOS transistor.

[0012] Furthermore, the depth of the first groove is 1 μm-1.5 μm.

[0013] Furthermore, the depth of the second groove is 5 μm-7 μm.

[0014] Furthermore, the width of the second groove is 2 μm to 6 μm.

[0015] Furthermore, the thickness of the first oxide layer and the second oxide layer are both 500Å~1000Å.

[0016] Furthermore, the impurity of the second P-type sublayer is B, and the doping concentration is 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃.

[0017] Furthermore, the impurities of the first N-type sublayer and the second N-type sublayer are P, and the doping concentration is 1E13atom / cm 3 ~1E17atom / cm 3 , the temperature is 800℃~1100℃.

[0018] Furthermore, the surfaces of the gate polysilicon and the capacitor polysilicon are 0.2 μm to 0.5 μm lower than the surfaces of the corresponding oxide layers.

[0019] According to an embodiment of the present invention, a method for preparing a MOS transistor is used to prepare the above-mentioned MOS transistor. When the MOS transistor is a Trench NMOS transistor, the method comprises:

[0020] Providing an N-type epitaxial layer;

[0021] Etching a first trench and a second trench spaced apart from the first trench on the N-type epitaxial layer, wherein the depth of the second trench is greater than the depth of the first trench;

[0022] Depositing oxide layers on the surfaces of the first trench and the second trench to form a first oxide layer and a second oxide layer respectively, wherein the second oxide layer is obtained by etching the oxide layer deposited at the bottom of the second trench, and the bottom surface of the second trench is partially exposed;

[0023] Depositing polysilicon in the grooves formed by the first oxide layer and the second oxide layer respectively and performing CMP grinding and etching to form gate polysilicon and capacitor polysilicon respectively;

[0024] Performing P-type doping in the capacitor polysilicon and in a preset region of the N-type epitaxial layer;

[0025] Performing N-type doping on the P-type doped portion to obtain a first N-type sublayer, a first P-type sublayer, a second N-type sublayer, and a second P-type sublayer, wherein the doping concentration of the first N-type sublayer is higher than the doping concentration of the N-type epitaxial layer, and the doping concentrations of the first N-type sublayer and the second N-type sublayer are the same;

[0026] or,

[0027] When the MOS transistor is a Trench PMOS transistor, the preparation method is to invert all doping in the Trench NMOS transistor.

[0028] Compared with the prior art: when the MOS transistor is a Trench NMOS transistor, a first trench and a second trench spaced from the first trench are arranged in the N-type epitaxial layer; a first oxide layer is deposited on the surface of the first trench, the trench formed by the first oxide layer is filled with gate polysilicon, and in the N-type epitaxial layer on the side of the first trench away from the second trench, a first N-type sublayer and a first P-type sublayer are sequentially arranged along the depth direction of the first trench, and the doping concentration of the first N-type sublayer is higher than the doping concentration of the N-type epitaxial layer; a second oxide layer is deposited on the surface of the second trench, the trench formed by the second oxide layer is filled with capacitor polysilicon, and the capacitor polysilicon is sequentially arranged along the depth direction of the second trench, and the doping concentrations of the first N-type sublayer and the second N-type sublayer are the same; wherein the depth of the second trench is greater than the depth of the first trench, and when the MOS transistor is a Trench PMOS transistor, by depositing a first oxide layer on the surface of the N-type epitaxial layer away from the second trench, the first N-type sublayer and the second P-type sublayer are sequentially arranged. All doping in the NMOS transistor is inverted. Specifically, since there is a capacitor polysilicon with an NPN structure, and the capacitance formed by the PN junction is related to the width of the depletion region and the size of the PN junction cross-sectional area, the width of the second trench and the doping concentration of the second P-type sublayer can be adjusted as needed to adjust the size of the capacitor. In addition, the formed NPN structure will have a PN junction in reverse bias regardless of whether the power MOS is in the on state or the off state, so that the branch here will not be turned on and will not affect the normal operation of the MOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of a slow-start power MOS transistor provided by an embodiment of the present invention;

[0030] Figure 2 A flowchart of a method for preparing a slow-start power MOS transistor provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of a process flow of a slow-start power MOS transistor provided in Example 1 of the present invention.

[0032] Description of main component symbols:

[0033]

[0034] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0036] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0038] refer to Figure 1 , Figure 1 A schematic diagram of the structure of a slow-start power MOS transistor provided in an embodiment of the present invention. Specifically, when the MOS transistor is a Trench NMOS transistor, the MOS transistor includes a first trench provided in an N-type epitaxial layer 1 and a second trench spaced apart from the first trench. It should be noted that the Trench NMOS transistor is a special structural form of an NMOS (N-type metal oxide semiconductor) transistor, and its main feature lies in its unique trench design.

[0039] A first oxide layer 2 is deposited on the surface of the first trench, and a gate polysilicon 3 is filled in the trench formed by the first oxide layer 2. The first oxide layer 2 serves as an isolation layer to isolate the gate polysilicon 3. In the N-type epitaxial layer 1 on the side of the first trench away from the second trench, a first N-type sublayer 4 and a first P-type sublayer 5 are sequentially arranged along the depth direction of the first trench. The doping concentration of the first N-type sublayer 4 is higher than the doping concentration of the N-type epitaxial layer 1, that is, the first N-type sublayer 4 is an N-type heavily doped layer;

[0040] A second oxide layer 6 is deposited on the side of the second groove, and the bottom surface of the second groove is partially exposed. The groove formed by the second oxide layer 6 is filled with capacitor polysilicon 7, and the second oxide layer 6 serves as an isolation layer to isolate the capacitor polysilicon 7, wherein the thickness of the first oxide layer 2 and the second oxide layer 6 are both 500Å~1000Å. Exemplarily, the thickness of the first oxide layer 2 and the second oxide layer 6 are both 500Å, 600Å, 700Å, 800Å, 900Å or 1000Å, but not limited to this. The capacitor polysilicon 7 is sequentially provided with a second N-type sublayer 71 and a second P-type sublayer 72 along the depth direction of the second groove, and the first N-type sublayer 4 and the second N-type sublayer 71 have the same doping concentration. Specifically, the impurities of the first N-type sublayer 4 and the second N-type sublayer 71 are P (phosphorus), and the doping concentration is 1E13atom / cm 3 ~1E17atom / cm 3 , the temperature is 800℃~1100℃, the impurity of the second P-type sublayer 72 is B (boron), and the doping concentration is 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃;

[0041] Among them, the depth of the second groove is greater than the depth of the first groove. Specifically, the depth of the first groove is 1μm~1.5μm. Exemplarily, the depth of the first groove is 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, etc., but not limited to this; the depth of the second groove is 5μm~7μm. Exemplarily, the depth of the second groove is 5μm, 5.5μm, 6μm, 6.5μm, or 7μm, etc., but not limited to this; the width of the second groove is 2μm~6μm. Exemplarily, the width of the second groove is 2μm, 3μm, 4μm, 5μm or 6μm, etc., but not limited to this.

[0042] It should be noted that the surfaces of the gate polysilicon 3 and the capacitor polysilicon 7 are 0.2μm~0.5μm lower than the surfaces of the corresponding oxide layers. Exemplarily, the surfaces of the gate polysilicon 3 and the capacitor polysilicon 7 are 0.2μm, 0.3μm, 0.4μm or 0.5μm lower than the surfaces of the corresponding oxide layers, but not limited to this. The purpose of the surfaces of the gate polysilicon 3 and the capacitor polysilicon 7 being lower than the surfaces of the corresponding oxide layers is to ensure that there will be no polysilicon residue to cause a short circuit.

[0043] On the basis of the above, an oxide layer is deposited as a dielectric layer, and then CT (through hole) etching is performed. Finally, metal aluminum is deposited to form the electrode of MOS. The N-type heavily doped top of the capacitor polysilicon is connected to the MOS gate (gate polysilicon) to form a parallel connection, where G represents the gate, S represents the source, D represents the drain, and N represents the gate. + The symbol indicates heavy doping.

[0044] It can be understood that the above is based on N-channel trench MOS as an example, but the power device is not limited to trench MOS. Figure 1 It can be found that the left side of the figure is a traditional trench NMOS structure. On the right side of the trench gate, there is a deeper trench, namely the second trench. The second trench is filled with polysilicon. The polysilicon consists of highly doped N-type on the top and P-type on the bottom, thus forming an NPN structure next to the traditional MOS.

[0045] In some other embodiments of the present invention, the N-type epitaxial layer may be composed of two parts, including an N-type substrate and an N-type epitaxial sublayer deposited on the N-type substrate, wherein the second trench extends through the N-type epitaxial sublayer into the N-type substrate. The reason is that the substrate doping concentration is generally fixed and high, and due to the PN junction capacitance characteristics, the capacitance obtained by a PN junction with a high doping concentration will be large, while the epitaxial layer is generally used as a pressure-resistant layer, and the concentration is relatively low, and the concentration will vary with the withstand voltage. There is too much variability, which is not conducive to the regulation of the required capacitance.

[0046] It can be understood that when the MOS transistor is a Trench PMOS transistor, it is obtained by inverting all doping in the Trench NMOS transistor. It can be understood that the capacitance is also adjusted by the doping concentration of the P region and the width of the deep trench. Specifically, the MOS transistor includes a first trench provided in the P-type epitaxial layer and a second trench spaced apart from the first trench.

[0047] A first oxide layer is deposited on the surface of the first trench, and a gate polysilicon is filled in the trench formed by the first oxide layer. A first P-type sublayer and a first N-type sublayer are sequentially arranged in the P-type epitaxial layer on the side of the first trench away from the second trench along the depth direction of the first trench, and the doping concentration of the first P-type sublayer is higher than the doping concentration of the P-type epitaxial layer;

[0048] A second oxide layer is deposited on the side of the second trench, the bottom surface of the second trench is partially exposed, the trench formed by the second oxide layer is filled with capacitor polysilicon, and the capacitor polysilicon is sequentially provided with a second P-type sublayer and a second N-type sublayer along the depth direction of the second trench, and the doping concentration of the first P-type sublayer and the second P-type sublayer is the same;

[0049] The depth of the second groove is greater than the depth of the first groove.

[0050] refer to Figure 2 , Figure 2 The present invention provides a flowchart of a method for preparing a slow-start power MOS transistor according to an embodiment of the present invention. Taking the MOS transistor as a Trench NMOS transistor as an example, the preparation method specifically includes the following steps:

[0051] S100: providing an N-type epitaxial layer;

[0052] Specifically, firstly, an N-type epitaxial layer is provided, which may be an N-type epitaxial substrate, and the substrate is not limited to an N-type substrate or a P-type substrate, and a first groove is etched on the substrate, wherein the depth of the first groove is 1 μm-1.5 μm.

[0053] S200: etching a first trench and a second trench spaced apart from the first trench on the N-type epitaxial layer, wherein a depth of the second trench is greater than a depth of the first trench;

[0054] The depth of the first groove is 1 μm-1.5 μm, the depth of the second groove is 5 μm-7 μm, and the width of the second groove is 2 μm-6 μm.

[0055] S300: depositing oxide layers on the surfaces of the first trench and the second trench to form a first oxide layer and a second oxide layer respectively, wherein the second oxide layer is obtained by etching the oxide layer deposited at the bottom of the second trench, and the bottom surface of the second trench is partially exposed;

[0056] In this embodiment, oxygen is introduced at a temperature of 800°C~1100°C to grow an oxide layer with a thickness of 500Å~1000Å. The oxide layer serves as a dielectric layer for the gate polysilicon sidewall and plays an isolation role. The higher the quality of the oxide layer, the better the isolation effect.

[0057] It can be understood that after the thermal oxidation treatment, an oxide layer of equal thickness is formed on the surface of the first groove and the second groove, and the oxide layer also forms a groove.

[0058] S400: depositing polysilicon in the grooves formed by the first oxide layer and the second oxide layer respectively and performing CMP grinding and etching to form gate polysilicon and capacitor polysilicon respectively;

[0059] After CMP polishing and etching, the surface of the gate polysilicon and the capacitor polysilicon is 0.2 μm to 0.5 μm lower than the surface of the corresponding oxide layer.

[0060] S500: performing P-type doping in the capacitor polysilicon and in a preset region of the N-type epitaxial layer;

[0061] Specifically, the P-type doping impurity is B (boron) with a doping concentration of 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃.

[0062] S600: performing N-type doping on the P-type doped portion to obtain a first N-type sublayer, a first P-type sublayer, a second N-type sublayer, and a second P-type sublayer, wherein the doping concentration of the first N-type sublayer is higher than the doping concentration of the N-type epitaxial layer, and the doping concentrations of the first N-type sublayer and the second N-type sublayer are the same;

[0063] Specifically, the N-type doped impurity is P (phosphorus), and the doping concentration is 1E13atom / cm 3 ~1E17atom / cm 3 , the temperature is 800℃~1100℃.

[0064] On the basis of the above, an oxide layer is deposited as a dielectric layer, and then the CT (through hole) is etched, and finally metal aluminum is deposited to form the MOS electrode, connecting the N-type heavily doped top of the capacitor polysilicon to the MOS gate (gate polysilicon) to form a parallel connection.

[0065] It can be understood that when the MOS transistor is a Trench PMOS transistor, the preparation method is to reverse all doping in the Trench NMOS transistor.

[0066] The present invention will be further described below with specific embodiments:

[0067] Example 1

[0068] Embodiment 1 of the present invention provides a method for preparing a slow-start power MOS transistor. Taking the MOS transistor as a TrenchNMOS transistor as an example, refer to Figure 3 , is a schematic diagram of a process flow of a slow-start power MOS transistor provided in Example 1 of the present invention. Specifically, the following steps are included:

[0069] (1) An N-type substrate 10 is provided, and a first trench and a second trench are respectively etched on the N-type substrate 10, wherein the depth of the first trench is 1 μm, the depth of the second trench is 5 μm, the width of the second trench is 2 μm, and the N-type doping impurity of the N-type substrate 10 is P, and the doping concentration is 5E19atom / cm 3 ;

[0070] (2) thermally oxidizing the N-type substrate 10 with the first trench and the second trench to grow an oxide layer on the surface of the first trench and the second trench as a dielectric layer of the polysilicon sidewall, wherein the second oxide layer 6 is obtained by etching the oxide layer deposited at the bottom of the second trench, and the bottom surface of the second trench is partially exposed. Specifically, oxygen is introduced at a temperature of 900° C. to grow the first oxide layer 2 and the second oxide layer 6 with a thickness of 500 Å;

[0071] (3) depositing polysilicon in the grooves formed by the first oxide layer 2 and the second oxide layer 6 respectively and performing CMP grinding and etching to form gate polysilicon 3 and capacitor polysilicon 7 respectively, wherein the surfaces of the gate polysilicon 3 and the capacitor polysilicon 7 are 0.2 μm lower than the surfaces of the corresponding oxide layers;

[0072] (4) P-type doping is performed in the capacitor polysilicon 7 and the predetermined area of ​​the N-type substrate 10, and the impurity is B with a doping concentration of 2E14 atoms / cm 3 , the temperature is 900℃;

[0073] (5) N-type doping is performed on the P-type doped part. The impurity of the N-type doping is P, and the doping concentration is 1E13atom / cm 3 , the temperature is 800° C. to obtain the first N-type sublayer 4 , the first P-type sublayer 5 , the second N-type sublayer 71 and the second P-type sublayer 72 .

[0074] Example 2

[0075] Embodiment 2 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 6 μm.

[0076] Example 3

[0077] Embodiment 3 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 7 μm.

[0078] Example 4

[0079] Embodiment 4 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the first trench is 1.2 μm, and the depth of the second trench is 6 μm.

[0080] Example 5

[0081] Embodiment 5 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the first trench is 1.4 μm, and the depth of the second trench is 6 μm.

[0082] Example 6

[0083] Embodiment 6 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 6 μm and the width of the second trench is 4 μm.

[0084] Example 7

[0085] Embodiment 7 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 6 μm and the width of the second trench is 6 μm.

[0086] Example 8

[0087] Embodiment 8 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 6 μm, P-type doping is performed in the capacitor polysilicon and in a preset area of ​​the N-type epitaxial layer, the impurity is B, and the doping concentration is 2E15 atom / cm 3 .

[0088] Example 9

[0089] Embodiment 9 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 6 μm, P-type doping is performed in the capacitor polysilicon and in a preset area of ​​the N-type epitaxial layer, the impurity is B, and the doping concentration is 2E16 atom / cm 3 .

[0090] Example 10

[0091] Embodiment 10 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 6 μm and the temperature of the P-type doping is 800° C.

[0092] Embodiment 11

[0093] Embodiment 11 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that the depth of the second trench is 6 μm and the temperature of the P-type doping is 1000° C.

[0094] Example 12

[0095] Embodiment 12 of the present invention provides a method for preparing a slow-start power MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Embodiment 1 in that all doping is inverted, and specifically includes the following steps:

[0096] (1) A P-type substrate is provided, and a first groove and a second groove are respectively etched on the P-type substrate, wherein the depth of the first groove is 1 μm, the depth of the second groove is 5 μm, the width of the second groove is 2 μm, and the P-type doping impurity of the P-type substrate is B, and the doping concentration is 1E18 atom / cm 3 , the temperature is 900℃;

[0097] (2) thermally oxidizing the P-type substrate with the first trench and the second trench to grow an oxide layer on the surface of the first trench and the second trench as a dielectric layer of the polysilicon sidewall, wherein the second oxide layer is obtained by etching the oxide layer deposited at the bottom of the second trench, and the bottom surface of the second trench is partially exposed. Specifically, oxygen is introduced at a temperature of 900° C. to grow the first oxide layer and the second oxide layer with a thickness of 500 Å;

[0098] (3) depositing polysilicon in the grooves formed by the first oxide layer and the second oxide layer respectively and performing CMP grinding and etching to form gate polysilicon and capacitor polysilicon respectively, wherein the surface of the gate polysilicon and the capacitor polysilicon is 0.2 μm lower than the surface of the corresponding oxide layer;

[0099] (4) N-type doping is performed in the capacitor polysilicon and the preset area of ​​the P-type substrate, the impurity is P, and the doping concentration is 1E13atom / cm 3 , the temperature is 800℃;

[0100] (5) P-type doping is performed on the N-type doped part. The P-type doping impurity is B and the doping concentration is 2E14atom / cm 3 , the temperature is 900℃.

[0101] Comparative Example 1

[0102] Comparative Example 1 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a slow-start power MOS transistor in Example 1 in that a second trench is not prepared and no additional NPN structure exists.

[0103] The MOS transistors prepared by the MOS transistor preparation method in Examples 1 to 12 and Comparative Example 1 were tested, and the specific results are as follows:

[0104]

[0105] It can be found that the Miller platform duration of the MOS transistors prepared by the embodiments of the present invention is significantly prolonged, among which the MOS transistor prepared by Embodiment 9 of the present invention is the best, with a Miller platform duration of 13.6 ns.

[0106] In summary, a slow-start power MOS transistor and a preparation method thereof in an embodiment of the present invention comprises: when the MOS transistor is a Trench NMOS transistor, a first trench and a second trench spaced apart from the first trench are arranged in an N-type epitaxial layer; a first oxide layer is deposited on the surface of the first trench, and the trench formed by the first oxide layer is filled with gate polysilicon; in the N-type epitaxial layer on the side of the first trench away from the second trench, a first N-type sublayer and a first P-type sublayer are sequentially arranged along the depth direction of the first trench, and the doping concentration of the first N-type sublayer is higher than the doping concentration of the N-type epitaxial layer; a second oxide layer is deposited on the surface of the second trench, and the trench formed by the second oxide layer is filled with capacitor polysilicon, and the capacitor polysilicon is sequentially arranged along the depth direction of the second trench, and the doping concentration of the first N-type sublayer and the second N-type sublayer is the same; wherein the depth of the second trench is greater than the depth of the first trench, and when the MOS transistor is a Trench PMOS transistor, by depositing a first oxide layer on the surface of the N-type epitaxial layer away from the second trench, a first N-type sublayer and a first P-type sublayer are sequentially arranged in the trench formed by the second oxide layer, and the doping concentration of the first N-type sublayer and the second N-type sublayer is the same; All doping in the NMOS transistor is inverted. Specifically, since there is a capacitor polysilicon with an NPN structure, and the capacitance formed by the PN junction is related to the width of the depletion region and the size of the PN junction cross-sectional area, the width of the second trench and the doping concentration of the second P-type sublayer can be adjusted as needed to adjust the size of the capacitor, so as to adjust the duration of the Miller platform. At the same time, this structure makes the MOS driving circuit simpler, the circuit integration is higher, and the cost is reduced. In addition, the formed NPN structure will have a PN junction in reverse bias regardless of whether the power MOS is in the on state or the off state, so that the branch here will not be turned on and will not affect the normal operation of the MOS device. It can be understood that when the MOS transistor is a Trench PMOS transistor, a PNP structure is obtained.

[0107] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A slow-start power MOS transistor, characterized in that: When the MOS transistor is a Trench NMOS transistor, the MOS transistor includes a first trench disposed in the N-type epitaxial layer and a second trench spaced apart from the first trench; A first oxide layer is deposited on the surface of the first trench, and a trench formed by the first oxide layer is filled with gate polysilicon. In the N-type epitaxial layer on the side of the first trench away from the second trench, a first N-type sublayer and a first P-type sublayer are sequentially arranged along the depth direction of the first trench, and the doping concentration of the first N-type sublayer is higher than the doping concentration of the N-type epitaxial layer; A second oxide layer is deposited on the side of the second trench, the bottom surface of the second trench is partially exposed, the trench formed by the second oxide layer is filled with capacitor polysilicon, and the capacitor polysilicon is sequentially provided with a second N-type sublayer and a second P-type sublayer along the depth direction of the second trench, and the first N-type sublayer and the second N-type sublayer have the same doping concentration; Wherein, the second N-type sublayer on the top of the capacitor polysilicon is connected to the gate polysilicon, and the depth of the second trench is greater than the depth of the first trench; When the MOS transistor is a Trench PMOS transistor, it is obtained by inverting all doping in the Trench NMOS transistor.

2. The slow-start power MOS transistor according to claim 1, characterized in that: The depth of the first groove is 1 μm-1.5 μm.

3. The slow-start power MOS transistor according to claim 2, characterized in that: The second groove has a depth of 5 μm to 7 μm.

4. The slow-start power MOS transistor according to claim 3, characterized in that: The width of the second groove is 2 μm-6 μm.

5. The slow-start power MOS transistor according to claim 4, characterized in that: The thickness of the first oxide layer and the second oxide layer are both 500Å~1000Å.

6. The slow-start power MOS transistor according to claim 5, characterized in that: The impurity of the second P-type sublayer is B, and the doping concentration is 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃.

7. The slow-start power MOS transistor according to claim 6, characterized in that: The impurities of the first N-type sublayer and the second N-type sublayer are P, and the doping concentration is 1E13atom / cm 3 ~1E17atom / cm 3 , the temperature is 800℃~1100℃.

8. The slow-start power MOS transistor according to claim 7, characterized in that: The surfaces of the gate polysilicon and the capacitor polysilicon are 0.2 μm to 0.5 μm lower than the surfaces of the corresponding oxide layers.

9. A method for preparing a slow-start power MOS transistor, characterized in that: Used to prepare the MOS transistor according to any one of claims 1 to 8, when the MOS transistor is a Trench NMOS transistor, the preparation method comprises: Providing an N-type epitaxial layer; Etching a first trench and a second trench spaced apart from the first trench on the N-type epitaxial layer, wherein the depth of the second trench is greater than the depth of the first trench; Depositing oxide layers on the surfaces of the first trench and the second trench to form a first oxide layer and a second oxide layer respectively, wherein the second oxide layer is obtained by etching the oxide layer deposited at the bottom of the second trench, and the bottom surface of the second trench is partially exposed; Depositing polysilicon in the grooves formed by the first oxide layer and the second oxide layer respectively and performing CMP grinding and etching to form gate polysilicon and capacitor polysilicon respectively; Performing P-type doping in the capacitor polysilicon and in a preset region of the N-type epitaxial layer; Performing N-type doping on the P-type doped portion to obtain a first N-type sublayer, a first P-type sublayer, a second N-type sublayer, and a second P-type sublayer, wherein the doping concentration of the first N-type sublayer is higher than the doping concentration of the N-type epitaxial layer, and the doping concentrations of the first N-type sublayer and the second N-type sublayer are the same; or, When the MOS transistor is a Trench PMOS transistor, the preparation method is to invert all doping in the Trench NMOS transistor.

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