Semiconductor structure, method of manufacturing thereof and memory

Abstract

The present disclosure provides a semiconductor structure, a preparation method thereof and a memory. The semiconductor structure comprises a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, a semiconductor layer, a source and a drain; the first gate and the second gate are respectively arranged on two sides of the semiconductor layer, the semiconductor layer comprises a channel layer and a barrier layer which are sequentially stacked in a direction from the second gate to the first gate, the channel layer and the barrier layer both comprise a metal oxide containing indium elements and gallium elements, and in the metal elements of the metal oxide, the atomic percentage of the indium elements in the channel layer is higher than that in the barrier layer. The semiconductor layer of the structure can make the carriers move in the channel layer with higher mobility, so that the carrier mobility of the transistor can also be effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device structure, its fabrication method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used device in computers. Traditional DRAM typically adopts a 1T1C architecture, where one transistor is connected to one capacitor. However, the capacitor not only presents the problem of needing to be continuously refreshed to maintain its charge, but also limits further miniaturization of the device.

[0003] The 2TOC (Two-Transistor, Capacitorless) memory design is a relatively good way to solve the above problems. Oxide-semiconductor transistors (OSTs) show promise for use in 2TOC dynamic random access memories. However, the electrical performance of OSTs, such as carrier mobility, still needs further improvement.

[0004] Public content

[0005] Therefore, it is necessary to provide a semiconductor structure and fabrication method to address the problems mentioned in the background art, so as to improve the carrier mobility of transistors.

[0006] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising: a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, a semiconductor layer, a source, and a drain;

[0007] The first gate and the second gate are respectively disposed on both sides of the semiconductor layer, the first gate dielectric layer is disposed between the first gate and the semiconductor layer, the second gate dielectric layer is disposed between the second gate and the semiconductor layer, and the semiconductor layer includes a channel layer and a barrier layer stacked sequentially in the direction from the second gate to the first gate. The source and the drain are spaced apart and are both electrically connected to the channel layer.

[0008] Both the channel layer and the barrier layer include metal oxides containing indium and gallium, and among the metal elements in the metal oxides, the atomic percentage of indium in the channel layer is higher than that of indium in the barrier layer.

[0009] In some embodiments of this disclosure, in the channel layer, the indium element accounts for 20% to 40% of the atomic percentage of the metal elements in the metal oxide.

[0010] In some embodiments of this disclosure, the atomic percentage of indium in the channel layer and the atomic percentage of indium in the barrier layer differ by 10% to 30% among the metal elements of the metal oxide.

[0011] In some embodiments of this disclosure, the energy level of the conduction band bottom of the metal oxide in the channel layer is 0.01 eV to 0.2 eV lower than the energy level of the conduction band bottom of the metal oxide in the barrier layer.

[0012] In some embodiments of this disclosure, the thickness of the barrier layer is 5 nm to 15 nm.

[0013] In some embodiments of this disclosure, the thickness of the channel layer is 10 nm to 15 nm.

[0014] In some embodiments of this disclosure, the materials of both the channel layer and the barrier layer include indium gallium zinc oxide or indium gallium oxide.

[0015] In some embodiments of this disclosure, a gate sidewall is also included, which is disposed on both sides of the first gate and the first gate dielectric layer.

[0016] Furthermore, according to some embodiments of this disclosure, a method for fabricating the above-described semiconductor structure is also provided, the method comprising the following steps:

[0017] The second gate is fabricated on the substrate;

[0018] The second gate dielectric layer is prepared on the second gate.

[0019] A channel layer, a barrier layer, and a first gate dielectric layer are sequentially stacked on the second gate dielectric layer, and a source and a drain electrically connected to the channel layer are fabricated; and,

[0020] The first gate is fabricated on the first gate dielectric layer.

[0021] In some embodiments of this disclosure, the channel layer, the barrier layer, and the first gate dielectric layer are sequentially stacked on the second gate dielectric layer, including:

[0022] A first semiconductor material layer and a second semiconductor material layer are stacked on the second gate dielectric layer;

[0023] The first gate dielectric layer and a patterned protective layer located on the first gate dielectric layer are fabricated on the second semiconductor material layer;

[0024] Etching removes the second semiconductor material layer not shielded by the protective layer, leaving the remaining second semiconductor material layer as a barrier layer; and,

[0025] The first semiconductor material layer, which is shielded by the barrier layer, is used as the channel layer.

[0026] In some embodiments of this disclosure, the preparation of the source and the drain electrically connected to the channel layer includes: performing ion implantation and annealing on the first semiconductor material layer not shielded by the barrier layer to form the source and the drain, respectively.

[0027] In some embodiments of this disclosure, a first semiconductor material layer and a second semiconductor material layer are stacked on the second gate dielectric layer, including:

[0028] The first semiconductor material layer is deposited by sputtering using a first target material, wherein the first target material comprises a metal oxide containing indium and gallium.

[0029] The second semiconductor material layer is deposited by sputtering using a second target. The second target includes a metal oxide containing indium and gallium, and the atomic percentage of indium in the first target is higher than that of indium in the second target.

[0030] In some embodiments of this disclosure, after depositing the first semiconductor material layer and before depositing the second semiconductor material layer, the method further includes annealing the first semiconductor material layer.

[0031] In some embodiments of this disclosure, after fabricating the first gate on the first gate dielectric layer, the method further includes: depositing a sidewall material layer on the first gate and the side of the first gate, etching the sidewall material layer, and retaining a portion of the sidewall material layer attached to the sidewall of the first gate as the gate sidewall.

[0032] Furthermore, according to some other embodiments of this disclosure, a storage device is also provided, the storage device including logic circuitry and a semiconductor structure provided according to the above embodiments, the logic circuitry being electrically connected to the semiconductor structure.

[0033] This semiconductor structure includes a semiconductor layer and a first gate and a second gate located on opposite sides of the semiconductor layer. In the direction from the second gate to the first gate, the semiconductor layer includes a channel layer and a barrier layer. Since the atomic percentage of indium in the channel layer is higher than that in the barrier layer, the channel layer has a higher carrier mobility, and the interface between the barrier layer and the channel layer has a potential barrier that prevents carriers from passing through. This semiconductor structure allows carriers to be confined to the channel layer with higher mobility, thus effectively improving the carrier mobility of the transistor. Furthermore, because the interface barrier effectively blocks carriers, this semiconductor structure also effectively prevents tunneling into the first gate dielectric layer caused by excessively high carrier mobility in the channel layer.

[0034] The above description is only an overview of the technical solution of this disclosure. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, the preferred embodiments of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a cross-sectional structure of a semiconductor structure;

[0037] Figure 2 for Figure 1 A schematic diagram of the local energy band structure of the channel layer and the barrier layer in the image;

[0038] Figure 3 A schematic diagram illustrating the steps of a semiconductor structure fabrication method;

[0039] Figure 4 This is a schematic diagram of a substrate and a second gate located on the substrate provided in this disclosure;

[0040] Figure 5 In order to be in Figure 4 A schematic diagram of the structure for fabricating the second gate dielectric layer based on the structure shown;

[0041] Figure 6 It shows in Figure 5 A schematic diagram of a structure for fabricating a first semiconductor material layer and a second semiconductor material layer based on the structure shown;

[0042] Figure 7A schematic diagram of a structure for fabricating a first gate dielectric layer on a second semiconductor material layer is shown;

[0043] Figure 8 It shows in Figure 7 A schematic diagram of a barrier layer formed based on the structure shown;

[0044] Figure 9 It shows in Figure 8 A schematic diagram showing the formation of a channel layer, source, and drain based on the structure shown.

[0045] Figure 10 It shows in Figure 9 A schematic diagram of the structure for fabricating the first gate based on the structure shown;

[0046] Figure 11 It shows in Figure 10 A schematic diagram of the structure for fabricating the gate sidewall based on the structure shown;

[0047] The reference numerals and their meanings in the accompanying drawings are as follows:

[0048] 100, Substrate; 101, Base material; 102, Insulating dielectric layer; 110, Semiconductor layer; 111, Channel layer; 1110, First semiconductor material layer; 112, Barrier layer; 1120, Second semiconductor material layer; 120, First gate; 130, First gate dielectric layer; 140, Second gate; 150, Second gate dielectric layer; 151, First dielectric sublayer; 152, Second dielectric sublayer; 160, Source; 170, Drain; 180, Gate sidewall; 210, Protective layer. Detailed Implementation

[0049] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] This disclosure provides a semiconductor structure, characterized in that it includes: a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, a semiconductor layer, a source, and a drain. The first gate and the second gate are respectively disposed on opposite sides of the semiconductor layer. The first gate dielectric layer is disposed between the first gate and the semiconductor layer, and the second gate dielectric layer is disposed between the second gate and the semiconductor layer. From the second gate to the first gate, the semiconductor layer includes a channel layer and a barrier layer stacked sequentially. The source and drain are spaced apart and electrically connected to the channel layer. Both the channel layer and the barrier layer include metal oxides containing indium and gallium, and in the metal elements of the metal oxides, the atomic percentage of indium in the channel layer is higher than that of indium in the barrier layer.

[0055] This semiconductor structure includes a semiconductor layer and a first gate and a second gate located on opposite sides of the semiconductor layer. In the direction from the second gate to the first gate, the semiconductor layer includes a channel layer and a barrier layer. Since the atomic percentage of indium in the channel layer is higher than that in the barrier layer, the channel layer has a higher carrier mobility, and the interface between the barrier layer and the channel layer has a potential barrier that prevents carriers from passing through. This semiconductor structure allows carriers to be confined to the channel layer with higher mobility, thus effectively improving the carrier mobility of the transistor. Furthermore, because the interface barrier effectively blocks carriers, this semiconductor structure also effectively prevents tunneling into the first gate dielectric layer caused by excessively high carrier mobility in the channel layer.

[0056] The embodiments disclosed herein are described with reference to cross-sectional views that serve as schematic representations of preferred embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this disclosure.

[0057] This is publicly available. Figure 1 This is a schematic cross-sectional view of a semiconductor structure. (Refer to...) Figure 1As shown, the semiconductor structure includes a first gate 120, a second gate 140, a first gate dielectric layer 130, a second gate dielectric layer 150, a semiconductor layer 110, a source 160, and a drain 170. The first gate 120 and the second gate 140 are respectively disposed on opposite sides of the semiconductor layer 110. The first gate dielectric layer 130 is disposed between the first gate 120 and the semiconductor layer 110. The second gate dielectric layer 150 is disposed between the second gate 140 and the semiconductor layer 110. The source 160 and the drain 170 are spaced apart and are both electrically connected to the channel layer 111. From the second gate 140 to the first gate 120, the semiconductor layer 110 includes a channel layer 111 and a barrier layer 112 stacked sequentially.

[0058] Both the channel layer 111 and the barrier layer 112 include metal oxides containing indium and gallium. For these indium and gallium-containing metal oxides, the higher the atomic percentage of indium in the metal, the higher the carrier mobility. Furthermore, the indium content also affects the energy level at the bottom of the conduction band of the metal oxide. When the indium content is high, the energy level at the bottom of the conduction band is closer to the Fermi level, meaning that the energy level at the bottom of the conduction band is lower. Combining these characteristics, by placing the barrier layer 112 on one side of the channel layer 111, a potential barrier exists between the bottom of the conduction band of the barrier layer 112 and the bottom of the conduction band of the channel layer 111. This confines carriers within the channel layer 111, allowing them to migrate within it, resulting in a high carrier mobility for the transistor.

[0059] It is understood that the first gate 120, the second gate 140, the first gate dielectric layer 130, the second gate dielectric layer 150, the semiconductor layer 110, the source 160, and the drain 170 can participate in the formation of a transistor. The channel layer 111 in the semiconductor layer 110 can serve as the channel in this transistor, and the first gate 120 and the second gate 140 can serve as the top gate and the bottom gate in this transistor, respectively. Therefore, this transistor has a dual-gate structure. In actual operation, by simultaneously controlling the first gate 120 and the second gate 140, the charge carriers can migrate in the channel layer 111 near the barrier layer 112. Furthermore, the interface between the barrier layer 112 and the channel layer 111 can confine the charge carriers within the channel layer 111, preventing the charge carriers from tunneling through the first gate dielectric layer 130 or the second gate dielectric layer 150.

[0060] In some examples of this embodiment, the semiconductor structure may further include a substrate 100, which may include a base material 101 and an insulating dielectric layer 102. (Refer to...) Figure 1As shown, the insulating dielectric layer 102 is disposed on the substrate, and the second gate 140, the semiconductor layer 110, and the first gate 120 can be disposed on the side of the insulating dielectric layer 102 away from the substrate. The substrate 101 can be used to fabricate other functional components in the semiconductor structure, or the substrate 101 can include other functional components in the semiconductor structure. The insulating dielectric layer 102 can be used to insulate the transistor from the substrate 101.

[0061] In some examples of this embodiment, the material of the substrate 101 can be a semiconductor material, for example, the material of the substrate 101 may include silicon.

[0062] In some examples of this embodiment, the material of the insulating dielectric layer 102 is selected from insulating materials. For example, the material of the insulating dielectric layer 102 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0063] In some examples of this embodiment, the metal oxide may be indium gallium oxide (IGO) or indium gallium zinc oxide (IGZO). Further, in this embodiment, the metal oxide is indium gallium zinc oxide.

[0064] In some examples of this embodiment, the metal oxides in the channel layer 111 and the barrier layer 112 are of the same type, for example, both the channel layer 111 and the barrier layer 112 are selected from indium gallium oxide or indium gallium zinc oxide.

[0065] In some examples of this embodiment, in the channel layer 111, the atomic percentage of indium in the metal oxide is 20% to 40%. For example, the metal oxide in the channel layer 111 is indium gallium zinc oxide, with the structural formula In. x GaZn z1 O, where x+y+z=1, and x is 0.2~0.4. Controlling the atomic proportion of indium in the metal oxide to 20%~40% can enable the channel layer 111 to have a higher carrier mobility, thereby improving the conductivity of the transistor.

[0066] In some examples of this embodiment, the atomic percentage of indium in the channel layer 111 and the atomic percentage of indium in the barrier layer 112 differs by 10% to 30% in the metal elements of the metal oxide. For example, the metal oxides in both the channel layer 111 and the barrier layer 112 are indium gallium zinc oxide, and the structural formula of the indium gallium zinc oxide in the channel layer 111 is In... a1 Ga b1 Zn c1 O, the structural formula of indium gallium zinc oxide in barrier layer 112 is In a2 Ga b2 Zn c2O, where a1+b1+c1=1, a2+b2+c2=1, and the difference between a1 and a2 is 0.1~0.3. By controlling the difference between a1 and a2 to be 0.1~0.3, the blocking layer 112 can have a good blocking ability for charge carriers.

[0067] Figure 2 It shows Figure 1 A partial energy band diagram of the channel layer 111 and the barrier layer 112. Figure 2 E in F The Fermi level, E, represents the energy level of a metal oxide. c1 E represents the energy level at the bottom of the conduction band of channel layer 111. c2 The energy level at the bottom of the conduction band of barrier layer 112 is represented by ΔE. c E represents c1 With E c2 The difference is represented by the vertical dashed line, which indicates the interface between the channel layer 111 and the barrier layer 112. (Refer to...) Figure 2 As shown, in some examples of this embodiment, the conduction band bottom of the metal oxide in the channel layer 111 is located at the energy level (i.e., E). c1 The energy level at which the conduction band bottom of the metal oxide in the barrier layer 112 is located (i.e., E) c2 The difference is 0.01 eV to 0.2 eV. △E c The higher the indium content, the greater the potential barrier at the interface between the channel layer 111 and the barrier layer 112, making it more difficult for charge carriers to pass through this interface. It is understandable that the conduction band bottom of the metal oxide can be controlled by changing the atomic percentage of indium. Furthermore, while changing the atomic percentage of indium, the oxygen defect content in the metal oxide can be controlled to achieve more precise control over the energy level at the conduction band bottom.

[0068] Reference Figure 1 As shown, in some examples of this embodiment, a second gate 140 is stacked on the substrate 100, a second gate dielectric layer 150 is stacked on the second gate 140, a channel layer 111 is stacked on the second gate dielectric layer 150, a barrier layer 112 is stacked on the channel layer 111, a first gate dielectric layer 130 is stacked on the barrier layer 112, a first gate 120 is stacked on the first gate dielectric layer 130, and a source 160 and a drain 170 are respectively disposed on both sides of the channel layer 111 and in contact with the channel layer 111. It can be understood that the first gate 120 can serve as the top gate of the transistor, and the second gate 140 can serve as the bottom gate of the transistor.

[0069] In some examples of this embodiment, the thickness of the barrier layer 112 can be 5 nm to 15 nm. Controlling the thickness of the barrier layer 112 to 5 nm to 30 nm can minimize or avoid the influence of the barrier layer 112 on the turn-off characteristics of the first gate 120 while effectively blocking charge carriers. Further, the thickness of the barrier layer 112 can be 5 nm to 10 nm. Even further, the thickness of the barrier layer 112 can be 6 nm to 8 nm.

[0070] In some examples of this embodiment, the thickness of the channel layer 111 can be 10 nm to 15 nm. Controlling the thickness of the channel layer 111 to 10 nm to 15 nm can improve the carrier mobility of the channel layer 111 while maintaining the device's turn-off characteristics. Further, the thickness of the channel layer 111 can be 10 nm to 15 nm. Even further, the thickness of the channel layer 111 can be 10 nm to 12 nm.

[0071] In this embodiment, since the barrier layer 112 can confine charge carriers as much as possible within the channel layer 111, a thinner first gate dielectric layer 130 can be used to improve device performance and reduce size. In some examples of this embodiment, the thickness of the first gate dielectric layer 130 can be controlled to be 5 nm to 15 nm. Further, the thickness of the first gate dielectric layer 130 can be 5 nm to 10 nm. Even further, the thickness of the first gate dielectric layer 130 can be 5 nm to 7 nm.

[0072] In some examples of this embodiment, the material of the first gate dielectric layer 130 may be selected from insulating materials. For example, the material of the first gate dielectric layer 130 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the first gate dielectric layer 130 is silicon oxide.

[0073] In some examples of this embodiment, the second gate dielectric layer 150 may include multiple sequentially stacked dielectric sublayers in a direction away from the second gate 140. (Refer to...) Figure 1 As shown, the second gate dielectric layer 150 includes a first dielectric sublayer 151 and a second dielectric sublayer 152. The first dielectric sublayer 151 may cover the top and sidewalls of the second gate 140, and the first dielectric sublayer 151 may have a flat surface.

[0074] In some examples of this embodiment, the materials of the first dielectric sublayer 151 and the second dielectric sublayer 152 can both be selected from insulating materials. For example, the material of the first dielectric sublayer 151 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the second dielectric sublayer 152 may also include one or more of silicon nitride, silicon oxide, and silicon oxynitride. Further, the materials of the first dielectric sublayer 151 and the second dielectric sublayer 152 may be different. For example, the material of the first dielectric sublayer 151 may be silicon nitride, and the material of the second dielectric sublayer 152 may be silicon oxide.

[0075] In some examples of this embodiment, the thickness of the second gate dielectric layer 150 can be controlled to be 50 nm to 500 nm.

[0076] In some examples of this embodiment, the materials of the first gate 120 and the second gate 140 may be selected from conductive materials. For example, the materials of the first gate 120 and the second gate 140 may include one or more of metals and doped polysilicon. The metal may be selected from one or more of titanium, gold, silver, copper, aluminum, and tungsten.

[0077] In some examples of this embodiment, the materials of the source 160 and the drain 170 can each be independently selected from conductive materials. For example, the materials of the source 160 and the drain 170 can include one or more of metals and doped metal oxides. In this embodiment, the materials of the source 160 and the drain 170 can be doped metal oxides.

[0078] Furthermore, this disclosure Figure 3 A schematic diagram illustrating the steps of a semiconductor structure fabrication method is also provided. (Refer to...) Figure 3 As shown, the method for fabricating this semiconductor structure includes steps S1 to S5.

[0079] Step S1: Fabricate a second gate on the substrate.

[0080] Figure 4 This is a schematic diagram of a substrate 100 and a second gate 140 located on the substrate 100 provided in this disclosure. (Refer to...) Figure 4 The substrate 100 may include a substrate 101 and an insulating dielectric layer 102 disposed on the substrate 101.

[0081] In some examples of this embodiment, the material of substrate 101 may be silicon. The material of substrate 101 may be used to fabricate a semiconductor device that can be electrically connected to a transistor subsequently fabricated over insulating dielectric layer 102 and further form a semiconductor assembly.

[0082] In some examples of this embodiment, the material of the insulating dielectric layer 102 is silicon oxide.

[0083] In some examples of this embodiment, fabricating the second gate 140 on the substrate 100 includes: depositing a conductive material on the insulating dielectric layer 102 and patterning the conductive material to form the second gate 140. The patterning process can be photolithography.

[0084] In some examples of this embodiment, the material of the second gate 140 may be selected from conductive materials. For example, the material of the second gate 140 may include one or more of a metal and doped polysilicon. The metal may be selected from one or more of titanium, gold, silver, copper, aluminum, and tungsten.

[0085] In some examples of this embodiment, the thickness of the second gate 140 can be controlled to be 5 nm to 100 nm during the fabrication of the second gate 140.

[0086] Step S2: Prepare a second gate dielectric layer on the second gate.

[0087] Figure 5 It shows in Figure 4 A schematic diagram of the fabrication of the second gate dielectric layer 150 based on the structure shown. (Refer to...) Figure 5 As shown, the second gate dielectric layer 150 covers the second gate 140. In this embodiment, the second gate dielectric layer 150 may also completely cover the second gate 140 and the substrate 100. The second gate dielectric layer 150 can be used to space the second gate 140 from other functional layers subsequently fabricated.

[0088] The material of the second gate dielectric layer 150 can be selected from insulating materials. For example, the material of the second gate dielectric layer 150 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. Alternatively, the second gate dielectric layer 150 may have a stacked structure, comprising multiple stacked dielectric sublayers. In this embodiment, the second gate dielectric layer 150 includes a first dielectric sublayer 151 and a second dielectric sublayer 152.

[0089] In some examples of this embodiment, fabricating the second gate dielectric layer 150 includes: depositing material of the first dielectric sublayer 151 on the substrate 100 and the second gate 140 to form the first dielectric sublayer 151, and depositing material of the second dielectric sublayer 152 on the first dielectric sublayer 151 to form the second dielectric sublayer 152.

[0090] The first dielectric sublayer 151 can be made of silicon nitride, and the second dielectric sublayer 152 can be made of silicon oxide.

[0091] In some examples of this embodiment, after depositing the material of the first dielectric sublayer 151, the method further includes: planarizing the surface of the first dielectric sublayer 151 to give the first dielectric sublayer 151 a flat surface. The planarization process may be chemical mechanical polishing.

[0092] In some examples of this embodiment, the thickness of the second gate dielectric layer 150 can be controlled to be 10 nm to 50 nm.

[0093] Step S3: A channel layer, a barrier layer, and a first gate dielectric layer are sequentially stacked on the second gate dielectric layer, and a source and drain electrically connected to the channel layer are fabricated.

[0094] In some examples of this embodiment, the preparation of a channel layer 111, a barrier layer 112, and a first gate dielectric layer 130 stacked sequentially on the second gate dielectric layer 150 includes: preparing a first semiconductor material layer 1110 and a second semiconductor material layer 1120 stacked on the second gate dielectric layer 150; preparing the first gate dielectric layer 130 and a patterned protective layer 210 on the second semiconductor material layer 1120; etching away the second semiconductor material layer 1120 not shielded by the protective layer 210, leaving the second semiconductor material layer 1120 as the barrier layer 112; and using the first semiconductor material layer 1110 shielded by the barrier layer 112 as the channel layer 111.

[0095] In some further examples of this embodiment, the preparation of the source 160 and drain 170 electrically connected to the channel layer 111 includes: performing ion implantation and annealing on the first semiconductor material layer 1110 that is not shielded by the blocking layer 112 to form the source 160 and drain 170, respectively.

[0096] Figure 6 It shows in Figure 5 A schematic diagram showing the fabrication of a first semiconductor material layer 1110 and a second semiconductor material layer 1120 based on the structure shown. (Refer to...) Figure 6 As shown, the first semiconductor material layer 1110 covers the second gate dielectric layer 150, and the second semiconductor material layer 1120 covers the first semiconductor material layer 1110.

[0097] The first semiconductor material layer 1110 is used to fabricate the channel layer 111 in subsequent processes, and the second semiconductor material layer 1120 is used to fabricate the barrier layer 112 in subsequent processes. Therefore, both the first semiconductor material layer 1110 and the second semiconductor material layer 1120 may include metal oxides containing indium and gallium, and the atomic percentage of indium in the metal elements in the first semiconductor material layer 1110 is higher than that in the second semiconductor material layer 1120.

[0098] In some examples of this embodiment, the first semiconductor material layer 1110 can be prepared by sputtering, for example, by depositing the first semiconductor material layer 1110 using a first target, wherein the first target includes indium and gallium. Further, the material of the first target may include indium gallium zinc oxide.

[0099] In some examples of this embodiment, the second semiconductor material layer 1120 can be prepared by sputtering, for example, by depositing the second semiconductor material layer 1120 using a second target, which includes indium and gallium. Further, the material of the second target can include indium gallium zinc oxide. It is understood that the atomic percentage of indium in the metal element in the first target is higher than the atomic percentage of indium in the metal element in the second target.

[0100] In some examples of this embodiment, during the fabrication of the first semiconductor material layer 1110, the thickness of the first semiconductor material layer 1110 can be controlled to be 20 nm to 60 nm. Further, the thickness of the first semiconductor material layer 1110 can be controlled to be 20 nm to 50 nm. Even further, the thickness of the first semiconductor material layer 1110 can be controlled to be 30 nm to 50 nm.

[0101] In some examples of this embodiment, during the fabrication of the second semiconductor material layer 1120, the thickness of the second semiconductor material layer 1120 can be controlled to be 5 nm to 30 nm. Further, the thickness of the second semiconductor material layer 1120 can be controlled to be 5 nm to 25 nm. Even further, the thickness of the second semiconductor material layer 1120 can be controlled to be 10 nm to 25 nm.

[0102] In some examples of this embodiment, after fabricating the first semiconductor material layer 1110 and before fabricating the second semiconductor material layer 1120, an annealing step of the first semiconductor material layer 1110 is included. Annealing the first semiconductor material layer 1110 helps to improve the oxygen vacancy defect distribution in the first semiconductor material layer 1110, thereby improving the carrier mobility of the first semiconductor material layer 1110.

[0103] In some examples of this embodiment, during the annealing process of the first semiconductor material layer 1110, the annealing temperature can be 200°C to 400°C, and the annealing time can be 30 min to 120 min.

[0104] In some examples of this embodiment, during the annealing of the first semiconductor material, the annealing environment gas may or may not contain oxygen. For example, the annealing environment gas may include oxygen with a volume percentage of 0% to 5%.

[0105] Figure 7 A schematic diagram of the structure on which a first gate dielectric layer 130 is fabricated on a second semiconductor material layer 1120 is shown. (Refer to...) Figure 7 As shown, the first gate dielectric layer 130 is disposed on the second semiconductor material layer 1120.

[0106] In some examples of this embodiment, the material of the first gate dielectric layer 130 may be selected from insulating materials. For example, the material of the first gate dielectric layer 130 is silicon oxide.

[0107] In some examples of this embodiment, the step of preparing the first gate dielectric layer 130 may include: depositing a material covering the second semiconductor material layer 1120 on the second semiconductor material layer 1120, and patterning the material of the first gate dielectric layer 130 to form the first gate dielectric layer 130.

[0108] Further, patterning the material of the first gate dielectric layer 130 includes: preparing a patterned protective layer 210 on the material of the first gate dielectric layer 130, and etching the material of the first gate dielectric layer 130 based on the protective layer 210 to form the first gate dielectric layer 130.

[0109] In some examples of this embodiment, the material of the patterned protective layer 210 is different from the material of the first gate dielectric layer 130. For example, the material of the protective layer 210 may include silicon nitride.

[0110] Figure 8 It shows in Figure 7 A schematic diagram of a structure in which a barrier layer 112 is formed based on the structure shown. (Combined with...) Figure 7 and Figure 8 As shown, the barrier layer 112 is fabricated based on the second semiconductor material layer 1120, and the barrier layer 112 is located below the protective layer 210 and the first gate dielectric layer 130.

[0111] In some examples of this embodiment, the barrier layer 112 may be formed by etching the second semiconductor material layer 1120. Figure 7 and Figure 8 As shown, since the barrier layer 112 is located below the protective layer 210 and the first gate dielectric layer 130, in the step of forming the barrier layer 112, the second semiconductor material layer 1120 can be etched based on the protective layer 210 to remove the second semiconductor material layer 1120 that is not covered by the protective layer 210.

[0112] In some examples of this embodiment, the second semiconductor material layer 1120 can be etched using either dry etching or wet etching. In this embodiment, dry etching can be used to etch the second semiconductor material layer 1120 without substantially affecting the first semiconductor material layer 1110.

[0113] Figure 9 It shows in Figure 8 A schematic diagram of the structure in which the channel layer 111 is formed based on the structure shown. (Combined with...) Figures 7-9 As shown, the channel layer 111 is fabricated based on the first semiconductor material layer 1110, and the channel layer 111 is also located below the protective layer 210 and the first gate dielectric layer 130.

[0114] In some examples of this embodiment, the channel layer 111 may be formed by ion implantation and annealing of the first semiconductor material layer 1110 that is not shielded by the protective layer 210, so that the first semiconductor material layer 1110 that is not shielded by the protective layer 210 forms the source 160 and the drain 170 respectively, and the first semiconductor material layer 1110 shielded by the protective layer 210 serves as the channel layer 111.

[0115] It is understandable that during the ion implantation and annealing process of the first semiconductor material layer 1110 that is not shielded by the protective layer 210, metal ions can be implanted to improve the conductivity of the implanted part, so that it can be used as the source 160 and the drain 170.

[0116] By directly converting a portion of the first semiconductor material layer 1110 into source 160 and drain 170 through ion implantation, the source 160, drain 170, and channel layer 111 are all fabricated based on the first semiconductor material layer 1110. The bonding between the source 160 and drain 170 and the channel layer 111 is stable and has good conductivity, and there is no need to additionally fabricate source-drain contacts between the source 160 and drain 170 and the channel layer 111. On the other hand, directly fabricating the source 160 and drain 170 based on the first semiconductor material layer 1110 can also save on fabrication processes and facilitate more precise control of the thickness of the source 160 and drain 170.

[0117] In step S3, a protective layer 210 is introduced, which can be used to define the positions of the first gate dielectric layer 130, the barrier layer 112, and the channel layer 111. After the channel layer 111 is formed, the protective layer 210 can be removed.

[0118] Step S4: Prepare the first gate.

[0119] Figure 10 It shows in Figure 9A schematic diagram of the structure for fabricating the first gate 120 based on the structure shown. (Refer to...) Figure 10 As shown, the first gate 120 is fabricated on the side of the first gate dielectric layer 130 away from the channel layer 111. It can be understood that the position of the first gate 120 corresponds to the position of the second gate 140, and the first gate 120 and the second gate 140 are used together to control the channel layer 111. The first gate 120 can serve as the top gate, and the second gate 140 can serve as the bottom gate.

[0120] In some examples of this embodiment, the step of fabricating the first gate 120 includes depositing material of the first gate 120 on the first gate dielectric layer 130 to form the first gate 120.

[0121] In some examples of this embodiment, the material of the first gate 120 may be selected from conductive materials. For example, the material of the first gate 120 may include one or more of a metal and doped polysilicon. The metal may be selected from one or more of titanium, gold, silver, copper, aluminum, and tungsten. In this embodiment, the materials of the first gate 120 and the second gate 140 may be the same.

[0122] In some examples of this embodiment, during the fabrication of the first gate 120, the material of the first gate 120 may also be deposited on the already fabricated source 160 and drain 170. However, the material of the first gate 120 outside the area where the first gate dielectric layer 130 is located can be selectively removed by patterning, so that the first gate 120 is located only on the first gate dielectric layer 130.

[0123] Step S5: Prepare the gate sidewall.

[0124] Figure 11 It shows in Figure 10 A schematic diagram of the structure for fabricating the gate sidewall 180 based on the structure shown. (Refer to...) Figure 11 As shown, the gate sidewall 180 is located on both sides of the first gate 120 to protect the first gate 120. Furthermore, the gate sidewall 180 can also be located on the source 160 and the drain 170 to effectively separate the first gate 120 from the source 160 and the drain 170.

[0125] In some examples of this embodiment, the material of the gate sidewall 180 may be selected from insulating materials. For example, the material of the gate sidewall 180 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the gate sidewall 180 may include silicon nitride.

[0126] Furthermore, in some examples of this embodiment, the step of fabricating the gate sidewall 180 may include: fabricating a sidewall material layer on the first gate 120 and on both sides of the first gate 120, etching the sidewall material layer, and retaining a portion of the sidewall material layer attached to both sides of the first gate 120 as the gate sidewall 180.

[0127] It is understood that the semiconductor structure disclosed herein can be fabricated through steps S1 to S5. This semiconductor structure can be used as an electronic device, including a memory.

[0128] Furthermore, this disclosure also provides a memory that includes logic circuitry and the semiconductor structure provided in this disclosure.

[0129] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0130] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0131] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor device and a preparation method thereof. The first gate and the second gate are arranged on two sides of the semiconductor layer, the first gate dielectric layer is arranged between the first gate and the semiconductor layer, the second gate dielectric layer is arranged between the second gate and the semiconductor layer, the semiconductor layer comprises a channel layer and a barrier layer which are sequentially arranged in the direction from the second gate to the first gate, and the source and the drain are arranged in a spaced mode and are electrically connected to the channel layer. The second gate dielectric layer comprises a first dielectric sublayer and a second dielectric sublayer; the first gate and the second gate are used for controlling the channel layer together, so that the carriers migrate in the channel layer close to one side of the barrier layer. The channel layer and the barrier layer both comprise a metal oxide containing indium elements and gallium elements, and in the metal elements of the metal oxide, the atomic percentage of the indium elements in the channel layer is higher than that in the barrier layer. In the channel layer, the atomic percentage of the indium elements in the metal elements of the metal oxide is 20%-40%.

2. The semiconductor structure of claim 1, wherein, In the metal elements of the metal oxide, the difference between the atomic percentage of the indium elements in the channel layer and that in the barrier layer is 10%-30%.

3. The semiconductor structure of claim 1, wherein, The difference between the energy level of the conduction band bottom of the metal oxide in the channel layer and that in the barrier layer is 0.01eV-0.2eV.

4. The semiconductor structure of claim 1, wherein, The thickness of the barrier layer is 5nm-15nm.

5. The semiconductor structure of any of claims 1-4, wherein the semiconductor structure is a semiconductor-on-insulator structure. The thickness of the channel layer is 10nm-15nm.

6. The semiconductor structure of any one of claims 1 to 4, wherein the semiconductor structure is a vertical semiconductor structure. The materials of the channel layer and the barrier layer both comprise indium gallium zinc oxide or indium gallium oxide.

7. The semiconductor structure of any of claims 1-4, wherein the semiconductor structure is a vertical semiconductor structure. The application further discloses a gate side wall which is arranged on two sides of the first gate and the first gate dielectric layer.

8. The semiconductor structure of any of claims 1-4, wherein, The application further discloses a preparation method of the semiconductor device.

9. A method of producing a semiconductor structure according to any one of claims 1 to 8, characterized in that, The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device.

11. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation method of the semiconductor device. The application further discloses a preparation 12. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: Preparation of a first semiconductor material layer and a second semiconductor material layer which are stacked on the second gate dielectric layer, comprising: Deposition of the first semiconductor material layer by sputtering using a first target material, the first target material comprising a metal oxide containing indium and gallium; Deposition of the second semiconductor material layer by sputtering using a second target material, the second target material comprising a metal oxide containing indium and gallium, and the atomic percentage of indium in the metal elements in the first target material is higher than the atomic percentage of indium in the metal elements in the second target material.

13. The method of claim 12, wherein the semiconductor structure is prepared by a method comprising: After deposition of the first semiconductor material layer and before deposition of the second semiconductor material layer, further comprising: annealing the first semiconductor material layer.

14. The method for preparing a semiconductor structure according to any one of claims 9 to 13, characterized in that, After preparation of the first gate on the first gate dielectric layer, further comprising: deposition of a sidewall material layer on the first gate and the side edges of the first gate, etching the sidewall material layer, and retaining the part of the sidewall material layer attached to the sidewall of the first gate as a gate sidewall.

15. A memory device, comprising: A logic circuit and a semiconductor structure according to any one of claims 1-8, the logic circuit being electrically connected to the semiconductor structure.

Images