A multi-mode programmable gain amplifier suitable for high-precision analog front-ends

Abstract

This invention relates to the field of analog integrated circuits, specifically to a multimode programmable gain amplifier suitable for high-precision analog front-ends. The invention adds a switching array and a pseudo-resistor VPR to the input capacitor of a traditional CCIA structure. A DAC-adjusted control voltage is simultaneously applied to the substrate and gate of the VPR, making the bandwidth adjustable from tens of Hz to 20kHz. Two sets of oppositely connected PMOS pseudo-resistors are used, improving the dynamic range and adapting to various PVT conditions. The input resistor uses a combination of R-2R resistor arrays and parallel resistor arrays, reducing the area while maintaining high gain linearity. Furthermore, drawing inspiration from high-precision DAC structures, a thermometer code is used in the high bits of the APGA control bit to reduce gain error. This invention is compatible with both capacitive and voltage signals, enabling multimode applications. While achieving digitally adjustable bandwidth, it also possesses high dynamic range and adjustment linearity, better adapting to signals of different frequencies.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuits, and more particularly to a multimodal programmable gain amplifier suitable for high-precision analog front-ends. Background Technology

[0002] The analog front end (AFE) is the analog circuit located between the sensor and the analog-to-digital converter (ADC) in an electronic system, and it is crucial for the system's information integrity and signal quality. For front-end applications such as MEMS sensors and bioelectrical signals, the signals have the characteristics of low frequency and high accuracy; their analog front-end circuits are suitable for using sigma-delta modulators as readouts for the analog-to-digital converter.

[0003] A programmable gain amplifier (PGA) can have its gain adjusted via an external digital control signal. In analog front-ends, it is often used as the pre-stage of a sigma-delta modulator to adjust the input signal amplitude to the optimal input range for the ADC, ideally at full scale. In such applications, the PGA needs to meet requirements for a large dynamic range and precise gain adjustment linearity, placing high demands on the circuitry.

[0004] Traditional analog front-end PGAs typically only allow for gain adjustment, have fixed bandwidth, and are only suitable for sensor applications with similar frequencies. Their portability and versatility across sensor applications at different frequencies are low. Therefore, different bandwidth PGAs need to be designed to meet the requirements of different types of sensor signals, increasing design complexity and cost.

[0005] Current variable bandwidth PGAs often suffer from narrow adjustment range and sensitivity to PVT changes, which restricts their multimodal applications. Therefore, how to make the bandwidth of the PGA variable while ensuring adjustment linearity and signal-to-noise ratio to achieve multimodal applications has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned problems or shortcomings, the present invention aims to provide a multimodal programmable gain amplifier (PGA) suitable for high-precision analog front-ends, meeting the needs of various sensor applications, and achieving digitally adjustable bandwidth while possessing high dynamic range and adjustment linearity.

[0007] The technical solution of this invention is as follows:

[0008] A multimodal PGA suitable for high-precision analog front-ends includes: a signal selector (MUX), a variable bandwidth instrumentation amplifier (VIA), and a precision programmable gain amplifier (APGA). The signals include voltage input signals Vin+ and Vin-, capacitor input signals Cin+ and Cin-, voltage output signals Vout+ and Vout-, a gating signal SEL, a coarse gain adjustment signal CGAIN, a fine gain adjustment signal FGAIN, and a bandwidth control signal VBW.

[0009] The positive output terminal of the signal selector MUX is connected to the positive input terminal of the variable bandwidth instrumentation amplifier VIA, the negative output terminal of MUX is connected to the negative input terminal of VIA, the two voltage input terminals of MUX are connected to Vin+ and Vin- respectively, and the two capacitor input terminals of MUX are connected to Cin+ and Cin- respectively. MUX selects the input signal of VIA as a voltage signal or a variable capacitance signal through the strobe signal SEL.

[0010] The VIA includes a fully differential operational amplifier (OP) with C IN0 C IN1 C IN2 …C INn and C F A group of n+2 pairs of capacitors, named S1, S2…S n It consists of a group of n pairs of switches, an m-bit DAC, a buffer, and a pair of variable pseudo-resistors VPR. The fully differential op, capacitor, switches, and VPR constitute the main part of the VIA, while the m-bit DAC and buffer constitute the control part of the VIA.

[0011] A set of n+1 capacitors C IN0 C IN1 C IN2 …C INn The capacitors are connected in parallel, with one end of the parallel connection serving as the positive input port of the VIA and the other end connected to the positive input port of the OP. The n+1 capacitors in the other group are connected in the same way, with one end of the parallel connection serving as the negative input port of the VIA and the other end connected to the negative input port of the OP. The parallel capacitors are connected to C. IN1 C IN2 …C INn Each of these pairs of switches is connected in series in a one-to-one correspondence with the others: S1, S2…S… n .

[0012] A capacitor C F VPR and its two ends are connected to the positive input and negative output terminals of the OP, respectively, and another capacitor C... FVPR is connected to the negative input and positive output of OP respectively; the positive output of OP is connected to the negative input of APGA as the positive output of VIA, and the negative output of OP is connected to the positive input of APGA as the negative output of VIA.

[0013] Bandwidth control signal VBW <m-1:0>Connect the input terminal of the m-bit DAC, connect the output terminal of the m-bit DAC to the input terminal of the buffer, and connect the output terminal of the buffer to the control terminals VC of a pair of VPRs; coarse gain adjustment signal CGAIN. <n-1:0>Connect n pairs of switches S1, S2, ..., S n The control terminal.

[0014] VIA amplifies minute signals or changing capacitances at the 10uV level using a capacitively coupled feedback (CCIA) structure, which offers advantages such as low noise and low power consumption. The input capacitor C is controlled by changing the opening and closing of the switch via the control signal CGAIN. IN The size of the feedback capacitor C is further altered to change the gain determined by the capacitor feedback, thus achieving variable gain. F The capacitance value is C, and the minimum input capacitance is C. IN0 The value is 72C, C IN0 C IN1 C IN2 …C INn The ratios are as follows: 1:1:2:4:…:2 n , 2 in total n+1 There are several gain levels; a minimum gain of 72x is obtained when all switches are open, and a maximum gain of 72x is obtained when all switches are closed. n+1 The gain is increased by a factor of 72, with a gain step of 72. The quiescent operating point of VIA is determined by a controllable pseudo-resistor VPR.

[0015] The APGA includes a fully differential operational amplifier (OP), a pair of R-2R switched resistor arrays, an input resistor array, and a pair of feedback capacitors (C). F A pair of feedback resistors R F A 2-bit binary to 3-bit thermometer code encoder, TCODER. The APGA input signals include the VIA outputs Vin+, Vin-, and a 6-bit fine gain adjustment signal FGAIN<5:0>.

[0016] A pair of R-2R switch resistor arrays includes 8 pairs of resistors R1, R2, R3, R4, R5, R6, R7, R8 and 4 pairs of single-pole double-throw switches S1, S2, S3, S4; the 2R resistors of the pair of R-2R switch resistor arrays are connected in a one-to-one correspondence, wherein the least significant pair of 2R resistors is directly connected, and the other 4 pairs of 2R resistors are connected through 4 pairs of single-pole double-throw switches.

[0017] The input resistor array includes 4 pairs of resistors R IN0 R IN1 R IN2 R IN3 and 3 pairs of switches S5, S6, and S7. Among them, R... IN1 R IN2 and R IN3 The resistance values ​​are the same, R IN0 The resistance value is R IN1 4 times, R F The value is R IN1 8 times; R IN1 R IN2 and R IN3 Switches S5, S6, and S7 are connected in series one by one, and then connected to R. IN0 They are connected in parallel; one end of the parallel switch is connected to the input of the OP, and the other end serves as the input of the entire APGA, and is connected in parallel to the R-2R switch resistor array.

[0018] A pair of C F and R F They are connected across the positive input and negative output terminals of the OP, and the negative input and positive output terminals, respectively; the negative and positive output terminals of the OP serve as the positive and negative output terminals of the entire circuit, corresponding to the output signals Vout+ and Vout-.

[0019] The fine gain adjustment signal FGAIN<5:0> is divided into two segments: the lower 4 bits FGAIN<0:3> and the higher 2 bits FGAIN<5:4>. The lower 4 bits FGAIN<0:3> are connected to the control signals of S1, S2, S3, and S4, while the higher 2 bits FGAIN<5:4> serve as the input signal for TCODER. The output of TCODER is the signal TESL<2:0>, which is connected to the control signals of S5, S6, and S7, respectively.

[0020] The APGA achieves gain adjustment from 1 to 16.75x, with 0.25x steps achieved based on R-2R switched resistors and a parallel resistor array. The 6-bit FGAIN provides fine-tuning for the overall PGA, achieving high linearity in gain adjustment. It employs a combination of R-2R and thermometer code: the higher two bits of FGAIN (5:4) are converted into thermometer code TSEL (2:0) via a thermometer code converter to control the switching of the lower parallel resistor array; the lower four bits of FGAIN (3:0) directly control the switching of the upper R-2R resistor array. This design reduces PGA amplification error by decreasing the bit error rate.

[0021] Furthermore, the controllable pseudo-resistor VPR includes four PMOS transistors M1, M2, M3 and M4, input / output terminals VA and VB, and a control terminal VC.

[0022] The VA terminal is connected to the source of M1 and the drain of M3; the drain of M1 is connected to the source of M2, the source of M3 is connected to the drain of M4, and the drain of M2 and the source of M4 are connected to the VB terminal; the control terminal VC is connected to the gate of M1, M2, M3, and M4 and the substrate.

[0023] Unlike the fixed-value pseudo-resistor of the traditional CCIA structure, this invention uses a voltage-controlled variable pseudo-resistor VPR. The control voltage is provided by an m-bit DAC, and the DAC output signal is input through a buffer. The control voltage output range is from VCM to VDD, and no other reference voltage is required. The variable bandwidth of the VIA is achieved by changing the resistance of the variable pseudo-resistor VPR.

[0024] VPR achieves wide-range and high-linearity bandwidth control. Traditional voltage-controlled pseudo-resistors typically include VPRs with the gate connected to the control voltage and VPRs with the substrate connected to the control voltage. The first type has a bandwidth control range of several kHz to 20 kHz, meeting the requirements for high-frequency signals such as those from MEMS, but its filtering effect on high-frequency noise is poor for low-frequency biological signals, failing to adequately meet the needs of multimodal applications. For VPRs with only the substrate connected to the control voltage, the bandwidth control range is from tens of Hz to less than 10 kHz, meeting the frequency requirements of low-frequency biological signals, but its bandwidth is insufficient for MEMS sensor signals with frequencies exceeding 10 kHz, leading to a decrease in signal-to-noise ratio and dynamic range, and even signal distortion, similarly failing to adequately meet the needs of multimodal applications. Therefore, the VPR of this invention connects the control signal to both the substrate and gate of the MOS transistor simultaneously. In this case, its bandwidth control range can meet a wide range from tens of Hz to greater than 20 kHz, better adapting to the needs from low-frequency bioelectrical signals to mid-frequency MEMS signals, and achieving low noise and high linearity.

[0025] Furthermore, the transmission signal-to-noise ratio of traditional pseudo-resistors is not ideal when processing signals with large amplitudes. This is mainly because changes in the output voltage cause voltage changes at one end of the pseudo-resistor, which in turn leads to changes in the pseudo-resistor's resistance value. This is particularly noticeable when the output signal is of different polarities. To address this issue, the VPR of this invention employs two PMOS transistors with opposite connection configurations. When the output signal is of different polarities, the two pseudo-resistors operate symmetrically, thereby achieving a higher transmission signal-to-noise ratio.

[0026] Compared with the prior art, the present invention has the following superior effects:

[0027] 1. This invention achieves variable bandwidth by adding a switch array and a voltage-controlled pseudo-resistor VPR to the input capacitor of the traditional CCIA structure. This allows it to better adapt to signals of different frequencies and is compatible with both capacitive sensors and voltage signals, enabling multimodal applications.

[0028] 2. This invention applies a control voltage simultaneously to the substrate and gate of the pseudo-resistor, enabling the system bandwidth to switch across a wide range from tens of Hz to 20 kHz. Furthermore, the use of two sets of oppositely connected PMOS pseudo-resistors improves the dynamic range. Adjusting the pseudo-resistor voltage using a DAC allows for adaptation to various PVT conditions.

[0029] 3. This invention reduces the area while maintaining high gain linearity by replacing the input resistor in a traditional resistive feedback PGA with a combination of an R-2R resistor array and a parallel resistor array. It also borrows the structure of a high-precision DAC, employing a thermometer code in the high-order bits of the APGA control to reduce gain error. Attached Figure Description

[0030] Figure 1 This is a circuit block diagram of the present invention;

[0031] Figure 2 Here is the circuit diagram for embodiment VIA;

[0032] Figure 3 This is a circuit diagram of the APGA of the present invention;

[0033] Figure 4 The circuit diagram for the voltage-controlled variable pseudo-resistor VPR is shown in the example.

[0034] Figure 5 This is a simulation diagram showing the bandwidth variation range of the circuit in the example embodiment;

[0035] Figure 6 This is a dynamic simulation diagram of the circuit in the example. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0037] like Figure 1 As shown, this invention provides a multimodal PGA suitable for high-precision analog front-ends, comprising: a signal selector MUX, a variable bandwidth instrumentation amplifier VIA, and a precision programmable gain amplifier APGA. The signal ports include voltage input ports Vin+ and Vin-, capacitor input ports Cin+ and Cin-, voltage output ports Vout+ and Vout-, a strobe signal SEL, coarse gain adjustment CGAIN, fine gain adjustment FGAIN, and bandwidth control VBW.

[0038] The positive output terminal of the signal selector MUX is connected to the positive input terminal of the variable bandwidth instrumentation amplifier VIA, the negative output terminal of MUX is connected to the negative input terminal of VIA, the two voltage input terminals of MUX are connected to Vin+ and Vin- respectively, the two capacitor input terminals of MUX are connected to Cin+ and Cin- respectively, and the strobe signal SEL controls the capacitor or voltage signal connected to it.

[0039] The positive output terminal of VIA is connected to the negative input terminal of APGA, and the negative output terminal of VIA is connected to the positive input terminal of APGA; the coarse gain adjustment terminal CGAIN is connected to VIA; and the bandwidth control terminal VBW is connected to VIA.

[0040] Example VIA is as follows Figure 2 As shown: Includes a fully differential operational amplifier (OP) and 6 pairs of capacitors (C). IN0 C IN1 C IN2 C IN3 C IN4 C F The system consists of four pairs of switches (S1, S2, S3, S4), an m-bit DAC, a buffer, and a pair of voltage-controlled variable pseudo-resistors (VPR). The fully differential op, capacitors, switches, and VPR constitute the main body of the VIA, while the m-bit DAC and buffer constitute the control section of the VIA.

[0041] The VIA signal ports are: positive input Vin+, negative input Vin-, positive output Vout+, negative output Vout-, 6-bit bandwidth control VBW<5:0>, and 4-bit coarse gain adjustment CGAIN<3:0>.

[0042] C in a set of capacitors IN0 C IN1 C IN2 C IN3 C IN4 The capacitors are connected in parallel, with one end serving as the positive input port of the VIA and the other set of parallel capacitors serving as the negative input port of the VIA; capacitors, C IN1 C IN2 C IN3 C IN4 Switches S1, S2, S3, and S4 are connected in series in a one-to-one correspondence; the other end of one set of capacitors connected in parallel is connected to the positive input terminal of the OP, and the other set is connected to the negative input terminal of the OP.

[0043] A capacitor C F VPR and its two ends are connected to the positive input and negative output terminals of the OP, respectively, and another capacitor C... F VPR and VPR are connected to the negative input and positive output of OP respectively; the positive and negative outputs of OP serve as the positive and negative outputs of VIA.

[0044] The bandwidth control terminal VBW<5:0> is connected to the input terminal of the m-bit DAC, the output terminal of the 6-bit DAC is connected to the input terminal of the buffer, and the output terminal of the buffer is connected to the control terminal VC of a pair of VPRs; the coarse adjustment terminal CGAIN<3:0> is connected to the control terminals of four pairs of switches S1, S2, S3, and S4.

[0045] The function of VIA is to amplify small signals or changing capacitances at the 10uV level, requiring a large gain. This is achieved using a capacitively coupled feedback (CCIA) structure, which offers advantages such as low noise and low power consumption. The input capacitor C is controlled by changing the opening and closing of the switch through the control signal CGAIN. IN The size of the feedback capacitor C is further altered to change the gain determined by the capacitor feedback, thus achieving variable gain. F The capacitance is C, and the minimum input capacitance CIN0 is 72C. IN0 C IN1 C IN2 C IN3 C IN4 The gain ratio is 1:1:2:4:8. There are 16 gain levels. A minimum gain of 72x is obtained when all switches are open, and a maximum gain of 1152x is obtained when all switches are open. The gain step is 72x. The quiescent operating point of VIA is determined by the controllable pseudo-resistor VPR.

[0046] The specific implementation of APGA is as follows: Figure 3 As shown: Includes a fully differential operational amplifier (OP), a pair of R-2R switched resistor arrays, an input resistor array, and a pair of feedback capacitors (C). F A pair of feedback resistors R F A 2-bit binary to 3-bit thermometer code encoder, TCODER. The APGA input signals include the VIA outputs Vin+, Vin-, and a 6-bit fine gain adjustment signal FGAIN<5:0>.

[0047] A pair of R-2R switch resistor arrays includes 8 pairs of resistors R1, R2, R3, R4, R5, R6, R7, and R8, and 4 pairs of single-pole double-throw switches S1, S2, S3, and S4. The 2R resistors of the pair of R-2R switch resistor arrays are connected in a one-to-one correspondence, where the least significant pair of 2R resistors is directly connected, and the other 4 pairs of 2R resistors are connected through the 4 pairs of single-pole double-throw switches. R1 and R2 are connected to one end of R6, R3 and R4 are connected to the connection points of R6 and R7, and R7 and R8, respectively, and R5 is connected to the other end of R8, and also serves as the output of the R-2R switch resistor array.

[0048] The input resistor array includes 4 pairs of resistors R IN0 R IN1 R IN2 R IN3 and 3 pairs of switches S5, S6, and S7. Among them, R... IN1 R IN2 and R IN3 The resistance values ​​are the same, R IN0 The resistance value is R IN1 4 times, R F The value is R IN1 8 times; R IN1 R IN2 and R IN3 Switches S5, S6, and S7 are connected in series one by one, and then connected to R. IN0 They are connected in parallel; one end of the parallel switch is connected to the input of the OP, and the other end serves as the input of the entire APGA, and is connected in parallel to the R-2R switch resistor array.

[0049] A pair of C F and R F They are connected across the positive input and negative output terminals of the OP, and the negative input and positive output terminals, respectively; the negative and positive output terminals of the OP serve as the positive and negative output terminals of the entire circuit, corresponding to the output signals Vout+ and Vout-.

[0050] The fine gain adjustment signal FGAIN<5:0> is divided into two segments: the lower 4 bits FGAIN<0:3> and the higher 2 bits FGAIN<5:4>. The lower 4 bits FGAIN<0:3> are connected to the control signals of S1, S2, S3, and S4, while the higher 2 bits FGAIN<5:4> serve as the input signal for TCODER. The output of TCODER is the signal TESL<2:0>, which is connected to the control signals of S5, S6, and S7, respectively.

[0051] The negative output terminal of APGA is connected to Vout+, and the positive output terminal is also connected to Vout+; the gain adjustment terminal CGAIN is connected to APGA.

[0052] The APGA implementation allows for gain adjustment from 1 to 16.75 times, in 0.25-fold increments. The APGA adjustment bit FGAIN, a 6-bit design, finely adjusts the overall PGA. R1, R2, R3, R4, R5, R6, R7, R8, and S1, S2, S3, S4 form an R-2R array, where the values ​​of R6, R7, and R8 are R, and the values ​​of R1, R2, R3, R4, and R5 are 2R. IN0 R IN1 R IN2 R IN3 Together with S5, S6, and S7, they form a parallel switching resistor array, R IN0 The value is 4R, R IN1 R IN2 R IN3 The value is R, R F The value is 8R.

[0053] When FGAIN<5:0>=6'b000000, all switches are open, and APGA obtains a minimum gain of 1; when FGAIN<5:0>=6'b001111, S1, S2, S3, and S4 are closed, the R-2R array is closed, and APGA obtains a gain of 4.75, with a gain step of 0.25; when FGAIN<5:0>=6'b111111, all switches are closed, and APGA obtains a maximum gain of 16.75.

[0054] The controllable pseudo-resistance VPR in the embodiment is as follows: Figure 4 As shown, it includes four PMOS transistors M1, M2, M3, and M4, with input / output terminals VA and VB, and a control terminal VC. Terminal VA is connected to the source of M1 and the drain of M3; the drain of M1 is connected to the source of M2, the source of M3 is connected to the drain of M4, and the drains of M2 and the sources of M4 are connected to terminal VB; the control terminal VC is connected to the gates of M1, M2, M3, and M4 and the substrate.

[0055] Unlike the fixed-value pseudo-resistor of the traditional CCIA structure, this invention uses a voltage-controlled variable pseudo-resistor VPR. The control voltage is provided by an m-bit DAC, and the DAC output signal is input through a buffer. The control voltage output range is from VCM to VDD, and no other reference voltage is required. The variable bandwidth of the VIA is achieved by changing the resistance of the variable pseudo-resistor VPR.

[0056] VPR achieves wide-range and high-linearity bandwidth control. Traditional voltage-controlled pseudo-resistors typically include VPRs with the gate connected to the control voltage and VPRs with the substrate connected to the control voltage. The first type has a bandwidth control range of several kHz to 20 kHz, meeting the requirements for high-frequency signals such as those from MEMS, but its filtering effect on high-frequency noise is poor for low-frequency biological signals, failing to adequately meet the needs of multimodal applications. For VPRs with only the substrate connected to the control voltage, the bandwidth control range is from tens of Hz to less than 10 kHz, meeting the frequency requirements of low-frequency biological signals, but its bandwidth is insufficient for MEMS sensor signals with frequencies exceeding 10 kHz, leading to a decrease in signal-to-noise ratio and dynamic range, and even signal distortion, similarly failing to adequately meet the needs of multimodal applications. Therefore, the VPR of this invention connects the control signal to both the substrate and gate of the MOS transistor simultaneously. In this case, its bandwidth control range can meet a wide range from tens of Hz to greater than 20 kHz, better adapting to the needs from low-frequency bioelectrical signals to mid-frequency MEMS signals, and achieving low noise and high linearity.

[0057] Furthermore, the transmission signal-to-noise ratio of traditional pseudo-resistors is unsatisfactory when processing signals with large amplitudes. This is primarily because changes in the output voltage cause voltage variations at one end of the pseudo-resistor, further leading to changes in the pseudo-resistor's resistance value. This is particularly noticeable when the output signal is of different polarities. To address this issue, this invention, VPR, employs two PMOS transistors with opposite connection configurations. When the output signal is of different polarities, the two pseudo-resistors operate symmetrically, thereby achieving a higher transmission signal-to-noise ratio. For example... Figure 5 As shown, when the control bit VBW<6:0> of the 6-bit DAC changes from 6'b010101 to 6'b110111, the control voltage VC changes from 1.2V to 1.7V, and the bandwidth of this invention changes from 85Hz to 20kHz.

[0058] like Figure 6 The figure shows a multimodal dynamic simulation diagram of the high-precision simulation front-end of the embodiment. As can be seen from the figure, the SNR is 102dB, which is a relatively high level.

[0059] As can be seen from the above embodiments, this invention adds a switching array and a pseudo-resistor VPR to the input capacitor of a traditional CCIA structure. The control voltage, adjusted by a DAC, is simultaneously applied to the substrate and gate of the pseudo-resistor VPR, enabling bandwidth switching over a wide range from tens of Hz to 20 kHz. Furthermore, the use of two sets of oppositely connected PMOS pseudo-resistors improves the dynamic range and adapts to various PVT conditions. Additionally, by replacing the input resistor in the traditional resistive feedback PGA with a combination of an R-2R resistor array and a parallel resistor array, the area is reduced while maintaining high gain linearity. Furthermore, drawing inspiration from high-precision DAC structures, a thermometer code is used in the high bits of the APGA control bit to reduce gain error. This invention is compatible with both capacitive and voltage signals, enabling multi-mode applications. It achieves digitally adjustable bandwidth while maintaining high dynamic range and adjustment linearity, better adapting to signals of different frequencies.

Claims

1. A multi-modal programmable gain amplifier suitable for high precision analog front-ends, characterized in that: The signal selector MUX, the variable bandwidth instrument amplifier VIA and the accurate programmable gain amplifier APGA; the signal has voltage input signal Vin+ and Vin-, capacitance input signal Cin+ and Cin-, voltage output signal Vout+ and Vout-, selection signal SEL, coarse gain adjustment signal CGAIN, fine gain adjustment signal FGAIN and bandwidth control signal VBW; The positive output end of the signal selector MUX is connected with the positive input end of the variable bandwidth instrument amplifier VIA, the negative output end of the signal selector MUX is connected with the negative input end of the variable bandwidth instrument amplifier VIA, the two voltage input ends of the signal selector MUX are connected with voltage input signal Vin+ and Vin- respectively, the two capacitance input ends of the signal selector MUX are connected with capacitance input signal Cin+ and Cin- respectively, and the signal selector MUX selects the input signal of the variable bandwidth instrument amplifier VIA as a voltage signal or a variable capacitance signal through the selection signal SEL. The variable bandwidth instrumentation amplifier VIA includes a fully differential operational amplifier OP1, n+2 pairs of capacitors C IN0 , C IN1 , C IN2 … C INn and C F1 , n pairs of switches S 11 , S 12 … S 1n , an m-bit DAC, a buffer Buffer, and a pair of variable pseudo-resistors VPR; Capacitor C in the first group of capacitors IN1 , C IN2 … C INn In turn one by one corresponding series switch S 11 , S 12 … S 1n , then in parallel with the capacitor C in the first group of capacitors IN0 The one end after parallel is the positive input terminal of the variable bandwidth instrument amplifier VIA, and the other end is connected to the positive input terminal of the full differential operational amplifier OP1; Capacitor C in the second group of capacitors IN0 , C IN1 , C IN2 … C INn The same connection mode is adopted, and the one end after parallel is the negative input terminal of the variable bandwidth instrument amplifier VIA, and the other end is connected to the negative input terminal of the full differential operational amplifier OP1; a capacitor C F1 and a variable pseudo-resistor VPR across between the positive input and the negative output of the fully differential operational amplifier OP1, another capacitor C F1 and another variable pseudo-resistor VPR across between the negative input and the positive output of the fully differential operational amplifier OP1; the positive output of the fully differential operational amplifier OP1 is connected to the negative input of the accurate programmable gain amplifier APGA as the positive output of the variable bandwidth instrumentation amplifier VIA, and the negative output of the fully differential operational amplifier OP1 is connected to the positive input of the accurate programmable gain amplifier APGA as the negative output of the variable bandwidth instrumentation amplifier VIA; Bandwidth control signal VBW <m-1:0>an input terminal of an m-bit DAC, an output terminal of the m-bit DAC is connected to an input terminal of a buffer Buffer, and an output terminal of the buffer Buffer is connected to control terminals VC of a pair of variable pseudo resistors VPR respectively; a coarse gain adjusting signal CGAIN <n-1:0>The control terminals of n pairs of switches S 11 , S 12 ,..., S 1n ; Wherein: the variable pseudo-resistor VPR includes four PMOS transistors M1, M2, M3 and M4, an input end VA, an output end VB and a control end VC; the input end VA is connected with the source of the PMOS transistor M1 and the drain of the PMOS transistor M3; the drain of the PMOS transistor M1 is connected with the source of the PMOS transistor M2, the source of the PMOS transistor M3 is connected with the drain of the PMOS transistor M4, and the drain of the PMOS transistor M2 and the source of the PMOS transistor M4 are connected with the output end VB; the control end VC is connected with the gate and substrate of the PMOS transistors M1, M2, M3 and M4; the control voltage of the variable pseudo-resistor VPR is provided by the m-bit DAC, the DAC output signal is input through the buffer, the control voltage output range is VCM to VDD, and no other reference voltage is needed; the variable bandwidth of the variable bandwidth instrument amplifier VIA is realized by changing the resistance of the variable pseudo-resistor VPR. The accurate programmable gain amplifier APGA includes a fully differential operational amplifier OP2, a pair of R-2R switched resistor arrays, an input resistor array, a pair of feedback capacitors C F2 , a pair of feedback resistors R F , a 2-bit to 3-bit thermometer code encoder TCODER; the signal input to the accurate programmable gain amplifier APGA is the signal output by the variable bandwidth instrumentation amplifier VIA and a 6-bit fine gain adjustment signal FGAIN<5:0>; A pair of R-2R switch resistor arrays include eight pairs of resistors R1, R2, R3, R4, R5, R6, R7 and R8 and four pairs of single-pole double-throw switches S1, S2, S3 and S4; the 2R resistors of the pair of R-2R switch resistor arrays are connected in a one-to-one corresponding manner, wherein the lowest pair of 2R resistors are directly connected, and the other four pairs of 2R resistors are connected through the four pairs of single-pole double-throw switches; The input resistance array includes 4 pairs of resistors R IN0 , R IN1 , R IN2 , R IN3 and 3 pairs of switches S5, S6, S7; wherein R IN1 , R IN2 and R IN3 have the same resistance, R IN0 has a resistance of 4 times R IN1 , the feedback resistor R F has a value of 8 times R IN1 ; R IN1 , R IN2 and R IN3 are respectively one-to-one corresponding to switches S5, S6 and S7 in series, and then are connected in parallel with R IN0 ; wherein the first group of input resistance array includes a group of resistors R IN0 , R IN1 , R IN2 , R IN3 and a group of switches S5, S6, S7, and the second group of input resistance array includes another group of resistors R IN0 , R IN1 , R IN2 , R IN3 and another group of switches S5, S6, S7; the first group of input resistance array is connected at one end to the positive input terminal of the full differential operational amplifier OP2, and at the other end to the positive input terminal of the entire precise programmable gain amplifier APGA, and is connected to a group of single-pole double-throw switches S1, S2, S3, S4 of the R-2R switch resistance array; the second group of input resistance array is connected at one end to the negative input terminal of the full differential operational amplifier OP2, and at the other end to the negative input terminal of the entire precise programmable gain amplifier APGA, and is connected to another group of single-pole double-throw switches S1, S2, S3, S4 of the R-2R switch resistance array; a feedback capacitor C F2 and a feedback resistor R F across the positive input and the negative output of the fully differential operational amplifier OP2, another feedback capacitor C F2 and another feedback resistor R F across the negative input and the positive output of the fully differential operational amplifier OP2; the negative output of the fully differential operational amplifier OP2 as the positive output of the entire circuit, corresponding to the voltage output signal Vout+; the positive output of the fully differential operational amplifier OP2 as the negative output of the entire circuit, corresponding to the voltage output signal Vout-. The fine gain adjustment signal FGAIN<5:0> is divided into two parts, low 4 bits FGAIN<0:3> and high 2 bits FGAIN<5:4>; the low 4 bits FGAIN<0:3> are connected with the control signals of the single-pole double-throw switches S1, S2, S3 and S4, and the high 2 bits FGAIN<5:4> are used as the input signals of the TCODER; the output end of the TCODER is the signal TESL<2:0>, which is connected with the control signals of the switches S5, S6 and S7.

2. The multi-modal programmable gain amplifier suitable for high-precision analog front end according to claim 1, wherein: The variable bandwidth instrument amplifier VIA amplifies a tiny signal of 10uV level or a changeable capacitance, adopts a capacitance coupling feedback structure CCIA, changes the closing and opening of switches through a control signal CGAIN to control the size of an input capacitance C IN , further changes the gain size determined by the capacitance feedback, and realizes variable gain; wherein a feedback capacitance C F1 has a capacitance value C, a minimum input capacitance C IN0 has a value of 72C, C IN0 , C IN1 , C IN2 … C INn have a ratio of 1:1:2:4:…:2 n , and there are 2 n+1 gears; when all the switches are opened, a minimum gain of 72 times is obtained, when all the switches are closed, a maximum gain of 72*2 n+1 times is obtained, and the gain step is 72 times; the static working point of the variable bandwidth instrument amplifier VIA is determined by a variable pseudo-resistance VPR.

3. The multi-mode programmable gain amplifier suitable for high-precision analog front end of claim 1, wherein: the accurate programmable gain amplifier APGA realizes gain adjustment of 1-16.75 times, wherein 0.25 times is realized by step based on R-2R switch resistance and parallel resistance array; 6-bit FGAIN is fine adjustment of the overall PGA to realize high linearity of gain adjustment, and R-2R and thermometer code combination form is adopted, high 2-bit FGAIN <5:4> is converted into thermometer code TSEL <2:0> by a thermometer code converter to control switching of the lower parallel resistance array; and low 4-bit FGAIN <3:0> directly controls switching of the upper R-2R resistance array. ​

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