Three-dimensional memory and preparation method thereof

Abstract

The present disclosure relates to a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes: a memory array structure and a peripheral structure. The memory array structure includes a plurality of isolation layers and a plurality of semiconductor layers alternately stacked. The peripheral structure is arranged on the peripheral side of the memory array structure and includes at least one stepped structure and a plurality of first bit lines and a plurality of second bit lines. The stepped structure includes a first step group extending along a first direction and a second step group extending along a second direction. The first step group includes a first conductive step, and the second step group includes a second conductive step; each first conductive step and each second conductive step is respectively connected to a semiconductor layer of a different layer. The first bit line is arranged on the upper surface corresponding to the first conductive step, and the second bit line is arranged on the upper surface corresponding to the second conductive step. The three-dimensional memory and the method for manufacturing the same are conducive to further improving the storage density and storage capacity of the three-dimensional memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. A memory cell typically includes a transistor and a capacitor, wherein the first electrode (e.g., the drain) of the transistor is electrically connected to the capacitor, the second electrode (e.g., the source) of the transistor is electrically connected to the bit line, and the control electrode (e.g., the gate) of the transistor is electrically connected to the word line. Furthermore, the control electrodes of the transistors in a row of memory cells can be electrically connected to a word line, and the second electrodes of the transistors in a column of memory cells can be electrically connected to a bit line.

[0003] As the demand for memory capacity continues to increase, memory cells are being arranged in three dimensions. For example, by continuously increasing the number of stacked layers of memory cells arranged in an array, a three-dimensional memory can be constructed, thereby increasing the storage density per unit area.

[0004] However, as the number of stacked memory cells increases, the number of bit lines, word lines, and supporting contact structures electrically connected to each memory cell also increases, which tends to occupy more area within the 3D memory and limit further increases in storage density and capacity. Therefore, improving the structure of 3D memory to further increase storage density and capacity is a pressing issue. Summary of the Invention

[0005] Based on this, embodiments of the present disclosure provide a three-dimensional memory and a method for manufacturing the same, so as to further improve the storage density and storage capacity of the three-dimensional memory.

[0006] On the one hand, some embodiments of the present disclosure provide a three-dimensional memory, comprising: a memory array structure and a peripheral structure. The memory array structure comprises: a plurality of isolation layers and a plurality of semiconductor layers alternately stacked. The peripheral structure is arranged on the peripheral side of the memory array structure, and the peripheral structure comprises: at least one stepped structure, a plurality of first bit lines, and a plurality of second bit lines. The stepped structure is arranged at a corner of the memory array structure, and comprises: a first step group extending along a first direction, and a second step group extending along a second direction; wherein the first direction and the second direction intersect. The first step group comprises a plurality of first conductive steps, and the second step group comprises a plurality of second conductive steps; each first conductive step and each second conductive step is respectively connected to a semiconductor layer of a different layer. A plurality of first bit lines are respectively arranged on the upper surface of the corresponding first conductive step. The first line extends in a direction perpendicular to the upper surface of the first conductive step. A plurality of second bit lines are respectively arranged on the upper surface of the corresponding second conductive step. The second bit lines extend in a direction perpendicular to the upper surface of the second conductive step.

[0007] In some embodiments, the first step group is located above the second step group; wherein the plurality of first bit lines are linearly arranged along the first direction; and / or the plurality of second bit lines are linearly arranged along the second direction.

[0008] In some embodiments, the number of second bit lines is greater than the number of first bit lines.

[0009] In some embodiments, the first direction and the second direction are orthogonal. Each first bit line and each second bit line are arranged in an L shape, wherein each first bit line is arranged as a short side of the L shape along the first direction, and each second bit line is arranged as a long side of the L shape along the second direction.

[0010] In some embodiments, the second bit line is located on a side of the first bit line facing away from the memory array structure.

[0011] In some embodiments, each first bit line is arranged in a direction away from the memory array structure; and each second bit line is arranged in a direction away from the first bit line.

[0012] In some embodiments, the distances between each second bit line and the memory array structure are equal.

[0013] In some embodiments, the first step group is located above the second step group; wherein the corner edges of the semiconductor layers corresponding to each first conductive step include arc-shaped edges; the center of curvature of the arc-shaped edges is located outside the semiconductor layer, and the curvature radius of the arc-shaped edges in multiple semiconductor layers gradually increases along the stacking direction of the semiconductor layers.

[0014] In some embodiments, a surface of each first bit line facing away from the corresponding first conductive step and a surface of each second bit line facing away from the corresponding second conductive step are located in the same plane.

[0015] In some embodiments, the three-dimensional memory further includes an insulating layer covering the stepped structure, wherein the first bit line and the second bit line both penetrate the insulating layer, and a surface of the first bit line facing away from the corresponding first conductive step and a surface of the second bit line facing away from the corresponding second conductive step are both flush with a surface of the insulating layer facing away from the stepped structure.

[0016] In some embodiments, the first conductive step and the second conductive step are respectively provided in the same layer and made of the same material as the corresponding semiconductor layer.

[0017] In some embodiments, the stepped structure further includes insulating steps disposed between adjacent first conductive steps and between adjacent second conductive steps, wherein the insulating steps are disposed in the same layer and made of the same material as the corresponding isolation layer.

[0018] On the other hand, according to some embodiments, the present disclosure provides a method for preparing a three-dimensional memory, comprising:

[0019] A substrate is provided, and isolation material layers and semiconductor material layers are alternately stacked on one side of the substrate to form a stacked structure; the stacked structure has a memory array area and a peripheral area arranged around the memory array area;

[0020] The patterned stacked structure is located in a portion of the peripheral region to form at least one stepped structure; the stepped structure is located at a corner of the memory array region, and the stepped structure includes a first step group and a second step group formed after patterning the semiconductor material layers; wherein the first step group extends along a first direction and includes a plurality of first conductive steps; the second step group extends along a second direction and includes a plurality of second conductive steps; and the first direction and the second direction intersect.

[0021] A first bit line is formed on the upper surface of each first conductive step, and a second bit line is formed on the upper surface of each second conductive step; wherein the first bit line extends in a direction perpendicular to the upper surface of the first conductive step; and the second bit line extends in a direction perpendicular to the upper surface of the second conductive step.

[0022] The embodiments of the present disclosure may or may have at least the following advantages:

[0023] In the disclosed embodiments, a stepped structure is provided in the peripheral region at the corners of a memory array structure, comprising a first step group extending in a first direction and a second step group extending in a second direction. A first bit line extending perpendicularly to the upper surface of each first conductive step within the first step group is formed, while a second bit line extending perpendicularly to the upper surface of each second conductive step within the second step group is formed. The first and second bit lines are connected to the semiconductor layer connected to the conductive step via their respective conductive steps. This not only allows any semiconductor layer to be connected to a corresponding bit line via the connected conductive steps, thereby reducing the total number of bit lines in the three-dimensional memory, but also effectively reduces the area occupied by the stepped structure by arranging the first and second bit lines in different directions, thereby increasing the plate area of ​​the capacitor within the memory array region and thereby effectively improving the storage density and storage capacity of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic structural diagram of a three-dimensional memory provided in some embodiments;

[0026] Figure 2 A schematic diagram illustrating the distribution of first and second bit lines in a three-dimensional memory provided in some embodiments;

[0027] Figure 3 A schematic cross-sectional view of a local area in a three-dimensional memory provided in some embodiments;

[0028] Figure 4 A flowchart of a method for preparing a three-dimensional memory provided in some embodiments;

[0029] Figure 5 A schematic structural diagram of a structure obtained after forming a stacked structure provided in some embodiments;

[0030] Figure 6 is a schematic diagram of a structure obtained after forming a first mask layer provided in some embodiments;

[0031] Figure 7 A schematic diagram of a structure obtained after forming a first isolation trench and a second isolation trench provided in some embodiments;

[0032] Figure 8A schematic diagram of a structure obtained after forming an isolation layer provided in some embodiments;

[0033] Figure 9 A schematic diagram of a structure obtained after forming a first isolation structure and a second isolation structure provided in some embodiments;

[0034] Figure 10 is a schematic diagram of a structure obtained after forming a second mask layer provided in some embodiments;

[0035] Figure 11 A schematic diagram of a structure obtained after forming a word line trench provided in some embodiments;

[0036] Figure 12 A schematic diagram of a structure obtained after forming a gate dielectric layer provided in some embodiments;

[0037] Figure 13 A schematic diagram of a structure obtained after forming a word line material layer provided in some embodiments;

[0038] Figure 14 A schematic diagram of a structure obtained after forming a word line provided in some embodiments;

[0039] Figure 15 is a schematic diagram of a structure obtained after forming a third mask layer provided in some embodiments;

[0040] Figure 16 A schematic diagram of a structure obtained after forming an initial first conductive step provided in some embodiments;

[0041] Figure 17 A schematic diagram of a structure obtained after forming a stepped structure provided in some embodiments;

[0042] Figure 18 A schematic diagram of a structure obtained after forming a first insulating layer is provided in some embodiments;

[0043] Figure 19 A schematic diagram of a structure obtained after forming an etching groove provided in some embodiments;

[0044] Figure 20 A schematic diagram of a structure obtained after forming a capacitor receiving groove provided in some embodiments;

[0045] Figure 21 A schematic diagram of a structure obtained after forming a capacitor provided in some embodiments;

[0046] Figure 22 A schematic diagram of a structure obtained after forming a first through hole and a second through hole provided in some embodiments;

[0047] Figure 23 A schematic diagram of a structure obtained after forming a first bit line and a second bit line is provided in some embodiments.

[0048] Description of reference numerals:

[0049] 1-substrate, R1-memory array region, R2-peripheral region, 2-memory array structure, L-stacked structure, L1-isolation layer, L10-isolation material layer, L2-semiconductor layer, L20-semiconductor material layer, O-virtual center line, 21A-first strip structure, 21B-second strip structure, 22-gate dielectric layer, P-channel region, C-capacitor, 23-first electrode layer, 24-dielectric layer, 25-second electrode layer, C1-first capacitor, C2-second capacitor, 3-peripheral structure, S-step structure, S1-first step group, 310-initial first conductive step, 320-initial first insulating step, 31A-first conductive step, 32 A-first insulating step, S2-second step group, 31B-second conductive step, 32B-second insulating step, 4-insulating layer, 41-first insulating layer, 42-second insulating layer, 50-isolation layer, 51-first isolation structure, 52-second isolation structure, 60-word line material layer, BL1-first bit line, BL2-second bit line, WL-word line, H1-first through hole, H2-second through hole, Gw-word line groove, Gk-etching groove, Gc-capacitor accommodating groove, G1-first isolation groove, G2-second isolation groove, Y1-first mask layer, Y2-second mask layer, Y3-third mask layer, Y4-fourth mask layer, Y5-fifth mask layer. DETAILED DESCRIPTION

[0050] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0052] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0053] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0055] The present disclosure provides a three-dimensional memory for further improving the storage density and storage capacity of the three-dimensional memory. Figure 1 、 Figure 2 and Figure 3 The three-dimensional memory includes: a memory array structure 2 and a peripheral structure 3 located on a substrate 1. The substrate 1 has a memory array region R1 and a peripheral region R2 surrounding the memory array region R1. The memory array structure 2 is located in the memory array region R1, and the peripheral structure 3 is located in the peripheral region R2. It can be understood that for the convenience of illustrating the internal structures of the memory array structure 2 and the peripheral structure 3, Figure 3 The insulating layers (eg, the first insulating layer 41 and the second insulating layer 42) shown in FIG. Figure 1 to express in .

[0056] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0057] For example, Figure 2 and Figure 3 As shown in FIG, the memory array structure 2 includes: a plurality of isolation layers L1 and a plurality of semiconductor layers L2 that are alternately stacked.

[0058] In some examples, the material of the isolation layer L1 can be one or a combination of insulating materials such as nitride, oxide, or oxynitride. For example, the isolation layer L1 is a silicon nitride layer.

[0059] In some examples, the semiconductor layer L2 includes, but is not limited to, a polysilicon (Poly) layer.

[0060] In some embodiments, the isolation layer L1 and the semiconductor layer L2 are alternately stacked, and may start from the isolation layer L1 and end with the semiconductor layer L2, or start from the isolation layer L1 and end with the isolation layer L1, or start from the semiconductor layer L2 and end with the isolation layer L1, or start from the semiconductor layer L2 and end with the semiconductor layer L2. In addition, the number of layers of the semiconductor layer L2 can be selected and set according to the product requirements and preparation process of the semiconductor structure. In some of the following embodiments, the storage array structure 2 starts from the isolation layer L1 and ends with the isolation layer L1 as an example for detailed description. In addition, the number of layers of the isolation layer L1 and the semiconductor layer L2 shown in the various figures of the present disclosure is only for schematic expression, and is not a specific limitation on the semiconductor structure.

[0061] For example, Figure 1 As shown in FIG, a peripheral structure 3 is disposed on the periphery of the memory array structure 2. The peripheral structure 3 includes at least one stepped structure S and a plurality of first bit lines BL1 and a plurality of second bit lines BL2. The stepped structure S is disposed at a corner of the memory array structure 2 and includes a first step group S1 extending along a first direction (e.g., the X direction) and a second step group S2 extending along a second direction (e.g., the Y direction). The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) intersect, for example, are orthogonal.

[0062] For example, the number of the first step group S1 and the second step group S2 can be one or more.

[0063] In some examples, the number of both the first step group S1 and the second step group S2 is plural. Moreover, in the same stair structure S, the plurality of first step groups S1 can be sequentially arranged along the second direction (e.g., the Y direction), and the plurality of second step groups S2 can be sequentially arranged along the first direction (e.g., the X direction).

[0064] For example, please see Figure 1 The first step group S1 includes a plurality of first conductive steps 31A, and the second step group S2 includes a plurality of second conductive steps 32A. Each first conductive step 31A and each second conductive step 32A is connected to a different semiconductor layer L2. A plurality of first bit lines BL1 are disposed on the upper surface of each first conductive step 31A. The first bit lines BL1 extend in a direction perpendicular to the upper surface of the first conductive step 31A (e.g., the Z direction). A plurality of second bit lines BL2 are disposed on the upper surface of each second conductive step 32A. The second bit lines BL2 extend in a direction perpendicular to the upper surface of the second conductive step 32A (e.g., the Z direction).

[0065] For example, the first bit line BL1 and the second bit line BL2 both include, but are not limited to, a columnar structure, such as a circular column, a rectangular column, a prism, or a special-shaped column.

[0066] For example, the materials of the first bit line BL1 and the second bit line BL2 include but are not limited to metal, such as tungsten or copper.

[0067] For example, a first barrier layer ( Figure 1 and Figure 3 (not shown in the figure). In addition, the first barrier layer also extends to cover the entire sidewall of the corresponding bit line.

[0068] Illustratively, the first barrier layer includes, but is not limited to, titanium nitride.

[0069] In some examples, such as Figure 3As shown in FIG, each first conductive step 31A in the same first step group S1 and each second conductive step 31B in the same second step group S2 are connected to different semiconductor layers L2. Furthermore, each first conductive step 31A and each second conductive step 31B are provided in the same layer and material as the corresponding semiconductor layer L2. That is, the conductive steps connected to the same semiconductor layer L2 and the semiconductor layer L2 can be different regions of the same semiconductor material layer, with the same material and the same number of layers. Therefore, the conductive steps connected to the same semiconductor layer L2 can be an integral structure with the semiconductor layer L2.

[0070] It will be appreciated that each first conductive step 31A and each second conductive step 31B is a doped region of a corresponding semiconductor material layer, and the type and concentration of the doping ions can be set as needed to achieve optimal conductivity. Furthermore, the step widths of each first conductive step 31A and each second conductive step 31B in the stepped structure S can be the same or different.

[0071] For example, please see Figure 1 and Figure 3 The stepped structure S also includes insulating steps disposed between adjacent first conductive steps 31A and between adjacent second conductive steps 31B; the insulating steps are disposed in the same layer and material as the corresponding isolation layer. For example, the multiple insulating steps include a first insulating step 32A disposed adjacent to the first conductive step 31A within the first step group S1, and a second insulating step 32B disposed adjacent to the second conductive step 31B within the second step group S2. Furthermore, each first insulating step 32A within the same first step group S1 and each second insulating step 32B within the same second step group S2 are respectively connected to different layers of the isolation layer L1. In this way, the insulating steps corresponding to the same isolation layer L1 form an integral structure with the isolation layer L1. That is, the insulating steps corresponding to the same isolation layer L1 and the isolation layer L1 can be different regions of the same isolation material layer, both having the same material and the same number of layers.

[0072] In some examples, such as Figure 1 and Figure 3 As shown in FIG, the outer sidewall of each first conductive step 31A facing away from the semiconductor layer L2 is flush with the outer sidewall of the adjacent first insulating step 32A above it facing away from the isolation layer L1. The outer sidewall of each second conductive step 31B facing away from the semiconductor layer L2 is flush with the outer sidewall of the adjacent second insulating step 32B above it facing away from the isolation layer L1. In this way, any conductive step and its adjacent insulating step above it can be formed through a single etching process.

[0073] For some examples, see Figure 2The outline shapes of the storage array region R1 and the peripheral region R2 include but are not limited to rectangles. The number of the step structures S can be one, two, three, or four, and any step structure S can be located at a corner of one side of the aforementioned rectangle.

[0074] In some embodiments, as Figures 1 to 3 As shown in , the first step group S1 is located above the second step group S2; wherein, multiple first bit lines BL1 are linearly arranged along a first direction (such as X direction); and / or, multiple second bit lines BL2 are linearly arranged along a second direction (such as Y direction).

[0075] In some embodiments, please combine Figures 1 to 3 It is understood that the number of second bit lines BL2 is the same as the number of first bit lines BL1, the number of second bit lines BL2 is greater than the number of first bit lines BL1, or the number of second bit lines BL2 is less than the number of first bit lines BL1, which are all allowed.

[0076] For some examples, see Figure 2 , the number of the second bit lines BL2 is greater than the number of the first bit lines BL1.

[0077] For some examples, see Figure 2 The first direction (e.g., X direction) and the second direction (e.g., Y direction) are orthogonal. Each first bit line BL1 and each second bit line BL2 are arranged in an L-shape; wherein each first bit line BL1 is arranged along the first direction (e.g., X direction) as the short side of the L-shape, and each second bit line BL2 is arranged along the second direction (e.g., Y direction) as the long side of the L-shape.

[0078] For some examples, see Figure 2 The second bit line BL2 is located on a side of the first bit line BL1 away from the memory array structure 2 .

[0079] For some examples, see Figure 2 , each first bit line BL1 is arranged in a direction away from the memory array structure 2; each second bit line BL2 is arranged in a direction away from the first bit line BL1.

[0080] In some embodiments, please refer to Figure 2 , the distances between each second bit line BL2 and the memory array structure 2 are equal.

[0081] In some embodiments, please combine Figures 1 to 3It is understood that the first step group S1 is located above the second step group S2; wherein, the corner edge of the semiconductor layer L2 corresponding to each first conductive step 31A includes an arc edge; the center of curvature of the arc edge is located outside the semiconductor layer L2, and the curvature radius of the arc edge in the multiple semiconductor layers L2 gradually increases along the stacking direction of the semiconductor layer L2 (for example, the third direction Z direction).

[0082] In some embodiments, as Figure 1 and Figure 3 As shown in FIG, the first bit lines BL1 and the second bit lines BL2 are located in the same plane away from surfaces of the corresponding conductive steps.

[0083] In some embodiments, see Figure 3 The three-dimensional memory device further includes an insulating layer 4 covering the stepped structure S. The insulating layer 4 can be a single-layer structure or a stacked structure, for example, including a first insulating layer 41 and a second insulating layer 42 stacked together. Each first bit line BL1 and each second bit line BL2 penetrates the insulating layer 4, and the surface of the first bit line BL1 facing away from the corresponding first conductive step 31A and the surface of the second bit line BL2 facing away from the corresponding second conductive step 31B are both flush with the surface of the insulating layer 4 facing away from the stepped structure S, for example, flush with the surface of the second insulating layer 42 facing away from the first insulating layer 41.

[0084] For example, the insulating layer 4 also extends to cover the surface of the memory array structure 2 facing away from the substrate 1 .

[0085] For example, see Figure 3 The memory array structure 2 further includes: a plurality of word lines WL and a plurality of capacitors C. The first insulating layer 41 covers the top isolation layer L1 and the top surfaces of the word lines WL, and the second insulating layer 42 covers the first insulating layer 41 and the top surfaces of the capacitors C.

[0086] In some embodiments, see Figure 3 , each semiconductor layer L2 includes: a plurality of strip structures extending along a first direction (for example, the X direction) and arranged in parallel and spaced apart; wherein the plurality of strip structures in each semiconductor layer L2 are arranged in columns along a third direction (for example, the Z direction) and in rows along a second direction (for example, the Y direction); the first direction (for example, the X direction) and the second direction (for example, the Y direction) are parallel to and intersect with the upper surface of the semiconductor layer L2.

[0087] For example, Figure 3As shown in the figure, the multiple strip structures in any semiconductor layer L2 include: a plurality of first strip structures 21A respectively arranged in a first strip structure group, and a plurality of second strip structures 21B respectively arranged in a second strip structure group; wherein the first strip structure group and the second strip structure group are symmetrical with respect to a virtual center line O as a symmetry axis, and the virtual center line O extends along a second direction (for example, the Y direction), and the second direction (for example, the Y direction) is perpendicular to the first direction (for example, the X direction).

[0088] For example, the word line WL extends in the same direction as the first bit line BL1 and the second bit line BL2, for example, perpendicular to the upper surface of the substrate 1. Furthermore, one word line WL corresponds to one column of strip structures. For example, one column of first strip structures 21A corresponds to one word line WL, and one column of second strip structures 21B corresponds to one word line WL.

[0089] For example, each strip structure (e.g., the first strip structure 21A and the second strip structure 21B) includes a channel region P and contact regions located on both sides of the channel region P, wherein one contact region is connected to the conductive step, and the other contact region is connected to the first electrode layer 23 of the capacitor C. Furthermore, of the two contact regions of any strip structure, one can be a source region, and the other can be a drain region.

[0090] Accordingly, in some examples, the memory array structure 2 further includes: a gate dielectric layer 22 disposed between each strip structure and the corresponding word line WL.

[0091] For example, the gate dielectric layer 22 surrounds the sidewalls of the channel region P of the strip structure. In this way, the strip structure and the gate dielectric layer 22 on the sidewalls thereof can form a transistor.

[0092] For example, the gate dielectric layer 22 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0093] In addition, the above-mentioned word line WL is a gate word line, which can be used as a memory word line WL and also serve as a gate of a corresponding transistor, thereby controlling the turning on and off of the transistor.

[0094] For example, the word line WL includes but is not limited to a columnar structure, such as a circular column, a rectangular column, a prism, or a special-shaped column.

[0095] By way of example, the material of the word line WL includes but is not limited to metal, such as metal tungsten or metal copper.

[0096] For example, a second barrier layer ( Figure 1 and Figure 3 not shown).

[0097] Illustratively, the second barrier layer includes, but is not limited to, titanium nitride.

[0098] In some embodiments, please refer to Figures 1 to 3 The memory array structure 2 further includes: a plurality of capacitors C. The capacitors C are arranged at one end of the corresponding strip structure away from the peripheral structure 3.

[0099] For example, the capacitor C includes a first electrode layer 23 , a dielectric layer 24 and a second electrode layer 25 that are stacked. The first electrode layer 23 is connected to the end surface of the corresponding strip structure that faces away from the peripheral structure 3 .

[0100] Illustratively, the first electrode layer 23 includes but is not limited to a titanium nitride layer.

[0101] Illustratively, the dielectric layer 24 includes, but is not limited to, a HK dielectric layer.

[0102] For example, the second electrode layer 25 includes but is not limited to a metal layer, such as a metal tungsten layer or a metal copper layer.

[0103] For example, a third barrier layer may be further provided between the second electrode layer 25 and the dielectric layer 24. The third barrier layer may be, for example, a titanium nitride layer.

[0104] As described above, each transistor and the connected capacitor C can constitute a memory cell of 1T1C architecture.

[0105] In some examples, the second electrode layers 25 of the plurality of capacitors C are an integral structure. The dielectric layers 24 of the plurality of capacitors C are an integral structure.

[0106] In some embodiments, see Figure 3 The plurality of capacitors C include: a first capacitor C1 respectively disposed at an end of the first strip structure 21A away from the peripheral structure 3 , and a second capacitor C2 respectively disposed at an end of the second strip structure 21B away from the peripheral structure 3 .

[0107] For example, the second electrode layer 25 of each first capacitor C1 and each second capacitor C2 is an integral structure. The dielectric layer 24 of each first capacitor C1 and each second capacitor C2 is an integral structure.

[0108] It is worth mentioning that in some examples, see Figure 1The three-dimensional memory further includes: a first isolation structure 51 located within the memory array region R1, and a second isolation structure 52 located within the peripheral region R2. The first isolation structure 51 extends along a first direction (e.g., the X direction), and multiple first isolation structures 51 can separate multiple strip-shaped structures in a second direction (e.g., the Y direction) to effectively isolate transistors adjacent to each other in the second direction (e.g., the Y direction). The second isolation structure 52 can extend along the contour of the peripheral region R2, for example, along the first direction (e.g., the X direction), to serve as a peripheral isolation structure between the memory array structure 2 and the conductive step 31 within the peripheral region R2.

[0109] Illustratively, the material of the first isolation structure 51 and the second isolation structure 52 is the same as the material of the isolation layer L1 .

[0110] As described above, in the disclosed embodiment, a stepped structure S is provided in the peripheral region R2 at the corner of the memory array structure 2. The stepped structure S includes a first step group S1 extending in a first direction (e.g., the X direction) and a second step group S2 extending in a second direction (e.g., the Y direction). A first bit line BL1 extending perpendicularly to the upper surface of each first conductive step 31A in the first step group S1 is formed, while a second bit line BL2 extending perpendicularly to the upper surface of each second conductive step 31B in the second step group S2 is formed. Furthermore, the first bit line BL1 and the second bit line BL2 are connected to the semiconductor layer L2 connected to the conductive step through their corresponding conductive steps. This not only allows any semiconductor layer L2 to be connected to a corresponding bit line through the connected conductive steps, thereby reducing the total number of bit lines in the three-dimensional memory, but also effectively reduces the area occupied by the stepped structure S by arranging the first and second bit lines BL1 and BL2 in different directions, thereby increasing the plate area of ​​the capacitor C in the memory array region R1 and effectively improving the storage density and storage capacity of the three-dimensional memory.

[0111] This disclosure also provides, according to some embodiments, a method for fabricating a three-dimensional memory device, for use in fabricating the three-dimensional memory devices described in some of the aforementioned embodiments. This method also possesses the technical advantages of the aforementioned three-dimensional memory devices. Furthermore, the aforementioned structure employed in the three-dimensional memory device reduces the difficulty of fabricating the device, thereby improving production efficiency and yield.

[0112] See also Figure 4 The preparation method of the three-dimensional memory includes the following steps.

[0113] S100 , providing a substrate, and alternately stacking isolation material layers and semiconductor material layers on one side of the substrate to form a stacked structure. The stacked structure has a memory array region and a peripheral region disposed around the memory array region.

[0114] S200: Patterning the portion of the stacked structure located in the peripheral area to form at least one stepped structure. The stepped structure is located at a corner of the memory array area and includes a first step group and a second step group formed after patterning the semiconductor material layers. The first step group extends along a first direction and includes a plurality of first conductive steps; the second step group extends along a second direction and includes a plurality of second conductive steps. The first and second directions intersect.

[0115] S300, forming a first bit line on the upper surface of each first conductive step, and forming a second bit line on the upper surface of each second conductive step; wherein the first bit line extends in a direction perpendicular to the upper surface of the first conductive step; and the second bit line extends in a direction perpendicular to the upper surface of the second conductive step.

[0116] In some embodiments, before forming a first bit line on the upper surface of each first conductive step and forming a second bit line on the upper surface of each second conductive step in step S300 , the manufacturing method further includes the following steps.

[0117] S240 , forming an insulating layer covering the stepped structure.

[0118] S280 , forming a plurality of first through holes and a plurality of second through holes in the insulating layer, so as to expose corresponding first conductive steps in the first through holes and expose corresponding second conductive steps in the second through holes.

[0119] Correspondingly, step S300 forms a first bit line on the upper surface of each first conductive step and a second bit line on the upper surface of each second conductive step, including: filling the first through hole with conductive material to form the first bit line; and filling the second through hole with conductive material to form the second bit line.

[0120] In some embodiments, the plurality of first through holes are linearly arranged along a first direction; and / or the plurality of second through holes are linearly arranged along a second direction.

[0121] In some embodiments, the first through holes are arranged in a direction away from the memory array area; and the second through holes are arranged in a direction away from the first through holes.

[0122] In some embodiments, the distances from each second through hole to the memory array region are equal.

[0123] In some embodiments, the portion of the patterned stacked structure located in the peripheral region in step S200 to form at least one stepped structure further includes the following steps.

[0124] S210 , patterning a plurality of semiconductor material layers layer by layer in a first direction along a stacking direction of the semiconductor material layers to form a plurality of initial first conductive steps.

[0125] S220 , patterning each initial first conductive step and the remaining semiconductor material layer layer by layer in the second direction along the stacking direction of the semiconductor material layer to form a plurality of first conductive steps and a plurality of second conductive steps, respectively.

[0126] In some embodiments, the preparation method further includes S230.

[0127] S230, patterning the portion of the stacked structure located at the corner of the storage array area so that the multiple semiconductor material layers form arc-shaped edges at the corner of the storage array area; wherein the center of curvature of the arc-shaped edge is located outside the corresponding semiconductor material layer, and the curvature radius of the arc-shaped edge in the multiple semiconductor material layers gradually increases along the stacking direction of the semiconductor material layers.

[0128] In some embodiments, the first conductive step and the arc-shaped edge corresponding to the same semiconductor material layer are patterned based on the same mask. That is, steps S220 and S230 can be performed simultaneously based on the same mask.

[0129] In some embodiments, before step S200 patterns the stacked structure in the portion of the peripheral region, the preparation method further includes the following steps.

[0130] S110 , patterning the stacked structure in a portion of the memory array region such that each semiconductor material layer is patterned to form a plurality of strip structures. The strip structures extend along a first direction (e.g., the X direction), and the strip structures are arranged in columns along a third direction (e.g., the Z direction) and in rows along a second direction (e.g., the Y direction). The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) are parallel to and intersect the upper surface of the semiconductor layer L2.

[0131] S120 , removing portions of each isolation material layer located in the first target region along a third direction to form a plurality of word line trenches; wherein one word line trench exposes a channel region of a column of strip structures.

[0132] S130 , forming a gate dielectric layer in the word line trench to cover the sidewalls of the channel region.

[0133] S140 , forming a word line covering the gate dielectric layer in the word line trench, wherein the extending direction of the word line is the same as the extending direction of the bit line.

[0134] In some embodiments, the preparation method further includes the following steps.

[0135] S250 , patterning the portion of the stacked structure located in the memory array area to form an etched groove, wherein the etched groove penetrates the stacked structure and extends along the second direction.

[0136] S260: Based on the etched grooves, portions of each semiconductor material layer located within a second target region are removed to form a plurality of capacitor accommodating grooves. The second target region is located between the wordline grooves and the etched grooves. The capacitor accommodating grooves expose end surfaces of the corresponding strip structures on a side adjacent to the etched grooves.

[0137] S270 , forming a capacitor in the capacitor receiving groove.

[0138] In some embodiments, step S270 of forming a capacitor in the capacitor receiving groove includes the following steps.

[0139] S271: forming a first electrode layer covering the inner wall of the capacitor receiving groove, wherein the first electrode layer is connected to the end surface of the corresponding strip structure close to the etching groove.

[0140] S272, forming a dielectric layer at least covering the first electrode layer.

[0141] S273 , forming a second electrode layer covering the dielectric layer and filling the capacitor receiving groove and the etching groove.

[0142] It is understood that the above steps S250 to S270 can be performed before or after step S300. Some embodiments of the present disclosure illustrate the example of steps S250 to S270 being performed before step S300, but the steps can be performed in other execution orders for adaptive adjustment.

[0143] It is understood that, unless otherwise explicitly stated herein, the steps of the above-described method for preparing a three-dimensional memory device are not strictly limited in order and may be performed in other orders. Furthermore, at least some of the steps in the above-described method for preparing a three-dimensional memory device may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be completed at the same time, but may be performed at different times. Their execution order does not necessarily need to be sequential, but may be performed simultaneously, alternately, or in rotation with other steps or at least a portion of their sub-steps or stages.

[0144] In order to more clearly illustrate the preparation method of the three-dimensional memory in some of the above embodiments, the following embodiments are exemplarily combined with Figures 5 to 23 Some implementation methods of the preparation method and some of its steps are given.

[0145] In step S100, refer to Figure 5 A substrate 1 is provided, and isolation material layers L10 and semiconductor material layers L20 are alternately stacked on one side of the substrate 1 to form a stacked structure L. The stacked structure L has a memory array region R1 and a peripheral region R2 disposed around the memory array region R1.

[0146] In step S110, please combine Figure 3 and Figures 6 to 8 It is understood that the patterned stacked structure L is located in a portion of the memory array region R1, so that each semiconductor material layer L20 is patterned to form a plurality of strip structures. The strip structures extend along a first direction (e.g., the X direction), and the strip structures are arranged in columns along a third direction (e.g., the Z direction) and in rows along a second direction (e.g., the Y direction). The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) are parallel to and intersect the upper surface of the semiconductor material layer L20.

[0147] For example, see Figure 6 A first mask layer Y1 is formed on the upper surface of the stack structure L. The first mask layer Y1 has a Figure 7 The mask patterns of the positions where the first isolation trench G1 and the second isolation trench G2 are formed are shown.

[0148] See also Figure 7 Based on the mask pattern in the first mask layer Y1, the stacked structure L is etched until the substrate 1 is exposed. A first isolation trench G1 is formed in the memory array region R1, and a second isolation trench G2 is formed in the peripheral region R2. The first isolation trench G1 extends along a first direction (e.g., the X direction), and multiple first isolation trenches G1 are used to separate multiple strip-shaped structures in a second direction (e.g., the Y direction). The second isolation trench G2 is located in the peripheral region R2 and can extend along the contour of the peripheral region R2, for example, along the first direction (e.g., the X direction).

[0149] See also Figure 8 After removing the first mask layer Y1 , an isolation layer 50 is formed to fill the first isolation trench G1 and the second isolation trench G2 and cover the upper surface of the stacked structure L.

[0150] For example, the material of the isolation layer 50 is the same as that of the isolation material layer L1, including but not limited to insulating materials such as nitride, oxide, or oxynitride. The isolation layer 50 is, for example, a silicon nitride layer or a silicon oxide layer.

[0151] See also Figure 9 The isolation layer 50 above the stacked structure L is removed, forming a first isolation structure 51 located in the first isolation trench G1 and a second isolation structure 52 located in the second isolation trench G2. The first isolation structure 51 can effectively isolate transistors adjacent to each other in the second direction (e.g., the Y direction). The second isolation structure 52 can serve as a peripheral isolation structure for the memory array structure 2 and the conductive steps within the peripheral region R2.

[0152] For example, the isolation layer 50 above the stacked structure L is removed by a grinding process, which includes but is not limited to a chemical mechanical polishing (CMP) process.

[0153] In step S120, please combine Figure 3 and Figures 10 to 12 It is understood that the portion of each isolation material layer L1 located in the first target area is removed along the third direction (eg, Z direction) to form a plurality of word line grooves Gw; wherein one word line groove Gw exposes a column of channel regions P of strip-shaped structures.

[0154] For example, see Figure 10 , a second mask layer Y2 is formed on the upper surface of the stack structure L, and the second mask layer Y2 has a mask pattern for defining the formation position of the word line WL. Figure 11 and Figure 12 Based on the mask pattern in the second mask layer Y2, the stacked structure L is etched along a third direction (e.g., the Z direction) to remove the portion of each isolation material layer L1 within the first target region, thereby forming a wordline trench Gw. Simultaneously, the portion of each semiconductor material layer L20 exposed within the wordline trench Gw corresponds to the channel region P of the stripe structure.

[0155] In step S130, refer to Figure 12 , a gate dielectric layer 22 is formed in the word line trench Gw to cover the sidewalls of the channel region P.

[0156] Illustratively, the gate dielectric layer 22 is formed by a deposition process.

[0157] The deposition processes mentioned here and below include but are not limited to atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, molecular layer deposition (MLD) process, etc.

[0158] In step S140, refer to Figure 13 , forming a word line material layer 60 that fills the word line groove Gw and covers the upper surface of the stack structure L. Figure 14 , the word line material layer 60 above the stack structure L is removed to form a word line WL located in the word line groove Gw.

[0159] For example, before forming the word line material layer 60, a second barrier layer may be formed conformally covering the surface of the gate dielectric layer 22 and the inner wall of the word line trench Gw. In this way, the word line material layer 60 may be formed on the surface of the second barrier layer and fill the word line trench Gw.

[0160] For example, the second barrier layer and the word line material layer 60 may be formed by a deposition process.

[0161] For example, the word line material layer 60 above the stack structure L is removed by a grinding process, which includes but is not limited to a CMP process.

[0162] In step S200, refer to Figures 15 to 17 The patterned stacked structure L is located in a portion of the peripheral region R2 to form at least one stepped structure S. The stepped structure S is located at a corner of the memory array region R1 and includes a first step group S1 and a second step group S2 formed after patterning the semiconductor material layers L20. The first step group S1 extends along a first direction (e.g., the X direction) and includes a plurality of first conductive steps 31A. The second step group S2 extends along a second direction (e.g., the Y direction) and includes a plurality of second conductive steps 31B. The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) intersect.

[0163] For example, the stepped structure S further includes a plurality of insulating steps formed after patterning of each isolation material layer L10, such as a first insulating step 32A disposed adjacent to the first conductive step 31A within the first step group S1, and a second insulating step 32B disposed adjacent to the second conductive step 31B within the second step group S2. The semiconductor material layer L20 and the adjacent isolation material layer L10 thereon can be formed through a single etching process.

[0164] In some embodiments, step S200 may include S210 to S230.

[0165] In step S210, refer to Figure 15 and Figure 16 , along the stacking direction of the semiconductor material layer L20 (for example, the third direction Z direction), multiple semiconductor material layers L20 are patterned layer by layer in a first direction (for example, the X direction) to form multiple initial first conductive steps 310.

[0166] Here, the initial first insulating step 320 adjacent to the initial first conductive step 310 is formed simultaneously with the initial first conductive step 310. Moreover, the number of the initial first conductive steps 310 formed is the same as the maximum number of first conductive steps 31A in the subsequent first step group S1.

[0167] For example, each initial first conductive step 310 can be formed by etching one by one from bottom to top. Accordingly, the aforementioned initial first conductive steps 310 can be formed by etching based on the same mask layer, or can be formed based on different mask layers. Here, each initial first conductive step 310 is formed based on a different mask layer, which can be manifested as: after an initial first conductive step 310 is formed based on a mask layer, the mask layer is removed and a new mask layer is formed to form another initial first conductive step 310. Here, each initial first conductive step 310 is formed by etching based on the same mask layer, which can be manifested as: after an initial first conductive step 310 is formed based on a mask layer, the mask layer is etched to form a new mask pattern to form another initial first conductive step 310 according to the new mask pattern in the mask layer.

[0168] The following is an example of the initial first conductive steps 310 being formed by etching based on the same mask layer.

[0169] For example, see Figure 15 and Figure 16 A third mask layer Y3 is formed on the upper surface of the stacked structure L, and a first mask pattern for defining the first initial first conductive step 310 is formed in the third mask layer Y3. Thus, the stacked structure L can be etched based on the first mask pattern until the target isolation material layer L10 is exposed. Accordingly, after the target isolation material layer L10 is exposed, a second mask pattern for defining the first initial first insulating step 320 and the initial first conductive step 310 can be formed in the third mask layer Y3. Thus, the stacked structure L can be etched based on the second mask pattern to form the first initial first conductive step 310 and the initial first insulating step 320 thereon. This process is repeated in this manner, thereby completing the preparation of each initial first conductive step 310.

[0170] It is understood that the initial thickness of the third mask layer Y3 can be selected and set according to the number of steps of each initial first conductive step 310 to ensure that there is still residual third mask layer Y3 after forming each initial first conductive step 310 without exposing the upper surface of the stacked structure L, for example Figure 16 As shown in .

[0171] In steps S220 and S230, please refer to Figure 17Each initial first conductive step 310 and the remaining semiconductor material layer L20 are patterned layer by layer in a second direction (e.g., the Y direction) along the stacking direction of the semiconductor material layer L20 (e.g., the third direction, the Z direction) to form a plurality of first conductive steps 31A and a plurality of second conductive steps 31B, respectively. Simultaneously, the portion of the stacked structure L located at the corner of the memory array region R1 is patterned so that the plurality of semiconductor material layers L20 form curved edges at the corner of the memory array region R1; wherein the center of curvature of the curved edge is located outside the corresponding semiconductor material layer L20, and the radius of curvature of the curved edge of the plurality of semiconductor material layers L20 gradually increases along the stacking direction of the semiconductor material layer L20 (e.g., the Z direction away from the substrate 1).

[0172] Here, the conductive step formed by the semiconductor material layer L20 with the arc-shaped edge is the first conductive step 31A.

[0173] In addition, it is understood that the first conductive step 31A, the second conductive step 31B and the arc-shaped edge of the semiconductor material layer L20 can be formed by etching the same mask layer or by etching different mask layers, which will not be described in detail here.

[0174] For example, see Figure 17 A fourth mask layer Y4 is formed on the surface of the structure obtained after forming each initial first conductive step 310. Mask patterns for defining the second conductive steps 31B are formed one by one inward from the outside along the second direction (e.g., the Y direction) in the fourth mask layer Y4. Based on the mask patterns, each initial first conductive step 310 and the remaining semiconductor material layer L20 are etched, thereby completing the formation of each first conductive step 31A, each second conductive step 31B, and multiple curved edges of the semiconductor material layer L20.

[0175] For example, Figure 17 As shown in FIG, each first conductive step 31A may constitute a plurality of first step groups S1 arranged in parallel in a second direction (e.g., the Y direction), and each second conductive step 31B may constitute a plurality of second step groups S2 arranged in parallel in a first direction (e.g., the X direction). Furthermore, the number of steps in each first step group S1 may gradually decrease along the first step group S1 from the inside out (e.g., as indicated by arrow T1) in the second direction (e.g., the Y direction). The number of steps in each second step group S2 may gradually increase along the second step group S2 from the inside out (e.g., as indicated by arrow T2) in the first direction (e.g., the X direction).

[0176] It is worth mentioning that in the process of forming the step structure S, if Figure 17 As shown in FIG, the portion of the second isolation structure 52 located in the peripheral region R1 is synchronously stepped.

[0177] In some embodiments, forming an insulating layer covering the stepped structure in step S240 may include S241 and S242 .

[0178] In step S241, refer to Figure 18 After forming the stepped structure S, a first insulating layer 41 is formed to cover the stepped structure S and the memory array region R1.

[0179] Here, each surface of the first insulating layer 41 is flat, which can be used to ensure a flat appearance of the three-dimensional memory.

[0180] In step S250, refer to Figure 19 The patterned stacked structure L is located in the portion of the memory array region R1, forming an etched groove Gk. The etched groove Gk penetrates the stacked structure L and extends along the second direction (eg, the Y direction). Furthermore, the etched groove Gk is formed along the virtual center line O.

[0181] In step S260, refer to Figure 20 Based on the etching groove Gk, the portion of each semiconductor material layer L20 located within the second target area is removed to form multiple capacitor accommodating grooves Gc. The second target area is located between the wordline groove Gw and the etching groove Gk. The capacitor accommodating grooves Gc expose the end surface of the corresponding strip structure near the etching groove Gk.

[0182] Here, after forming the capacitor accommodating groove Gc, the semiconductor material layers L20 remaining in the memory array region R1 of the stacked structure L respectively constitute corresponding semiconductor layers L2 , and the isolation material layers L10 remaining in the memory array region R1 respectively constitute corresponding isolation layers L1 .

[0183] It can be understood that after the first isolation structure 51 is formed, the plurality of first isolation structures 51 can separate the semiconductor material layer L20 in the memory array region R1 into a plurality of strip structures in the second direction (e.g., the Y direction). Based on this, after the etching groove Gk is formed, any semiconductor material layer L20 can be patterned to form a first strip structure group and a second strip structure group that are bilaterally symmetrical with the virtual center line O as the symmetry axis, wherein the first strip structure group includes a plurality of first strip structures 21A arranged in parallel and spaced apart, and the second strip structure group includes a plurality of second strip structures 21B arranged in parallel and spaced apart (which can be combined with the first strip structure group). Figure 3 Accordingly, the plurality of capacitor accommodating grooves Gc formed based on the etched grooves Gk further include: first capacitor accommodating grooves formed on the side of the first strip structure 21A close to the etched grooves Gk, and second capacitor accommodating grooves formed on the side of the second strip structure 21B close to the etched grooves Gk. Furthermore, the first capacitor accommodating grooves correspond one-to-one with the first strip structure 21A, and the second capacitor accommodating grooves correspond one-to-one with the second strip structure 21B.

[0184] In step S270, refer to Figure 21 and Figure 22 , a capacitor is formed in the capacitor receiving groove Gc, for example, a first capacitor C1 is formed in the first capacitor receiving groove, and a second capacitor C2 is formed in the second capacitor receiving groove.

[0185] Illustratively, forming the capacitor C in the capacitor receiving groove Gc includes steps S271 to S273 .

[0186] In step S271 , a first electrode layer 23 is formed to cover the inner wall of the capacitor receiving groove Gc.

[0187] Here, the first electrode layer 23 conformally covers the inner wall of the corresponding capacitor accommodating groove Gc and is connected to the end surface of the corresponding strip structure on the side close to the etched groove Gk. The first electrode layer 23 can be formed using an ALD process. Furthermore, the first electrode layers 23 in adjacent capacitor accommodating grooves Gc in the third direction (e.g., the Z direction) can be insulated by the isolation layer L1, and the first electrode layers 23 in adjacent capacitor accommodating grooves Gc in the second direction (e.g., the Y direction) can be insulated by the first isolation structure 51.

[0188] In step S272 , a dielectric layer 24 is formed to at least cover the first electrode layer 23 .

[0189] Here, if Figure 21 As shown in FIG, the dielectric layer 24 can be formed using an ALD process. The dielectric layer 24 conformally covers the inner surface of the first electrode layer 23 and extends to cover the inner wall of the etched groove Gk. In this way, the dielectric layer 24 in each first capacitor C1 and each second capacitor C2 is an integrated structure.

[0190] In step S273, a second electrode layer 25 is formed to cover the dielectric layer 24 and fill the capacitor receiving groove Gc and the etching groove Gk. In this way, the second electrode layer 25 in each first capacitor C1 and each second capacitor C2 is an integrated structure.

[0191] In some examples, the dielectric layer 24 and the second electrode layer 25 can be obtained by sequentially stacking a dielectric material layer and a second electrode material layer and then grinding and removing the dielectric material layer and the second electrode material layer above the first insulating layer 41 .

[0192] For example, the top surface of the dielectric layer 24 and the top surface of the second electrode layer 25 are both flush with the surface of the first insulating layer 41 facing away from the substrate 1 .

[0193] In addition, in some examples, before forming the second electrode layer 25 , a third barrier layer conformally covering the dielectric layer 24 may be formed first, and then the second electrode layer 25 conformally covering the third barrier layer and filling the capacitor receiving groove may be formed.

[0194] In step S280, refer to Figure 22 A plurality of first through holes H1 and a plurality of second through holes H2 are formed in the insulating layer 4 to expose corresponding first conductive steps 31A in the first through holes H1 and expose corresponding second conductive steps 31B in the second through holes H2.

[0195] Here, both the first through-hole H1 and the second through-hole H2 extend along a third direction (e.g., the Z direction). Furthermore, the plurality of first through-holes H1 in any stepped structure S can be linearly arranged along the extension direction of the first step group S1, for example, along the first direction (X direction). The plurality of second through-holes H2 in any stepped structure S can be linearly arranged along the extension direction of the second step group S2, for example, along the second direction (Y direction).

[0196] For example, the first through hole H1 and the second through hole H2 further extend through adjacent insulating steps above the corresponding conductive steps.

[0197] In some examples, such as Figure 22 As shown in FIG, a second insulating layer 42 is formed covering the first insulating layer 41 and the capacitor C, so that the first insulating layer 41 and the second insulating layer 42 together constitute the aforementioned insulating layer 4. A fifth mask layer Y5 is formed on the upper surface of the second insulating layer 42, and a mask pattern for defining the position where the bit line BL is to be formed is formed in the fifth mask layer Y5. Based on the mask pattern in the fifth mask layer Y5, the insulating layer 4 (including the second insulating layer 42 and the first insulating layer 41) and the corresponding insulating steps are etched until the corresponding conductive steps are exposed, thereby forming each of the first through hole H1 and the second through hole H2.

[0198] In step S300, refer to Figure 23 A conductive material is filled into the first through hole H1 to form a first bit line BL1; and a conductive material is filled into the second through hole H2 to form a second bit line BL2. Each bit line is located on the upper surface of the corresponding conductive step and extends in a third direction (e.g., the Z direction) perpendicular to the upper surface.

[0199] For example, the conductive material is a metal material, such as metal tungsten or metal copper.

[0200] For example, before filling the conductive material, a first barrier layer may be formed to conformally cover the inner walls of each through hole (including the first through hole H1 and the second through hole H2). In this way, the conductive material covers the surface of the first barrier layer and fills the corresponding through hole to form the corresponding bit line.

[0201] For example, the conductive material filling can be performed before removing the fifth mask layer Y5. In this way, the conductive material can be deposited to cover the upper surface of the fifth mask layer Y5. Then, the fifth mask layer Y5 and excess conductive material above the insulating layer 4 can be removed by a grinding process. This ensures that the top surface of each bit line is flush with the upper surface of the insulating layer 4.

[0202] It should be noted that the "one-time etching process" mentioned in some of the above embodiments can be understood as: etching based on the pattern of the same mask layer to form the same pattern; it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.

[0203] In addition, the “etching” mentioned in some of the above embodiments may also be matched with the etching requirements, such as dry etching, wet etching, or a combination of dry etching and wet etching.

[0204] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0205] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A three-dimensional memory, characterized in that: include: A memory array structure comprising: a plurality of isolation layers and a plurality of semiconductor layers stacked alternately; and A peripheral structure is provided on the peripheral side of the storage array structure; the peripheral structure includes: At least one stepped structure is provided at a corner of the memory array structure; the stepped structure comprises: a first step group extending along a first direction, and a second step group extending along a second direction; wherein the first direction and the second direction intersect; the first step group comprises a plurality of first conductive steps, and the second step group comprises a plurality of second conductive steps; each of the first conductive steps and each of the second conductive steps is respectively connected to a different layer of the semiconductor layer; A plurality of first bit lines are respectively disposed on the upper surface corresponding to the first conductive step; the first bit lines extend in a direction perpendicular to the upper surface of the first conductive step; a plurality of second bit lines, each disposed on an upper surface corresponding to the second conductive step; the second bit lines extending in a direction perpendicular to the upper surface of the second conductive step; In which, the first step group is located above the second step group; in which, the corner edge of the semiconductor layer corresponding to each of the first conductive steps includes an arc-shaped edge; the center of curvature of the arc-shaped edge is located outside the semiconductor layer, and the curvature radius of the arc-shaped edge in the multiple semiconductor layers gradually increases along the stacking direction of the semiconductor layer.

2. The three-dimensional memory according to claim 1, wherein: The first step group is located above the second step group; wherein a plurality of the first bit lines are linearly arranged along the first direction; and / or a plurality of the second bit lines are linearly arranged along the second direction.

3. The three-dimensional memory according to claim 1 or 2, characterized in that The number of the second bit lines is greater than the number of the first bit lines.

4. The three-dimensional memory according to claim 3, wherein: The first direction and the second direction are orthogonal; each first bit line and each second bit line are arranged in an L shape; wherein each first bit line is arranged as a short side of the L shape along the first direction; each second bit line is arranged as a long side of the L shape along the second direction.

5. The three-dimensional memory according to claim 4, wherein: The second bit line is located on a side of the first bit line away from the memory array structure.

6. The three-dimensional memory according to claim 1 or 2, characterized in that: Each of the first bit lines is arranged in a direction away from the memory array structure; and each of the second bit lines is arranged in a direction away from the first bit lines.

7. The three-dimensional memory according to claim 6, wherein: The distances between each of the second bit lines and the memory array structure are equal.

8. The three-dimensional memory according to claim 1, wherein: Each of the first bit lines is away from the surface corresponding to the first conductive step, and each of the second bit lines is away from the surface corresponding to the second conductive step, and are located in the same plane; The three-dimensional memory also includes: an insulating layer covering the stepped structure; wherein the first bit line and the second bit line both pass through the insulating layer, and the surface of the first bit line facing away from the corresponding first conductive step and the surface of the second bit line facing away from the corresponding second conductive step are both flush with the surface of the insulating layer facing away from the stepped structure.

9. A method for preparing a three-dimensional memory, characterized in that: include: Providing a substrate, and alternately stacking isolation material layers and semiconductor material layers on one side of the substrate to form a stacked structure; The stacked structure comprises a storage array area and a peripheral area arranged around the storage array area; Patterning a portion of the stacked structure located in the peripheral region to form at least one stepped structure; the stepped structure is located at a corner of the memory array region, and the stepped structure includes a first step group and a second step group formed after each of the semiconductor material layers is patterned; wherein the first step group extends along a first direction and includes a plurality of first conductive steps; the second step group extends along a second direction and includes a plurality of second conductive steps; and the first direction and the second direction intersect; A first bit line is formed on the upper surface of each of the first conductive steps, and a second bit line is formed on the upper surface of each of the second conductive steps; wherein the first bit line extends in a direction perpendicular to the upper surface of the first conductive step; and the second bit line extends in a direction perpendicular to the upper surface of the second conductive step; The step of patterning the portion of the stacked structure located in the peripheral region to form at least one stepped structure comprises: Patterning the plurality of semiconductor material layers layer by layer in the first direction along the stacking direction of the semiconductor material layers to form a plurality of initial first conductive steps; Patterning each of the initial first conductive steps and the remaining semiconductor material layers layer by layer in the second direction along the stacking direction of the semiconductor material layers to form a plurality of first conductive steps and a plurality of second conductive steps respectively; The portion of the stacked structure located at the corner of the storage array area is patterned so that the multiple semiconductor material layers form arc-shaped edges at the corner of the storage array area; wherein the center of curvature of the arc-shaped edge is located outside the corresponding semiconductor material layer, and the curvature radius of the arc-shaped edge in the multiple semiconductor material layers gradually increases along the stacking direction of the semiconductor material layer.

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