Three-dimensional memory and preparation method thereof

Abstract

The present disclosure relates to a three-dimensional memory and a method for preparing the same. The three-dimensional memory comprises: a memory array structure, at least one step structure, and a plurality of bit lines. The memory array structure comprises: a plurality of isolation layers and a plurality of semiconductor layers stacked alternately. The step structure is arranged on one side of the memory array structure, and comprises: a plurality of step groups arranged along a first direction. Each step group extends along a second direction, and adjacent step groups are staggered in the stacking direction of the semiconductor layer; wherein the first direction and the second direction intersect; the step group comprises a plurality of conductive steps, and each conductive step is connected to a corresponding semiconductor layer. A plurality of bit lines are respectively arranged on the upper surface of the corresponding conductive steps. The bit lines extend in a direction perpendicular to the upper surface of the conductive step. The three-dimensional memory and the method for preparing the same are conducive to further improving the storage density and storage capacity of the three-dimensional memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. A memory cell typically includes a transistor and a capacitor, wherein the first electrode (e.g., the drain) of the transistor is electrically connected to the capacitor, the second electrode (e.g., the source) of the transistor is electrically connected to the bit line, and the control electrode (e.g., the gate) of the transistor is electrically connected to the word line. Furthermore, the control electrodes of the transistors in a row of memory cells can be electrically connected to a word line, and the second electrodes of the transistors in a column of memory cells can be electrically connected to a bit line.

[0003] As the demand for memory capacity continues to increase, memory cells are being arranged in three dimensions. For example, by continuously increasing the number of stacked layers of memory cells arranged in an array, a three-dimensional memory can be constructed, thereby increasing the storage density per unit area.

[0004] However, as the number of stacked memory cells increases, the number of bit lines, word lines, and supporting contact structures electrically connected to each memory cell also increases, which tends to occupy more area within the 3D memory and limit further increases in storage density and capacity. Therefore, improving the structure of 3D memory to further increase storage density and capacity is a pressing issue. Summary of the Invention

[0005] Based on this, embodiments of the present disclosure provide a three-dimensional memory and a method for manufacturing the same, so as to further improve the storage density and storage capacity of the three-dimensional memory.

[0006] Some embodiments of the present disclosure provide a three-dimensional memory, comprising: a memory array structure, at least one step structure, and a plurality of bit lines. The memory array structure comprises: a plurality of isolation layers and a plurality of semiconductor layers stacked alternately. The step structure is arranged on one side of the memory array structure, comprising: a plurality of step groups arranged along a first direction. Each step group extends along a second direction, and adjacent step groups are staggered in the stacking direction of the semiconductor layer; wherein the first direction and the second direction intersect; the step group comprises a plurality of conductive steps, and each conductive step is connected to a corresponding semiconductor layer. A plurality of bit lines are respectively arranged on the upper surface of the corresponding conductive steps. The bit lines extend in a direction perpendicular to the upper surface of the conductive steps.

[0007] In some embodiments, conductive steps with the same step number in the plurality of step groups are arranged in rows along the first direction, and the conductive steps in the same row have the same width; the width is the size of the conductive step in the second direction.

[0008] In some embodiments, the conductive steps in the same step group have the same length, where the length is the size of the conductive step in the first direction.

[0009] In some embodiments, the lengths of the conductive steps in different step groups are the same.

[0010] In some embodiments, the multiple step groups include: a central step group and multiple first step groups and multiple second step groups that are symmetrical with respect to the central step group; wherein, the conductive steps with the same serial number in the multiple first step groups extend downward in sequence in a direction away from the central step group, and the conductive steps with the same serial number in the multiple second step groups extend downward in sequence in a direction away from the central step group.

[0011] In some embodiments, any semiconductor layer other than the top semiconductor layer is correspondingly connected to a plurality of conductive steps, and a bit line is provided on the upper surface of at least one conductive step correspondingly connected to any semiconductor layer.

[0012] In some embodiments, the semiconductor layer and the corresponding conductive steps are provided in the same layer and made of the same material.

[0013] In some embodiments, the step group further includes: insulating steps disposed between adjacent conductive steps, wherein the insulating steps are disposed in the same layer and made of the same material as the corresponding isolation layer.

[0014] In some embodiments, conductive steps with the same step number in the plurality of step groups are arranged in rows along a first direction. The plurality of bit lines includes: a plurality of bit line groups; wherein a bit line group includes: at least two bit lines located in the same row. Adjacent bit line groups are staggered in the first direction.

[0015] In some embodiments, the multiple step groups include: a central step group and a plurality of first step groups and a plurality of second step groups that are symmetrical with respect to the central step group; wherein, the multiple bit line groups arranged on the upper surface of the conductive steps in each first step group are linearly arranged along a third direction; the multiple bit line groups arranged on the upper surface of the conductive steps in each second step group are linearly arranged along a fourth direction; and the third direction and the fourth direction intersect with the first direction and the second direction, respectively.

[0016] In some embodiments, the number of the stepped structures is two, and the two stepped structures are symmetrically arranged on two opposite sides of the memory array structure in the second direction with the memory array structure as the center.

[0017] In some embodiments, surfaces of the plurality of bit lines facing away from the corresponding conductive steps are located in the same plane.

[0018] In some embodiments, the three-dimensional memory further comprises: an insulating layer covering the stepped structure; wherein the plurality of bit lines all penetrate the insulating layer, and surfaces of the bit lines facing away from the corresponding conductive steps are flush with a surface of the insulating layer facing away from the stepped structure.

[0019] Some embodiments of the present disclosure further provide a method for preparing a three-dimensional memory, which is used to prepare the three-dimensional memory in some of the above embodiments. The method for preparing the three-dimensional memory includes the following steps.

[0020] A substrate is provided, and isolation material layers and semiconductor material layers are alternately stacked on one side of the substrate to form a stacked structure. The stacked structure has a memory array area and a wiring area arranged on at least one side of the memory array area.

[0021] A patterned stacked structure is located in a portion of the wiring area to form at least one stepped structure. The stepped structure is located on one side of the memory array area and includes multiple step groups arranged along a first direction, each extending along a second direction. The first direction and the second direction intersect, and adjacent step groups are staggered in the stacking direction of the semiconductor layers. The step groups include multiple conductive steps formed by patterning different semiconductor material layers.

[0022] Bit lines are respectively formed on the upper surfaces of the plurality of conductive steps, and the bit lines extend in a direction perpendicular to the upper surfaces of the conductive steps.

[0023] In some embodiments, the patterned stacked structure is located in a portion of the wiring region to form at least one stepped structure, including the following steps.

[0024] The semiconductor material layer of the lower half is retained, and the semiconductor material layer of the upper half is patterned multiple times in the second direction to form a plurality of initial conductive steps.

[0025] Each initial conductive step and the semiconductor material layer in the lower half are patterned multiple times in a first direction to form a plurality of step groups.

[0026] The embodiments of the present disclosure may or may have at least the following advantages:

[0027] In an embodiment of the present disclosure, a staircase structure is provided on at least one side of a memory array structure, such that the staircase structure includes a plurality of step groups arranged along a first direction, each step group including a plurality of conductive steps arranged along a second direction, and each conductive step is connected to a corresponding semiconductor layer. Furthermore, adjacent step groups are staggered in the stacking direction of the semiconductor layers in the memory array structure. This allows for a compact arrangement of the conductive steps in the plurality of step groups in both the first and second directions, thereby facilitating a reduction in the planar area occupied by the staircase structure in the three-dimensional memory. For example, compared to the planar area occupied by the staircase structure in the related art in a three-dimensional memory, the planar area occupied by the staircase structure in the present application can be reduced by half or more. This can correspondingly increase the planar area occupied by the memory array region in the three-dimensional memory, thereby facilitating an increase in the number of memory cells and the plate area of ​​the capacitor within the memory array region, thereby effectively improving the storage density and storage capacity of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic structural diagram of a three-dimensional memory provided in some embodiments;

[0030] Figure 2 A schematic diagram of the distribution of bit lines in a three-dimensional memory provided in some embodiments;

[0031] Figure 3 A schematic structural diagram of a stepped structure provided in some embodiments;

[0032] Figure 4 A schematic diagram of the structure of another three-dimensional memory provided in some embodiments;

[0033] Figure 5 for Figure 4 A schematic cross-sectional view of a three-dimensional memory device taken along the AA direction is shown;

[0034] Figure 6 A flowchart of a method for preparing a three-dimensional memory provided in some embodiments;

[0035] Figure 7 A schematic structural diagram of a structure obtained after forming a stacked structure provided in some embodiments;

[0036] Figure 8is a schematic diagram of a structure obtained after forming a first mask layer provided in some embodiments;

[0037] Figure 9 A schematic diagram of a structure obtained after forming a first isolation trench and a second isolation trench provided in some embodiments;

[0038] Figure 10 A schematic diagram of a structure obtained after forming an isolation layer provided in some embodiments;

[0039] Figure 11 A schematic diagram of a structure obtained after forming a first isolation structure and a second isolation structure provided in some embodiments;

[0040] Figure 12 is a schematic diagram of a structure obtained after forming a second mask layer provided in some embodiments;

[0041] Figure 13 A schematic diagram of a structure obtained after forming a word line trench provided in some embodiments;

[0042] Figure 14 A schematic diagram of a structure obtained after forming a gate dielectric layer provided in some embodiments;

[0043] Figure 15 A schematic diagram of a structure obtained after forming a word line material layer provided in some embodiments;

[0044] Figure 16 A schematic diagram of a structure obtained after forming a word line provided in some embodiments;

[0045] Figure 17 A schematic diagram of a structure obtained after forming a protective layer provided in some embodiments;

[0046] Figure 18 is a schematic diagram of a structure obtained after forming a first lateral mask provided in some embodiments;

[0047] Figure 19 is a schematic diagram of a structure obtained after forming a second lateral mask provided in some embodiments;

[0048] Figure 20 A schematic diagram of a structure obtained after forming initial conductive steps provided in some embodiments;

[0049] Figure 21 A schematic diagram of a structure obtained after forming a first vertical mask and performing a first vertical patterning, provided in some embodiments;

[0050] Figure 22is a schematic diagram of a structure obtained after forming a second vertical mask provided in some embodiments;

[0051] Figure 23 A schematic diagram of a structure obtained after forming a stepped structure provided in some embodiments;

[0052] Figure 24 A schematic diagram of a structure obtained after forming a first insulating layer is provided in some embodiments;

[0053] Figure 25 A schematic diagram of a structure obtained after forming an etching groove provided in some embodiments;

[0054] Figure 26 A schematic diagram of a structure obtained after forming a capacitor receiving groove provided in some embodiments;

[0055] Figure 27 A schematic diagram of a structure obtained after forming a capacitor provided in some embodiments;

[0056] Figure 28 A schematic diagram of a structure obtained after forming a through hole provided in some embodiments;

[0057] Figure 29 FIG. 1 is a schematic diagram of a structure obtained after forming a bit line in some embodiments.

[0058] Description of reference numerals:

[0059] 1-substrate, R1-memory array region, R2-wiring region, 2-memory array structure, L-stacked structure, L1-isolation layer, L10-isolation material layer, L2-semiconductor layer, L20-semiconductor material layer, O-virtual center line, 21A-first strip structure, 21B-second strip structure, 22-gate dielectric layer, P-channel region, C-capacitor, 23-first electrode layer, 24-dielectric layer, 25-second electrode layer, C1-first capacitor, C2-second capacitor, S-step structure, S1-step group, S10-center step group, S11-first step group, S12-second step group, 310-initial conductive step, 320-initial insulating step, 31-conductive step, 32-insulating step Step, 4-insulating layer, 41-first insulating layer, 42-second insulating layer, 50-isolation layer, 51-first isolation structure, 52-second isolation structure, 60-word line material layer, 7-protective layer, B-bit line group, BL-bit line, WL-word line, H-through hole, Gw-word line groove, Gk-etching groove, Gc-capacitor accommodating groove, G1-first isolation groove, G2-second isolation groove, Y1-first mask layer, Y2-second mask layer, Y3-third mask layer, Y41-first horizontal mask, Y42-second horizontal mask, Y4i+1-i+1th horizontal mask, Y51-first vertical mask, Y52-second vertical mask, Y5j+1-j+1th vertical mask, Y6-sixth mask layer. DETAILED DESCRIPTION

[0060] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0062] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0063] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0064] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0065] The present disclosure provides a three-dimensional memory for further improving the storage density and storage capacity of the three-dimensional memory. Figure 1 、 Figure 2 and Figure 3 The three-dimensional memory device includes a memory array structure 2 located on a substrate 1. Substrate 1 includes a memory array region R1 and a wiring region R2 located on at least one side of memory array region R1. For example, wiring region R2 may be provided on both sides of memory array region R1 that are opposite in the X direction, or may be provided only on one side of memory array region R1. Memory array structure 2 is located in memory array region R1.

[0066] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0067] For example, Figure 1 As shown in FIG, the memory array structure 2 includes: a plurality of isolation layers L1 and a plurality of semiconductor layers L2 that are alternately stacked.

[0068] In some examples, the material of the isolation layer L1 can be one or a combination of insulating materials such as nitride, oxide, or oxynitride. For example, the isolation layer L1 is a silicon nitride layer.

[0069] In some examples, the semiconductor layer L2 includes, but is not limited to, a polysilicon (Poly) layer.

[0070] In some embodiments, the isolation layer L1 and the semiconductor layer L2 are alternately stacked, and may start from the isolation layer L1 and end with the semiconductor layer L2, or start from the isolation layer L1 and end with the isolation layer L1, or start from the semiconductor layer L2 and end with the isolation layer L1, or start from the semiconductor layer L2 and end with the semiconductor layer L2. In addition, the number of layers of the semiconductor layer L2 can be selected and set according to the product requirements and preparation process of the semiconductor structure. In some of the following embodiments, the storage array structure 2 starts from the isolation layer L1 and ends with the isolation layer L1 as an example for detailed description. In addition, the number of layers of the isolation layer L1 and the semiconductor layer L2 shown in the various figures of the present disclosure is only for schematic expression, and is not a specific limitation on the semiconductor structure.

[0071] In addition, illustratively, the thickness of each isolation layer L1 is the same, and the thickness of each semiconductor layer L2 is the same. Further, illustratively, the thickness of each isolation layer L1 is the same as the thickness of each semiconductor layer L2.

[0072] In some embodiments, as Figure 1As shown in , the three-dimensional memory further includes: at least one stair structure S and a plurality of bit lines BL. The stair structure S is disposed on one side of the memory array structure 2 and includes: a plurality of step groups arranged along a first direction (e.g., the Y direction). Each step group extends along a second direction (e.g., the X direction), and adjacent step groups are staggered in the stacking direction of the semiconductor layer L2 (e.g., the Z direction). The first direction (e.g., the Y direction) and the second direction (e.g., the X direction) intersect, for example, are orthogonal.

[0073] In some embodiments, as Figure 1 As shown in FIG, wiring regions R2 are provided on opposite sides of the memory array region R1 in the X direction. There are two stepped structures S, which are symmetrically arranged on opposite sides of the memory array structure 2 in the second direction (e.g., the X direction) with the memory array structure 2 as the center. One stepped structure S can be correspondingly arranged in one wiring region R2.

[0074] In some embodiments, see Figure 1 Each step group includes a plurality of conductive steps 31, and each conductive step 31 is connected to a corresponding semiconductor layer L2. A plurality of bit lines BL are disposed on the upper surfaces of corresponding conductive steps 31. The bit lines BL extend in a direction perpendicular to the upper surfaces of the conductive steps 31 (e.g., the Z direction).

[0075] For example, the surfaces of each bit line BL facing away from the corresponding conductive step 31 are located in the same plane.

[0076] For example, the bit line BL includes but is not limited to a columnar structure, such as a circular column, a rectangular column, a prism, or a special-shaped column.

[0077] For example, the material of the bit lines BL includes but is not limited to metal, such as metal tungsten or metal copper.

[0078] For example, a first barrier layer ( Figure 1 Furthermore, the first barrier layer also extends to cover the entire sidewall of the corresponding bit line BL to block the bit line BL and the insulating layer outside the sidewall of the bit line BL ( Figure 1 not shown).

[0079] Illustratively, the first barrier layer includes, but is not limited to, titanium nitride.

[0080] In the disclosed embodiment, a staircase structure S is provided on at least one side of the memory array structure 2, such that the staircase structure S includes multiple step groups arranged along a first direction (e.g., the Y direction), each step group including multiple conductive steps 31 arranged along a second direction (e.g., the X direction), and each conductive step 31 is connected to a corresponding semiconductor layer L2. Furthermore, adjacent step groups are staggered in the stacking direction (e.g., the Z direction) of the semiconductor layer L2. This allows for a compact arrangement of the conductive steps 31 in the multiple step groups in both the first direction (e.g., the Y direction) and the second direction (e.g., the X direction), thereby reducing the planar area occupied by the staircase structure S in the three-dimensional memory. For example, compared to the planar area occupied by staircase structures in three-dimensional memory devices in the related art, the planar area occupied by the staircase structure S in the present application can be reduced by half or more. This can correspondingly increase the planar area occupied by the memory array region R1 in the three-dimensional memory device, thereby facilitating an increase in the number of memory cells and the plate area of ​​the capacitor within the memory array region, effectively improving the storage density and storage capacity of the three-dimensional memory device.

[0081] It can be understood that the number of steps in the stepped structure S will be different depending on the number of stacked semiconductor layers L2. Figure 1 In the figure, the number of stacked layers of the semiconductor layer L2 is 13. Figure 3 The stacking number of semiconductor layers L2 is 12 layers, but the aforementioned number of layers does not constitute a relevant limitation of the present application and is only used to illustrate the multi-layer stacking of semiconductor layers L2. Figure 3 In the figure, each step group is marked with a dotted arrow, and the serial number of each step in any step group is marked with a circled digital serial number, so as to illustrate the arrangement and extension of each step group, rather than to limit the structure of each step group.

[0082] In addition, the present application does not limit the number of step groups in the stepped structure S and the number of conductive steps 31 in any step group, as long as any semiconductor layer L2 can be connected to at least one conductive step 31 .

[0083] For example, the number of step groups in any stepped structure S is less than or equal to the number of stacked layers of the semiconductor layer L2 in the memory array structure 2 .

[0084] For example, in the same step structure S, the number of conductive steps 31 in the multiple step groups is the same.

[0085] For example, in the same stepped structure S, the number of the conductive steps 31 in any step group is greater than or equal to half the number of stacked layers of the semiconductor layer L2 in the memory array structure 2 .

[0086] In some embodiments, as Figure 1As shown in , any semiconductor layer L2 other than the top semiconductor layer L2 is correspondingly connected to a plurality of conductive steps 31 , and a bit line BL is provided on the upper surface of at least one conductive step 31 correspondingly connected to any semiconductor layer L2 .

[0087] For example, in the same stepped structure S, the top semiconductor layer L2 may be connected to only one conductive step 31 in the step group. Furthermore, in the same stepped structure S, the number of conductive steps 31 connected to each semiconductor layer L2 may first increase and then decrease along the stacking direction of the semiconductor layers L2.

[0088] For example, Figure 3 As shown in FIG, the semiconductor layer L2 and the corresponding conductive step 31 are provided in the same layer and made of the same material. That is, the conductive step 31 corresponding to the same semiconductor layer L2 and the semiconductor layer L2 can be different regions of the same semiconductor material layer, with the same material and the same layer position. Therefore, the conductive step 31 corresponding to the same semiconductor layer L2 can be an integral structure with the semiconductor layer L2.

[0089] Here, each conductive step 31 may be a doped region of a corresponding semiconductor material layer, and the type and concentration of the doped ions may be set according to requirements to provide better conductivity.

[0090] For example, Figure 3 As shown in , the step group also includes insulating steps 32 disposed between adjacent conductive steps 31. The insulating steps 32 are provided in the same layer and material as the corresponding isolation layer L1. That is, each insulating step 32 in the same step group can be connected to a different layer of isolation layer L1. In this way, the insulating steps 32 connected to the same isolation layer L1 form an integral structure with the isolation layer L1. In other words, the insulating steps 32 connected to the same isolation layer L1 and the isolation layer L1 can be different regions of the same isolation material layer, both having the same material and the same number of layers.

[0091] In some examples, such as Figure 1 and Figure 3 As shown in FIG, the outer sidewall of each conductive step 31 facing away from the semiconductor layer L2 is flush with the outer sidewall of the upper adjacent insulating step 32 facing away from the isolation layer L1. In this way, any conductive step 31 and its upper adjacent insulating step 32 can be formed by a single etching process.

[0092] In some examples, such as Figure 1 and Figure 3 As shown in , the misalignment of adjacent step groups in the stacking direction (eg, Z direction) of the semiconductor layer L2 can be expressed as: the misalignment in the Z direction is the sum of the thicknesses of one conductive step 31 and one insulating step 32 .

[0093] In some embodiments, please refer to Figure 3 The conductive steps 31 with the same step number in the multiple step groups are arranged in a row along the first direction (for example, the Y direction), and the width W of each conductive step 31 in the same row is the same; the width W is the size of the conductive step 31 in the second direction (for example, the X direction).

[0094] In some embodiments, please refer to Figure 3 The length D of each conductive step 31 in the same step group is the same, and the length D is the size of the conductive step 31 in the first direction (for example, the Y direction).

[0095] In some embodiments, the length D of each conductive step 31 in different step groups is the same.

[0096] In some embodiments, see Figure 1 and Figure 3 The multiple step groups include: a central step group S10 and multiple first step groups S11 and multiple second step groups S12 that are symmetrical with respect to the central step group S10; wherein, the conductive steps 31 with the same sequence number in the multiple first step groups S11 extend downward in sequence along a direction away from the central step group S10 (for example, the Y direction), and the conductive steps 31 with the same sequence number in the multiple second step groups S12 extend downward in sequence along a direction away from the central step group S10 (for example, the Y direction).

[0097] Here, extending downward means extending in a direction close to the substrate 1 .

[0098] It can be understood that in some of the above embodiments, each semiconductor layer L2 can be connected to one or more conductive steps 31 at the same time.

[0099] In some embodiments, multiple bit lines BL are formed on multiple conductive steps 31 connected to the same semiconductor layer L1, allowing any semiconductor layer L1 to be electrically connected to external circuits via multiple bit lines BL. Furthermore, to meet the storage density requirements of the three-dimensional memory, the number of bit lines BL connected to any semiconductor layer L1 can be appropriately set based on current requirements.

[0100] For example, any semiconductor layer L1 is connected to four bit lines BL, the orthographic projection outline of the memory array structure 2 on the substrate 1 is rectangular, and the four bit lines BL can be respectively arranged at four corners of the memory array structure 2 .

[0101] For example, if the storage density of the 3D memory needs to be further improved, the number of bit lines BL connected to any semiconductor layer L1 can be reduced, for example, any semiconductor layer L1 can be connected to two bit lines BL, or any semiconductor layer L1 can be connected to one bit line BL.

[0102] For example, a bit line BL is formed on any conductive step 31 connected to the same semiconductor layer L1, so that any semiconductor layer L1 can be electrically connected to an external circuit through a bit line BL, thereby reducing the total number of bit lines BL in the three-dimensional memory and achieving the maximum improvement in the storage density of the three-dimensional memory by using the least number of bit lines BL.

[0103] In addition, the plurality of bit lines BL in the three-dimensional memory may also be arranged according to some preset rules. The following embodiments exemplarily provide some possible arrangements of the bit lines BL, but are not limited thereto.

[0104] In some embodiments, please combine Figure 2 and Figure 3 It is understood that conductive steps 31 with the same step number in the multiple step groups are arranged in rows along a first direction (e.g., the Y direction). The multiple bit lines BL include multiple bit line groups B, wherein each bit line group B includes at least two bit lines BL located in the same row. Furthermore, different bit line groups BL are staggered in the first direction (e.g., the Y direction).

[0105] For example, Figure 2 As shown in FIG, the misalignment of adjacent bit line groups B in the first direction (eg, the Y direction) may be expressed as being offset by a distance of one bit line BL in the Y direction.

[0106] In some embodiments, please combine Figure 1 、 Figure 2 and Figure 3 It is understood that the multiple bit line groups B arranged on the upper surface of the conductive step 31 in each first step group S11 are linearly arranged along the third direction (for example, the X1 direction); the multiple bit line groups B arranged on the upper surface of the conductive step 31 in each second step group S12 are linearly arranged along the fourth direction (for example, the Y1 direction); the third direction (for example, the X1 direction) and the fourth direction (for example, the Y1 direction) respectively intersect with the first direction (for example, the Y direction) and the second direction (for example, the X direction).

[0107] In some embodiments, see Figure 4 The three-dimensional memory further includes an insulating layer 4 covering the stepped structure S. The insulating layer 4 can be a single-layer structure or a stacked structure, for example, including a first insulating layer 41 and a second insulating layer 42 stacked together. The plurality of bit lines BL all penetrate the insulating layer 4, and the surfaces of the bit lines BL facing away from the corresponding conductive steps 31 are flush with the surface of the insulating layer 4 facing away from the stepped structure S, for example, flush with the surface of the second insulating layer 42 facing away from the first insulating layer 41.

[0108] For example, the insulating layer 4 also extends to cover the surface of the memory array structure 2 facing away from the substrate 1 .

[0109] It should be noted that in Figure 4 and Figure 5 In the three-dimensional memory shown, the insulating layer 4 does not completely cover part of the sidewalls of the stepped structure S. However, it can be understood that it is also permitted for the insulating layer 4 to completely cover the sidewalls of the stepped structure S.

[0110] In some embodiments, please combine Figure 1 、 Figure 2 and Figure 4 It is understood that the memory array structure 2 further includes: a plurality of word lines WL and a plurality of capacitors C. The first insulating layer 41 covers the top isolation layer L1 and the top surfaces of the word lines WL, and the second insulating layer 42 covers the first insulating layer 41 and the top surfaces of the capacitors C.

[0111] In some embodiments, see Figure 4 and Figure 5 , each semiconductor layer L2 includes: a plurality of strip structures extending along a second direction (for example, the X direction) and arranged in parallel and spaced apart; wherein the plurality of strip structures in each semiconductor layer L2 are arranged in columns along a direction perpendicular to the substrate 1 (for example, the Z direction) and in rows along the first direction (for example, the Y direction); the second direction (for example, the X direction) and the first direction (for example, the Y direction) are parallel to and intersect with the upper surface of the semiconductor layer L2.

[0112] For example, Figure 5 As shown in the figure, the multiple strip structures in any semiconductor layer L2 include: a plurality of first strip structures 21A respectively arranged in a first strip structure group, and a plurality of second strip structures 21B respectively arranged in a second strip structure group; wherein the first strip structure group and the second strip structure group are symmetrical with respect to a virtual center line O as a symmetry axis, and the virtual center line O extends along a first direction (for example, the Y direction), and the first direction (for example, the Y direction) is perpendicular to the second direction (for example, the X direction).

[0113] For example, the word lines WL extend in the same direction as the bit lines BL, for example, both extending perpendicular to the upper surface of the substrate 1. Furthermore, one word line WL corresponds to one column of strip structures. For example, one column of first strip structures 21A corresponds to one word line WL, and one column of second strip structures 21B corresponds to one word line WL.

[0114] For example, each strip structure (e.g., the first strip structure 21A and the second strip structure 21B) includes a channel region P and contact regions located on opposite sides of the channel region P in a second direction (e.g., the X direction), wherein one contact region is connected to the conductive step 31, and the other contact region is connected to the first electrode layer 23 of the capacitor C. Furthermore, of the two contact regions of any strip structure, one may be a source region, and the other may be a drain region.

[0115] Accordingly, in some examples, the memory array structure 2 further includes: a gate dielectric layer 22 disposed between each strip structure and the corresponding word line WL.

[0116] For example, the gate dielectric layer 22 surrounds the sidewalls of the channel region P of the strip structure. In this way, the strip structure and the gate dielectric layer 22 on the sidewalls thereof can form a transistor.

[0117] For example, the gate dielectric layer 22 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0118] In addition, the above-mentioned word line WL is a gate word line, which can be used as a memory word line WL and also serve as a gate of a corresponding transistor, thereby controlling the turning on and off of the transistor.

[0119] For example, the word line WL includes but is not limited to a columnar structure, such as a circular column, a rectangular column, a prism, or a special-shaped column.

[0120] By way of example, the material of the word line WL includes but is not limited to metal, such as metal tungsten or metal copper.

[0121] For example, a second barrier layer ( Figure 5 not shown).

[0122] Illustratively, the second barrier layer includes, but is not limited to, titanium nitride.

[0123] In some embodiments, please refer to Figure 5 The capacitor C is disposed at the end of the corresponding strip structure away from the conductive step 31. The capacitor C includes a first electrode layer 23, a dielectric layer 24, and a second electrode layer 25, which are stacked. The first electrode layer 23 is connected to the end of the corresponding strip structure away from the conductive step 31.

[0124] Illustratively, the first electrode layer 23 includes but is not limited to a titanium nitride layer.

[0125] Illustratively, the dielectric layer 24 includes, but is not limited to, a HK dielectric layer.

[0126] For example, the second electrode layer 25 includes but is not limited to a metal layer, such as a metal tungsten layer or a metal copper layer.

[0127] For example, a third barrier layer may be further provided between the second electrode layer 25 and the dielectric layer 24. The third barrier layer may be, for example, a titanium nitride layer.

[0128] As described above, each transistor and the connected capacitor C can constitute a memory cell of 1T1C architecture.

[0129] In some examples, the second electrode layers 25 of the plurality of capacitors C are an integral structure. The dielectric layers 24 of the plurality of capacitors C are an integral structure.

[0130] In some embodiments, see Figure 5 The plurality of capacitors C include: first capacitors C1 respectively disposed at one end of the corresponding first strip structure 21A away from the corresponding conductive step 31 , and second capacitors C2 respectively disposed at one end of the corresponding second strip structure 21B away from the corresponding conductive step 31 .

[0131] For example, the second electrode layer 25 of each first capacitor C1 and each second capacitor C2 is an integral structure. The dielectric layer 24 of each first capacitor C1 and each second capacitor C2 is an integral structure.

[0132] It is worth mentioning that in some embodiments, see Figure 1 and Figure 2 The three-dimensional memory further includes: a plurality of first isolation structures 51 and a plurality of second isolation structures 52. The first isolation structures 51 extend along the second direction (e.g., the X direction), and the plurality of first isolation structures 51 can separate a plurality of strip-shaped structures in the first direction (e.g., the Y direction) to effectively isolate transistors adjacent to each other in the first direction (e.g., the Y direction). The second isolation structure 52 can be disposed on the side of the memory array structure 2 where the step structure S is not disposed. For example, two second isolation structures 52 are disposed on opposite sides of the memory array structure 2 in the first direction (e.g., the Y direction), and extend in the same direction as the first isolation structure 51, to serve as peripheral isolation structures for the memory array structure 2 and each conductive step 31 in the step structure S.

[0133] Illustratively, the material of the first isolation structure 51 and the second isolation structure 52 is the same as the material of the isolation layer L1 .

[0134] This disclosure also provides, according to some embodiments, a method for fabricating a three-dimensional memory device, for use in fabricating the three-dimensional memory devices described in some of the aforementioned embodiments. This method also possesses the technical advantages of the aforementioned three-dimensional memory devices. Furthermore, the aforementioned structure employed in the three-dimensional memory device reduces the difficulty of fabricating the device, thereby improving production efficiency and yield.

[0135] See also Figure 6 The preparation method of the three-dimensional memory includes the following steps.

[0136] S100 , providing a substrate, and alternately stacking isolation material layers and semiconductor material layers on one side of the substrate to form a stacked structure. The stacked structure has a memory array region and a wiring region disposed on at least one side of the memory array region.

[0137] S200: Patterning the stacked structure in the wiring area to form at least one stepped structure. The stepped structure is located on one side of the memory array area and includes a plurality of step groups arranged along a first direction, each extending along a second direction. The first and second directions intersect, and adjacent step groups are staggered in the stacking direction of the semiconductor layers. The step groups include a plurality of conductive steps formed by patterning different semiconductor material layers.

[0138] S300 , forming bit lines on the upper surfaces of the plurality of conductive steps, respectively, wherein the bit lines extend in a direction perpendicular to the upper surfaces of the conductive steps.

[0139] In some embodiments, before performing step S300 to form bit lines on the upper surfaces of the plurality of conductive steps, the preparation method further includes S230 and S270 .

[0140] S230 , forming an insulating layer covering the stepped structure.

[0141] S270, forming a plurality of through holes in the insulating layer to expose corresponding conductive steps in the through holes. Accordingly, step S300 forms bit lines on the upper surfaces of the plurality of conductive steps, including: filling the through holes with conductive material to form the bit lines.

[0142] In some embodiments, in step S200 , the patterned stacked structure is located before the portion of the wiring area, and the preparation method further includes S150 .

[0143] S150 , forming a protection layer covering corresponding surfaces of the stacked structure L in the memory array region.

[0144] Illustratively, the protection layer is a metal hard mask layer.

[0145] Here, the protective layer can protect the various layers within the memory array area to prevent adverse effects from the subsequent step-structure etching process. For example, during the formation of a vertical mask and the vertical patterning process, it can prevent the corresponding layers within the memory array area from extending inward and etching, thereby effectively ensuring the formation position of the step structure. Accordingly, after the step structure is subsequently etched, the protective layer can be removed.

[0146] In some embodiments, after patterning the portion of the stacked structure located in the wiring area in step S200, any semiconductor material layer other than the top semiconductor material layer may be patterned to form a plurality of conductive steps. Accordingly, bit lines are formed on the upper surfaces of the plurality of conductive steps, further comprising: forming a bit line on the surface of at least one of the plurality of conductive steps formed after patterning the semiconductor material layer.

[0147] In some embodiments, step S200 of patterning a portion of the stacked structure located in the wiring region to form at least one stepped structure may include the following steps.

[0148] S210 , retaining the semiconductor material layer of the lower half layer, and patterning the semiconductor material layer of the upper half layer multiple times in the second direction to form a plurality of initial conductive steps.

[0149] S220 , patterning each initial conductive step and the lower half semiconductor material layer multiple times in a first direction to form a plurality of step groups.

[0150] In some embodiments, the lower half layer and the upper half layer can be arranged as half the number of stacked semiconductor material layers. For example, if the number of stacked semiconductor material layers is an even number, then the lower half layer and the upper half layer can each be half the number of stacked semiconductor material layers. For example, if the number of stacked semiconductor material layers is an odd number, then the lower half layer can have one more layer than the upper half layer to ensure that the lower half layer and the upper half layer are both integers. However, this is not limiting, and other embodiments are possible.

[0151] In some embodiments, the number of semiconductor material layers is N; the number of initial conductive steps is i+1, where i is a positive integer and 2≤i+1≤N / 2. Step S210 patterns the upper half of the semiconductor material layer multiple times in the second direction to form a plurality of initial conductive steps, including steps S211 to S213.

[0152] S211: Form a first lateral mask on a side of the Nth semiconductor material layer facing away from the substrate, and etch the Nth semiconductor material layer based on the first lateral mask to perform a first lateral patterning.

[0153] S212: Remove a portion of the first lateral mask of the target width for the first time along the second direction to form a second lateral mask, and etch the Nth to N-1th semiconductor material layers based on the second lateral mask to perform a second lateral patterning.

[0154] S213, gradually increase the number of times the first lateral mask removes the target width portion in the second direction and perform the corresponding lateral patterning process, until the first lateral mask is removed for the i-th time along the second direction to form the i+1th lateral mask; based on the i+1th lateral mask, etch the N-th to Ni-th semiconductor material layers, and perform the i+1th lateral patterning to form i+1 initial conductive steps.

[0155] In some embodiments, the number of semiconductor material layers that are not laterally patterned is M, where M≥N / 2; and the number of step groups is j+1 or 2j+1, where j is a positive integer and 1≤j≤M+1.

[0156] Here, when the number of step groups is 2j+1, the multiple step groups may include: a central step group and j first step groups and j second step groups that are symmetrical with respect to the central step group; wherein, the conductive steps with the same serial number in each first step group extend downward in sequence in a direction away from the central step group (toward a direction close to the substrate), and the conductive steps with the same serial number in each second step group extend downward in sequence in a direction away from the central step group (toward a direction close to the substrate).

[0157] Accordingly, step S220 performs multiple patterning on each initial conductive step and the lower half semiconductor material layer in the first direction to form a plurality of step groups, including: S221 to S223.

[0158] S221 , forming a first vertical mask covering each initial conductive step; etching each initial conductive step based on the first vertical mask to perform a first patterning.

[0159] S222, removing a portion of the first vertical mask of a target length for the first time along the first direction to form a second vertical mask; etching each initial conductive step and the Mth semiconductor material layer based on the second vertical mask to perform a second vertical patterning.

[0160] S223, gradually increase the number of times the first vertical mask removes the target length portion in the first direction and perform the corresponding vertical patterning process, until the first vertical mask is used to remove the target length portion for the jth time along the first direction to form the j+1th vertical mask; based on the j+1th vertical mask, each initial conductive step and the Mth to M-j+1th semiconductor material layers are etched, and the j+1th vertical patterning is performed to form j+1 or 2j+1 step groups.

[0161] It should be supplemented that, in some embodiments, before step S200 of patterning the portion of the stacked structure located in the wiring area to form at least one stepped structure, the preparation method further includes the following steps.

[0162] S110, patterning the stacked structure in a portion of the memory array region such that each semiconductor material layer is patterned to form a plurality of strip structures. The strip structures extend along a second direction (e.g., an X direction), and the strip structures are arranged in columns along a direction perpendicular to the substrate (e.g., a Z direction) and in rows along a first direction (e.g., a Y direction). The second direction (e.g., the X direction) and the first direction (e.g., the Y direction) are parallel to and intersect the upper surface of the substrate.

[0163] S120 , removing portions of each isolation material layer located in the first target region along a direction perpendicular to the substrate to form a plurality of word line trenches; wherein one word line trench exposes a channel region of a column of strip-shaped structures.

[0164] S130 , forming a gate dielectric layer in the word line trench to cover the sidewalls of the channel region.

[0165] S140 , forming a word line covering the gate dielectric layer in the word line trench, wherein the extending direction of the word line is the same as the extending direction of the bit line.

[0166] In some embodiments, the preparation method further includes the following steps.

[0167] S240 , patterning the portion of the stacked structure located in the memory array area to form an etched groove, wherein the etched groove penetrates the stacked structure and extends in a direction perpendicular to the substrate.

[0168] S250: Based on the etched grooves, portions of each semiconductor material layer located within a second target region are removed to form a plurality of capacitor accommodating grooves. The second target region is located between the wordline grooves and the etched grooves. The capacitor accommodating grooves expose end surfaces of the corresponding strip structures on a side adjacent to the etched grooves.

[0169] S260 , forming a capacitor in the capacitor receiving groove.

[0170] In some embodiments, step S260 of forming a capacitor in the capacitor receiving groove includes the following steps.

[0171] S261: forming a first electrode layer covering the inner wall of the capacitor receiving groove, wherein the first electrode layer is connected to the end surface of the corresponding strip structure close to the etching groove.

[0172] S262, forming a dielectric layer at least covering the first electrode layer.

[0173] S263 , forming a second electrode layer covering the dielectric layer and filling the capacitor receiving groove and the etching groove.

[0174] It is understood that the above steps S240 to S260 can be performed before or after step S300. Some embodiments of the present disclosure illustrate the example of steps S240 to S260 being performed before step S300, but the steps can be implemented in other execution orders for adaptive adjustment.

[0175] It is understood that, unless otherwise explicitly stated herein, the steps of the above-described method for preparing a three-dimensional memory device are not strictly limited in order and may be performed in other orders. Furthermore, at least some of the steps in the above-described method for preparing a three-dimensional memory device may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be completed at the same time, but may be performed at different times. Their execution order does not necessarily need to be sequential, but may be performed simultaneously, alternately, or in rotation with other steps or at least a portion of their sub-steps or stages.

[0176] In order to more clearly illustrate the preparation method of the three-dimensional memory in some of the above embodiments, the following embodiments are exemplarily combined with Figures 7 to 29 Some implementation methods of the preparation method and some of its steps are given.

[0177] In step S100, refer to Figure 7 A substrate 1 is provided, and isolation material layers L10 and semiconductor material layers L20 are alternately stacked on one side of the substrate 1 to form a stacked structure L. The stacked structure L has a memory array region R1 and a wiring region R2 disposed on at least one side of the memory array region R1.

[0178] In step S110, please combine Figure 5 and Figures 8 to 11 It is understood that the patterned stacked structure L is located in a portion of the memory array region R1, so that each semiconductor material layer L20 is patterned to form a plurality of strip structures. The strip structures extend along a second direction (e.g., the X direction), and the strip structures are arranged in columns along a direction perpendicular to the substrate (e.g., the Z direction) and in rows along a first direction (e.g., the Y direction). The second direction (e.g., the X direction) and the first direction (e.g., the Y direction) are parallel to and intersect the upper surface of the semiconductor material layer L20.

[0179] For example, see Figure 8 A first mask layer Y1 is formed on the upper surface of the stack structure L. The first mask layer Y1 has a Figure 9 The mask patterns of the positions where the first isolation trench G1 and the second isolation trench G2 are formed are shown.

[0180] See also Figure 9 Based on the mask pattern in the first mask layer Y1, the stacked structure L is etched until the substrate 1 is exposed, thereby forming a plurality of first isolation trenches G1 and a plurality of second isolation trenches G2. The first isolation trenches G1 are located in the memory array region R1 and extend along the second direction (e.g., the X direction). The plurality of first isolation trenches G1 are used to separate a plurality of strip-shaped structures in the first direction (e.g., the Y direction). The second isolation trenches G2 can be disposed on a side of the memory array region R1 where the wiring region R2 is not disposed. For example, two second isolation trenches G2 can be disposed on opposite sides of the memory array region R1 in the first direction (e.g., the Y direction), and extend in the same direction as the first isolation trenches G1.

[0181] See also Figure 10 After removing the first mask layer Y1 , an isolation layer 50 is formed to fill the first isolation trench G1 and the second isolation trench G2 and cover the upper surface of the stacked structure L.

[0182] For example, the material of the isolation layer 50 is the same as that of the isolation material layer L1, including but not limited to insulating materials such as nitride, oxide, or oxynitride. The isolation layer 50 is, for example, a silicon nitride layer or a silicon oxide layer.

[0183] See also Figure 11 The isolation layer 50 above the stacked structure L is removed, forming a first isolation structure 51 located in the first isolation trench G1 and a second isolation structure 52 located in the second isolation trench G2. The first isolation structure 51 can effectively isolate transistors adjacent to each other in a first direction (e.g., the Y direction). The second isolation structure 52 can serve as a peripheral isolation structure for the memory array structure 2 and the conductive steps within the staircase structure S.

[0184] For example, the isolation layer 50 above the stacked structure L is removed by a grinding process, which includes but is not limited to a chemical mechanical polishing (CMP) process.

[0185] In step S120, please combine Figure 5 and Figures 12 to 14 It is understood that the portion of each isolation material layer L1 located in the first target area is removed along a direction perpendicular to the substrate 1 (eg, Z direction) to form a plurality of word line grooves Gw; wherein one word line groove Gw exposes a column of channel regions P of strip-shaped structures.

[0186] For example, see Figure 12 , a second mask layer Y2 is formed on the upper surface of the stack structure L, and the second mask layer Y2 has a mask pattern for defining the formation position of the word line WL. Figure 13 and Figure 14 Based on the mask pattern in the second mask layer Y2, the stacked structure L is etched perpendicularly to the substrate 1 (e.g., in the Z direction), removing the portion of each isolation material layer L1 within the first target region to form a wordline trench Gw. Simultaneously, the portion of each semiconductor material layer L20 exposed within the wordline trench Gw becomes the channel region P of the corresponding stripe structure.

[0187] In step S130, refer to Figure 14 , a gate dielectric layer 22 is formed in the word line trench Gw to cover the sidewalls of the channel region P.

[0188] Illustratively, the gate dielectric layer 22 is formed by a deposition process.

[0189] The deposition processes mentioned here and below include but are not limited to atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, molecular layer deposition (MLD) process, etc.

[0190] In step S140, refer to Figure 15 , forming a word line material layer 60 that fills the word line groove Gw and covers the upper surface of the stack structure L. Figure 16 , the word line material layer 60 above the stack structure L is removed to form a word line WL located in the word line groove Gw.

[0191] For example, before forming the word line material layer 60, a second barrier layer may be formed conformally covering the surface of the gate dielectric layer 22 and the inner wall of the word line trench Gw. In this way, the word line material layer 60 may be formed on the surface of the second barrier layer and fill the word line trench Gw.

[0192] For example, the second barrier layer and the word line material layer 60 may be formed by a deposition process.

[0193] For example, the word line material layer 60 above the stack structure L is removed by a grinding process, which includes but is not limited to a CMP process.

[0194] In step S150, refer to Figure 17 A protective layer 7 is formed at least in the memory array region R1 to cover the corresponding surface of the stacked structure L. Thus, the protective layer 7 can be used to protect the various layers of the structure in the memory array region R1 to prevent adverse effects caused by the subsequent etching process of the stepped structure S. Accordingly, after the stepped structure S is subsequently etched, the protective layer 7 can be removed.

[0195] Illustratively, the protection layer 7 is a metal hard mask layer.

[0196] In step S200, refer to Figures 18 to 23 The patterned stacked structure L is located in the wiring region R2 to form at least one step structure S. The step structure S is located on one side of the memory array region R1 and includes multiple step groups. The multiple step groups are arranged along a first direction (e.g., the Y direction), and each step group extends along a second direction (e.g., the X direction). The first direction (e.g., the Y direction) and the second direction (e.g., the X direction) intersect. Adjacent step groups are staggered in the stacking direction (e.g., the Z direction) of the semiconductor material layer L20. The step groups include multiple conductive steps 31 formed by patterning different semiconductor material layers L20.

[0197] For example, the stepped structure S further includes a plurality of insulating steps 32 formed after each isolation material layer L10 is patterned; wherein, the semiconductor material layer L20 and the isolation material layer L10 adjacent thereto can be etched using a single etching process.

[0198] In some embodiments, step S200 may include S210 to S220.

[0199] In step S210, refer to Figure 18 and Figure 19 The semiconductor material layer L20 in the lower half is retained, and the semiconductor material layer L20 in the upper half is patterned multiple times in the second direction (e.g., the X direction) to form a plurality of initial conductive steps 310. Furthermore, corresponding initial insulating steps 320 (i.e., initial insulating steps 320 adjacent to and above the initial conductive steps 310) can be formed simultaneously with the initial conductive steps 310.

[0200] For example, the number of semiconductor material layers L20 is N, and the number of initial conductive steps 310 is i+1, where i is a positive integer and 2≤i+1≤N / 2. Step S210 may include S211 to S213.

[0201] In step S211, refer to Figure 18 A first lateral mask Y41 is formed on the side of the Nth semiconductor material layer L20 (ie, the top semiconductor material layer) facing away from the substrate 1. The Nth semiconductor material layer L20 is etched based on the first lateral mask Y41 to perform a first lateral patterning.

[0202] In step S212, please combine Figure 18 and Figure 19 It is understood that a portion of the first lateral mask Y41 having a target width (i.e., the width corresponding to the conductive step 31) is removed for the first time along the second direction (e.g., the X direction) to form a second lateral mask Y42. The semiconductor material layers L20 from the Nth layer to the N-1th layer are etched based on the second lateral mask Y42 to perform a second lateral patterning.

[0203] In step S213, please combine Figure 19 and Figure 20 It is understood that the number of times the first lateral mask Y41 removes the target width portion in the second direction (for example, the X direction) is increased one by one and the corresponding lateral patterning process is performed until the portion of the first lateral mask (for example, the X direction) with the target width is removed for the i-th time along the second direction (for example, the X direction) to form the i+1th lateral mask Y4i+1; the N-layer to Ni-layer semiconductor material layer L20 is etched based on the i+1th lateral mask Y4i+1, and the i+1th lateral patterning is performed to form i+1 initial conductive steps 310.

[0204] As described above, after forming i+1 initial conductive steps 310, the number of semiconductor material layers that have not been laterally patterned is, for example, M, where M ≥ N / 2; and the number of step groups is j+1 or 2j+1, where j is a positive integer and 1 ≤ j ≤ M+1. Accordingly, step S220 may include steps S221 to S223.

[0205] In step S221, please combine Figure 20 and Figure 21 It is understood that a first vertical mask Y51 is formed to cover each initial conductive step 310 ; and each initial conductive step 310 is etched based on the first vertical mask Y51 to perform the first patterning.

[0206] In step S222, refer to Figure 22 The first vertical mask Y51 is removed for the first time along the first direction (e.g., the Y direction) by a target length (i.e., the length corresponding to the conductive step 31) to form a second vertical mask Y52. The initial conductive steps 320 and the Mth semiconductor material layer L20 are then etched using the second vertical mask Y52 to perform a second vertical patterning operation.

[0207] In step S223, please combine Figure 22 and Figure 23 It is understood that the number of times the first vertical mask Y51 removes the target length portion in the first direction (for example, the Y direction) is increased one by one and the corresponding vertical patterning process is performed until the first vertical mask Y51 is removed for the jth time along the first direction (for example, the Y direction) with a target length to form the j+1th vertical mask Y5j+1; based on the j+1th vertical mask Y5j+1, each initial conductive step 310 and the Mth to M-j+1th semiconductor material layers L20 are etched, and the j+1th vertical patterning is performed to form j+1 or 2j+1 step groups.

[0208] For example, Figure 23 As shown in , when the number of step groups is 2j+1, the multiple step groups may include: a central step group S10 and j first step groups S11 and j second step groups S12 that are symmetrical with the central step group S10; wherein, the conductive steps 31 with the same serial number in each first step group S11 extend downward in sequence along a direction away from the central step group S10 (toward a direction close to the substrate 1), and the conductive steps 31 with the same serial number in each second step group S12 extend downward in sequence along a direction away from the central step group S10 (toward a direction close to the substrate 1).

[0209] Here, the arrangement and distribution of each step group can be seen in Figure 23 The distribution of the arrows in the figure, the serial number identification of the conductive steps 31 in each step group can be combined with Figure 3 Understand.

[0210] It is worth mentioning that in the process of forming the step structure S, if Figure 23 As shown in FIG, the second isolation structure 52 is located in a portion of the wiring region R2 that is synchronously stepped.

[0211] In some embodiments, forming an insulating layer covering the stepped structure in step S230 may include S231 and S232 .

[0212] In step S231, refer to Figure 24 After forming the stepped structure S, a first insulating layer 41 is formed to cover the stepped structure S and the memory array region R1.

[0213] Here, each surface of the first insulating layer 41 is flat, which can be used to ensure a flat appearance of the three-dimensional memory.

[0214] In step S240, refer to Figure 25 The patterned stacked structure L is located in the portion of the memory array region R1, forming an etched groove Gk. The etched groove Gk penetrates the stacked structure L and extends along a first direction (eg, the Y direction). Furthermore, the etched groove Gk is formed along a virtual center line O.

[0215] In step S250, refer to Figure 26 Based on the etching groove Gk, the portion of each semiconductor material layer L20 located within the second target area is removed to form multiple capacitor accommodating grooves Gc. The second target area is located between the wordline groove Gw and the etching groove Gk. The capacitor accommodating grooves Gc expose the end surface of the corresponding strip structure near the etching groove Gk.

[0216] Here, after forming the capacitor accommodating groove Gc, the semiconductor material layers L20 remaining in the memory array region R1 of the stacked structure L respectively constitute corresponding semiconductor layers L2 , and the isolation material layers L10 remaining in the memory array region R1 respectively constitute corresponding isolation layers L1 .

[0217] It can be understood that after the first isolation structure 51 is formed, the plurality of first isolation structures 51 can separate the semiconductor material layer L20 in the memory array region R1 into a plurality of strip structures in the first direction (e.g., the Y direction). Based on this, after the etching groove Gk is formed, any semiconductor material layer L20 can be patterned to form a first strip structure group and a second strip structure group that are bilaterally symmetrical with the virtual center line O as the symmetry axis, wherein the first strip structure group includes a plurality of first strip structures 21A arranged in parallel and spaced apart, and the second strip structure group includes a plurality of second strip structures 21B arranged in parallel and spaced apart (which can be combined with the first strip structure group). Figure 5Accordingly, the plurality of capacitor accommodating grooves Gc formed based on the etched grooves Gk further include: first capacitor accommodating grooves formed on the side of the first strip structure 21A close to the etched grooves Gk, and second capacitor accommodating grooves formed on the side of the second strip structure 21B close to the etched grooves Gk. Furthermore, the first capacitor accommodating grooves correspond one-to-one with the first strip structure 21A, and the second capacitor accommodating grooves correspond one-to-one with the second strip structure 21B.

[0218] In step S260, refer to Figure 26 and Figure 27 , a capacitor is formed in the capacitor receiving groove Gc, for example, a first capacitor C1 is formed in the first capacitor receiving groove, and a second capacitor C2 is formed in the second capacitor receiving groove.

[0219] Illustratively, forming the capacitor C in the capacitor receiving groove Gc includes steps S261 to S263 .

[0220] In step S261 , a first electrode layer 23 is formed to cover the inner wall of the capacitor receiving groove Gc.

[0221] Here, the first electrode layer 23 conformally covers the inner wall of the corresponding capacitor accommodating groove Gc and is connected to the end surface of the corresponding strip structure on the side close to the etched groove Gk. The first electrode layer 23 can be formed using an ALD process. Furthermore, the first electrode layers 23 in adjacent capacitor accommodating grooves Gc in a direction perpendicular to the substrate 1 (e.g., the Z direction) can be insulated by the isolation layer L1, and the first electrode layers 23 in adjacent capacitor accommodating grooves Gc in the first direction (e.g., the Y direction) can be insulated by the first isolation structure 51.

[0222] In step S262 , a dielectric layer 24 is formed to at least cover the first electrode layer 23 .

[0223] Here, if Figure 27 As shown in FIG, the dielectric layer 24 can be formed using an ALD process. The dielectric layer 24 conformally covers the inner surface of the first electrode layer 23 and extends to cover the inner wall of the etched groove Gk. In this way, the dielectric layer 24 in each first capacitor C1 and each second capacitor C2 is an integrated structure.

[0224] In step S263, a second electrode layer 25 is formed to cover the dielectric layer 24 and fill the capacitor receiving groove Gc and the etching groove Gk. In this way, the second electrode layer 25 in each first capacitor C1 and each second capacitor C2 is an integrated structure.

[0225] In some examples, the dielectric layer 24 and the second electrode layer 25 can be obtained by sequentially stacking a dielectric material layer and a second electrode material layer and then grinding and removing the dielectric material layer and the second electrode material layer above the first insulating layer 41 .

[0226] For example, the top surface of the dielectric layer 24 and the top surface of the second electrode layer 25 are both flush with the surface of the first insulating layer 41 facing away from the substrate 1 .

[0227] In addition, in some examples, before forming the second electrode layer 25 , a third barrier layer conformally covering the dielectric layer 24 may be formed first, and then the second electrode layer 25 conformally covering the third barrier layer and filling the capacitor receiving groove may be formed.

[0228] In step S232, if Figure 28 As shown in FIG, a second insulating layer 42 is formed to cover the first insulating layer 41 and the capacitor C, so that the first insulating layer 41 and the second insulating layer 42 together constitute the aforementioned insulating layer 4.

[0229] In some examples, such as Figure 28 As shown in FIG, a sixth mask layer Y6 is formed on the upper surface of the second insulating layer 42, and a mask pattern for defining the position where the bit line BL is to be formed is formed in the sixth mask layer Y6. Based on the mask pattern in the sixth mask layer Y6, the insulating layer 4 (including the second insulating layer 42 and the first insulating layer 41) and the corresponding insulating steps 32 are etched until the corresponding conductive steps 31 are exposed, thereby forming each through hole H.

[0230] In step S270, please continue to refer to Figure 28 , a plurality of through holes H are formed in the insulating layer 4 so as to expose the corresponding conductive steps 31 in the through holes H.

[0231] Here, the through holes H extend in a direction perpendicular to the substrate 1 (eg, the Z direction), and each through hole H also penetrates the adjacent insulating step 32 above the corresponding conductive step 31 .

[0232] In step S300, refer to Figure 29 A conductive material is filled in the through hole H to form a bit line BL. Each bit line BL is located on the upper surface of the corresponding conductive step 31 and extends in a direction perpendicular to the upper surface (eg, the Z direction).

[0233] For example, the conductive material is a metal material, such as metal tungsten or metal copper.

[0234] For example, before filling the conductive material, a first barrier layer may be formed to conformally cover the inner wall of each through hole H. In this way, the conductive material covers the surface of the first barrier layer and fills the corresponding through hole to form a corresponding bit line.

[0235] For example, the conductive material filling can be performed before removing the sixth mask layer Y6. In this way, the conductive material can be deposited to cover the upper surface of the sixth mask layer Y6. Then, the sixth mask layer Y6 and excess conductive material above the insulating layer 4 can be removed by a grinding process. This ensures that the top surface of each bit line BL is flush with the upper surface of the insulating layer 4.

[0236] It is worth noting that after patterning the portion of the stacked structure L located in the wiring region R2 in step S200, any semiconductor material layer L20 other than the top semiconductor material layer L20 can be patterned to form a plurality of conductive steps 31. Accordingly, step S300 further includes forming a bit line BL on the surface of at least one of the plurality of conductive steps 31 formed after patterning the same semiconductor material layer L20.

[0237] It should be noted that the "one-time etching process" mentioned in some of the above embodiments can be understood as: etching based on the pattern of the same mask layer to form the same pattern; it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.

[0238] In addition, the “etching” mentioned in some of the above embodiments may also be matched with the etching requirements, such as dry etching, wet etching, or a combination of dry etching and wet etching.

[0239] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0240] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A three-dimensional memory, characterized in that: include: A memory array structure comprising: a plurality of isolation layers and a plurality of semiconductor layers alternately stacked; At least one step structure; the step structure is disposed on one side of the memory array structure, comprising: a plurality of step groups arranged along a first direction; each step group extends along a second direction, and adjacent step groups are staggered in the stacking direction of the semiconductor layers; wherein the first direction and the second direction intersect; the step group includes a plurality of conductive steps, and each conductive step is connected to a corresponding semiconductor layer; A plurality of bit lines are respectively arranged on the upper surface corresponding to the conductive steps; the bit lines extend in a direction perpendicular to the upper surface of the conductive steps; The plurality of step groups include: a central step group and a plurality of first step groups and a plurality of second step groups that are bilaterally symmetrical with the central step group as the center; Wherein, the plurality of bit lines include: a plurality of bit line groups; Among them, the multiple bit line groups arranged on the upper surface of the conductive steps in each first step group are linearly arranged along a third direction; the multiple bit line groups arranged on the upper surface of the conductive steps in each second step group are linearly arranged along a fourth direction; the third direction and the fourth direction respectively intersect with the first direction and the second direction.

2. The three-dimensional memory according to claim 1, wherein: The conductive steps with the same step number in the plurality of step groups are arranged in a row along the first direction, and the conductive steps in the same row have the same width; the width is the size of the conductive step in the second direction.

3. The three-dimensional memory according to claim 1, wherein: The conductive steps in the same step group have the same length, where the length is the size of the conductive step in the first direction.

4. The three-dimensional memory according to claim 3, wherein: The lengths of the conductive steps in different step groups are the same.

5. The three-dimensional memory according to claim 1, wherein: The plurality of step groups include: a central step group and a plurality of first step groups and a plurality of second step groups that are bilaterally symmetrical with the central step group as the center; Among them, the conductive steps with the same sequence number in the plurality of first step groups extend downward in sequence in a direction away from the central step group, and the conductive steps with the same sequence number in the plurality of second step groups extend downward in sequence in a direction away from the central step group.

6. The three-dimensional memory according to any one of claims 1 to 5, characterized in that Any semiconductor layer other than the top semiconductor layer is correspondingly connected to a plurality of the conductive steps, and the bit line is provided on the upper surface of at least one of the conductive steps to which any semiconductor layer is correspondingly connected.

7. The three-dimensional memory according to claim 6, wherein: The semiconductor layer and the corresponding conductive steps are provided in the same layer and made of the same material.

8. The three-dimensional memory according to claim 7, wherein: The step group further includes: insulating steps arranged between adjacent conductive steps; the insulating steps and the corresponding isolation layers are provided in the same layer and made of the same material.

9. The three-dimensional memory according to claim 6, wherein: The conductive steps with the same step number in the plurality of step groups are arranged in a row along the first direction; wherein, The bit line group includes: at least two bit lines located in the same row; Adjacent bit line groups are staggered in the first direction.

10. The three-dimensional memory according to claim 1, wherein: The number of the stepped structures is two, and the two stepped structures are symmetrically arranged on two opposite sides of the storage array structure in the second direction with the storage array structure as the center.

11. The three-dimensional memory according to claim 6, wherein: The plurality of bit lines are located in the same plane away from surfaces corresponding to the conductive steps.

12. The three-dimensional memory according to claim 11, wherein: Also includes: An insulating layer covering the stepped structure; wherein the plurality of bit lines all penetrate the insulating layer, and surfaces of the bit lines facing away from the corresponding conductive steps are flush with a surface of the insulating layer facing away from the stepped structure.

13. A method for preparing a three-dimensional memory, characterized in that: include: Providing a substrate, and alternately stacking isolation material layers and semiconductor material layers on one side of the substrate to form a stacked structure; The stacked structure comprises a storage array area and a wiring area arranged on at least one side of the storage array area; The stacked structure is patterned in the wiring area to form at least one stepped structure; the stepped structure is located on one side of the memory array area, and the stepped structure includes a plurality of step groups; the plurality of step groups are arranged along a first direction, and each step group extends along a second direction; wherein the first direction and the second direction intersect; adjacent step groups are staggered in the stacking direction of the semiconductor layer; and the step groups include a plurality of conductive steps formed after patterning different semiconductor material layers; forming bit lines on the upper surfaces of the plurality of conductive steps, respectively, wherein the bit lines extend in a direction perpendicular to the upper surfaces of the conductive steps; The plurality of step groups include: a central step group and a plurality of first step groups and a plurality of second step groups that are bilaterally symmetrical with the central step group as the center; Wherein, the plurality of bit lines include: a plurality of bit line groups; Among them, the multiple bit line groups arranged on the upper surface of the conductive steps in each first step group are linearly arranged along a third direction; the multiple bit line groups arranged on the upper surface of the conductive steps in each second step group are linearly arranged along a fourth direction; the third direction and the fourth direction respectively intersect with the first direction and the second direction.

14. The method for preparing a three-dimensional memory according to claim 13, wherein: The portion of the stacked structure located in the wiring area is patterned to form at least one stepped structure, comprising: retaining the semiconductor material layer in the lower half and patterning the semiconductor material layer in the upper half multiple times in the second direction to form a plurality of initial conductive steps; Each of the initial conductive steps and the semiconductor material layer in the lower half is patterned multiple times in a first direction to form a plurality of step groups.

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