Three-dimensional memory and preparation method thereof

Abstract

The present disclosure relates to a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes a memory array structure and a peripheral structure. The memory array structure includes a plurality of alternately stacked isolation layers and a plurality of semiconductor layers. The peripheral structure is disposed on the periphery of the memory array structure. The peripheral structure includes at least one stepped structure and a plurality of bit lines. The stepped structure includes a plurality of conductive steps. The conductive steps are connected to corresponding semiconductor layers. The bit lines are disposed on the upper surfaces of corresponding conductive steps and extend in a direction perpendicular to the upper surfaces. The three-dimensional memory and its method for manufacturing the same are conducive to further improving the storage density and storage capacity of the three-dimensional memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. A memory cell typically includes a transistor and a capacitor, wherein the first electrode (e.g., the drain) of the transistor is electrically connected to the capacitor, the second electrode (e.g., the source) of the transistor is electrically connected to the bit line, and the control electrode (e.g., the gate) of the transistor is electrically connected to the word line. Furthermore, the control electrodes of the transistors in a row of memory cells can be electrically connected to a word line, and the second electrodes of the transistors in a column of memory cells can be electrically connected to a bit line.

[0003] As the demand for memory capacity continues to increase, memory cells are being arranged in three dimensions. For example, by continuously increasing the number of stacked layers of memory cells arranged in an array, a three-dimensional memory can be constructed, thereby increasing the storage density per unit area.

[0004] However, as the number of stacked memory cells increases, the number of bit lines, word lines, and supporting contact structures electrically connected to each memory cell also increases, which tends to occupy more area within the 3D memory and limit further increases in storage density and capacity. Therefore, improving the structure of 3D memory to further increase storage density and capacity is a pressing issue. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a three-dimensional memory and a method for manufacturing the same, so as to further improve the storage density and storage capacity of the three-dimensional memory.

[0006] In one aspect, some embodiments of the present disclosure provide a three-dimensional memory device comprising a memory array structure and a peripheral structure. The memory array structure comprises a plurality of alternately stacked isolation layers and a plurality of semiconductor layers. The peripheral structure is disposed on a peripheral side of the memory array structure. The peripheral structure comprises at least one stepped structure and a plurality of bit lines. The stepped structure comprises a plurality of conductive steps, each connected to a corresponding semiconductor layer. The bit lines are disposed on the upper surfaces of corresponding conductive steps and extend in a first direction perpendicular to the upper surface.

[0007] In some embodiments, the plurality of bit lines are linearly arranged along an extension direction of the staircase structure.

[0008] In some embodiments, surfaces of the plurality of bit lines facing away from the corresponding conductive steps are located in the same plane.

[0009] In some embodiments, the three-dimensional memory structure further includes: an insulating layer covering the staircase structure; wherein the bit line passes through the insulating layer, and a surface of the bit line away from the corresponding conductive step is flush with a surface of the insulating layer away from the staircase structure.

[0010] In some embodiments, the conductive step and the corresponding semiconductor layer are an integrated structure.

[0011] In some embodiments, the stepped structure further includes: insulating steps disposed between adjacent conductive steps; the insulating steps and the isolation layer are an integral structure.

[0012] In some embodiments, each semiconductor layer includes: a plurality of strip structures extending along a second direction and spaced parallel to each other; wherein the plurality of strip structures in each semiconductor layer are arranged in columns along the first direction and in rows along the third direction; and the second and third directions are parallel to and intersect the top surface of the semiconductor layer. The memory array structure further includes: a plurality of word lines. The word lines extend in the same direction as the bit lines, and each word line corresponds to a column of strip structures.

[0013] In some embodiments, the stripe structure includes a channel region. The memory array structure further includes: a gate dielectric layer disposed between each channel region and the corresponding word line.

[0014] In some embodiments, the memory array structure further includes: a plurality of capacitors, wherein the capacitors are disposed at one end of the corresponding strip structure away from the surrounding structure.

[0015] In some embodiments, the capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer stacked together, wherein the first electrode layer is connected to the end surface of the corresponding strip structure facing away from the surrounding structure. The second electrode layers of the plurality of capacitors are an integrated structure.

[0016] In some embodiments, the plurality of strip structures in any of the semiconductor layers include: a plurality of first strip structures respectively arranged in a first strip structure group, and a plurality of second strip structures respectively arranged in a second strip structure group; wherein the first strip structure group and the second strip structure group are bilaterally symmetrical about a virtual centerline as an axis of symmetry, and the virtual centerline extends along a third direction perpendicular to the second direction. The plurality of capacitors include: a first capacitor respectively arranged at an end of the corresponding first strip structure facing away from the surrounding structure, and a second capacitor respectively arranged at an end of the corresponding second strip structure facing away from the surrounding structure; wherein the second electrode layer of each first capacitor and each second capacitor is an integral structure.

[0017] In some embodiments, there are two stepped structures. The two stepped structures are arranged on the left and right sides of the memory array structure with the virtual center line as the axis of symmetry; wherein the conductive steps in one stepped structure are connected to the first strip structure, and the conductive steps in the other stepped structure are connected to the second strip structure.

[0018] On the other hand, according to some embodiments, the present disclosure provides a method for preparing a three-dimensional memory, comprising:

[0019] A substrate is provided, and isolation material layers and semiconductor material layers are alternately stacked on one side of the substrate to form a stacked structure; the stacked structure has a memory array area and a peripheral area arranged around the memory array area;

[0020] The patterned stacked structure is located in a portion of the peripheral region to form at least one stepped structure; the stepped structure includes a plurality of conductive steps formed after patterning each semiconductor material layer;

[0021] A bit line is formed on the upper surface of each conductive step, and the bit line extends in a direction perpendicular to the upper surface.

[0022] The embodiments of the present disclosure may or may have at least the following advantages:

[0023] In the disclosed embodiments, bit lines are disposed in a peripheral region. A stepped structure is provided within the peripheral region, connecting the conductive steps within the stepped structure to corresponding semiconductor layers within the memory array structure. Furthermore, the bit lines are positioned on the upper surfaces of the corresponding conductive steps and extend in a first direction perpendicular to the upper surfaces of the conductive steps. This not only allows any semiconductor layer to be connected to a corresponding bit line via the connected conductive steps, thereby reducing the total number of bit lines, but also effectively improves the area utilization of the memory array region, increasing the plate area of ​​the capacitor within the memory array region, thereby effectively increasing the storage density and storage capacity of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic structural diagram of a three-dimensional memory provided in some embodiments;

[0026] Figure 2 for Figure 1 A schematic cross-sectional view of a local area in the three-dimensional memory;

[0027] Figure 3 for Figure 1 A schematic cross-sectional view of the three-dimensional memory along the AA direction;

[0028] Figure 4 A flowchart of a method for preparing a three-dimensional memory provided in some embodiments;

[0029] Figure 5 A flowchart of another method for preparing a three-dimensional memory provided in some embodiments;

[0030] Figure 6 is a flow chart of a method for preparing a capacitor provided in some embodiments;

[0031] Figure 7 A schematic structural diagram of a structure obtained after forming a stacked structure provided in some embodiments;

[0032] Figure 8 is a schematic diagram of a structure obtained after forming a first mask layer provided in some embodiments;

[0033] Figure 9 A schematic diagram of a structure obtained after forming a first isolation trench and a second isolation trench provided in some embodiments;

[0034] Figure 10 A schematic diagram of a structure obtained after forming an isolation layer provided in some embodiments;

[0035] Figure 11 A schematic diagram of a structure obtained after forming a first isolation structure and a second isolation structure provided in some embodiments;

[0036] Figure 12 is a schematic diagram of a structure obtained after forming a second mask layer provided in some embodiments;

[0037] Figure 13 A schematic diagram of a structure obtained after forming a word line trench provided in some embodiments;

[0038] Figure 14 A schematic diagram of a structure obtained after forming a gate dielectric layer provided in some embodiments;

[0039] Figure 15 A schematic diagram of a structure obtained after forming a word line material layer provided in some embodiments;

[0040] Figure 16 A schematic diagram of a structure obtained after forming a word line provided in some embodiments;

[0041] Figure 17 is a schematic diagram of a structure obtained after forming a third mask layer provided in some embodiments;

[0042] Figure 18 A schematic diagram of a structure obtained after forming a stepped structure provided in some embodiments;

[0043] Figure 19 for Figure 18 The structure shown is a cross-sectional schematic diagram along the AA direction;

[0044] Figure 20 is a schematic diagram of a structure obtained after forming an insulating layer provided in some embodiments;

[0045] Figure 21 is a schematic diagram of a structure obtained after forming a fourth mask layer provided in some embodiments;

[0046] Figure 22 A schematic diagram of a structure obtained after forming an etching groove provided in some embodiments;

[0047] Figure 23 for Figure 22 The structure shown is a cross-sectional schematic diagram along the AA direction;

[0048] Figure 24 A schematic diagram of a structure obtained after forming a capacitor receiving groove provided in some embodiments;

[0049] Figure 25 A schematic diagram of a structure obtained after forming a capacitor provided in some embodiments;

[0050] Figure 26 A schematic diagram of a structure obtained after forming a through hole provided in some embodiments;

[0051] Figure 27 FIG. 1 is a schematic diagram of a structure obtained after forming a bit line in some embodiments.

[0052] Description of reference numerals:

[0053] 1-substrate, R1-memory array region, R2-peripheral region, 2-memory array structure, L-stacked structure, L1-isolation layer, L10-isolation material layer, L2-semiconductor layer, L20-semiconductor material layer, M-transistor, 21-strip structure, O-virtual center line, 21A-first strip structure, 21B-second strip structure, 22-gate dielectric layer, P-channel region, C-capacitor, 23-first electrode layer, 24-dielectric layer, 25-second electrode layer, C1-first capacitor, C2-second capacitor, 3-peripheral structure, S-staircase structure, 31-conductive step, 32-insulating step, 4-insulating layer, 41-first insulating layer, 42-second insulating layer, 50-isolation layer, 51-first isolation structure, 52-second isolation structure, 60-word line material layer, BL-bit line, WL-word line, H-through hole, Gw-word line groove, Gk-etching groove, Gc-capacitor accommodating groove, G1-first isolation groove, G2-second isolation groove, Y1-first mask layer, Y2-second mask layer, Y3-third mask layer, Y4-fourth mask layer, Y5-fifth mask layer. DETAILED DESCRIPTION

[0054] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0057] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0059] The present disclosure provides a three-dimensional memory for further improving the storage density and storage capacity of the three-dimensional memory. Figure 1 、 Figure 2 and Figure 3 The three-dimensional memory includes: a memory array structure 2 and a peripheral structure 3 located on a substrate 1. The substrate 1 has a memory array region R1 and a peripheral region R2 surrounding the memory array region R1. The memory array structure 2 is located in the memory array region R1, and the peripheral structure 3 is located in the peripheral region R2. It can be understood that for the convenience of illustrating the internal structures of the memory array structure 2 and the peripheral structure 3, Figure 2 and Figure 3 The insulating layer 4 shown in FIG. Figure 1 to express in .

[0060] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0061] For example, Figure 2As shown in FIG, the memory array structure 2 includes: a plurality of isolation layers L1 and a plurality of semiconductor layers L2 that are alternately stacked.

[0062] In some examples, the material of the isolation layer L1 can be one or a combination of insulating materials such as nitride, oxide, or oxynitride. For example, the isolation layer L1 is a silicon nitride layer.

[0063] In some examples, the semiconductor layer L2 includes, but is not limited to, a polysilicon (Poly) layer.

[0064] In some embodiments, the isolation layer L1 and the semiconductor layer L2 are alternately stacked, and may start from the isolation layer L1 and end with the semiconductor layer L2, or start from the isolation layer L1 and end with the isolation layer L1, or start from the semiconductor layer L2 and end with the isolation layer L1, or start from the semiconductor layer L2 and end with the semiconductor layer L2. In addition, the number of layers of the semiconductor layer L2 can be selected and set according to the product requirements and preparation process of the semiconductor structure. In some of the following embodiments, the storage array structure 2 starts from the isolation layer L1 and ends with the isolation layer L1 as an example for detailed description. In addition, the number of layers of the isolation layer L1 and the semiconductor layer L2 shown in the various figures of the present disclosure is only for schematic expression, and is not a specific limitation on the semiconductor structure.

[0065] For example, Figure 2 As shown in FIG, peripheral structure 3 is disposed around memory array structure 2. Peripheral structure 3 includes at least one stepped structure S and a plurality of bit lines BL. Step structure S includes a plurality of conductive steps 31; conductive steps 31 are connected to semiconductor layer L2. Bit lines BL are disposed on the upper surfaces of corresponding conductive steps 31 and extend in a first direction (e.g., the Z direction) perpendicular to the upper surfaces.

[0066] For example, the bit line BL includes but is not limited to a columnar structure, such as a circular column, a rectangular column, a prism, or a special-shaped column.

[0067] By way of example, the material of the bit line BL includes but is not limited to metal, such as tungsten or copper.

[0068] For example, a first barrier layer ( Figures 1 to 3 (not shown in FIG. 1 ). The first barrier layer may further extend to cover the sidewalls of the bit line BL.

[0069] Illustratively, the first barrier layer includes, but is not limited to, titanium nitride.

[0070] In some examples, such as Figure 2 and Figure 3As shown in FIG, the conductive step 31 and the corresponding semiconductor layer L2 are integrally structured. That is, the conductive step 31 and the corresponding semiconductor layer L2 can be different regions of the same semiconductor material layer, both having the same material and the same number of layers. It can be understood that the conductive step 31 is a doped region of the corresponding semiconductor material layer, and the type and concentration of the doping ion can be set as required to achieve optimal conductivity. Furthermore, the step widths of the conductive steps 31 in the stepped structure S can be the same or different.

[0071] For example, please see Figure 1 、 Figure 2 and Figure 3 The stepped structure S further includes insulating steps 32 disposed between adjacent conductive steps 31. Furthermore, the insulating steps 32 and the corresponding isolation layer L1 are integrally formed. That is, the insulating steps 32 and the corresponding isolation layer L1 can be different regions of the same isolation material layer, with the same material and the same number of layers.

[0072] In some examples, such as Figure 1 As shown in FIG, the outer sidewall of the conductive step 31 facing away from the semiconductor layer L2 is flush with the outer sidewall of the upper adjacent insulating step 32 facing away from the isolation layer L1. In this way, the conductive step 31 and the upper adjacent insulating step 32 can be formed by a single etching process.

[0073] In some examples, the outline shapes of the storage array region R1 and the peripheral region R2 may both be rectangular or circular.

[0074] For example, the outline of the storage array region R1 is a rectangle. The number of the stepped structures S can be one, two, three or four, and one stepped structure S can be located on one side of the rectangle and extend away from the corresponding side of the rectangle.

[0075] For example, the outline of the storage array region R1 is a circle, and the stepped structure S extends outward along the radial direction of the circle.

[0076] In some embodiments, as Figure 1 and Figure 2 As shown in FIG, a plurality of bit lines BL are linearly arranged along the extending direction of the staircase structure S. As shown in FIG.

[0077] In some embodiments, please refer to Figure 1 、 Figure 2 and Figure 3 , the plurality of bit lines BL are located in the same plane away from the surface of the corresponding conductive step 31 .

[0078] In some embodiments, the three-dimensional memory further includes: an insulating layer 4 covering the stepped structure S; wherein the bit line BL passes through the insulating layer 4 , and the surface of the bit line BL away from the corresponding conductive step 31 is flush with the surface of the insulating layer 4 away from the stepped structure S.

[0079] For example, the insulating layer 4 also extends to cover the surface of the memory array structure 2 facing away from the substrate 1 .

[0080] For example, the insulating layer 4 may be a single-layer structure or a stacked-layer structure.

[0081] In some examples, such as Figure 2 and Figure 3 As shown in FIG, the insulating layer 4 includes a first insulating layer 41 and a second insulating layer 42 which are stacked.

[0082] In some embodiments, see Figure 2 and Figure 3 , each semiconductor layer L2 includes: a plurality of strip structures 21 extending along a second direction (for example, the X direction) and arranged in parallel and spaced apart; wherein, the plurality of strip structures 21 in each semiconductor layer L2 are arranged in columns along a first direction (for example, the Z direction) and in rows along a third direction (for example, the Y direction); the second direction (for example, the X direction) and the third direction (for example, the Y direction) are parallel to the upper surface of the semiconductor layer L2 and intersect.

[0083] For example, the memory array structure 2 further includes: a plurality of word lines WL. The word lines WL extend in the same direction as the bit lines BL, for example, perpendicular to the upper surface of the substrate 1. Moreover, one word line WL corresponds to one column of the strip structures 21.

[0084] For example, the strip structure 21 includes a channel region P and contact regions located on both sides of the channel region P, wherein one contact region is connected to the conductive step 31, and the other contact region is connected to the first electrode layer 23 of the capacitor C. Moreover, of the two contact regions of any strip structure 21, one can be a source region, and the other can be a drain region.

[0085] Accordingly, in some examples, the memory array structure 2 further includes: a gate dielectric layer 22 disposed between each strip structure 21 and the corresponding word line WL.

[0086] For example, the gate dielectric layer 22 surrounds the sidewalls of the channel region P of the strip structure 21. In this way, the strip structure 21 and the gate dielectric layer 22 on the sidewalls thereof can constitute a transistor M.

[0087] For example, the gate dielectric layer 22 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0088] In addition, the word line WL is a gate word line, which can be used as a memory word line WL and also as a gate of a corresponding transistor M, thereby controlling the transistor M to be turned on and off.

[0089] For example, the word line WL includes but is not limited to a columnar structure, such as a circular column, a rectangular column, a prism, or a special-shaped column.

[0090] By way of example, the material of the word line WL includes but is not limited to metal, such as metal tungsten or metal copper.

[0091] For example, a second barrier layer ( Figures 1 to 3 not shown).

[0092] Illustratively, the second barrier layer includes, but is not limited to, titanium nitride.

[0093] In some embodiments, see Figure 1 The memory array structure 2 further includes a plurality of capacitors C. The capacitors C are disposed at one end of the corresponding strip structure 21 away from the peripheral structure 3 .

[0094] For example, please combine Figure 1 and Figure 3 It is understood that the capacitor C includes a first electrode layer 23 , a dielectric layer 24 and a second electrode layer 25 which are stacked. The first electrode layer 23 is connected to the end surface of the corresponding strip structure 21 facing away from the peripheral structure 3 .

[0095] Illustratively, the first electrode layer 23 includes but is not limited to a titanium nitride layer.

[0096] Illustratively, the dielectric layer 24 includes, but is not limited to, a HK dielectric layer.

[0097] For example, the second electrode layer 25 includes but is not limited to a metal layer, such as a metal tungsten layer or a metal copper layer.

[0098] For example, a third barrier layer may be further provided between the second electrode layer 25 and the dielectric layer 24. The third barrier layer may be, for example, a titanium nitride layer.

[0099] As described above, each transistor M and the connected capacitor C can constitute a memory cell of 1T1C architecture.

[0100] In some examples, the second electrode layers 25 of the plurality of capacitors C are an integral structure. The dielectric layers 24 of the plurality of capacitors C are an integral structure.

[0101] In some embodiments, see Figure 2 and Figure 3, the multiple strip structures 21 in any semiconductor layer L2 include: a plurality of first strip structures 21A respectively arranged in a first strip structure group, and a plurality of second strip structures 21B respectively arranged in a second strip structure group; wherein, the first strip structure group and the second strip structure group are symmetrical with respect to a virtual center line O as a symmetry axis, and the virtual center line O extends along a third direction (for example, the Y direction), and the third direction (for example, the Y direction) is perpendicular to the second direction (for example, the X direction).

[0102] Accordingly, the plurality of capacitors C include: a first capacitor C1 respectively disposed at an end of the first strip structure 21A away from the peripheral structure 3 , and a second capacitor C2 respectively disposed at an end of the second strip structure 21B away from the peripheral structure 3 .

[0103] For example, the second electrode layer 25 of each first capacitor C1 and each second capacitor C2 is an integral structure. The dielectric layer 24 of each first capacitor C1 and each second capacitor C2 is an integral structure.

[0104] In some examples, such as Figure 3 As shown in FIG, there are two stepped structures S. The two stepped structures S are arranged on the left and right sides of the memory array structure 2 with a virtual center line O as the axis of symmetry. The virtual center line O extends along a third direction (e.g., the Y direction). Accordingly, the conductive steps 31 in one stepped structure S are connected to the first strip structure 21A, and the conductive steps 31 in the other stepped structure S are connected to the second strip structure 21B.

[0105] It is worth mentioning that in some examples, see Figure 1 The three-dimensional memory further includes: a first isolation structure 51 located within the memory array region R1, and a second isolation structure 52 located within the peripheral region R2. The first isolation structure 51 extends along a second direction (e.g., the X direction). Multiple first isolation structures 51 can separate multiple strip structures 21 in a third direction (e.g., the Y direction), thereby effectively isolating transistors M adjacent to each other in the third direction (e.g., the Y direction). The second isolation structure 52 can extend along the contour of the peripheral region R2, for example, along the second direction (e.g., the X direction), to serve as a peripheral isolation structure between the memory array structure 2 and the conductive step 31 within the peripheral region R2.

[0106] Illustratively, the material of the first isolation structure 51 and the second isolation structure 52 is the same as the material of the isolation layer L1 .

[0107] As described above, in the disclosed embodiment, the bit lines BL are disposed in the peripheral region R2. By providing a stepped structure S in the peripheral region R2, the conductive steps 31 within the stepped structure S are connected to the semiconductor layers L2 in the memory array structure 2. Furthermore, the bit lines BL are located on the upper surfaces of the corresponding conductive steps 31 and extend in a first direction perpendicular to the upper surfaces of the conductive steps 31. This not only allows any semiconductor layer L2 to be connected to a corresponding bit line BL via the connected conductive steps 31, thereby reducing the total number of bit lines BL, but also effectively improves the area utilization of the memory array region R1, thereby increasing the plate area of ​​the capacitor C within the memory array region R1, thereby effectively increasing the storage density and storage capacity of the three-dimensional memory.

[0108] This disclosure also provides, according to some embodiments, a method for fabricating a three-dimensional memory device, for use in fabricating the three-dimensional memory devices described in some of the aforementioned embodiments. This method also possesses the technical advantages of the aforementioned three-dimensional memory devices. Furthermore, the aforementioned structure employed in the three-dimensional memory device reduces the difficulty of fabricating the device, thereby improving production efficiency and yield.

[0109] See also Figure 4 The preparation method of the three-dimensional memory includes the following steps.

[0110] S100 , providing a substrate, and alternately stacking isolation material layers and semiconductor material layers on one side of the substrate to form a stacked structure having a memory array region and a peripheral region disposed around the memory array region.

[0111] S200 , patterning the portion of the stacked structure located in the peripheral region to form at least one stepped structure. The stepped structure includes a plurality of conductive steps formed after patterning each semiconductor material layer.

[0112] S300 , forming a bit line on the upper surface of each conductive step, wherein the bit line extends along a first direction perpendicular to the upper surface.

[0113] In some embodiments, see Figure 5 Before step S200 patterns the stacked structure in the peripheral area, the preparation method further includes the following steps.

[0114] S110, patterning the stacked structure in a portion of the memory array area so that each semiconductor material layer is patterned to form a plurality of strip structures. The strip structures extend along a second direction, and the strip structures are arranged in columns along the first direction and in rows along a third direction; the second direction and the third direction are parallel to and intersect the upper surface of the semiconductor material layer.

[0115] S120 , removing portions of each isolation material layer located in the first target region along a first direction to form a plurality of word line trenches; wherein one word line trench exposes a channel region of a column of strip structures.

[0116] S130 , forming a gate dielectric layer in the word line trench to cover the sidewalls of the channel region.

[0117] S140 , forming a word line covering the gate dielectric layer in the word line trench, wherein the extending direction of the word line is the same as the extending direction of the bit line.

[0118] In some embodiments, please refer to Figure 5 , the preparation method also includes the following steps.

[0119] S220 , patterning the portion of the stacked structure located in the memory array area to form an etched groove, wherein the etched groove penetrates the stacked structure and extends along the third direction.

[0120] S230: Based on the etched grooves, portions of each semiconductor material layer located within a second target region are removed to form a plurality of capacitor accommodating grooves. The second target region is located between the wordline grooves and the etched grooves. The capacitor accommodating grooves expose end surfaces of corresponding strip structures on a side adjacent to the etched grooves.

[0121] S240 , forming a capacitor in the capacitor receiving groove.

[0122] In some embodiments, see Figure 6 Step S230 forms a capacitor in the capacitor receiving groove, including the following steps.

[0123] S241: forming a first electrode layer covering the inner wall of the capacitor receiving groove, wherein the first electrode layer is connected to the end surface of the corresponding strip structure close to the etching groove.

[0124] S242, forming a dielectric layer at least covering the first electrode layer.

[0125] S243 , forming a second electrode layer covering the dielectric layer and filling the capacitor receiving groove and the etching groove.

[0126] It is understood that the above steps S220 to S240 can be performed before or after step S300. Some embodiments of the present disclosure illustrate the example of steps S220 to S240 being performed before step S300, but the steps can be implemented in other execution orders for adaptive adjustment.

[0127] In some embodiments, see Figure 5 Before forming the bit lines on the upper surfaces of the conductive steps in step S300, the preparation method further includes the following steps.

[0128] S210 , forming an insulating layer covering the stepped structure.

[0129] S250 , forming a plurality of through holes in the insulating layer to expose corresponding conductive steps.

[0130] Accordingly, step S300 forms a bit line on the upper surface of each conductive step, including filling a conductive material in each through hole to form the bit line.

[0131] It can be understood that some steps in the above-mentioned method for preparing the three-dimensional memory are Figure 4 、 Figure 5 and Figure 6 The steps are shown in the order indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and they can be executed in other orders. Figure 4 、 Figure 5 and Figure 6 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution is not necessarily sequential, but can be performed simultaneously, in turn, or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0132] In order to more clearly illustrate the preparation method of the three-dimensional memory in some of the above embodiments, the following embodiments are exemplarily combined with Figures 7 to 27 Some implementation methods of the preparation method and some of its steps are given.

[0133] In step S100, refer to Figure 7 A substrate 1 is provided, and isolation material layers L10 and semiconductor material layers L20 are alternately stacked on one side of the substrate 1 to form a stacked structure L. The stacked structure L has a memory array region R1 and a peripheral region R2 disposed around the memory array region R1.

[0134] In step S110, please combine Figure 2 、 Figure 3 and Figures 8 to 11 It is understood that the patterned stacked structure L is located in a portion of the memory array region R1, so that each semiconductor material layer L20 is patterned to form a plurality of strip structures 21. The strip structures 21 extend along a third direction (e.g., the Y direction), and each strip structure 21 is arranged in columns along a first direction (e.g., the Z direction) and in rows along a second direction (e.g., the X direction). The third direction (e.g., the Y direction) and the second direction (e.g., the X direction) are parallel to and intersect the upper surface of the semiconductor material layer L20.

[0135] For example, see Figure 8A first mask layer Y1 is formed on the upper surface of the stack structure L. The first mask layer Y1 has a Figure 9 The mask patterns of the positions where the first isolation trench G1 and the second isolation trench G2 are formed are shown.

[0136] See also Figure 9 Based on the mask pattern in the first mask layer Y1, the stacked structure L is etched until the substrate 1 is exposed. A first isolation trench G1 is formed in the memory array region R1, and a second isolation trench G2 is formed in the peripheral region R2. The first isolation trench G1 extends along the second direction (e.g., the X direction), and the plurality of first isolation trenches G1 are used to separate the plurality of strip structures 21 in the third direction (e.g., the Y direction). The second isolation trench G2 is located in the peripheral region R2 and can extend along the contour of the peripheral region R2, for example, along the second direction (e.g., the X direction).

[0137] See also Figure 10 After removing the first mask layer Y1 , an isolation layer 50 is formed to fill the first isolation trench G1 and the second isolation trench G2 and cover the upper surface of the stacked structure L.

[0138] For example, the material of the isolation layer 50 is the same as that of the isolation material layer L1, including but not limited to insulating materials such as nitride, oxide, or oxynitride. The isolation layer 50 is, for example, a silicon nitride layer or a silicon oxide layer.

[0139] See also Figure 11 The isolation layer 50 above the stacked structure L is removed, forming a first isolation structure 51 located in the first isolation trench G1 and a second isolation structure 52 located in the second isolation trench G2. The first isolation structure 51 can effectively isolate transistors M adjacent to each other in the third direction (e.g., the Y direction). The second isolation structure 52 can serve as a peripheral isolation structure for the memory array structure 2 and the conductive step 31 in the peripheral region R2.

[0140] For example, the isolation layer 50 above the stacked structure L is removed by a grinding process, which includes but is not limited to a chemical mechanical polishing (CMP) process.

[0141] In step S120, please combine Figure 2 and Figure 12 、 Figure 13 It is understood that the portion of each isolation material layer L1 located in the first target area is removed along a first direction (eg, Z direction) to form a plurality of word line grooves Gw; wherein one word line groove Gw exposes the channel region P of a column of strip structures 21 .

[0142] For example, see Figure 12, a second mask layer Y2 is formed on the upper surface of the stack structure L, and the second mask layer Y2 has a mask pattern for defining the formation position of the word line WL. Figure 13 Based on the mask pattern in the second mask layer Y2, the stacked structure L is etched along a first direction (e.g., the Z direction) to remove the portion of each isolation material layer L1 within the first target region, thereby forming a wordline trench Gw. Simultaneously, the portion of each semiconductor material layer L20 exposed within the wordline trench Gw corresponds to the channel region P of the strip structure 21.

[0143] In step S130, refer to Figure 14 , a gate dielectric layer 22 is formed in the word line trench Gw to cover the sidewalls of the channel region P.

[0144] Illustratively, the gate dielectric layer 22 is formed by a deposition process.

[0145] The deposition processes mentioned here and below include but are not limited to atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, molecular layer deposition (MLD) process, etc.

[0146] In step S140, refer to Figure 15 , forming a word line material layer 60 that fills the word line groove Gw and covers the upper surface of the stack structure L. Figure 16 , the word line material layer 60 above the stack structure L is removed to form a word line WL located in the word line groove Gw.

[0147] For example, before forming the word line material layer 60, a second barrier layer may be formed conformally covering the surface of the gate dielectric layer 22 and the inner wall of the word line trench Gw. In this way, the word line material layer 60 may be formed on the surface of the second barrier layer and fill the word line trench Gw.

[0148] For example, the second barrier layer and the word line material layer 60 may be formed by a deposition process.

[0149] For example, the word line material layer 60 above the stack structure L is removed by a grinding process, which includes but is not limited to a CMP process.

[0150] In step S200, refer to Figure 17 and Figure 18 The patterned stacked structure L is located in the peripheral region R2 to form at least one stepped structure S. The stepped structure S includes a plurality of conductive steps 31 formed after patterning each semiconductor material layer L20.

[0151] For example, the stepped structure S further includes a plurality of insulating steps 32 formed after each isolation material layer L10 is patterned. The semiconductor material layer L20 and the adjacent isolation material layer L10 thereon can be formed by a single etching process.

[0152] For example, each conductive step 31 in the stepped structure S can be formed by etching one by one from bottom to top. Accordingly, each conductive step 31 can be formed by etching based on the same mask layer or based on different mask layers.

[0153] Here, each conductive step 31 is formed based on a different mask layer, which can be expressed as follows: after a conductive step 31 is formed based on a mask layer, the mask layer is removed and a new mask layer is formed to form another conductive step 31 .

[0154] Here, each conductive step 31 is formed by etching based on the same mask layer, which can be expressed as: after forming a corresponding conductive step 31 based on a mask layer, etching the mask layer to form a new mask pattern to form another conductive step 31 according to the new mask pattern in the mask layer.

[0155] The following is an example of the conductive steps 31 being formed by etching based on the same mask layer.

[0156] For example, see Figure 17 , a third mask layer Y3 is formed on the upper surface of the stacked structure L, and a first mask pattern for defining a first insulating step is formed in the third mask layer Y3. In this way, the stacked structure L can be etched based on the first mask pattern until the first isolation material layer L10 is exposed. Accordingly, after the first insulating step is formed, a second mask pattern for defining a second insulating step and a first conductive step can be formed in the third mask layer Y3. In this way, the stacked structure L can be etched based on the second mask pattern until the second isolation material layer L10 is exposed, thereby forming the first conductive step and the second insulating step adjacent thereto. Furthermore, after the second insulating step is formed, a third mask pattern for defining a third insulating step and a second conductive step can be formed in the third mask layer Y3. In this way, the stacked structure L can be etched based on the third mask pattern until the third isolation material layer L10 is exposed, thereby forming the second conductive step and the third insulating step adjacent thereto. And so on, thereby completing the preparation of the stepped structure S.

[0157] It is understood that the initial thickness of the third mask layer Y3 can be set according to the number of the conductive steps 31 in the stepped structure S to ensure that there is still residual third mask layer Y3 after the stepped structure S is formed without exposing the upper surface of the stacked structure L, for example Figure 18 As shown in .

[0158] For example, see Figure 19In step S200, the patterned stacked structure L is formed in the portion of the peripheral region R2 to form at least one stepped structure S. The process further includes forming two stepped structures S on the left and right sides of the memory array region R1 with the virtual center line O as the axis of symmetry. The virtual center line O extends along a third direction (e.g., the Y direction), which is perpendicular to the second direction (e.g., the X direction).

[0159] It is worth mentioning that in the process of forming the step structure S, if Figure 19 As shown in FIG, the portion of the second isolation structure 52 located in the peripheral region R1 is synchronously stepped.

[0160] In step S210, refer to Figure 20 After forming the stepped structure S, the method for preparing the three-dimensional memory further includes: removing the remaining third mask layer Y3, and forming a first insulating layer 41 covering the stepped structure S and the surface of the remaining third mask layer Y3.

[0161] Here, each surface of the first insulating layer 41 is flat, which can be used to ensure a flat appearance of the three-dimensional memory.

[0162] In step S220, refer to Figures 21 to 23 The patterned stacked structure L is located in the portion of the memory array region R1, forming an etched groove Gk. The etched groove Gk penetrates the stacked structure L and extends along a third direction (eg, the Y direction).

[0163] For example, see Figure 21 A fourth mask layer Y4 is formed on the upper surface of the first insulating layer 41, and a film for defining a Figure 22 The mask pattern of the position where the etching groove Gk is formed is shown.

[0164] See also Figure 22 and Figure 23 The stacked structure L is etched based on the mask pattern in the fourth mask layer Y4 until the substrate 1 is exposed, thereby forming an etched groove Gk in the memory array region R1. The etched groove Gk is formed along the virtual center line O.

[0165] In step S230, refer to Figure 24 Based on the etched groove Gk, the portion of each semiconductor material layer L20 located within the second target region is removed to form a plurality of capacitor accommodating grooves Gc. The second target region is located between the wordline grooves Gw and the etched grooves Gk. The capacitor accommodating grooves Gc expose the end surface of the corresponding strip structure 21 on the side closest to the etched grooves Gk.

[0166] Here, after forming the capacitor accommodating groove Gc, the semiconductor material layers L20 remaining in the memory array region R1 of the stacked structure L respectively constitute corresponding semiconductor layers L2 , and the isolation material layers L10 remaining in the memory array region R1 respectively constitute corresponding isolation layers L1 .

[0167] It can be understood that after the first isolation structure 51 is formed, the plurality of first isolation structures 51 can separate the semiconductor material layer L20 in the memory array region R1 into a plurality of strip structures 21 in the third direction (eg, Y direction). Based on this, after the etching groove Gk is formed, as shown in FIG. Figure 23 As shown in , any semiconductor material layer L20 can be patterned to form a first strip structure group and a second strip structure group that are bilaterally symmetrical with respect to the virtual center line O as the symmetry axis, wherein the first strip structure group includes a plurality of first strip structures 21A arranged in parallel and spaced apart, and the second strip structure group includes a plurality of second strip structures 21B arranged in parallel and spaced apart. Accordingly, as Figure 24 As shown in FIG, the multiple capacitor accommodating grooves Gc formed based on the etched grooves Gk further include: first capacitor accommodating grooves formed on the side of the first strip structure 21A near the etched grooves Gk, and second capacitor accommodating grooves formed on the side of the second strip structure 21B near the etched grooves Gk. Furthermore, the first capacitor accommodating grooves correspond one-to-one with the first strip structure 21A, and the second capacitor accommodating grooves correspond one-to-one with the second strip structure 21B.

[0168] Furthermore, in some examples, such as Figure 23 and Figure 24 As shown in the figure, the two stepped structures S are respectively located on the left and right sides of the storage array area R1 with the virtual center line O as the symmetry axis, and the conductive step 31 of one of the stepped structures S is correspondingly connected to the first strip structure 21A, and the conductive step 31 in the other stepped structure S is correspondingly connected to the second strip structure 21B.

[0169] In step S240, refer to Figure 25 , a capacitor is formed in the capacitor receiving groove Gc, for example, a first capacitor C1 is formed in the first capacitor receiving groove, and a second capacitor C2 is formed in the second capacitor receiving groove.

[0170] Illustratively, forming the capacitor C in the capacitor receiving groove Gc includes steps S241 to S243 .

[0171] In step S241 , a first electrode layer 23 is formed to cover the inner wall of the capacitor receiving groove Gc.

[0172] Here, the first electrode layer 23 conformally covers the inner wall of the corresponding capacitor accommodating groove Gc and is connected to the end surface of the corresponding strip structure 21 on the side close to the etched groove Gk. The first electrode layer 23 can be formed using an ALD process. Furthermore, the first electrode layers 23 in adjacent capacitor accommodating grooves Gc in a first direction (e.g., the Z direction) can be insulated by an isolation layer L1, and the first electrode layers 23 in adjacent capacitor accommodating grooves Gc in a third direction (e.g., the Y direction) can be insulated by a first isolation structure 51.

[0173] In step S242 , a dielectric layer 24 is formed to at least cover the first electrode layer 23 .

[0174] Here, if Figure 25 As shown in FIG, the dielectric layer 24 can be formed using an ALD process. The dielectric layer 24 conformally covers the inner surface of the first electrode layer 23 and extends to cover the inner wall of the etched groove Gk. In this way, the dielectric layer 24 in each first capacitor C1 and each second capacitor C2 is an integrated structure.

[0175] In step S243, a second electrode layer 25 is formed to cover the dielectric layer 24 and fill the capacitor receiving groove Gc and the etching groove Gk. In this way, the second electrode layer 25 in each first capacitor C1 and each second capacitor C2 is an integrated structure.

[0176] In some examples, the dielectric layer 24 and the second electrode layer 25 can be obtained by sequentially stacking a dielectric material layer and a second electrode material layer and then grinding and removing the dielectric material layer and the second electrode material layer above the first insulating layer 41 .

[0177] For example, the top surface of the dielectric layer 24 and the top surface of the second electrode layer 25 are both flush with the surface of the first insulating layer 41 facing away from the substrate 1 .

[0178] In addition, in some examples, before forming the second electrode layer 25 , a third barrier layer conformally covering the dielectric layer 24 may be formed first, and then the second electrode layer 25 conformally covering the third barrier layer and filling the capacitor receiving groove may be formed.

[0179] In step S250, refer to Figure 26 , a plurality of through holes H are formed in the insulating layer 4 to expose the corresponding conductive steps 31 .

[0180] Here, the through hole H extends along a first direction (eg, Z direction). Furthermore, the through holes H located on either side of the memory array region R1 may be linearly arranged along the extension direction of the stepped structure S, such as along a second direction (X direction).

[0181] Illustratively, the through hole H also extends through the adjacent insulating step 32 above the corresponding conductive step 31 .

[0182] In some examples, such as Figure 26 As shown in FIG, a second insulating layer 42 is formed covering the first insulating layer 41 and the capacitor C, so that the first insulating layer 41 and the second insulating layer 42 together constitute the aforementioned insulating layer 4. A fifth mask layer Y5 is formed on the upper surface of the second insulating layer 42, and a mask pattern for defining the position where the bit line BL is to be formed is formed in the fifth mask layer Y5. Based on the mask pattern in the fifth mask layer Y5, the insulating layer 4 (including the second insulating layer 42 and the first insulating layer 41) and the corresponding insulating step 32 are etched until the corresponding conductive step 31 is exposed, thereby forming a through hole H.

[0183] In step S300, refer to Figure 27 Conductive materials are filled into each through hole to form a plurality of bit lines BL. Each bit line BL is located on the upper surface of the corresponding conductive step 31 and extends perpendicular to the first direction (eg, the Z direction).

[0184] For example, the conductive material is a metal material, such as metal tungsten or metal copper.

[0185] For example, before filling the conductive material, a first barrier layer may be formed to conformally cover the inner wall of the through hole H. In this way, the conductive material covers the surface of the first barrier layer and fills the through hole H to form the bit line BL.

[0186] For example, the conductive material filling can be performed before removing the fifth mask layer Y5. Thus, the conductive material can be deposited to cover the upper surface of the fifth mask layer Y5. Then, the fifth mask layer Y5 and excess conductive material above the insulating layer 4 can be removed by a grinding process. This ensures that the top surface of the bit line BL is flush with the upper surface of the insulating layer 4, for example, flush with the upper surface of the second insulating layer 42.

[0187] It should be noted that the "one-time etching process" mentioned in some of the above embodiments can be understood as: etching based on the pattern of the same mask layer to form the same pattern; it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.

[0188] In addition, the “etching” mentioned in some of the above embodiments may also be matched with the etching requirements, such as dry etching, wet etching, or a combination of dry etching and wet etching.

[0189] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0190] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A three-dimensional memory, characterized in that: include: A memory array structure comprising: a plurality of isolation layers and a plurality of semiconductor layers stacked alternately; and A peripheral structure is provided on the peripheral side of the storage array structure; the peripheral structure includes: At least one stepped structure; the stepped structure includes a plurality of conductive steps; the conductive steps are correspondingly connected to the semiconductor layer; A plurality of bit lines; the bit lines are arranged on the upper surface corresponding to the conductive step and extend along a first direction perpendicular to the upper surface; Each of the semiconductor layers includes: a plurality of strip structures extending along a second direction and arranged in parallel and spaced apart; wherein the plurality of strip structures in each of the semiconductor layers are arranged in columns along the first direction and in rows along a third direction; the second direction and the third direction are parallel to and intersect with the upper surface of the semiconductor layer; The storage array structure further comprises: a plurality of capacitors; the capacitors are arranged at one end of the strip structure away from the peripheral structure; the capacitors comprise a first electrode layer, a dielectric layer, and a second electrode layer that are stacked; The plurality of strip structures in any of the semiconductor layers include: a plurality of first strip structures respectively arranged in a first strip structure group, and a plurality of second strip structures respectively arranged in a second strip structure group; wherein the first strip structure group and the second strip structure group are bilaterally symmetrical with respect to a virtual center line as an axis of symmetry, and the virtual center line extends along the third direction, and the third direction is perpendicular to the second direction; The plurality of capacitors include: first capacitors respectively arranged at one end of the first strip structure facing away from the peripheral structure, and second capacitors respectively arranged at one end of the second strip structure facing away from the peripheral structure; wherein the second electrode layer of each of the first capacitors and each of the second capacitors is an integral structure; Among them, the number of the stepped structures is two, and the two stepped structures are arranged on the left and right sides of the storage array structure with the virtual center line as the axis of symmetry; among them, the conductive steps in one of the stepped structures correspond to the first strip structure, and the conductive steps in the other stepped structure correspond to the second strip structure.

2. The three-dimensional memory according to claim 1, wherein: A plurality of the bit lines are linearly arranged along an extending direction of the staircase structure.

3. The three-dimensional memory according to claim 1, wherein: The plurality of bit lines are located in the same plane away from surfaces corresponding to the conductive steps.

4. The three-dimensional memory according to claim 3, wherein: Also includes: An insulating layer covering the stepped structure; wherein the bit line passes through the insulating layer, and a surface of the bit line facing away from the corresponding conductive step is flush with a surface of the insulating layer facing away from the stepped structure.

5. The three-dimensional memory according to claim 1, wherein: The conductive step and the correspondingly connected semiconductor layer are an integrated structure.

6. The three-dimensional memory according to claim 1, wherein: The stepped structure further includes: insulating steps arranged between adjacent conductive steps; the insulating steps and the corresponding isolation layers are an integral structure.

7. The three-dimensional memory according to any one of claims 1 to 6, wherein: The strip structure includes a channel region; The storage array structure further includes: A plurality of word lines; the word lines extend in the same direction as the bit lines, and one word line corresponds to one column of the strip structures; The gate dielectric layer is disposed between each of the channel regions and the corresponding word line.

8. The three-dimensional memory according to claim 7, wherein: The first electrode layer is connected to the end surface of the corresponding strip structure away from the peripheral structure; the second electrode layers of the plurality of capacitors are an integrated structure.

9. A method for preparing a three-dimensional memory, characterized in that: include: Providing a substrate, and alternately stacking isolation material layers and semiconductor material layers on one side of the substrate to form a stacked structure; The stacked structure comprises a storage array area and a peripheral area arranged around the storage array area; Patterning the portion of the stacked structure located in the peripheral region to form at least one stepped structure; the stepped structure includes a plurality of conductive steps formed after patterning each of the semiconductor material layers; forming a bit line on the upper surface of each of the conductive steps, wherein the bit line extends in a direction perpendicular to the upper surface; Before patterning the portion of the stacked structure located in the peripheral area, the preparation method further includes: Patterning a portion of the stacked structure located in the memory array area so that each of the semiconductor material layers forms a plurality of strip structures after patterning, wherein the strip structures extend along a second direction, and each of the strip structures is arranged in a column along the first direction and in a row along a third direction; the second direction and the third direction are parallel to and intersect with the upper surface of the semiconductor material layer; Wherein, the preparation method further comprises: Patterning a portion of the stacked structure located in the memory array area to form an etched groove, wherein the etched groove penetrates the stacked structure and extends along the third direction; forming a plurality of capacitor accommodating grooves, wherein the capacitor accommodating grooves expose end surfaces of corresponding strip structures close to a side of the etched groove; forming a capacitor in the capacitor receiving groove, wherein the capacitor is disposed at an end of the strip structure away from the peripheral area; The capacitor is formed in the capacitor receiving groove, comprising: forming a first electrode layer covering the inner wall of the capacitor receiving groove; forming a dielectric layer covering at least the first electrode layer; forming a second electrode layer covering the dielectric layer and filling the capacitor receiving groove and the etching groove; The plurality of strip structures in any of the semiconductor material layers include: a plurality of first strip structures respectively arranged in a first strip structure group, and a plurality of second strip structures respectively arranged in a second strip structure group; wherein the first strip structure group and the second strip structure group are bilaterally symmetrical with respect to a virtual center line as an axis of symmetry, and the virtual center line extends along the third direction, and the third direction is perpendicular to the second direction; The plurality of capacitors include: first capacitors respectively disposed at ends of the first strip structures facing away from the peripheral region, and second capacitors respectively disposed at ends of the second strip structures facing away from the peripheral region; wherein the second electrode layers of the first capacitors and the second capacitors are integrally formed; Among them, the number of the stepped structures is two, and the two stepped structures are arranged on the left and right sides of the storage array area with the virtual center line as the symmetry axis; among them, the conductive step in one of the stepped structures corresponds to the first strip structure, and the conductive step in the other stepped structure corresponds to the second strip structure.

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