DDR controller test system and method based on FPGA platform

Abstract

The present invention provides a DDR controller test system and method based on an FPGA platform, wherein the system comprises: a host computer, a DDR controller to be verified arranged on the FPGA platform, a DDR PHY and a DDR particle; wherein the host computer is connected to an embedded processor via a preset interface, the embedded processor is connected to the DDR controller, the DDR PHY is connected to the DDR controller, and the DDR particle is connected to the DDR PHY; the host computer is used to send configuration parameters to the embedded processor via the preset interface, the embedded processor generates relevant test parameters according to the configuration parameters and sends them to the DDR controller and the DDR PHY; the DDR controller, the DDR PHY and the DDR particle perform relevant test operations according to the test parameters. The above invention can complete the independent test of the DDR controller.

Description

Technical Field

[0001] The present invention relates to the field of chip detection technology, and more specifically, to a DDR controller testing system and method based on an FPGA platform. Background Art

[0002] At present, DDR SDRAM (Double Data Rate) mainly refers to SDRAM using DDR technology. Its memory interface is usually divided into two parts: memory control logic (MC) and physical layer interface (PHY). The DDR PHY is a physical layer interface used to control and manage the DDR memory interface, connecting DDR particles and DDR controller.

[0003] However, the current FPGA (Field Programmable Gate Array) platform can only provide a fusion version of DDR PHY and DDR controller, and cannot effectively split these two functional modules. Therefore, if you need to verify the self-developed DDR controller separately, you need to forward it to the FPGA DDR controller through a bridge, and then indirectly control the data communication of PHY through the FPGADDR controller. It can be seen that this method will lead to certain limitations in the functional verification of the DDR controller, and the verification is not sufficient.

[0004] Therefore, there is an urgent need for an FPGA platform verification system that can effectively complete the independent functional verification of the DDR controller. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a DDR controller testing system and method based on an FPGA platform to solve the problems that the existing verification method requires bridging, resulting in certain limitations in DDR controller function verification and insufficient verification.

[0006] The present invention provides a DDR controller test system based on an FPGA platform, comprising: a host computer, a DDR controller to be verified, a DDR PHY and a DDR particle arranged on the FPGA platform; wherein the host computer is connected to an embedded processor of the FPGA platform through a preset interface, the embedded processor is connected to the DDR controller, the DDR PHY is connected to the DDR controller, and the DDR particle is connected to the DDR PHY; the host computer is used to send configuration parameters to the embedded processor through the preset interface, the embedded processor generates relevant test parameters according to the configuration parameters and sends them to the DDR controller and the DDR PHY; the DDR controller, the DDR PHY and the DDR particle perform relevant test operations according to the test parameters.

[0007] In addition, an optional technical solution is that the preset interface includes a PCIE interface and an AXI bridge connected to each other; wherein the host computer is connected to the embedded processor via the PCIE interface and the AXI bridge in sequence; and the DDR controller is connected to the embedded processor via the AXI bridge.

[0008] In addition, an optional technical solution is that it also includes an AXI to APB interface connected to the AXI bridge, and the AXI to APB interface is connected to the DDR controller and the DDR PHY respectively; wherein the embedded processor configures system parameters of the DDR controller and the DDR PHY through the AXI bridge and the AXI to APB interface in turn.

[0009] In addition, an optional technical solution is that the DDR PHY includes a clock reset submodule, a power-on initialization submodule, an APB function configuration submodule, a command / address processing submodule, a data processing submodule, a simple MC controller submodule, a DFI interface adapter submodule, and an IO serial-to-parallel conversion submodule; wherein the DDR PHY is connected to the DDR controller through the DFI interface adapter submodule, and is connected to the DDR particles through the IO serial-to-parallel conversion submodule.

[0010] In addition, an optional technical solution is that the IO serial-to-parallel conversion submodule includes a C / A conversion submodule connected to the power-on initialization submodule and the command / address processing submodule, and a data conversion submodule connected to the data processing submodule; wherein the DDR PHY sends read and write commands and address information to the DDR particles through the C / A conversion submodule; and, through the data conversion submodule, it is connected to the DDR particles to transmit read data or write data.

[0011] In addition, an optional technical solution is to perform relevant test operations according to the test parameters, including a data reading and writing training process and a data reading and writing test process; wherein the data reading and writing training process includes: sending training write data to the command / address processing submodule through the simple MC controller submodule, and sending write commands and address information to the C / A conversion submodule through the command / address processing submodule, and sending the training write data to the data processing submodule; the data processing submodule performs write processing on the training write data, and sends the processed data to the DDR particles through the data conversion submodule, and at the same time, the C / A conversion submodule converts the write command and address information and sends them to the DDR particles; the DDR particles process the processed data according to the converted write commands and address information. The simple MC controller submodule performs a data writing operation; sends a data read command to the command / address processing submodule through the simple MC controller submodule, and sends a read command and address information to the C / A conversion submodule through the command / address processing submodule; the C / A conversion submodule converts the read command and address information and sends them to the DDR particles, so that the DDR particles obtain corresponding training read data according to the converted read command and address information and send them to the data processing submodule through the data conversion submodule; the data processing submodule performs read and write processing and delay control processing on the training read data and then feeds back to the simple MC controller submodule; the simple MC controller submodule adjusts the delay time according to the sent training write data and the obtained training read data to complete the data reading and writing training process.

[0012] In addition, an optional technical solution is that the data read and write test process includes: the embedded processor sends a write command and address information and test write data to the DDR PHY through the AXI bridge, the DDR controller and the DFI interface adapter module in sequence, and the DDR particle performs a write operation on the test write data according to the write command and address information; the embedded processor sends a read command and address information to the DDR PHY through the AXI bridge, the DDR controller and the DFI interface adapter module in sequence, and the DDR particle obtains corresponding test read data according to the read command and address information, and feeds back to the embedded processor through the DDR PHY; the embedded processor determines the test result of the DDR controller according to the test write data and the test read data.

[0013] In addition, an optional technical solution is that the DDR particles include DDR4 particles, DDR5 particles, LPDDR4 particles and LPDDR5 particles.

[0014] In addition, an optional technical solution is that the test parameters include test instructions and test data.

[0015] On the other hand, the present invention also provides a DDR controller testing method based on an FPGA platform, using the above-mentioned DDR controller testing system based on an FPGA platform to test a target DDR controller, the method comprising: setting configuration parameters through a host computer and sending them to an embedded processor through a preset interface; the embedded processor generates relevant test parameters according to the configuration parameters and sends them to the DDR controller and DDR PHY; the DDR controller, the DDR PHY and the DDR particles perform relevant test operations according to the test parameters.

[0016] By utilizing the above-mentioned DDR controller testing system and method based on FPGA platform, when testing the target DDR controller, the user can set the configuration parameters through the host computer and send them to the embedded processor of the FPGA platform. The embedded processor generates relevant test parameters according to the configuration parameters and sends them to the DDR controller and DDR PHY, so that the DDR controller, DDRPHY and DDR particles perform relevant test operations according to the test parameters. The DDR controller directly faces the interface of DDR PHY, and the functional test is more sufficient and comprehensive, and can support multiple types and modes of DDR controllers.

[0017] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0019] Figure 1 A schematic diagram of a DDR controller test system based on an FPGA platform according to an embodiment of the present invention;

[0020] Figure 2 A data sending and receiving flow chart of a DDR controller test system based on an FPGA platform according to an embodiment of the present invention;

[0021] Figure 3 A configuration flow chart of a DDR controller test system based on an FPGA platform according to an embodiment of the present invention;

[0022] Figure 4A structural schematic diagram of a DDR PHY according to an embodiment of the present invention;

[0023] Figure 5 A power-on initialization flow chart of a DDR PHY according to an embodiment of the present invention;

[0024] Figure 6 A flowchart of data reading and writing training of DDR PHY according to an embodiment of the present invention;

[0025] Figure 7 FIG. 4 is a flow chart of a data read and write test of a DDR PHY according to an embodiment of the present invention.

[0026] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0027] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0029] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the field to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0030] To describe in detail the FPGA-based DDR controller testing system and method of the present invention, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Figures 1 to 7 The schematic principles of the DDR controller testing system based on the FPGA platform according to the embodiment of the present invention are shown from different angles.

[0032] like Figures 1 to 7 As shown together, the DDR controller test system based on the FPGA platform of the embodiment of the present invention includes: a host computer, a DDR controller to be verified set on the FPGA platform, a DDR PHY and a DDR particle; wherein the host computer is connected to the embedded processor of the FPGA platform through a preset interface, the embedded processor is connected to the DDR controller, the DDR PHY is connected to the DDR controller, and the DDR particle is connected to the DDR PHY; system software can be installed in the host computer, so that the user can configure relevant configuration parameters, such as DDR parameters and test sequences, and send the configuration parameters to the embedded processor through the preset interface, the embedded processor generates relevant test parameters (including test instructions and test data) according to the configuration parameters and sends them to the DDR controller and DDR PHY; finally, the DDR controller, DDR PHY and DDR particles perform relevant test operations (including instruction sending and data reading and writing, etc.) according to the test parameters, and output the final test results through the embedded processor, and display them on the host computer, so that the user can grasp the relevant test information in time.

[0033] The above-mentioned preset interface further includes a PCIE interface and an AXI bridge connected to each other; wherein the host computer is connected to the embedded processor via the PCIE interface and the AXI bridge in sequence; and the DDR controller and the embedded processor can also be connected via the AXI bridge, such as Figure 2 As shown by the red dotted line in the figure, the data transmission between the host computer and the embedded processor can be completed through the PCIE interface and the AXI bridge, while the data transmission between the embedded processor and the DDR particles can be completed through the AXI bridge, FFR controller and DDR PHY.

[0034] In addition, when the embedded processor configures system parameters according to the instructions of the host computer, such as Figure 3 As shown, the embedded processor generates relevant test parameters according to the configuration parameters sent by the host computer and sends them to the DDR controller and DDR PHY. At this time, it also includes an AXI to APB interface connected to the AXI bridge. The AXI to APB interface is connected to the DDR controller and DDR PHY respectively. The embedded processor configures system parameters of the DDR controller and DDR PHY through the AXI bridge and the AXI to APB interface in turn. It can be seen that the AXI to APB interface is mainly used for protocol conversion of data and signals, so it can be applied to different scenarios. Specifically, the bus bridging setting can be flexibly performed according to application requirements.

[0035] like Figure 4As shown, in the test system of the present invention, the DDR PHY further includes a clock reset submodule, a power-on initialization submodule, an APB function configuration submodule, a command / address processing submodule, a data processing submodule, a simple MC controller submodule, a DFI interface adapter submodule, and an IO serial-to-parallel conversion submodule; wherein, the DDR PHY is connected to the DDR controller through the DFI interface adapter submodule, and is connected to the DDR particles through the IO serial-to-parallel conversion submodule, and the data processing submodule includes functions such as data reading and writing, delay control, and alignment training.

[0036] DFI stands for DDR PHY Interface, which is the industry standard interface between DDR controller and DDR PHY. The DFI protocol defines the signal, timing and interaction behavior of the interface between the controller and PHY. After the DFI standardizes the PHY interface, it can enhance the interoperability between DDR controllers / PHY IPs of different manufacturers and reduce the cost of integrated development of DDR subsystems.

[0037] Specifically, the IO serial-to-parallel conversion submodule includes a C / A conversion submodule (i.e., IO serial-to-parallel conversion cmd / adder) connected to the power-on initialization submodule and the command / address processing submodule, and a data conversion submodule (i.e., IO serial-to-parallel conversion data) connected to the data processing submodule; wherein, the DDR PHY sends read and write commands and address information to the DDR particles through the C / A conversion submodule; and, through the data conversion submodule, it is connected to the DDR particles to transmit read data or write data. The above-mentioned C / A conversion submodule is connected to the DDR particles through the c / a control line, and the data conversion submodule is connected to the DDR particles through the data line. However, by independently modularizing the DDR PHY, it can be connected to the DDR controller. As a core component, it can get rid of the limitations of the FPGA platform itself, provide a DFI / APB interface to the outside, and support data intercommunication of various types of DDR controllers.

[0038] As a specific example, the working process of DDR PHY can be divided into several stages: power-on initialization, data read and write training, and data read and write test. Figure 5 The power-on initialization process of the DDR PHY according to an embodiment of the present invention is shown. When the power-on initialization configuration of the HHR particle is performed, it will be slightly different for different DDR particles, such as DDR4 particles, DDR5 particles, LPDDR4 particles, and LPDDR5 particles, but the general configuration process is as follows:

[0039] 1. Unset RESET and activate CKE (ClockEnable, clock enable signal);

[0040] 2. Enable clock CK_t / CK_c to realize differential clock input;

[0041] 3. Issue the MRS command and load the mode registers in the preset order;

[0042] 4. Perform ZQ calibration;

[0043] 5. Put the DDR particles into IDLE state to complete the initialization configuration.

[0044] Among them, after the initialization is completed, the DDR particles are in an idle state, but the memory still cannot run. At this time, the data read and write training process needs to be performed through the DDR PHY, and then data can be written to the DDR particles or valid data can be read from the DDR particles.

[0045] Specifically, Figure 6 The DDR PHY data reading and writing training process according to an embodiment of the present invention is illustrated.

[0046] like Figure 6 As shown, the DDR PHY data reading and writing training process of the embodiment of the present invention includes:

[0047] 1. Send training write data to the command / address processing submodule through the simple MC controller submodule (as the stimulus source of the training process, which can generate relevant instructions and data), and send write commands and address information to the C / A conversion submodule through the command / address processing submodule, and send training write data to the data processing submodule;

[0048] 2. The data processing submodule processes the training write data and sends the processed data to the DDR particles through the data conversion submodule. At the same time, the C / A conversion submodule converts the write command and address information and sends them to the DDR particles.

[0049] 3. The DDR particles write the processed data according to the converted write command and address information; send the data read command to the command / address processing submodule through the simple MC controller submodule, and send the read command and address information to the C / A conversion submodule through the command / address processing submodule;

[0050] 4. The C / A conversion submodule converts the read command and address information and sends them to the DDR particles, so that the DDR particles obtain the corresponding training read data according to the converted read command and address information and send them to the data processing submodule through the data conversion submodule;

[0051] 5. The data processing submodule performs read and write processing and delay control processing on the training read data and then feeds back to the simple MC controller submodule; the simple MC controller submodule adjusts the delay time according to the sent training write data and the obtained training read data to complete the data reading and writing training process. It should be noted that each delay parameter will be trained once, so as to obtain the training result of each delay, which will be fed back to the embedded processor, and finally the reasonable range of the delay parameter will be obtained. The embedded processor will then select the optimal delay parameter in the reasonable range and reset it to the DDR PHY.

[0052] It can be seen that since the delay required by DDR particles at different rates is different, the main purpose of the above data read and write training is to adjust the delay so that the current delay parameters are within the optimal range. After the data read and write training is completed, the data read and write test can be performed. During the data read and write test, the simple MC controller submodule will release the read and write control and data paths, which will be accessed by the external DDR controller and enter the DFI data read and write process.

[0053] Specifically, Figure 7 The DDR PHY data reading and writing test process according to an embodiment of the present invention is shown.

[0054] like Figure 7 As shown, the DDR PHY data reading and writing test process of the embodiment of the present invention includes:

[0055] 1. The embedded processor sends write commands, address information, and test write data to the DDR PHY through the AXI bridge, DDR controller, and DFI interface adapter module in sequence. The DDR particles perform write operations on the test write data according to the write commands and address information.

[0056] 2. The embedded processor sends read commands and address information to the DDR PHY through the AXI bridge, DDR controller and DFI interface adapter module in sequence. The DDR particles obtain the corresponding test read data according to the read commands and address information, and feed it back to the embedded processor through the DDR PHY.

[0057] 3. Finally, the embedded processor determines the test result of the DDR controller based on the test write data and the test read data.

[0058] Specifically, similar to the data read and write training process, in the data read and write test process, the DFI interface adapter submodule first obtains the test write data sent by the DDR controller to the command / address processing submodule, and sends the write command and address information to the C / A conversion submodule through the command / address processing submodule, and sends the test write data to the data processing submodule; then, the data processing submodule writes the test write data, and sends the processed data to the DDR particles through the data conversion submodule, and at the same time, the C / A conversion submodule converts the write command and address information and sends it to the DDR particles. Then, the DDR particles write the processed test write data according to the converted write command and address information.

[0059] Then, the data read command is sent to the command / address processing submodule through the DDR controller, and the read command and address information are sent to the C / A conversion submodule through the command / address processing submodule; the C / A conversion submodule converts the read command and address information and sends them to the DDR particles, so that the DDR particles obtain the corresponding test read data according to the converted read command and address information and send them to the data processing submodule through the data conversion submodule;

[0060] Then, the data processing submodule reads and writes the test read data and feeds it back to the DDR controller, which then feeds it back to the embedded processor through the DDR controller. Finally, the embedded processor determines whether the verification is passed based on the comparison between the sent test write data and the acquired test read data. If the data cannot be reliably written or read or an error occurs in the data, the error information is reported to the host computer through the PCIE interface.

[0061] Corresponding to the above-mentioned DDR controller testing system based on FPGA platform, the present invention also provides a DDR controller testing method based on FPGA platform, and uses the above-mentioned DDR controller testing system based on FPGA platform to test the target DDR controller.

[0062] Specifically, the DDR controller testing method based on the FPGA platform of the embodiment of the present invention includes: setting configuration parameters through a host computer and sending them to an embedded processor through a preset interface; the embedded processor generates relevant test parameters according to the configuration parameters and sends them to the DDR controller and DDR PHY; the DDR controller, DDR PHY and DDR particles perform relevant test operations according to the test parameters.

[0063] It should be noted that the embodiments of the DDR controller testing method based on FPGA platform provided by the present invention can refer to the description in the embodiment of the DDR controller testing system based on FPGA platform, which will not be described in detail here.

[0064] According to the FPGA platform-based DDR controller testing system and method of the present invention, by independently modularizing DDR PHY, it is possible to support various types and modes of DDR controllers, and can be applied to the verification process before chip SOC tape-out. The DDR controller directly faces the DDR PHY interface, and the function verification is more sufficient and comprehensive, the timing is adjustable and controllable, the application field is wide, and the test effect is accurate and reliable.

[0065] As described above, the DDR controller test system and method based on the FPGA platform according to the present invention are described by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various improvements can be made to the DDR controller test system and method based on the FPGA platform proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A DDR controller test system based on FPGA platform, characterized in that: include: The host computer, the DDR controller to be verified, the DDR PHY and the DDR particles set on the FPGA platform; wherein, The host computer is connected to the embedded processor of the FPGA platform through a preset interface, the embedded processor is connected to the DDR controller, the DDR PHY is connected to the DDR controller, and the DDR particles are connected to the DDR PHY; The host computer is used to send the configuration parameters to the embedded processor through the preset interface, and the embedded processor generates relevant test parameters according to the configuration parameters and sends them to the DDR controller and the DDR PHY; The DDR controller, the DDR PHY and the DDR particles perform related test operations according to the test parameters; The preset interface includes a PCIE interface and an AXI bridge connected to each other; The DDR controller test system based on the FPGA platform also includes an AXI to APB interface connected to the AXI bridge, and the AXI to APB interface is connected to the DDR controller and the DDR PHY respectively; wherein, The embedded processor sequentially configures system parameters of the DDR controller and the DDR PHY through the AXI bridge and the AXI to APB interface.

2. The DDR controller test system based on FPGA platform according to claim 1, characterized in that: The host computer is connected to the embedded processor via the PCIE interface and the AXI bridge in sequence; and the DDR controller is connected to the embedded processor via the AXI bridge.

3. The DDR controller test system based on FPGA platform according to claim 1, characterized in that: The DDR PHY includes a clock reset submodule, a power-on initialization submodule, an APB function configuration submodule, a command / address processing submodule, a data processing submodule, a simple MC controller submodule, a DFI interface adapter submodule, and an IO serial-to-parallel conversion submodule; wherein, The DDR PHY is connected to the DDR controller via the DFI interface adapter submodule, and is connected to the DDR particles via the IO serial-to-parallel conversion submodule.

4. The DDR controller test system based on FPGA platform according to claim 3, characterized in that: The IO serial-to-parallel conversion submodule includes a C / A conversion submodule connected to the power-on initialization submodule and the command / address processing submodule, and a data conversion submodule connected to the data processing submodule; wherein, The DDR PHY sends read and write commands and address information to the DDR particles through the C / A conversion submodule; and is connected to the DDR particles through the data conversion submodule to transmit read data or write data.

5. The DDR controller test system based on FPGA platform according to claim 4, characterized in that: Execute relevant test operations according to the test parameters, including a data reading and writing training process and a data reading and writing test process; wherein the data reading and writing training process includes: Sending training write data to the command / address processing submodule through the simple MC controller submodule, sending write commands and address information to the C / A conversion submodule through the command / address processing submodule, and sending the training write data to the data processing submodule; The data processing submodule performs write processing on the training write data, and sends the processed data to the DDR particle through the data conversion submodule. Meanwhile, the C / A conversion submodule converts the write command and address information and sends them to the DDR particle. The DDR particles perform a write operation on the processed data according to the converted write command and address information; Sending a data read command to the command / address processing submodule through the simple MC controller submodule, and sending a read command and address information to the C / A conversion submodule through the command / address processing submodule; The C / A conversion submodule converts the read command and address information and sends them to the DDR particle, so that the DDR particle obtains corresponding training read data according to the converted read command and address information and sends them to the data processing submodule through the data conversion submodule; The data processing submodule performs read and write processing and delay control processing on the training read data and then feeds back to the simple MC controller submodule; The simple MC controller submodule adjusts the delay time according to the sent training write data and the acquired training read data to complete the data reading and writing training process.

6. The DDR controller test system based on FPGA platform according to claim 5, characterized in that: The data reading and writing test process includes: The embedded processor sends a write command and address information and test write data to the DDR PHY through the AXI bridge, the DDR controller and the DFI interface adapter module in sequence, and the DDR particle performs a write operation on the test write data according to the write command and address information; The embedded processor sends a read command and address information to the DDR PHY through the AXI bridge, the DDR controller and the DFI interface adapter module in sequence, and the DDR particle obtains corresponding test read data according to the read command and address information, and feeds back to the embedded processor through the DDR PHY; The embedded processor determines a test result of the DDR controller according to the test write data and the test read data.

7. The DDR controller test system based on FPGA platform according to claim 1, characterized in that: The DDR particles include DDR4 particles, DDR5 particles, LPDDR4 particles and LPDDR5 particles.

8. The DDR controller test system based on FPGA platform according to claim 1, characterized in that: The test parameters include test instructions and test data.

9. A DDR controller testing method based on FPGA platform, characterized in that: Using the FPGA platform-based DDR controller test system as claimed in any one of claims 1 to 8 to test the target DDR controller, the method comprising: Set configuration parameters through the host computer and send them to the embedded processor through the preset interface; The embedded processor generates relevant test parameters according to the configuration parameters and sends them to the DDR controller and DDRPHY; The DDR controller, the DDR PHY and the DDR particles perform related test operations according to the test parameters.

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