Display panel, display device and display method

Abstract

The present disclosure provides a display panel, a display device and a display method, and relates to the technical field of display. The display panel comprises a pixel array, comprising a plurality of pixel units; a driving circuit, comprising Q data pins and N control pins, Q and N are integers greater than 1; a control circuit, electrically connected with M data pins in the Q data pins, the N control pins and the plurality of pixel units, M < Q, M is a positive integer, and the control circuit is configured to output M data signals from the M data pins to the plurality of pixel units under the control of N control signals from the N control pins; wherein the data signals comprise N data sub-signals, and the N data sub-signals are respectively written into N columns of pixel units in the plurality of pixel units under the control of the N control signals.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel, display device, and display method. Background Technology

[0002] Some display products typically drive pixel units in a one-to-many manner. For example, data signals are provided to multiple pixel units via a single source line. As the requirements for narrow bezels in display panels gradually increase, it is necessary to provide data signals to more pixel units via a single source line to reduce the number of source lines, thereby effectively narrowing the bezels.

[0003] However, as the amount of data in the pixel units that the source line needs to connect increases, the connection method between the source line and the pixel units and driver chip in the display panel will change accordingly. Furthermore, the connection method between the source line and the driver chip will also affect the size of the driver chip, thus having an adverse effect on narrowing the bezel. Summary of the Invention

[0004] This disclosure provides a display panel, a display device, and a display method.

[0005] According to a first aspect, this disclosure provides a display panel, comprising: a pixel array including multiple columns of pixel units; a driving circuit including Q data pins and N control pins, where Q and N are integers greater than 1; and a control circuit electrically connected to M data pins of the Q data pins, the N control pins, and the multiple columns of pixel units, where M < Q and M is a positive integer, the control circuit being configured to output M data signals from the M data pins to the multiple columns of pixel units under the control of N control signals from the N control pins; wherein the data signals include N data sub-signals, and the N data sub-signals are respectively written into the N columns of pixel units under the control of the N control signals.

[0006] According to a second aspect, this disclosure provides a display device, including: a display panel provided in embodiments of this disclosure; and a main control unit configured to output image data to the display panel; wherein the display panel is further configured to display a data signal obtained based on the image data.

[0007] According to a third aspect, this disclosure provides a display method, comprising: under the control of N control signals from N control pins of a driving circuit, outputting M data signals from M data pins of Q data pins of the driving circuit to a pixel array; wherein the data signals include N data sub-signals, and the N data sub-signals are respectively written into N columns of pixel units in the pixel array under the control of the N control signals. Attached Figure Description

[0008] Figure 1A schematic diagram of the structure of a display panel according to an embodiment of the present disclosure is shown;

[0009] Figure 2 A schematic diagram of the structure of a drive circuit according to an embodiment of the present disclosure is shown;

[0010] Figure 3 A schematic diagram of a drive circuit according to another embodiment of the present disclosure is shown;

[0011] Figure 4 A schematic diagram showing the arrangement of control pins and data pins according to an embodiment of the present disclosure is provided.

[0012] Figure 5 A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown;

[0013] Figure 6 A schematic diagram of the structure of a control unit according to an embodiment of the present disclosure is shown;

[0014] Figure 7A A schematic diagram of a control unit according to an embodiment of the present disclosure is shown;

[0015] Figure 7B A timing diagram of control signals according to an embodiment of the present disclosure is shown;

[0016] Figure 8 A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown;

[0017] Figure 9A A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown;

[0018] Figure 9B A schematic diagram of the structure of a storage cell according to an embodiment of the present disclosure is shown;

[0019] Figure 10A A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown;

[0020] Figure 10B A schematic diagram of the structure of a storage cell according to another embodiment of the present disclosure is shown;

[0021] Figure 11A A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown;

[0022] Figure 11B A schematic diagram of the structure of a storage cell according to another embodiment of the present disclosure is shown;

[0023] Figure 12A A schematic diagram of a control unit according to another embodiment of the present disclosure is shown;

[0024] Figure 12B A timing diagram of control signals according to another embodiment of the present disclosure is shown;

[0025] Figure 13 A schematic diagram of the structure of a storage cell according to another embodiment of the present disclosure is shown;

[0026] Figure 14 A schematic diagram of the structure of a storage cell according to another embodiment of the present disclosure is shown;

[0027] Figure 15 A schematic diagram of the structure of a storage cell according to another embodiment of the present disclosure is shown;

[0028] Figure 16 A schematic diagram of the structure of a display device according to an embodiment of the present disclosure is shown;

[0029] Figure 17 A schematic diagram of the structure of a display device according to another embodiment of the present disclosure is shown; and

[0030] Figure 18 A flowchart illustrating a display method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0033] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" can refer to a direct connection between two components, or to a connection between two components via one or more other components, wherein the connection method is electrical connection or electrical coupling. Additionally, the two components can also be connected or coupled via wired or wireless means.

[0034] It should be noted that, in the description of the embodiments of this disclosure, D1, ..., DQ can represent either a data pin or a data signal provided by a data pin. Similarly, the symbols C1, ..., CN can represent either a control pin or a control signal provided by a control pin. The following embodiments are the same and will not be described again.

[0035] Figure 1 A schematic diagram of the structure of a display panel according to an embodiment of the present disclosure is shown.

[0036] like Figure 1 As shown, the display panel 100 includes a pixel array 110, a driving circuit 120, and a control circuit 130.

[0037] In this embodiment of the disclosure, the pixel array 110 includes multiple columns of pixel units. For example, a pixel unit can be a pixel, and each pixel includes multiple light-emitting units. A pixel unit can be a sub-pixel, and each sub-pixel includes a light-emitting element. For example, the pixel array 110 can be multiple sub-pixels arranged in an array. When the light-emitting elements in the pixel array 110 are lit, the display panel 100 displays an image. For example, the display panel 100 can be an active matrix organic light-emitting diode (AMOLED) panel, and the light-emitting element is an OLED.

[0038] In this embodiment, the driving circuit 120 may be a display driver integrated circuit (DDIC), which sends data signals and scan signals to the pixel array 110 to cause the light-emitting elements of the pixel array 110 to emit light. Alternatively, the driving circuit 120 may be a touch and display driver integration circuit (TDDIC), which sends data circuit signals and scan signals to the pixel array 110 based on a received touch signal indicating a touch command, causing the light-emitting elements of the pixel array 110 to emit light based on the touch command.

[0039] In an embodiment of the present disclosure, the driving circuit 120 includes Q data pins D1, …, DQ and N control pins C1, …, CN, where Q and N are integers greater than 1. The data pins D1, …, DQ are used to output data signals to the pixel array 110, and the control pins C1, …, CN are used to output control signals C1, …, CN, and the control pins C1, …, CN are used to control the control circuit 130 to provide the data signals from the data pins D1, …, DQ to the pixel array 110.

[0040] For example, the display panel 100 may include a display area and a non-display area. The pixel array 110 is provided with light-emitting elements in the display area, and the driving circuit 120 and the control circuit 130 may be provided in the non-display area of the display panel 100.

[0041] In an embodiment of the present disclosure, the control circuit 130 is electrically connected to M of the Q data pins, N control pins, and multiple columns of pixel units, where M < Q and M is a positive integer.

[0042] For example, M of the Q data pins are electrically connected to the control circuit 130 via M source lines, and M data signals are output to the control circuit 130 via the M source lines. Under the control of N control signals C1, …, CN from the N control pins C1, …, CN, the control circuit 130 outputs M data signals from the M data pins to multiple columns of pixel units.

[0043] In an embodiment of the present disclosure, each of the M data signals includes N data sub-signals. The control circuit 130 may be a multiplexer, and the control circuit 130 may perform multiplexing on the data signals to output N data sub-signals based on one data signal. For example, each data signal may include N data voltages, and under the control of the N control signals C1, …, CN, the control circuit 130 may perform multiplexing on the data signals to output N data sub-signals, and each data sub-signal has one of the N data voltages of the N data voltages. The data sub-signals are written into the pixel units to drive the light-emitting elements of the pixel units to emit light. The data voltage of the data sub-signal indicates the light-emitting brightness value of the light-emitting element.

[0044] The N data sub-signals in each data signal may be respectively for N columns of pixel units in the pixel array 110. The N data sub-signals are respectively written into N columns of pixel units in multiple columns of pixel units under the control of the N control signals C1, …, CN.

[0045] For example, one of the N control signals C1, ..., CN can control one of the N data sub-signals to be written into one column of pixel units in the N columns of pixel units. The N data sub-signals output via a source line can be written into the N columns of pixel units respectively, thereby realizing the provision of data sub-signals to N pixel units in one row of pixels in the pixel array 110 via a source line.

[0046] In this embodiment of the present disclosure, data sub-signals can be provided to (M×N) columns of pixel units in the pixel array 110 through the M data pins in the driving circuit 120. The driving circuit 120 includes Q data pins D1, ..., DQ, each of which can output data sub-signals to N columns of pixel units. The driving circuit 120 can provide data sub-signals to a maximum of (Q×N) columns of pixel units.

[0047] In this embodiment, the control circuit 130 performs multiplexing of the data signal, allowing a single data signal output from one source line to be written into N columns of pixel units, thereby driving N columns of pixel units through a single data pin. For display panels with the same resolution, as N increases, M decreases, thus reducing the number of source lines. For display panels with lower resolution, N can be kept constant while M is reduced, further reducing the number of source lines. For panels with higher resolution, N can be increased while M remains constant, thus avoiding increasing the number of source lines. Furthermore, by setting the number of control pins of the control circuit 130 to be the same as the number of columns of pixel units that one source line needs to drive, multiple selections of a single data signal can be achieved, providing data sub-signals to N columns of pixel units through a single data signal, which is beneficial for narrowing the bezel of the display panel 100.

[0048] Figure 2 A schematic diagram of the structure of a drive circuit according to an embodiment of the present disclosure is shown.

[0049] like Figure 2 As shown, the driving circuit 220 includes Q first storage cells S1-1, ..., S1-Q corresponding to Q data pins D1, ..., DQ.

[0050] In this embodiment of the disclosure, a first storage unit is used to store the data that needs to be output by a data pin. For example, the first storage unit stores the data signal that needs to be output by the corresponding data pin. The M data signals include M×N data sub-signals, and each first storage unit can store the voltage values ​​of the N data voltages included in each data signal.

[0051] In this embodiment of the disclosure, M first storage cells corresponding to M data pins store M×C data sub-signals out of M×N data sub-signals, where N>C and C is a positive integer. For example, the maximum storage capacity of each first storage cell can be the data volume of C data sub-signals. (QM) first storage cells corresponding to (QM) data pins store M×(NC) data sub-signals out of M×N data sub-signals.

[0052] Since (QM) data pins, excluding M data pins, do not output data signals, the (QM) first memory cells corresponding to the (QM) data pins do not need to store data signals for the (QM) data pins. Therefore, the (QM) first memory cells corresponding to the (QM) data pins can be borrowed.

[0053] If the M first memory cells corresponding to the M data pins are full, the remaining M×(NC) data sub-signals out of the M×N data sub-signals can be stored in the (QM) first memory cells corresponding to the (QM) data pins. The maximum storage capacity (QM)×C of the (QM) first memory cells can be greater than or equal to the data volume of the M×(NC) data sub-signals.

[0054] In this embodiment of the disclosure, when the number of data pins outputs a data signal, the driving circuit 220 obtains the corresponding data sub-signal from the first storage cell corresponding to the data pin. The driving unit 220 also obtains the data sub-signal that the data pin needs to output from (QM) first storage cells.

[0055] In this embodiment, the first storage unit can be a temporary storage unit. For example, when the data pin output by the data pin needs to light up the first row of pixel units in N columns of pixel units, the first storage unit stores N data sub-signals that need to be written to the N pixel units in the first row of pixel units. After the first row of pixel units is lit up, the data sub-signals stored in the first storage unit are cleared, and then N data sub-signals that need to be written to the N pixel units in the second row of pixel units are written.

[0056] In this embodiment, the maximum data capacity of each first storage unit in the driving circuit 220 can be assumed to be the data volume of C data sub-signals. When M×N ≤ Q×C, the Q first storage units S1-1, ..., S1-Q in the driving circuit 220 can accommodate M×N data sub-signals. In this case, there is no need to add extra storage space to the driving circuit 220 to accommodate more data sub-signals, thus avoiding an increase in the area of ​​the driving circuit 220. When using the driving circuit 220 to provide data sub-signals to M×N column pixel units, it is also possible to avoid adjusting the structure of the driving circuit 220, reducing the difficulty of driving the pixel array.

[0057] Figure 3 A schematic diagram of a drive circuit according to another embodiment of the present disclosure is shown.

[0058] like Figure 3 As shown, the driving circuit 320 includes Q first storage units S1-1, ..., S1-Q and second storage units S2 corresponding to Q data pins D1, ..., DQ.

[0059] In this embodiment of the present disclosure, the second storage unit S2 stores (M×N)-(Q×C) data sub-signals out of M×N data sub-signals, wherein the data amount of (Q×C) data sub-signals is the maximum storage amount of Q first storage units, and M×N>Q×C.

[0060] In this embodiment of the disclosure, when M×N>Q×C, the remaining (M×N)-(Q×C) data sub-signals from the M×N data sub-signals are stored in the second storage unit S2.

[0061] In this embodiment of the disclosure, the second storage unit S2 can store the data signals that need to be output by some of the M data pins. For example, the data signal that needs to be output by a specific data pin among the M data pins can be stored in the second storage unit S2 and the first storage unit corresponding to the specific data pin. The data signals that need to be output by the remaining data pins among the M data pins other than the specified data pin can be stored in the corresponding first storage unit and (QM) first storage units corresponding to (QM) data pins.

[0062] In this embodiment, the second storage unit S2 can also be a temporary storage unit. The second storage unit S2 stores data sub-signals in the same way as the first storage unit, and will not be described again for the sake of simplicity.

[0063] Combination Figure 4 The arrangement of the control pins and data pins provided in this disclosure is illustrated.

[0064] Figure 4A schematic diagram of the arrangement of control pins and data pins according to an embodiment of the present disclosure is shown.

[0065] like Figure 4 As shown, M of the Q data pins D1, ..., DQ are spaced apart from the remaining (QM) data pins. The (QM) data pins do not output data signals, while the M data pins output data signals.

[0066] For example, the data pin Dd can be a dummy pin. The data pin Dd does not output a data signal, therefore the data pin Dd does not have a source line. The data pin Ds outputs a data signal, therefore the data pin Ds has a source line.

[0067] Because the M data pins are spaced apart from the (QM) data pins, there is a certain gap between the source lines led out from the M data pins, which can reduce the coupling effect between the source lines.

[0068] In this embodiment of the disclosure, N control pins C1, ..., CN are respectively disposed on both sides of M data pins, and at least one data pin is provided between the control pins C1, ..., CN and the M data pins.

[0069] For example, in a row of pins in a driver circuit, the pins on both sides are configured as control signals to output control signals, while the pin in the middle is configured as a data pin to output data. Depending on the resolution of the display panel, some of the multiple data pins are configured to output data, while the remaining data pins are configured as dummy pins and do not output data signals.

[0070] For example, two data pins located at the edge of a set of data pins can be configured as dummy pins. This allows dummy pins to be stored between the data pins that output data signals and the control pins. Control pins require signal lines to output control signals, and in this case, there is also a certain gap between the signal line and the source line to reduce the coupling effect between the signal line and the source line.

[0071] In this embodiment of the disclosure, based on the quantitative relationship between M and (QM), the M data pins and the dummy pins of (QM) can be evenly spaced. It should be noted that this disclosure does not limit the spacing between the M data pins and the dummy pins of (QM).

[0072] Figure 5 A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown.

[0073] like Figure 5 As shown, the display panel 500 includes a pixel array 510, a driving circuit 520, and a driving circuit 530.

[0074] In this embodiment, the pixel array 510 and the driving circuit 520 can refer to the pixel array 110 and the driving circuit 120 described above, and will not be repeated for the sake of brevity.

[0075] In this embodiment, the control circuit 530 includes M control units C1, ..., CM. Each of the M control units C1, ..., CM is electrically connected to one of the M data pins, and each control unit is electrically connected to a data pin that needs to output a data signal. Each of the M control units C1, ..., CM is electrically connected to N columns of pixel units and N control pins C1, ..., CN. Each control unit is electrically connected to the N columns of pixel units and the N control pins C1, ..., CN.

[0076] In this embodiment of the disclosure, each control unit, under the control of N control signals, converts the data signal from the electrically connected data pin into N data sub-signals, and writes the N data sub-signals into N column pixel units respectively.

[0077] For example, data pin D1 is electrically connected to control unit CU1 and N control pins C1, ..., CN; data pin Dm is electrically connected to control unit CUm and N control pins C1, ..., CN; and data pin DM is electrically connected to control unit CUM and N control pins C1, ..., CN. For example, under the control of the N control signals C1, ..., CN, control unit CUm performs N-way selection on the data signal from data pin Dm, outputting N data sub-signals. These N data sub-signals are respectively written into N columns of pixel units electrically connected to control unit CUm to drive the light-emitting elements of the N columns of pixel units to emit light.

[0078] Figure 6 A schematic diagram of the structure of a control unit according to an embodiment of the present disclosure is shown.

[0079] like Figure 6 As shown, the control unit CU includes an input terminal INPUT, N output terminals OUT1, ..., OUTN, and control terminals E1, ..., EN.

[0080] In this embodiment of the disclosure, the input terminal INPUT of the control unit CU is electrically connected to the corresponding data pin among the M data pins. For example, refer to... Figure 5 The input terminal INPUT of control unit CU1 is electrically connected to the data pin D1, the input terminal INPUT of control unit CUm is electrically connected to the data pin Dm, and the input terminal INPUT of control unit CUM is electrically connected to the data pin DM.

[0081] In this embodiment of the disclosure, the N output terminals OUT1, ..., OUTN of the control unit CU are electrically connected to the N columns of pixel units via N data lines. The N control terminals E1, ..., EN of the control unit CU are electrically connected to the N control pins.

[0082] For example, the control unit CU receives N control signals via N control terminals E1, ..., EN, and performs N-way selection on the data signal received via the input terminal INPUT, so that the N data voltages included in the data signal are written to the N output terminals OUT1, ..., OUTN respectively, so that the N output terminals OUT1, ..., OUTN output N data sub-signals.

[0083] like Figure 6 As shown, the control unit CU also includes N transistors T1, ..., TN. The control electrodes of the N transistors are electrically connected to the N control terminals E1, ..., EN, respectively. The first electrodes of the N transistors T1, ..., TN are electrically connected to the N output terminals OUT1, ..., OUTN, and the second electrodes of the N transistors are electrically connected to the input terminal INPUT.

[0084] In this embodiment, a transistor is turned on or off under the control of a control signal, allowing a data signal to be output to the output terminal electrically connected to the transistor. For example, N transistors T1, ..., TN can all be PMOS transistors. When the control signal is low, the transistor is turned on, and the data signal can be output to the output terminal electrically connected to the turned-on transistor. It should be noted that, for example, N transistors T1, ..., TN can also all be NMOS transistors. When the control signal is high, the transistor is turned on, and the data signal can be output to the output terminal electrically connected to the turned-on transistor.

[0085] In this embodiment of the disclosure, under the control of N control signals, the control circuit CU writes N data sub-signals onto N data lines, and writes the N data sub-signals to N column pixel units respectively via the N data lines.

[0086] For example, the first terminals of N transistors T1, ..., TN are electrically connected to N output terminals OUT1, ..., OUTN via N data lines. When the transistors are turned on, the data voltage of the data signal can be written into the data lines electrically connected to the first terminals of the transistors, forming a data sub-signal. When all N data lines have been written with data voltage, the N data lines can simultaneously output their stored data sub-signals to their respective electrically connected pixel units. This ensures that the light-emitting units of each row of pixel units in the N columns of pixel units emit light simultaneously, avoiding poor image display.

[0087] For example, in the nth time period, the nth control signal out of N control signals is at the first level, and all other control signals are at the second level. The nth data sub-signal out of N data sub-signals is written to the nth data line out of N data lines, where 1 ≤ n ≤ N, and n is a positive integer. The control unit CU writes the N data sub-signals to the N columns of pixel units via the N data lines.

[0088] For example, the transistor is a PMOS transistor, with a first voltage level of low and a second voltage level of high. In the first time period, the control signal provided by control terminal E1 is low, while the control signals provided by control terminals E2, ..., EN are high. At this time, transistor T1 is turned on, and transistors T2, ..., TN are turned off. The data voltage provided by the data signal is written to the data line electrically connected to the first terminal of transistor T1. Similarly, in the Nth time period, the control signal provided by control terminal EN is low, while the control signals provided by control terminals E1, ..., EN-1 are high. At this time, transistor TN is turned on, and transistors T1, ..., TN-1 are turned off. The data voltage provided by the data signal is written to the data line electrically connected to the first terminal of transistor TN. After N time periods, data voltages are written to all N data lines. At this point, N data sub-signals are written to N column pixel units via the N data lines.

[0089] Figure 7A A schematic diagram of a control unit according to an embodiment of the present disclosure is shown.

[0090] like Figure 7A As shown, N=9, and the data signal output from data pin D1 can drive 9 columns of pixel units. Pixel 1 includes sub-pixels R1, G1, and B1; pixel Pixel 2 includes sub-pixels R2, G2, and B2; and pixel Pixel 13 includes sub-pixels R3, G3, and B3. Sub-pixels R1, G1, B1, R2, G2, B2, and R3, G3, B3 can be 9 sub-pixels in one row of the 9 columns of pixel units. Sub-pixels R1, G1, B1, R2, G2, B2, and R3, G3, B3 can be arranged in Real RGB format.

[0091] The control unit CU includes nine transistors T1, ..., T9, all of which are PMOS transistors. The drive circuit 720 includes nine control pins C1, ..., C9. The data pin D1 of the drive circuit 720 outputs a data signal D1 to the control unit CU. Based on the control signals C1, ..., C9 from the control pins C1, ..., C9, the control unit CU performs multiplexing on the data signal D1, outputting nine data sub-signals.

[0092] In this embodiment, transistor T1 has its control electrode electrically connected to control pin C1, its first electrode electrically connected to sub-pixel R1, and its second electrode electrically connected to data pin D1. Transistor T2 has its control electrode electrically connected to control pin C2, its first electrode electrically connected to sub-pixel G1, and its second electrode electrically connected to data pin D1. Transistor T3 has its control electrode electrically connected to control pin C3, its first electrode electrically connected to sub-pixel B1, and its second electrode electrically connected to data pin D1. Transistor T4 has its control electrode electrically connected to control pin C4, its first electrode electrically connected to sub-pixel R2, and its second electrode electrically connected to data pin D1. Transistor T5 has its control electrode electrically connected to control pin C5, its first electrode electrically connected to sub-pixel G2, and its second electrode electrically connected to data pin D1. Transistor T6 has its control electrode electrically connected to control pin C2, its first electrode electrically connected to sub-pixel B2, and its second electrode electrically connected to data pin D1. Transistor T7 has its control electrode electrically connected to control pin C7, its first electrode electrically connected to sub-pixel R3, and its second electrode electrically connected to data pin D1. Transistor T8 has its gate electrode connected to control pin C8, its first electrode connected to sub-pixel G3, and its second electrode connected to data pin D1. Transistor T9 has its gate electrode connected to control pin C9, its first electrode connected to sub-pixel B3, and its second electrode connected to data pin D1.

[0093] Combination Figure 7B The timing sequence of control signals C1 to C9 is shown to illustrate the working process of the control unit CU. Figure 7B A timing diagram of control signals according to an embodiment of the present disclosure is shown.

[0094] During the first time period P1, control signal C1 is low, and control signals C2 to C9 are high. Under the control of the low level of control signal C1, transistor T1 is turned on. Under the control of the high level of control signals C2 to C9, transistors T2 to T9 are turned off. The data signal D1, representing the data voltage VR1 during the first time period P1, is written to the data line electrically connected to the first terminal of transistor T1.

[0095] During the second time period P2, control signal C2 is low, while control signals C1, C3-C9 are high. Under the control of the low level of control signal C2, transistor T2 is turned on. Under the control of the high level of control signals C1, C3-C9, transistors T1, T3-T9 are turned off. The data signal D1, representing the data voltage VG1, is written to the data line electrically connected to the first electrode of transistor T2 during the second time period P2.

[0096] Similarly, during time intervals P3 to P9, the voltage of data signal D1 is sequentially written onto the data lines electrically connected to the first terminals of transistors T3 to T9. After nine time intervals, data voltage is written onto all nine data lines.

[0097] After data voltages are written on all nine data lines, the control unit CU writes nine data sub-signals to the nine sub-pixels via the nine data lines, so that the data sub-signals are written into the pixel circuit of the sub-pixel to drive the gate of the transistor.

[0098] Figure 8 A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown.

[0099] like Figure 8 As shown, the display panel 800 includes a pixel array 810, a driving circuit 820, and a control circuit 830. The pixel array 810 and the control circuit 830 can be referred to the pixel array 110 and the control circuit 130 described above, and will not be repeated for the sake of simplicity.

[0100] In this embodiment of the disclosure, the driving circuit 820 includes a storage unit 821, a level switching unit 822, and a digital-to-analog converter 823.

[0101] In this embodiment of the disclosure, for each data pin outputting a data signal, storage unit 821 stores N raw data voltages obtained based on image data from the main control unit. Storage unit 821 may include the first storage unit and the second storage unit described above.

[0102] The level switching unit 822 performs level switching on N raw data voltages. The digital-to-analog converter 823 converts the level-switched N raw data voltages from digital signals to analog signals, which are then used as data signals.

[0103] For example, the driving circuit 820 may also include a timing controller TCON and a gamma correction unit. Image data from the main control unit can be a video signal. The timing controller can convert the video signal into a data signal. The video signal indicates the brightness information of each sub-pixel, and the data signal indicates the data voltage corresponding to the brightness information. The timing controller converts the brightness information into data voltages. For example, N raw data voltages are the data voltages converted by the timing controller. The N raw data voltages can be stored in random access memory (RAM).

[0104] The gamma correction unit can perform gamma correction on N raw data voltages and store the corrected data voltages in a register. The gamma-corrected data voltages are read from the register and written to storage unit 821, which can temporarily store the gamma-corrected data voltages. The register can also be a non-volatile memory; when the drive circuit 820 is powered off, the data stored in storage unit 821 is lost, but the gamma-corrected data voltages can be read again from the register.

[0105] In this embodiment, the level switching unit 822 can boost the gamma-corrected data voltage to meet the driving capability of the sub-pixels. The digital-to-analog converter 823 converts the boosted data voltage from a digital signal to an analog signal to obtain a data signal.

[0106] In this embodiment of the disclosure, the driving circuit 820 may further include an amplifier, which amplifies the data signal output by the digital-to-analog converter 823 and outputs the amplified data signal via a data pin.

[0107] In this embodiment, the driving circuit 820 may include M level switching units, M digital-to-analog converters, and M amplifiers. One level switching unit, one digital-to-analog converter, and one amplifier can process N raw data voltages.

[0108] The following is an illustrative explanation of the driving process using a driving circuit comprising 241 data pins. For example, the data signal output from each data pin of the driving circuit can drive 6 columns of sub-pixels, and the maximum data capacity of the first memory cell corresponding to each data pin can be 6 data sub-signals. For example, the 241 data pins include 240 data pins for outputting data signals and 1 dummy pin. The driving circuit can drive (240×6) columns of sub-pixels. For example, the resolution of the display panel can be 480×480, and the display panel includes 1440 columns of sub-pixels.

[0109] Figure 9A A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown.

[0110] like Figure 9A As shown, the display panel 900 includes a pixel array 910, a driving circuit 920, and a control circuit 930.

[0111] In this embodiment of the disclosure, the driving circuit 920 may include 241 data pins D0, ..., D240, 9 control pins C1, ..., C9 and multiple input pins INPUT PIN.

[0112] For example, multiple input pins (INPUT PIN) can receive image data from the main control unit. The driver circuit 920 converts the image data into a data signal.

[0113] For example, control pins C1 to C4 can be sequentially arranged on one side of the drive circuit 920, and control pins C5 to C9 can be sequentially arranged on the other side of the drive circuit 920. Data pins D0 and D240 are dummy pins. Data pin D0 is used to separate control pin C4 and data pin D1, and data pin D240 is used to separate control pin C5 and data pin D239.

[0114] In this embodiment of the disclosure, each data pin is used to drive 9 columns of sub-pixels. For a display panel with a resolution of 480×480, the driving circuit 920 can lead out source lines through 160 of the 241 data pins to drive 1440 columns of sub-pixels.

[0115] The driver circuit 920 includes 81 dummy pins and 160 data pins for data signals. One dummy pin can be positioned between every two adjacent data pins. For example, data pins D1 and D2 output data signals, and data pin D3 is a dummy pin. Data pins D3 and D4 output data signals, and data pin D5 is a dummy pin.

[0116] In this embodiment of the disclosure, the control circuit 930 includes 160 control units CU1, ..., CU160. Each data pin for outputting a data signal has a source line leading out and electrically connected to a control unit via the source line. Each of the 160 control units CU1, ..., CU160 is electrically connected to nine control pins C1, ..., C9.

[0117] In this embodiment of the disclosure, every two data pins and one dummy pin are grouped into a pin group. For example, data pins D1, D2, and D3 are grouped into a pin group, data pins D4, D5, and D6 are grouped into a pin group, ..., data pins D238, D239, and D240 are grouped into a pin group.

[0118] The first storage cell corresponding to each data pin can store a maximum of 6 data sub-signals. For example, the first storage cell corresponding to data pins D1 and D2 can only store 6 data sub-signals used to drive 6 sub-pixels. Since data pins D1 and D2 need to output 9 data sub-signals used to drive 9 sub-pixels, the remaining 2×3 data sub-signals can be stored in the first storage cell corresponding to the virtual pin.

[0119] Combination Figure 9B The method of storing data sub-signals is illustrated.

[0120] Figure 9B A schematic diagram of the structure of a storage unit according to an embodiment of the present disclosure is shown.

[0121] like Figure 9B As shown, the first storage units corresponding to data pins D1, D2, and D3 are S1-1, S1-2, and S1-3, respectively. Each first storage unit may include 6 registers, and each register can store one data sub-signal.

[0122] For example, the data signal output from data pin D1 is used to drive pixels Pixel1, Pixel2, and Pixel3. The first storage unit S1-1 corresponding to data pin D1 can store the data signal DP1 for pixel Pixel1 and the data signal DP2 for pixel Pixel2. Data signal DP1 includes data sub-signals DR1, DG1, and DB1 used to drive three sub-pixels in pixel Pixel1, and data signal DP2 includes data sub-signals DR2, DG2, and DB2 used to drive three sub-pixels in pixel Pixel2. The data signal DP3 used to drive pixel Pixel3 is stored in the first storage unit S1-3 corresponding to data pin D3, and data signal DP3 includes data sub-signals DR3, DG3, and DB3 for three sub-pixels.

[0123] Similarly, the data signal output from data pin D2 is used to drive pixels Pixel4, Pixel5, and Pixel6. The first storage unit S1-2 corresponding to data pin D2 can store the data signal DP4 of pixel Pixel4. Data signal DP4 includes data sub-signals DR4, DG4, and DB4 used to drive three sub-pixels in pixel Pixel4, and data signal DP5 includes data sub-signals DR5, DG5, and DB5 used to drive three sub-pixels in pixel Pixel5. The data signal DP6 used to drive pixel Pixel6 is stored in the first storage unit S1-3 corresponding to data pin D3, and data signal DP6 includes data sub-signals DR6, DG6, and DB6 for three sub-pixels.

[0124] In this embodiment of the disclosure, 240 first storage units corresponding to 240 data pins can be used to store 1440 data signals for driving one row of sub-pixels in 1440 columns of sub-pixels.

[0125] Figure 10A A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown.

[0126] like Figure 10A As shown, the display panel 1000 includes a pixel array 1010, a driving circuit 1020, and a control circuit 1030.

[0127] In this embodiment, the driving circuit 1020 may include 241 data pins D0, ..., D240, 9 control pins C1, ..., C9, and multiple input pins INPUT PIN. For example, the multiple input pins INPUT PIN can receive image data from the main control unit. The driving circuit 1020 converts the image data into data signals.

[0128] For example, the configuration of control pins C1 to C9 can be referenced from the configuration of control pins C1 to C9 in the drive circuit 1020 described above. For the sake of simplicity, this disclosure will not repeat it.

[0129] The driver circuit 1020 includes 61 dummy pins and 180 data pins for data signals. One dummy pin can be positioned between every three adjacent data pins. For example, data pins D1, D2, and D3 output data signals, and data pin D4 is a dummy pin. Data pins D5, D6, and D7 output data signals, and data pin D8 is a dummy pin.

[0130] In this embodiment of the disclosure, the control circuit 1030 includes 180 control units CU1, ..., CU180. Each data pin for outputting a data signal has a source line leading out and electrically connected to a control unit via the source line. Each of the 180 control units CU1, ..., CU180 is electrically connected to nine control pins C1, ..., C9.

[0131] The driving circuit 1020 can achieve (180×9) columns of sub-pixels through 180 data output signals. For example, the resolution of the display panel can be 540×480, and the display panel includes 1620 columns of sub-pixels.

[0132] In this embodiment of the disclosure, every three data pins and one dummy pin are grouped into a pin group. For example, data pins D1, D2, D3, and D4 are grouped into a pin group, data pins D5, D6, D7, and D8 are grouped into a pin group, ..., data pins D237, D238, D239, and D240 are grouped into a pin group.

[0133] The first storage unit corresponding to each data pin can store a maximum of 6 data sub-signals. For example, the first storage unit corresponding to data pins D1, D2, D3, and D4 can only store 6 data sub-signals used to drive 6 sub-pixels. Since data pins D1, D2, D3, and D4 all need to output 9 data sub-signals for driving 9 sub-pixels, 6 of the remaining 3×3 data sub-signals can be stored in the first storage unit corresponding to the virtual pin, and the remaining 3 data sub-signals can be stored in the second storage unit S2.

[0134] Combination Figure 10B The method of storing data sub-signals is illustrated.

[0135] Figure 10B A schematic diagram of the structure of a storage unit according to another embodiment of the present disclosure is shown.

[0136] like Figure 10BAs shown, the first storage units corresponding to data pins D1, D2, D3, and D4 are S1-1, S1-2, S1-3, and S1-4, respectively. Each first storage unit may include 6 registers, and each register can store one data sub-signal.

[0137] For example, the data signal output from data pin D1 is used to drive pixels Pixel1, Pixel2, and Pixel3. The first storage unit S1-1 corresponding to data pin D1 can store the data signal DP1 for pixel Pixel1 and the data signal DP2 for pixel Pixel2. Data signal DP1 includes data sub-signals DR1, DG1, and DB1 for driving three sub-pixels in pixel Pixel1, and data signal DP2 includes data sub-signals DR2, DG2, and DB2 for driving three sub-pixels in pixel Pixel2. The data signal DP3 for driving pixel Pixel3 is stored in the first storage unit S1-4 corresponding to data pin D4, and data signal DP3 includes data sub-signals DR3, DG3, and DB3 for three sub-pixels.

[0138] Similarly, the data signal output from data pin D2 is used to drive pixels Pixel4, Pixel5, and Pixel6. The first storage unit S1-2 corresponding to data pin D2 can store the data signal DP4 of pixel Pixel4. Data signal DP4 includes data sub-signals DR4, DG4, and DB4 used to drive three sub-pixels in pixel Pixel4, and data signal DP5 includes data sub-signals DR5, DG5, and DB5 used to drive three sub-pixels in pixel Pixel5. The data signal DP6 used to drive pixel Pixel6 is stored in the first storage unit S1-4 corresponding to data pin D4, and data signal DP6 includes data sub-signals DR6, DG6, and DB6 for three sub-pixels.

[0139] The data signal output from data pin D3 is used to drive pixels Pixel7, Pixel8, and Pixel9. The first storage unit S1-3 corresponding to data pin D3 can store the data signal DP7 for pixel Pixel7 and the data signal DP8 for pixel Pixel8. Data signal DP7 includes data sub-signals DR7, DG7, and DB7 used to drive three sub-pixels in pixel Pixel7, and data signal DP8 includes data sub-signals DR8, DG8, and DB8 used to drive three sub-pixels in pixel Pixel8. The data signal DP9 used to drive pixel Pixel9 is stored in the second storage unit S2, and data signal DP9 includes the data sub-signals DR9, DG9, and DB9 for three sub-pixels.

[0140] In this embodiment of the disclosure, the second storage unit S2 and the 240 first storage units corresponding to the 240 data pins can be used to store 1620 data signals for driving one row of sub-pixels in 1620 columns of sub-pixels.

[0141] In this embodiment of the disclosure, the data signal DP3 used to drive pixel Pixel 3 can also be stored in the second storage unit S2, and the data signal DP9 used to drive pixel Pixel 9 can also be stored in the first storage units S1-4. Alternatively, the data signal DP6 used to drive pixel Pixel 6 can also be stored in the second storage unit S2, and the data signal DP9 used to drive pixel Pixel 9 can also be stored in the first storage units S1-4.

[0142] Figure 11A A schematic diagram of the structure of a display panel according to another embodiment of the present disclosure is shown.

[0143] like Figure 11A As shown, the display panel 1100 includes a pixel array 1110, a driving circuit 1120, and a control circuit 1130.

[0144] In this embodiment, the driving circuit 1120 may include 241 data pins D0, ..., D240, 9 control pins C1, ..., C9, and multiple input pins INPUT PIN. For example, the multiple input pins INPUT PIN can receive image data from the main control unit. The driving circuit 1120 converts the image data into data signals.

[0145] For example, the configuration of control pins C1 to C9 can be referenced from the configuration of control pins C1 to C9 in the drive circuit 1020 described above. For the sake of simplicity, this disclosure will not repeat it.

[0146] The driver circuit 1120 includes 121 dummy pins and 120 data pins for data signals. The 120 data pins are arranged sequentially and alternately with the 121 dummy pins. For example, data pin D1 outputs a data signal, and data pin D2 is a dummy pin. Data pin D3 outputs a data signal, and data pin D4 is a dummy pin.

[0147] In this embodiment of the disclosure, the control circuit 1130 includes 120 control units CU1, ..., CU120. Each data pin for outputting a data signal has a source line leading out and electrically connected to a control unit via the source line. Each of the 120 control units CU1, ..., CU120 is electrically connected to nine control pins C1, ..., C9.

[0148] The driving circuit 1120 can achieve (120×9) columns of sub-pixels through 120 data output signals. For example, the resolution of the display panel can be 360×480, and the display panel includes 1080 columns of sub-pixels.

[0149] In this embodiment of the disclosure, a data pin and a dummy pin are grouped into a pin group. For example, data pins D1 and D2 are grouped into a pin group, data pins D3 and D4 are grouped into a pin group, ..., data pins D239 and D240 are grouped into a pin group.

[0150] The first memory cell corresponding to each data pin can store a maximum of 6 data sub-signals. For example, the first memory cell corresponding to data pin D1 can only store 6 data sub-signals used to drive 6 sub-pixels. Since data pin D1 needs to output 9 data sub-signals for driving 9 sub-pixels, the remaining 3 data sub-signals can be stored in the first memory cell corresponding to data pin D2.

[0151] Combination Figure 11B The method of storing data sub-signals is illustrated.

[0152] Figure 11B A schematic diagram of the structure of a storage unit according to another embodiment of the present disclosure is shown.

[0153] like Figure 11B As shown, the first storage units corresponding to data pins D1 and D2 are S1-1 and S1-2, respectively. Each first storage unit may include 6 registers, and each register can store one data sub-signal.

[0154] For example, the data signal output from data pin D1 is used to drive pixels Pixel1, Pixel2, and Pixel3. The first storage unit S1-1 corresponding to data pin D1 can store the data signal DP1 for pixel Pixel1 and the data signal DP2 for pixel Pixel2. Data signal DP1 includes data sub-signals DR1, DG1, and DB1 for driving three sub-pixels in pixel Pixel1, and data signal DP2 includes data sub-signals DR2, DG2, and DB2 for driving three sub-pixels in pixel Pixel2. The data signal DP3 for driving pixel Pixel3 is stored in the first storage unit S1-2 corresponding to data pin D2, and data signal DP3 includes data sub-signals DR3, DG3, and DB3 for three sub-pixels.

[0155] In this embodiment of the disclosure, the data signal DP3 used to drive pixel Pixel 3 can also be stored in the second storage unit S2, and the data signal DP9 used to drive pixel Pixel 9 can also be stored in the first storage units S1-4. Alternatively, the data signal DP6 used to drive pixel Pixel 6 can also be stored in the second storage unit S2, and the data signal DP9 used to drive pixel Pixel 9 can also be stored in the first storage units S1-4.

[0156] Figure 12A A schematic diagram of a control unit according to another embodiment of the present disclosure is shown.

[0157] like Figure 12A As shown, N=8, and the data signal output from data pin D1 can drive 8 columns of pixel units. Pixel 1 includes sub-pixels R1, G1-1, B1, and G1-2; pixel Pixel 2 includes sub-pixels R2, G2-1, B2, and G2-2; pixel Pixel 3 includes sub-pixels R3, G3-1, B3, and G3-2; and pixel Pixel 4 includes sub-pixels R4, G4-1, B4, and G4-2.

[0158] Subpixels R1, G1-1, B1, G1-2 and R2, G2-1, B2, G2-2 can be the 8 subpixels in the first row of the 8-column pixel unit. Subpixels R3, G3-1, B3, G3-2 and R4, G4-1, B4, G4-2 can be the 8 subpixels in the second row of the 8-column pixel unit. Subpixels R1, G1-1, B1, G1-2, R2, G2-1, B2, G2-2, R3, G3-1, B3, G3-2 and R4, G4-1, B4, G4-2 can be arranged in an RGBG pattern.

[0159] The control unit CU includes eight transistors T1, ..., T8, all of which are PMOS transistors. The drive circuit 1220 includes eight control pins C1, ..., C8. The data pin D1 of the drive circuit 1220 outputs a data signal D1 to the control unit CU. Based on the control signals C1, ..., C8 from the control pins C1, ..., C8, the control unit CU performs multiplexing on the data signal D1, outputting eight data sub-signals.

[0160] In this embodiment, transistor T1 has its control electrode electrically connected to control pin C1, its first electrode electrically connected to sub-pixel R1, and its second electrode electrically connected to data pin D1. Transistor T2 has its control electrode electrically connected to control pin C2, its first electrode electrically connected to sub-pixel G1, and its second electrode electrically connected to data pin D1. Transistor T3 has its control electrode electrically connected to control pin C3, its first electrode electrically connected to sub-pixel B1, and its second electrode electrically connected to data pin D1. Transistor T4 has its control electrode electrically connected to control pin C4, its first electrode electrically connected to sub-pixel R2, and its second electrode electrically connected to data pin D1. Transistor T5 has its control electrode electrically connected to control pin C5, its first electrode electrically connected to sub-pixel G2, and its second electrode electrically connected to data pin D1. Transistor T6 has its control electrode electrically connected to control pin C2, its first electrode electrically connected to sub-pixel B2, and its second electrode electrically connected to data pin D1. Transistor T7 has its control electrode electrically connected to control pin C7, its first electrode electrically connected to sub-pixel R3, and its second electrode electrically connected to data pin D1. The control electrode of transistor T8 is electrically connected to the control pin C8, the first electrode is electrically connected to the sub-pixel G3, and the second electrode is electrically connected to the data pin D1.

[0161] Combination Figure 12B The timing sequence of control signals C1 to C8 is shown to illustrate the working process of the control unit CU. Figure 12B A timing diagram of control signals according to another embodiment of the present disclosure is shown.

[0162] During the first time period P1, control signal C1 is low, and control signals C2 to C8 are high. Under the control of the low level of control signal C1, transistor T1 is turned on. Under the control of the high level of control signals C2 to C8, transistors T2 to T8 are turned off. The data signal D1-1 used to drive the first row of sub-pixels is written to the data line electrically connected to the first electrode of transistor T1 during the first time period P1 using the data voltage VB1.

[0163] During the second time period P2, control signal C2 is low, while control signals C1, C3-C8 are high. Under the control of the low level of control signal C2, transistor T2 is turned on. Under the control of the high level of control signals C1, C3-C8, transistors T1, T3-T8 are turned off. The data signal D1-1 used to drive the first row of sub-pixels is written to the data line electrically connected to the first electrode of transistor T2 during the second time period P2, based on the data voltage VG1-1.

[0164] Similarly, during time intervals P3 to P8, the voltage of data signal D1-1 is sequentially written onto the data lines electrically connected to the first terminals of transistors T3 to T8. After eight time intervals, data voltage is written onto all eight data lines.

[0165] After data voltages are written on all eight data lines, the control unit CU writes eight data sub-signals to the eight sub-pixels of the first row via the eight data lines, so that the data sub-signals are written into the pixel circuit of the sub-pixel to drive the gate of the transistor.

[0166] After the first row of sub-pixels is illuminated, during time periods P1 to P8, the data signals D1-2 used to drive the second row of sub-pixels are sequentially written onto the data lines electrically connected to the first electrodes of transistors T3 to T8. After data voltages are written onto all eight data lines, the control unit CU writes the eight data sub-signals to the eight sub-pixels of the second row via the eight data lines, thereby writing the data sub-signals into the pixel circuits of the sub-pixels to drive the gates of the transistors.

[0167] Figure 12A The arrangement of control and data pins in the shown drive circuit can be referenced. Figure 9A , Figure 10A and Figure 11A The arrangement of control and data pins, and the connection method between the control unit and control pins in the control circuit can be found in [reference needed]. Figure 9A , Figure 10A and Figure 11A The connection method is shown in the figure.

[0168] exist Figure 12A The eight control pins in the illustrated drive circuit 1220 can be respectively located on both sides of the drive circuit, with four control pins on each side. Data pins D0 and D240 are dummy pins. Data pin D0 is used to separate control pin C4 and data pin D1, and data pin D240 is used to separate control pin C5 and data pin D239.

[0169] pass Figure 12A The driving circuit shown can drive 1280 columns of sub-pixels by bringing out source lines from 160 of the 241 data pins. A dummy pin can be set between every two adjacent data pins of the 160 data pins.

[0170] Combination Figure 13 The method of storing data sub-signals is illustrated. Figure 13 A schematic diagram of the structure of a storage unit according to another embodiment of the present disclosure is shown.

[0171] like Figure 13 As shown, the first storage units corresponding to data pins D1, D2, and D3 are S1-1, S1-2, and S1-3, respectively. Each first storage unit may include 6 registers, and each register can store one data sub-signal.

[0172] For example, the data signal output from data pin D1 is used to drive pixels Pixel1 and Pixel2. The first storage unit S1-1 corresponding to data pin D1 can store the data sub-signals DR1, DG1-1, DB1, and DG1-2 of the data signal of pixel Pixel1, and the data sub-signals DR2 and DG2-1 of the data signal of pixel Pixel2. The data sub-signals DB3 and DG2-2 used to drive sub-pixels B2 and G2-2 in pixel Pixel2 are stored in the first storage unit S1-3 corresponding to data pin D3.

[0173] Similarly, the data signal output from data pin D2 is used to drive pixels Pixel3 and Pixel4. The first storage unit S1-2 corresponding to data pin D2 can store the data sub-signals DR3, DG3-1, DB3, and DG3-2 of the data signal for pixel Pixel3, and the data sub-signals DR4 and DG4-1 of the data signal for pixel Pixel4. The data sub-signals DB4 and DG4-2 used to drive sub-pixels B4 and G4-2 in pixel Pixel4 are stored in the first storage unit S1-3 corresponding to data pin D3.

[0174] pass Figure 12A The driving circuit shown can drive 1440 columns of sub-pixels by bringing out source lines from 180 of the 241 data pins. A dummy pin can be set between every three adjacent data pins in the 180 data pins.

[0175] Combination Figure 14 The method of storing data sub-signals is illustrated. Figure 14 A schematic diagram of the structure of a storage unit according to another embodiment of the present disclosure is shown.

[0176] like Figure 14 As shown, the first storage units corresponding to data pins D1, D2, D3, and D4 are S1-1, S1-2, S1-3, and S1-4, respectively. Each first storage unit may include 6 registers, and each register can store one data sub-signal.

[0177] For example, the data signal output from data pin D1 is used to drive pixels Pixel1 and Pixel2. The first storage unit S1-1 corresponding to data pin D1 can store the data sub-signals DR1, DG1-1, DB1, and DG1-2 of the data signal of pixel Pixel1, and the data sub-signals DR2 and DG2-1 of the data signal of pixel Pixel2. The data sub-signals DB3 and DG2-2 used to drive sub-pixels B2 and G2-2 in pixel Pixel2 are stored in the first storage unit S1-4 corresponding to data pin D3.

[0178] Similarly, the data signal output from data pin D2 is used to drive pixels Pixel3 and Pixel4. The first storage unit S1-2 corresponding to data pin D2 can store the data sub-signals DR3, DG3-1, DB3, and DG3-2 of the data signal for pixel Pixel3, and the data sub-signals DR4 and DG4-1 of the data signal for pixel Pixel4. The data sub-signals DB4 and DG4-2 used to drive sub-pixels B4 and G4-2 in pixel Pixel4 are stored in the first storage unit S1-4 corresponding to data pin D4.

[0179] Similarly, the data signal output from data pin D3 is used to drive pixels Pixel5 and Pixel6. The first storage unit S1-3 corresponding to data pin D3 can store the data sub-signals DR5, DG5-1, DB5, and DG5-2 of the data signal for pixel Pixel5, and the data sub-signals DR6 and DG6-1 of the data signal for pixel Pixel6. The data sub-signals DB6 and DG6-2 used to drive sub-pixels B6 and G6-2 in pixel Pixel6 are stored in the first storage unit S1-4 corresponding to data pin D4.

[0180] pass Figure 12A The driving circuit shown can drive 960 columns of sub-pixels by bringing out source lines from 120 of the 241 data pins. The 120 data pins and 121 dummy pins are arranged alternately.

[0181] Combination Figure 15 The method of storing data sub-signals is illustrated. Figure 15 A schematic diagram of the structure of a storage unit according to another embodiment of the present disclosure is shown.

[0182] like Figure 15 As shown, the first storage units corresponding to data pins D1 and D2 are S1-1 and S1-2, respectively. Each first storage unit may include 6 registers, and each register can store one data sub-signal.

[0183] For example, the data signal output from data pin D1 is used to drive pixels Pixel1 and Pixel2. The first storage unit S1-1 corresponding to data pin D1 can store the data sub-signals DR1, DG1-1, DB1, and DG1-2 of the data signal of pixel Pixel1, and the data sub-signals DR2 and DG2-1 of the data signal of pixel Pixel2. The data sub-signals DB3 and DG2-2 used to drive sub-pixels B2 and G2-2 in pixel Pixel2 are stored in the first storage unit S1-2 corresponding to data pin D2.

[0184] Figure 16 A schematic diagram of the structure of a display device according to an embodiment of the present disclosure is shown.

[0185] like Figure 16 As shown, the display device 1600 includes a display panel 1601 and a main control unit 1602.

[0186] In this embodiment of the disclosure, the display panel 1601 may refer to the display panel 100, display panel 500, display panel 800, display panel 900, display panel 1000 and display panel 1100 described above.

[0187] In this embodiment of the disclosure, the main control unit 1602 outputs image data to the display panel 1601, and the display panel 1601 displays data signals obtained based on the image data.

[0188] Figure 17 A schematic diagram of the structure of a display device according to another embodiment of the present disclosure is shown.

[0189] like Figure 17 As shown, the display device 1700 includes a display panel 1701, a main control unit 1702, a main flexible printed circuit (MFPC) 1703, a fan-out packaging (FOP) circuit board 1704, and a connector 1705.

[0190] In this embodiment of the disclosure, the display panel 1701 includes a pixel array 1710, a driving circuit 1720, and a control circuit 1730. The pixel array 1710, the driving circuit 1720, and the control circuit 1730 can be referred to the pixel array 110, the driving circuit 120, and the control circuit 130 described above, and will not be repeated for the sake of brevity.

[0191] In this embodiment of the disclosure, the input pins of the driver circuit 1720 are led out as transmission lines. For example, the transmission line can be a Mobile Industry Processor Interface (MIPI) transmission line. The main control unit 1702 is electrically connected to the driver circuit 1720 via the transmission line. The transmission line leads from the driver circuit 1720 to the pins of the FOP circuit board 1704. The transmission line is arranged on the MFPC 1703 and the FOP circuit board 1704, which are bonded to the MFPC 1703. The transmission line crosses the MFPC 1703 and the FOP circuit board 1704 and connects to the connector 1705.

[0192] Connector 1705 engages with main control unit 1702, thereby enabling communication between main control unit 1702 and drive circuit 1720. For example, connector 770 can be a board-to-board (BTB) connector.

[0193] Figure 18 A flowchart illustrating a display method according to an embodiment of the present disclosure is shown.

[0194] like Figure 18 As shown, the display method includes step S1810.

[0195] In the embodiments of this disclosure, the display method can be applied to the display panels 100, 500, 800, 900, 1000 and 1100 described above.

[0196] During operation of S1810, under the control of N control signals from N control pins of the drive circuit, M data signals from M data pins out of Q data pins of the drive circuit are output to the pixel array.

[0197] In this embodiment of the disclosure, the data signal includes N data sub-signals, which are written into N columns of pixel units in the pixel array under the control of N control signals.

[0198] In this embodiment of the disclosure, step S1810 is similar to the operation performed by the panel 100, display panel 500, display panel 800, display panel 900, display panel 1000 and display panel 1100 described above, and will not be repeated here.

[0199] In this embodiment of the disclosure, the display method further includes: receiving image data from the main control unit; and converting the image data into M data signals, wherein each of the M data signals includes N data sub-signals, and the N data sub-signals are written into the N columns of pixel units in the multi-column pixel units under the control of the N control signals.

[0200] In this embodiment of the disclosure, the display method further includes: during the nth time period, the nth control signal among the N control signals is at a first level, and the control signals other than the nth control signal are at a second level; the nth data sub-signal among the N data sub-signals is written to the nth data line among the N data lines, 1≤n≤N, where n is a positive integer; and the N data sub-signals are written to the N column pixel units respectively via the N data lines.

[0201] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and combinations of blocks in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0202] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0203] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A display panel, comprising: A pixel array, comprising multiple columns of pixel units; The driving circuit includes Q data pins and N control pins, where Q and N are integers greater than 1; The control circuit is electrically connected to M data pins of the Q data pins, the N control pins and the multi-column pixel unit, where M < Q and M is a positive integer. The control circuit is configured to output M data signals from the M data pins to the multi-column pixel unit under the control of N control signals from the N control pins. The data signal includes N data sub-signals, which are written into the N column pixel units of the multi-column pixel unit under the control of the N control signals. The driving circuit includes: Q first memory cells corresponding to Q data pins; The M data signals include M×N data sub-signals. The M first storage units corresponding to the M data pins are configured to store M×C data sub-signals among the M×N data sub-signals. The (QM) first storage units corresponding to the (QM) data pins are configured to store M×(NC) data sub-signals among the M×N data sub-signals. The (QM) data pins do not output data signals. N>C, and C is a positive integer.

2. The display panel according to claim 1, wherein, The driving circuit also includes: The second storage unit is configured to store (M×N)-(Q×C) data sub-signals from the M×N data sub-signals, wherein the data amount of the (Q×C) data sub-signals is the maximum storage amount of the Q first storage units, and M×N>Q×C.

3. The display panel according to claim 1, wherein, Of the Q data pins, M data pins are spaced apart from the remaining (QM) data pins, and the (QM) data pins do not output data signals.

4. The display panel according to claim 3, wherein, The N control pins are respectively disposed on both sides of the M data pins, and at least one of the (QM) data pins is provided between the control pins and the M data pins.

5. The display panel according to claim 1, wherein, The control circuit includes: M control units are electrically connected to the M data pins, and each control unit is electrically connected to N columns of pixel units and the N control pins in the multi-column pixel unit. The control unit is configured to, under the control of the N control signals, convert the data signal from the electrically connected data pin into the N data sub-signals, and write the N data sub-signals into the N column pixel units respectively.

6. The display panel according to claim 5, wherein, The control unit includes: The input terminal is electrically connected to the corresponding data pin among the M data pins; N output terminals are electrically connected to the N columns of pixel units via N data lines; and N control terminals are electrically connected to the N control pins respectively.

7. The display panel according to claim 6, wherein, The control unit includes: There are N transistors, with the control electrodes of the N transistors electrically connected to the N control terminals, the first electrodes of the N transistors electrically connected to the N output terminals, and the second electrodes of the N transistors electrically connected to the input terminals.

8. The display panel according to claim 6, wherein, The control circuit is further configured to, under the control of the N control signals, write the N data sub-signals onto the N data lines, and write the N data sub-signals to the N column pixel units respectively via the N data lines.

9. The display panel according to claim 1, wherein, The driving circuit includes: The storage unit is configured to store N raw data voltages based on image data from the main control unit; A level switching unit is configured to switch the levels of the N raw data voltages; and A digital-to-analog converter is configured to convert N raw data voltages after level switching from digital signals into analog signals, wherein the analog signals are the data signals.

10. A display device, comprising: The display panel according to any one of claims 1-9; as well as The main control unit is configured to output image data from the main control unit to the display panel; The display panel is further configured to display the data signal obtained based on the image data.

11. A display method, comprising: Under the control of N control signals from N control pins of the driving circuit, M data signals from M data pins out of Q data pins of the driving circuit are output to the pixel array; The data signal includes N data sub-signals, which are written into N columns of pixel units in the pixel array under the control of the N control signals. The driving circuit includes: Q first memory cells corresponding to Q data pins; The M data signals include M×N data sub-signals. The M first storage units corresponding to the M data pins are configured to store M×C data sub-signals among the M×N data sub-signals. The (QM) first storage units corresponding to the (QM) data pins are configured to store M×(NC) data sub-signals among the M×N data sub-signals. The (QM) data pins do not output data signals. N>C, and C is a positive integer.

12. The display method according to claim 11, further comprising: Receive image data from the main control unit; as well as The image data is converted into the M data signals.

13. The display method according to claim 12, further comprising: In the nth time period, the nth control signal among the N control signals is at the first level, and the control signals other than the nth control signal are at the second level. The nth data sub-signal among the N data sub-signals is written to the nth data line among the N data lines, 1≤n≤N, where n is a positive integer. as well as The N data sub-signals are written to the N columns of pixel units via the N data lines.

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