Semiconductor device, manufacturing method, memory, and electronic device

Abstract

The application provides a semiconductor device, a preparation method, a memory and an electronic device. The semiconductor device comprises: a first semiconductor structure, a first isolation layer and a second semiconductor structure which are sequentially stacked along a first direction; wherein the first direction is perpendicular to the first isolation layer; the first semiconductor structure comprises at least one first standard unit, each first standard unit comprises two sub-units, and each sub-unit comprises two first transistors; the second semiconductor structure comprises at least one second standard unit, each second standard unit comprises two second transistors; a power supply track is located between the two first transistors of each sub-unit, and the power supply track is connected with a first source-drain structure of the first transistor; and a conductive channel is located in the second semiconductor structure, a first end of the conductive channel is connected with a power supply metal structure in the second semiconductor structure, and a second end of the conductive channel extends along the first direction and is connected with the power supply track through the first isolation layer.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a semiconductor device, a fabrication method, a memory, and an electronic device. Background Technology

[0002] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacking transistors, by integrating two or more layers of transistors in a vertical space, further increases transistor integration density and has become one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] Existing Static Random Access Memory (SRAM) cells are all fabricated based on a single layer of transistors, and because there are many components in an SRAM cell, the SRAM is relatively large. Summary of the Invention

[0004] This application provides a semiconductor device, a fabrication method, a memory, and an electronic device to improve the integration density of transistors.

[0005] According to a first aspect of the embodiments of this application, a semiconductor device is provided, comprising:

[0006] A first semiconductor structure, a first isolation layer, and a second semiconductor structure are stacked sequentially along a first direction; wherein the first direction is perpendicular to the first isolation layer; the first semiconductor structure includes at least one first standard unit, each first standard unit includes two sub-units, and each sub-unit includes two first transistors; the second semiconductor structure includes at least one second standard unit, and each second standard unit includes two second transistors.

[0007] A power rail is located between the two first transistors in each of the sub-units, and the power rail is connected to the first source-drain structure of the first transistor;

[0008] A conductive channel is located within the second semiconductor structure, and a first end of the conductive channel is connected to a power supply metal structure within the second semiconductor structure. A second end of the conductive channel extends along the first direction and passes through the first isolation layer to connect to the power rail.

[0009] According to a second aspect of the embodiments of this application, a method for fabricating a semiconductor device is provided, comprising:

[0010] A substrate is etched to form a first initial semiconductor structure, a first isolation layer, and a second initial semiconductor structure stacked sequentially along a first direction; wherein, the first direction is a direction perpendicular to the first isolation layer; the first initial semiconductor structure includes at least one first standard cell, each first standard cell includes two sub-cells, and each sub-cell includes two first transistors; the second initial semiconductor structure includes at least one second standard cell, and each second standard cell includes two second transistors.

[0011] A power rail is formed between the two first transistors in each of the sub-units; and the power rail is connected to the first source-drain structure of the first transistor.

[0012] A first semiconductor structure is formed based on at least one of the two sub-units within the first standard unit;

[0013] A conductive channel is formed within the second initial semiconductor structure; a first end of the conductive channel is connected to a power supply metal structure within the second initial semiconductor structure, and a second end of the conductive channel extends along the first direction and passes through the first isolation layer to connect to the power rail;

[0014] The second semiconductor structure is formed based on the second initial semiconductor structure in which the conductive channels are formed.

[0015] According to a third aspect of the embodiments of this application, a memory is provided, comprising: the semiconductor device shown in the first aspect of the embodiments of this application.

[0016] According to a fourth aspect of the present application, an electronic device is provided, including: a circuit board and a memory as shown in the third aspect of the present application, wherein the memory is disposed on the circuit board.

[0017] In the semiconductor device provided in this application embodiment, a power rail is provided within a first semiconductor structure, and the power rail is connected to the first source-drain structure of a first transistor within the first semiconductor structure. A conductive channel is provided within a second semiconductor structure, with its first end connected to a power supply metal structure within the second semiconductor structure, and its second end extending along a first direction and passing through a first isolation layer between the first and second semiconductor structures to connect to the power rail within the first semiconductor structure. This achieves an electrical connection between the power supply metal structure within the second semiconductor structure and the power rail within the first semiconductor structure, electrically leading the power supply metal structure from the second semiconductor structure to the power rail within the first semiconductor structure to supply power to the first transistor within the first semiconductor structure. This further reduces the size of the semiconductor structure and increases integration density.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;

[0021] Figure 2 This is a design layout of a semiconductor device according to an embodiment of this application;

[0022] Figures 3 to 9 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application;

[0023] Figures 10 to 16 This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of this application;

[0024] Figures 17 to 23 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application;

[0025] Figures 24 to 32 This is a schematic diagram illustrating the fabrication process of another semiconductor device according to an embodiment of this application.

[0026] In the figures above: 10, semiconductor structure; 11, first semiconductor structure; 111, first dielectric wall; 112, power rail; 113, first source / drain metal structure; 114, first gate metal structure; 115, first source / drain structure; 116, first metal interconnect layer; 12, second semiconductor structure; 12a, second initial semiconductor structure; 121, second dielectric wall; 122, conductive channel; 123, second source / drain metal structure; 124, second gate metal structure; 125, second coupling metal structure; 126, second source / drain structure; 127, first dielectric layer; 128, photoresist layer; 128a, etching opening; 129, first trench; 1210 1211, second trench; 1212, second metal interconnect layer; 1213, first coupling metal structure; 1214, sacrificial fill layer; 1215, third isolation layer; 13, first isolation layer; 14, gate direct connection structure; 15, gate cut-off structure; T1, first transistor; T2, second transistor; VSS, source metal line; VDD, drain metal line; WL, word line; BL, first bit line; BL', second bit line; PG1, first PG transistor; PG2, second PG transistor; PD1, first PD transistor; PD2, second PD transistor; PU1, first PU transistor; PU2, second PU transistor. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0028] With Moore's Law continuously evolving, and beyond the technology node of gate-all-around FETs (GAA), further miniaturizing transistor size is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. This technology is considered one of the key technologies for continuing the miniaturization of integrated circuits.

[0029] In one embodiment, there are two methods for fabricating stacked transistors: the first is a monolithic stacking method, and the second is a sequential method.

[0030] Existing SRAM cells are all based on single-layer transistor fabrication, and because there are many components in an SRAM cell, the integration density and size of SRAM are relatively large.

[0031] To address the aforementioned technical problems, this application provides a semiconductor device and a method for fabricating the same, which can be used to prepare the semiconductor device provided in this application. In this application, the semiconductor device can be applied to semiconductor devices such as memory and processors.

[0032] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. (Refer to...) Figure 1 As shown, the preparation method includes at least the following steps:

[0033] Step S101: Etch the substrate to form a first initial semiconductor structure, a first isolation layer, and a second initial semiconductor structure that are stacked sequentially along a first direction;

[0034] Step S102: A power rail is formed between the two first transistors in each sub-unit; and the power rail is connected to the first source-drain structure of the first transistor.

[0035] Step S103: Based on two sub-units within a plurality of first standard units, a first semiconductor structure is formed;

[0036] Step S104: A conductive channel is formed in the second initial semiconductor structure; the first end of the conductive channel is connected to the power supply metal structure in the second semiconductor structure, and the second end of the conductive channel extends along the first direction and passes through the first isolation layer to connect with the power rail.

[0037] Step S105: Based on the second initial semiconductor structure with conductive channels formed, a second semiconductor structure is formed.

[0038] It should be noted that, Figure 1 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 1 The steps shown can be adjusted in order according to actual needs.

[0039] In some embodiments, the semiconductor device may be a stacked flip transistor.

[0040] The semiconductor device includes a first semiconductor structure and a second semiconductor structure arranged back-to-back. It should be noted that, since the first and second semiconductor structures are arranged back-to-back and stacked together, in this embodiment, the first semiconductor structure can also be referred to as a front-side transistor, and the second semiconductor structure can also be referred to as a back-side transistor. Correspondingly, each device in the front-side transistor can also be referred to as a front-side device; for example, the first source / drain metal structure in the first semiconductor structure can be referred to as a front-side source / drain metal structure, and similarly, the second source / drain metal structure in the second semiconductor structure can be referred to as a back-side source / drain metal structure.

[0041] In the embodiments of this application, the first semiconductor structure and the second semiconductor structure in the semiconductor device can be the same type of transistor, such as any of the following: planar transistor, Fin Field Effect Transistor (FinFET), Gate-All-Around Field Effect Transistor (GAAFET), and Forksheet transistor, etc. The embodiments of this application do not specifically limit the type of the first semiconductor structure and the second semiconductor structure, and they can also be other types of transistors.

[0042] like Figure 2 As shown, Figure 2 This is a design layout of a semiconductor device according to an embodiment of this application. Figure 2 (a) in the diagram is a front view of the first semiconductor structure; Figure 2 (b) in the diagram represents the backside layout of the second semiconductor structure. Here, the V0 in the frontside layout of the semiconductor device can be one or more; this embodiment of the present disclosure does not limit this, as long as the arrangement of V0 can meet the design rules.

[0043] In step S101, the substrate is etched to form a first initial semiconductor structure, a first isolation layer, and a second initial semiconductor structure that are sequentially stacked along a first direction.

[0044] The first direction is the direction perpendicular to the first isolation layer.

[0045] Understandably, the process of fabricating semiconductor devices involves first providing a substrate, and then etching the substrate to form a first initial semiconductor structure, a first isolation layer, and a second initial semiconductor structure. It is noteworthy that the first isolation layer is located between the first semiconductor structure and the second semiconductor structure, serving to isolate the two semiconductor structures.

[0046] It should be noted that the substrate may include a first substrate layer, an intermediate dielectric layer, and a second substrate layer stacked sequentially. Here, the substrate includes, but is not limited to, a silicon-on-insulator (SOI) substrate, which typically includes a buried oxide layer (i.e., an intermediate dielectric layer) and a top substrate layer (i.e., a first substrate layer) and a bottom substrate layer (i.e., a second substrate layer) located on opposite sides of the buried oxide layer.

[0047] The materials of the first substrate layer and the second substrate layer include semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The materials of the first substrate layer and the second substrate layer may be the same or different.

[0048] The material of the intermediate dielectric layer includes insulating materials, such as at least one of silicon oxide, silicon nitride, and silicon nitride.

[0049] The first initial semiconductor structure includes at least one first standard cell, each first standard cell including two sub-cells, and each sub-cell including two first transistors; the second initial semiconductor structure includes at least one second standard cell, each second standard cell including two second transistors. It should be noted that the embodiments of this application are illustrated using the example of a first initial semiconductor structure including one first standard cell and a second initial semiconductor structure including one second standard cell.

[0050] The first transistor has a first polarity, and the second transistor has a second polarity; the first polarity and the second polarity are different. In some embodiments, the first polarity is n-type, and the second polarity is p-type.

[0051] In some embodiments, step S101 above may include:

[0052] The substrate is etched to form multiple active structures, each active structure including a first active portion for fabricating a first semiconductor structure, a second active portion for fabricating a second semiconductor structure, and an insulating portion located between the first active portion and the second active portion;

[0053] An insulating material is deposited on the active structure and the substrate to form an isolation structure; the isolation structure encapsulates the active structure.

[0054] Remove a portion of the first active part from the isolation structure to expose the first active part;

[0055] Based on the exposed first active portion, a plurality of first transistors are formed within a first initial semiconductor structure;

[0056] A portion of the second active part is removed from the isolation structure to expose the second active part and form a first isolation layer; the first isolation layer surrounds the insulating part;

[0057] At least one target active structure in the active structure is subjected to fin cutting until the second active part of the target active structure is removed, forming a first trench;

[0058] Based on the retained second active portion, a plurality of second transistors are formed within the second initial semiconductor structure; wherein the retained second active portion and the removed second active portion are respectively located on both sides of the second dielectric wall of the second initial semiconductor structure.

[0059] Understandably, since the active structure comprises three parts—a first active part, a second active part, and an insulating part—and these parts are formed through the same etching process, the substrate can also be configured to comprise three parts: a first substrate layer, an intermediate dielectric layer, and a second substrate layer. The first substrate layer is used to fabricate the first active part, the second substrate layer is used to fabricate the second active part, and the insulating part is used to isolate the first and second active parts.

[0060] Specifically, when the first and second semiconductor structures in the semiconductor device are FinFETs, the active structure is a fin structure; when the first and second semiconductor structures in the semiconductor device are GAAFETs, the active structure is a nanosheet structure; and when the first and second semiconductor structures in the semiconductor device are planar transistors, the active structure is a block structure.

[0061] In some embodiments, when the first semiconductor structure and the second semiconductor structure in the semiconductor structure are fin field-effect transistors or planar transistors, both the top substrate and the bottom substrate are single-layer structures. For example, the bottom substrate and the top substrate can be single-layer silicon (Si) material.

[0062] In other embodiments, when the first semiconductor structure and the second semiconductor structure in the semiconductor structure are nanosheet field-effect transistors, both the top substrate and the bottom substrate are stacked structures. For example, the top substrate and the bottom substrate can be a stack formed by alternating deposition of silicon and silicon germanium (SiGe).

[0063] In the embodiments of this application, the isolation structure can be a shallow trench isolation (STI) structure. The insulating material forming the isolation structure can be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc., and the embodiments of this application do not specifically limit it.

[0064] In some embodiments, the height of the isolation structure is greater than the height of the active structure; after the isolation structure is formed, the above method may include performing chemical-mechanical planarization (CMP) on the isolation structure.

[0065] By performing chemical mechanical planarization on the isolation structure, the etching depth of different areas of the isolation structure can be made the same during subsequent etching, thus ensuring that the height of the exposed active structure is the same.

[0066] It should be noted that the etching process mentioned in the embodiments of this application may include, but is not limited to, any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal process. The embodiments of this application do not specifically limit this process.

[0067] The active region of the first transistor can be formed by doping the first active portion. The doping ions of the first active portion may include n-type ions (e.g., nitrogen ions, phosphorus ions, arsenic ions, etc.).

[0068] The first gate dielectric layer and the first gate metal structure can be formed by at least one of the processes such as thin film deposition, etching, and thermal oxidation, and the first source and drain structure of the first transistor can be formed by at least one of the processes such as epitaxy and doping, thereby completing the fabrication of the first transistor.

[0069] The material of the first gate dielectric layer includes at least one of silicon oxide, silicon nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc., and the material of the first gate metal structure includes conductive materials, such as tungsten nitride, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, polycrystalline silicon, doped polycrystalline silicon, etc.

[0070] It should be noted that, for ease of explanation, the first source / drain structure mentioned in the embodiments of this application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. Furthermore, the second source / drain structure, the first source / drain metal structure, the second source / drain metal structure, the source / drain groove, etc., are all similar to the first source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".

[0071] In some embodiments, the method further includes: forming a first source-drain metal structure based on the first source-drain structure.

[0072] Exemplarily, an insulating material (such as silicon dioxide (SiO2)) may be deposited on the first active portion and the first source / drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active portion and the first source / drain structure. A portion of the first interlayer dielectric layer above the first source / drain structure is etched until the upper surface of the first source / drain structure is exposed to form a first source / drain metal recess. Metal material is deposited in the first source / drain metal recess to form a first source / drain metal structure.

[0073] After the first transistor is formed, the wafer is flipped and the substrate is removed to expose the surfaces of the isolation structure and the second active portion that are far from the first semiconductor structure, so as to facilitate the subsequent fabrication of the second semiconductor structure.

[0074] It is understandable that after the wafer is flipped and the substrate is removed, the isolation structure wraps the second active part and the insulating part. The part of the isolation structure that wraps the second active part is removed, while the part of the isolation structure that wraps the insulating part is retained (for easy distinction, this retained part of the isolation structure is called the first isolation layer). The first isolation layer can be formed between the first semiconductor structure and the second semiconductor structure. The first isolation layer is used to isolate the first semiconductor structure and the second semiconductor structure.

[0075] At least one target active structure in the active structure is subjected to fin cutting until the second active part of the target active structure is removed, forming a first trench.

[0076] Understandably, an anti-reflective material can be deposited on the active structure and the first isolation layer to form a bottom anti-reflective coating (BARC); photoresist is then coated on the anti-reflective layer, and the photoresist is exposed and developed to form the back fin cut region in the photolithographic pattern (see...). Figure 2 (b) in the middle.

[0077] According to the fin cut region, the anti-reflective layer is etched until the second active portion of the target active structure under the photolithographic pattern is exposed. Then, the second active portion of the target active structure under the photolithographic pattern is selectively etched, and the etching stops at the insulating portion of the target active structure. Next, the anti-reflective layer and photoresist are removed.

[0078] After completing the fin cutting process of at least one target active structure, a plurality of second transistors are formed within the second initial semiconductor structure based on the retained second active portion.

[0079] It is worth noting that the retained second active portion and the removed second active portion are located on both sides of the second dielectric wall of the second semiconductor structure.

[0080] Here, the active region of the second transistor can be formed by doping the retained second active region. The dopant ions in the second active region include p-type ions.

[0081] The second transistor can be fabricated by employing at least one of the following processes: thin film deposition, etching, thermal oxidation, etc., to form the second gate dielectric layer and the second gate metal structure; and by employing at least one of the following processes: epitaxy, doping, etc., to form the second source / drain structure. The material of the second gate dielectric layer can be similar to that of the first gate dielectric layer, and the material of the second gate metal structure can be similar to that of the first gate metal structure.

[0082] In some embodiments, the method further includes: forming a second source-drain metal structure based on the second source-drain structure.

[0083] Exemplarily, an insulating material (such as SiO2) can be deposited on the second active portion and the second source / drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active portion and the second source / drain structure. A portion of the second interlayer dielectric layer above the second source / drain structure is etched until the upper surface of the second source / drain structure is exposed to form a second source / drain metal recess. Metal material is deposited in the second source / drain metal recess to form a second source / drain metal structure.

[0084] In step S102, a power rail is formed within the first initial semiconductor structure.

[0085] Here, the power rail may be located between the two first transistors of each sub-unit of the first initial semiconductor structure; it can be understood that the power rail may be located between the first active parts of a pair of active structures of each sub-unit.

[0086] In some embodiments, an oxide material may be deposited on the active structure and the first insulating layer to form a first insulating layer; a metal material may be deposited on the first insulating layer to form a first metal structure; the first metal structure may be etched to a predetermined height to form a second metal structure; the region of the second metal structure located outside the first active portion of the pair of active structures may be etched to obtain a third metal structure located between the first active portions of the pair of active structures; an oxide may be deposited on the third metal structure to form a power rail; the power rail may be located between the first active portions of the pair of active structures.

[0087] In some embodiments, the preset height is lower than the height of the first active part of the active structure, which is not limited here.

[0088] In this embodiment, the power rail is electrically connected to the first source-drain structure of the first transistor; it can be understood that the power rail is used to supply power to the first transistor.

[0089] In some embodiments, the power rail is electrically connected to the first source structure of the first transistor. Exemplarily, a semiconductor material may be deposited on the first source structure to form a second dielectric layer; the second dielectric layer may be etched until the power rail is exposed to form a first trench; and a metal material may be filled into the first trench to form a first metal interconnect structure. The first metal interconnect structure is used to achieve the electrical connection between the power rail and the first source structure.

[0090] In step S103, a first semiconductor structure is formed based on the first transistors of two sub-units within at least one first standard unit.

[0091] It is understandable that after the first transistor is formed, the first transistor of the two sub-units of the first standard cell within the first initial semiconductor structure is subjected to pre-processing and back-end processing to form the first semiconductor structure.

[0092] In some embodiments, the above preparation method further includes forming a first dielectric wall on the power rail.

[0093] After the power rails are formed, dielectric material is deposited on the power rails to form initial dielectric walls. The initial dielectric walls covering the power rails are then etched to form the first dielectric wall.

[0094] It is worth noting that the power rails and the first dielectric wall are stacked sequentially along the first direction.

[0095] In some embodiments, the above-described fabrication method further includes forming a third isolation layer between the first transistor and the first dielectric wall and between the first dielectric wall and the power rail, wherein the material of the third isolation layer includes silicon oxide.

[0096] In step S104, a conductive channel extending in a first direction is formed within the second initial semiconductor structure.

[0097] It is worth noting that the first end of the conductive channel is connected to the power supply metal structure within the second initial semiconductor structure, and the second end of the conductive channel extends through the first isolation layer and connects to the power rail. It can be understood that the conductive channel achieves an electrical connection between the power rail on the front side of the semiconductor device and the power supply metal structure on the back side of the semiconductor device, thereby allowing the power supply metal structure on the back side of the semiconductor device to be electrically led out to the power rail on the front side of the semiconductor device, thus supplying power to the first transistor on the front side of the semiconductor device.

[0098] In some embodiments, step S104 above includes:

[0099] After forming a first dielectric layer within the second semiconductor structure, a patterned photoresist layer is formed on the first dielectric layer. The photoresist layer includes at least one etching opening. The projection of the etching opening along a first direction is located within the second dielectric wall of the second semiconductor structure, and the etching opening is located between the removed second active portion and the retained second active portion.

[0100] The second dielectric wall of the first dielectric layer and the second semiconductor structure is etched based on the etching opening until the power rails in the first semiconductor structure are exposed, forming the second trench.

[0101] The second trench is filled to form a conductive channel.

[0102] Figures 3 to 9 This is a schematic diagram illustrating the structure of a semiconductor device according to an embodiment of this application. Figure 3 Show semiconductor device along Figure 2 A cross-sectional view along the dashed line A-A'; Figure 4 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line B-B'; Figure 5Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line C-C'; Figure 6 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line D-D'; Figure 7 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line E-E'; Figure 8 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line F-F'; Figure 9 Show semiconductor device along Figure 2 A cross-sectional view along the dashed line G-G'.

[0103] like Figures 3 to 5 As shown, the semiconductor device 10 includes a first dielectric wall 111 and a second dielectric wall 121; wherein the first dielectric wall 111 is located between two first transistors T1 in each sub-unit of the first semiconductor structure 11, and the second dielectric wall 121 is located within the second semiconductor structure 12; and the first dielectric wall 111, the power rail 112, and the second dielectric wall 121 are stacked sequentially along a first direction. A conductive channel 122 is located on the second dielectric wall 121, and the conductive channel 122 extends through the second dielectric wall 121 and the first isolation layer 13 and is connected to the power rail 112.

[0104] In some embodiments, such as Figure 3 and Figure 5 As shown, each second standard cell includes two conductive channels 122, and the two conductive channels 122 are respectively located on the side away from the gate cut-off structure 15 in the second source-drain structure of the two second transistors T2 in the second standard cell.

[0105] Figures 10 to 16 This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of this application. For ease of understanding, Figures 10 to 16 Only show along Figure 2 A cross-sectional view along the dashed line A-A'.

[0106] The following will combine Figures 3 to 9 as well as Figures 10 to 16 The above step S103 and the semiconductor device obtained are described by example.

[0107] Reference Figure 10 and Figure 11 As shown, after the first dielectric layer 127 is formed in the second initial semiconductor structure 12a, a photoresist layer 128 can be formed on the first dielectric layer 127 by processes such as coating and drying. The photoresist layer 128 is then exposed and developed to transfer the mask pattern on the mask to the photoresist layer 128 (i.e., to form a patterned photoresist layer 128), thereby forming at least one etching opening 128a in the photoresist layer 128.

[0108] Here, the mask pattern is used to define the etching locations of the conductive channel 122. For example... Figure 10 and Figure 11 As shown, the etching opening 128a is located between the removed second active portion and the retained second active portion, and the projection of the etching opening 128a along the first direction is located within the second dielectric wall 121 of the second initial semiconductor structure 12a.

[0109] Reference Figure 12 As shown, the first dielectric layer 127 is etched based on the etching opening 128a until the second dielectric wall 121 of the second initial semiconductor structure 12a is exposed; the exposed second dielectric wall 121 is etched until the power rail 112 in the first semiconductor structure 11 is exposed, forming a second trench 1210. A conductive channel 122 can be formed based on the second trench 1210.

[0110] In some embodiments, filling the second trench to form a conductive channel includes:

[0111] An insulating material is deposited on the first dielectric layer to form a second isolation layer; the second isolation layer at least covers the sidewalls of the second trench and the exposed power rails;

[0112] Etch a portion of the second isolation layer covering the power rails to expose the power rails;

[0113] Metallic material is deposited in the second trench where the second isolation layer is formed to form a conductive channel.

[0114] like Figures 13 to 14 As shown, after forming the second trench 1210, the remaining photoresist layer 128 is removed, exposing the first dielectric layer 127; an insulating material (such as silicon nitride (SiN)) is isotropically deposited on the exposed first dielectric layer 127 to form a second isolation layer 1211. The second isolation layer 1211 covers the first dielectric layer 127, the sidewalls of the second trench 1210, and the exposed power rails 112.

[0115] like Figure 15 As shown, the second isolation layer 1211 is anisotropically etched to remove the second isolation layer 1211 covering the power rail 112 and the first dielectric layer 127, exposing the power rail 112.

[0116] like Figure 16 As shown, a metal material is deposited in the second trench 1210 to form a conductive channel 122; and after forming the conductive channel 122, a subsequent process is performed on the first dielectric layer 127 to form a second metal interconnect layer 1212, thereby obtaining a second semiconductor structure 12.

[0117] It is understandable that by performing processes such as inter-interconnect dielectric deposition, metal line formation, and lead-out pad formation on the first dielectric layer, a second metal interconnect layer of the second semiconductor structure can be formed.

[0118] See Figure 16 The first semiconductor structure 11 includes a first metal interconnect layer 116, which includes signal lines; the second semiconductor structure 12 includes a second metal interconnect layer 1212, which includes power lines.

[0119] It is worth noting that the power supply metal structure within the second semiconductor structure can be a power line within the second metal interconnect layer.

[0120] It should be noted that in the semiconductor device shown in the embodiments of this application, the signal lines are disposed on the front side of the semiconductor device, i.e., within the first semiconductor structure; the power lines are disposed on the back side of the semiconductor device, i.e., within the second semiconductor structure. Here, the power lines may include a source metal line (VSS) and a drain metal line (VDD); the signal lines may include a word line (WL), a first bit line (BL), and a second bit line (BL').

[0121] In some embodiments, both the first metal interconnect layer and the second metal interconnect layer include: an M0 interconnect layer and an M1 interconnect layer.

[0122] The first end of the conductive channel is connected to the VSS in the second metal interconnect layer, and the second end of the conductive channel is connected to the power rail in the first semiconductor structure, thereby realizing the electrical connection between the power rail on the front side of the semiconductor device and the power supply metal structure on the back side of the semiconductor device.

[0123] In other embodiments, step S103 above includes:

[0124] After fin cutting the target active structure, the bottom of the first trench is etched until the first trench and the power rail in the first semiconductor structure have an overlap height in the first direction.

[0125] The first trench is filled to form a conductive channel.

[0126] Figures 17 to 23 This is a schematic diagram illustrating the structure of a semiconductor device according to an embodiment of this application. Figure 17 Show semiconductor device along Figure 2 A cross-sectional view along the dashed line A-A'; Figure 18 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line B-B'; Figure 19 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line C-C'; Figure 20 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line D-D'; Figure 21 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line E-E'; Figure 22 Show semiconductor device along Figure 2 A cross-sectional view along the direction of the dashed line F-F'; Figure 23 Show semiconductor device along Figure 2 A cross-sectional view along the dashed line G-G'.

[0127] like Figure 17 and Figure 19 As shown, the semiconductor device 10 includes: a first dielectric wall 111 and a second dielectric wall 121; wherein, the first dielectric wall 111 is located between two first transistors T1 in each sub-unit of the first semiconductor structure 11, and the second dielectric wall 121 is located in the second semiconductor structure 12; and the first dielectric wall 111, the power rail 112 and the second dielectric wall 121 are stacked sequentially along a first direction.

[0128] Each second standard cell includes two conductive channels 122. Each conductive channel 122 and the second source-drain metal structure 123 of a second transistor T2 in the second standard cell are located on both sides of the second dielectric wall 121, and the projection of each conductive channel 122 toward the second dielectric wall 121 at least partially overlaps with the power rail 112.

[0129] The portion of the sidewall in the conductive channel 122 that overlaps with the power rail 112 is in electrical contact with the exposed power rail 112.

[0130] Figures 24 to 32 This is a schematic diagram illustrating the fabrication process of another semiconductor device according to an embodiment of this application. For ease of understanding, Figures 24 to 32 Only show along Figure 2 A cross-sectional view along the direction of the dashed line A-A'.

[0131] The following will combine Figures 17 to 23 as well as Figures 24 to 32 The above step S103 and the semiconductor device obtained are described by example.

[0132] See Figure 24 and Figure 25 After fin cutting is performed on the target active structure to form the first trench 129, the bottom of the first trench 129 is etched along the first direction.

[0133] The bottom of the first trench 129 can be etched by controlling the etching depth until the first trench 129 and the power rail 112 in the first semiconductor structure 11 have an overlap height H in the first direction. A conductive channel 122 can be formed based on the first trench 129.

[0134] In some embodiments, filling the first trench to form a conductive channel includes:

[0135] The first trench is filled to form a sacrificial filler layer; the top surface of the sacrificial filler layer is flush with the opening of the first trench.

[0136] The second semiconductor structure is processed using front-end technology until a gate cut-off structure is formed.

[0137] Remove the sacrificial fill layer in the first trench;

[0138] Etch part of the trench wall in the first trench until the power rail and the second dielectric wall are exposed;

[0139] Metallic material is deposited in the first trench to form a conductive channel.

[0140] like Figure 26 As shown, after the etching process of the first trench 129 is completed, a sacrificial material is filled into the first trench 129 to form a sacrificial filling layer 1214; and the sacrificial filling layer 1214 is subjected to chemical-mechanical planarization (CMP) treatment so that the top surface of the sacrificial filling layer 1214 is flush with the groove opening of the first trench 129.

[0141] like Figure 26 As shown, after the sacrificial fill layer 1214 is formed, the second initial semiconductor structure 12a is processed by front-end technology until the gate cut-off structure 15 is formed.

[0142] For example, after forming the sacrificial fill layer, a second dielectric wall is formed within the second initial semiconductor structure; and the gate region of the second initial semiconductor structure is opened by photolithography, and polysilicon is deposited in the gate region to form a pseudo gate structure; after forming the pseudo gate structure, insulating material is deposited on the sidewalls of the pseudo gate structure according to standard procedures to form the spacer wall of the second transistor.

[0143] A second source / drain structure is formed on the retained second active portion; the dummy gate structure is removed to expose the gate region, and metal material is deposited in the gate region to form a second gate metal structure of the second initial semiconductor structure; and insulating material is deposited in other regions besides the gate region to form a second interlayer dielectric layer.

[0144] After removing the dummy gate structure and before forming the second gate metal structure, an insulating material can be deposited on the surface of the second active part to form a second gate dielectric layer, following standard procedures.

[0145] Photoresist is coated onto the second gate metal structure, and after forming a photoresist pattern, a gate cutting process is performed on the second gate metal structure in the back gate cutting region to form a gate cutting groove. After removing the photoresist, an insulating material (such as SiN) is filled into the gate switching groove to form a groove. Figure 26 The gate cut-off structure is shown.

[0146] like Figure 27 and Figure 28 As shown, after forming the gate cut-off structure 15 of the second initial semiconductor structure 12a, the first trench 129 is selectively etched to remove the sacrificial fill layer 1214 within the first trench 129. Then, selective etching continues on the first trench 129 to remove the exposed third isolation layer 1215 (i.e., the layer enclosing the second dielectric wall 121 and the power rail 112). Figure 28 The third isolation layer at the location indicated by the dashed box is etched until the power rail 112 and the second dielectric wall 121 are exposed.

[0147] like Figure 29 As shown, metallic material is deposited in the first trench 129 to form a conductive channel 122.

[0148] In some embodiments, the method further includes:

[0149] A first dielectric layer is formed based on a second initial semiconductor structure in which conductive channels are formed.

[0150] A portion of the first dielectric layer is etched to form a first via; the first via connects a conductive channel and a power supply metal structure within the second initial semiconductor structure.

[0151] Metal material is deposited in the first through hole to form the first coupled metal structure.

[0152] like Figures 30 to 32 As shown, after depositing metal material in the first trench 129 to form a conductive channel 122, the second initial semiconductor structure 12a can continue to undergo front-end processing according to the front-end process flow until the first dielectric layer 127 is formed. A first coupling metal structure 1213 is formed in the first dielectric layer 127; and after forming the first coupling metal structure 1213, back-end processing is performed on the first dielectric layer 127 to form a second metal interconnect layer 1212.

[0153] It should be noted that the first dielectric layer is formed after the front-end processing of the second semiconductor structure and before the back-end processing of the second semiconductor structure. Accordingly, the first dielectric layer is located between the device layer and the second metal interconnect layer of the second semiconductor structure. See [link to documentation]. Figure 32 The first semiconductor structure 11 includes a first metal interconnect layer 116, which includes signal lines (WL, BL, and BL'); the second semiconductor structure 12 includes a second metal interconnect layer 1212, which includes power lines (VSS and VDD).

[0154] It is worth noting that the power supply metal structure within the second initial semiconductor structure can be a power line within the second metal interconnect layer.

[0155] The first end of the conductive channel is connected to the VSS in the second metal interconnect layer through the first coupling metal structure, and the sidewall of the conductive channel near the second end is connected to the power rail in the first semiconductor structure, thereby realizing the electrical connection between the power rail on the front of the semiconductor device and the power supply metal structure on the back of the semiconductor device.

[0156] The first dielectric layer is formed after the front-end processing of the second initial semiconductor structure is completed and before the back-end processing of the second initial semiconductor structure is performed. Accordingly, the first dielectric layer is located between the device layer and the second metal interconnect layer of the second initial semiconductor structure.

[0157] In some embodiments, forming a first coupling metal structure within the first dielectric layer includes:

[0158] A via (i.e., a first via) is etched in the first dielectric layer by photolithography. The surface of the first via near the second active part is connected to a conductive channel, and the surface of the first via away from the second active part is connected to a power line of the second metal interconnect layer. A first coupling metal structure can be formed by depositing metal material in the first via. The first coupling metal structure is electrically connected to the conductive channel and the power line.

[0159] In some embodiments, the method further includes:

[0160] After forming a first dielectric layer within the second initial semiconductor structure, a portion of the first dielectric layer is etched to form a plurality of second vias; the second vias connect the second gate metal structure of each second transistor in the second standard cell to the second source / drain metal structure of another second transistor.

[0161] Metallic material is deposited in the second through-hole to form a second coupled metallic structure.

[0162] Understandably, through photolithography, a via (i.e., a second via) is etched in the first dielectric layer. The surface of the second via near the second active part is connected to the second gate metal structure of a second transistor in the second standard cell, and the surface of the second via near the second source / drain metal structure is connected to the second source / drain metal structure of another second transistor in the second standard cell. By depositing metal material in the second via, a second coupling metal structure can be formed. The second coupling metal structure is electrically connected to the second gate metal structure of a second transistor and the second source / drain metal structure of another second transistor in the second standard cell.

[0163] It should be noted that when the second initial semiconductor structure includes a second standard cell, the second initial semiconductor structure includes two second coupling metal structures. One second coupling metal structure is electrically connected to the second gate metal structure of one second transistor and the second source / drain metal structure of another second transistor in the second standard cell. The other second coupling metal structure is electrically connected to the second gate metal structure of another second transistor and the second source / drain metal structure of another second transistor in the second standard cell, thereby realizing cross-coupling between the two second transistors in the second standard cell.

[0164] In some embodiments, such as Figure 2 As shown, the semiconductor device is a six-transistor static random access memory (SRAM) cell;

[0165] The plurality of first transistors include: a first transmission gate PG transistor, a second PG transistor, a first pull-down PD transistor, and a second PD transistor; the first PG transistor and the first PD transistor are arranged side by side in a second direction; the second PD transistor and the second PG transistor are arranged side by side in a second direction; the first PG transistor and the second PD transistor are arranged side by side in a third direction; the first PD transistor and the second PG transistor are arranged side by side in a third direction; the second direction is the length direction of the second gate metal structure; the third direction is the direction perpendicular to the second direction;

[0166] The plurality of second transistors include a first pull-up PU transistor and a second PU transistor; the projection of the first PU transistor toward the first direction coincides with the first PD transistor, and the projection of the second PU transistor toward the first direction coincides with the second PD transistor.

[0167] It is understandable that, such as Figure 2As shown, the first semiconductor structure includes: a first PG transistor (PG1), a second PG transistor (PG2), a first PD transistor (PD1), and a second PD transistor (PD2). The first PG transistor PG1, the second PG transistor PG2, the first PD transistor PD1, and the second PD transistor PD2 are arranged in a "2×2" configuration, with the first PG transistor PG1 and the first PD transistor PD1 in the same row; the second PD transistor PD2 and the second PG transistor PG2 in the same row; the first PG transistor PG1 and the second PD transistor PD2 in the same column; and the first PD transistor PD1 and the second PG transistor PG2 in the same column.

[0168] Accordingly, the second semiconductor structure includes a first PU transistor (i.e., PU1) and a second PU transistor (i.e., PU2). The first PU transistor PU1 and the second PU transistor PU2 are located in different columns.

[0169] In the semiconductor device provided in this application embodiment, a power rail is provided within a first semiconductor structure, and the power rail is connected to the first source-drain structure of a first transistor within the first semiconductor structure. A conductive channel is provided within a second semiconductor structure, with its first end connected to a power supply metal structure within the second semiconductor structure, and its second end extending along a first direction and passing through a first isolation layer between the first and second semiconductor structures to connect to the power rail within the first semiconductor structure. This achieves an electrical connection between the power supply metal structure within the second semiconductor structure and the power rail within the first semiconductor structure, electrically leading the power supply metal structure from the second semiconductor structure to the power rail within the first semiconductor structure to supply power to the first transistor within the first semiconductor structure. This further reduces the size of the semiconductor structure and increases integration density.

[0170] Furthermore, the semiconductor device is a six-transistor SRAM cell, and the first semiconductor structure and the second semiconductor structure together form a flip-chip stacked transistor (i.e., semiconductor device). The combination of the flip-chip stacked transistor and the six-transistor SRAM cell can reduce the spacing between adjacent devices, thereby significantly improving the integration density.

[0171] Furthermore, signal lines (WL, BL, and BL') are disposed in the first metal interconnect layer of the first semiconductor structure, and power lines (VDD and VSS) are disposed in the second metal interconnect layer of the second semiconductor structure, so that the power lines (VDD, VSS) and signal lines (WL, BL, and BL') can achieve a wider area, thereby reducing parasitics.

[0172] Furthermore, the semiconductor device provided in this application embodiment can be inspected using detection and analysis instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the semiconductor device provided in this application embodiment can be inspected by TEM slicing to detect the back fin area, the first coupling metal structure, conductive channels, the first metal interconnect layer, and the second interconnect layer. Alternatively, the interconnection of the SRAM can be directly detected by the channel layout.

[0173] This application provides a memory, including a semiconductor structure as described in the above embodiments. Specific limitations of the semiconductor structure can be found above. Figure 2 The semiconductor devices shown will not be described in detail here.

[0174] This application provides an electronic device, including a circuit board and a memory as described in the above embodiments, wherein the memory is disposed on the circuit board. The memory includes the semiconductor device described above. Specific limitations of the semiconductor structure can be found above. Figure 2 The semiconductor devices shown will not be described in detail here.

[0175] The semiconductor devices and their fabrication methods provided in this application can be applied to next-generation integrated circuit manufacturing processes and have great application potential.

[0176] The features disclosed in the several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0177] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0178] In the description of the embodiments in this application, the terms "an embodiment," "an example," "a specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0179] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure, a first isolation layer, and a second semiconductor structure are stacked sequentially along a first direction; wherein the first direction is perpendicular to the first isolation layer; the first semiconductor structure includes at least one first standard unit, each first standard unit includes two sub-units, and each sub-unit includes two first transistors; the second semiconductor structure includes at least one second standard unit, and each second standard unit includes two second transistors. A power rail is located between the two first transistors in each of the sub-units, and the power rail is connected to the first source-drain structure of the first transistor; A conductive channel is located within the second semiconductor structure, and a first end of the conductive channel is connected to a power supply metal structure within the second semiconductor structure. A second end of the conductive channel extends along the first direction and passes through the first isolation layer to connect to the power rail.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes: A first dielectric wall is located between the two first transistors in each of the sub-units of the first semiconductor structure; The second dielectric wall is located within the second semiconductor structure, and the first dielectric wall, the power rail, and the second dielectric wall are stacked sequentially along the first direction; The conductive channel extends through the second dielectric wall and the first isolation layer and connects to the power rail.

3. The semiconductor device according to claim 2, characterized in that, Each of the second standard cells includes two conductive channels, and the two conductive channels are respectively located on the side away from the gate cutoff structure in the second source-drain structure of the two second transistors in the second standard cell.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes: A first dielectric wall is located between the two first transistors in each of the sub-units of the first semiconductor structure; The second dielectric wall is located within the second semiconductor structure, and the first dielectric wall, the power rail, and the second dielectric wall are stacked sequentially along the first direction; Each of the second standard cells includes two conductive channels, each conductive channel and a second transistor within the second standard cell are located on opposite sides of the second dielectric wall, and the projection of each conductive channel toward the second dielectric wall at least partially overlaps with the power rail; The portion of the sidewall in the conductive channel that overlaps with the power rail is in electrical contact with the exposed power rail.

5. The semiconductor device according to claim 4, characterized in that, The second transistor includes a second gate metal structure and a second source-drain metal structure; a first dielectric layer is formed on the second gate metal structure and the second source-drain metal structure; The semiconductor device further includes: Multiple first coupling metal structures are located within the first dielectric layer, and each first coupling metal structure connects the conductive channel and the power supply metal structure.

6. The semiconductor device according to claim 5, characterized in that, The second semiconductor structure further includes: Multiple second coupling metal structures are located within the first dielectric layer; The second gate metal structure of each of the second transistors in the second standard cell is connected to the second source-drain metal structure of another second transistor through the second coupling metal structure.

7. The semiconductor device according to claim 5 or 6, characterized in that, The semiconductor device is a six-transistor static random access memory (SRAM) cell. The first semiconductor structure includes: a first PG transistor, a second PG transistor, a first PD transistor, and a second PD transistor; the first PG transistor and the first PD transistor are arranged side by side in a second direction; the second PD transistor and the second PG transistor are arranged side by side in the second direction; the first PG transistor and the second PD transistor are arranged side by side in a third direction, and the first PD transistor and the second PG transistor are arranged side by side in the third direction; the second direction is the length direction of the second gate metal structure; the third direction is a direction perpendicular to the second direction; The second semiconductor structure includes a first PU transistor and a second PU transistor; the projection of the first PU transistor toward the first direction coincides with the first PD transistor, and the projection of the second PU transistor toward the first direction coincides with the second PD transistor; the first direction is perpendicular to the second direction, and the first direction is perpendicular to the third direction.

8. A method for fabricating a semiconductor device, characterized in that, The method is used to prepare the semiconductor device according to any one of claims 1 to 7, the method comprising: A substrate is etched to form a first initial semiconductor structure, a first isolation layer, and a second initial semiconductor structure stacked sequentially along a first direction; wherein, the first direction is a direction perpendicular to the first isolation layer; the first initial semiconductor structure includes at least one first standard cell, each first standard cell includes two sub-cells, and each sub-cell includes two first transistors; the second initial semiconductor structure includes at least one second standard cell, and each second standard cell includes two second transistors. A power rail is formed between the two first transistors in each of the sub-units; and the power rail is connected to the first source-drain structure of the first transistor. A first semiconductor structure is formed based on at least one of the two sub-units within the first standard unit; A conductive channel is formed within the second initial semiconductor structure; a first end of the conductive channel is connected to a power supply metal structure within the second initial semiconductor structure, and a second end of the conductive channel extends along the first direction and passes through the first isolation layer to connect to the power rail; The second semiconductor structure is formed based on the second initial semiconductor structure in which the conductive channels are formed.

9. The method according to claim 8, characterized in that, The etched substrate forms a first initial semiconductor structure, a first isolation layer, and a second initial semiconductor structure stacked sequentially, including: The substrate is etched to form a plurality of active structures, each of the active structures including a first active portion for fabricating the first semiconductor structure, a second active portion for fabricating the second semiconductor structure, and an insulating portion located between the first active portion and the second active portion; An insulating material is deposited on the active structure and the substrate to form an isolation structure; the isolation structure encapsulates the active structure. Remove a portion of the isolation structure that encloses the first active part to expose the first active part; Based on the exposed first active portion, a plurality of first transistors are formed within the first initial semiconductor structure; A portion of the insulating structure that encloses the second active portion is removed to expose the second active portion and form the first insulating layer; the first insulating layer surrounds the insulating portion; At least one target active structure in the active structure is subjected to fin cutting until the second active part of the target active structure is removed, forming a first trench; Based on the retained second active portion, a plurality of second transistors are formed within the second initial semiconductor structure; wherein the retained second active portion and the removed second active portion are respectively located on both sides of the second dielectric wall of the second initial semiconductor structure.

10. The method according to claim 9, characterized in that, The formation of a conductive channel within the second initial semiconductor structure includes: After forming a first dielectric layer within the second initial semiconductor structure, a patterned photoresist layer is formed on the first dielectric layer, the photoresist layer including at least one etching opening; wherein the projection of the etching opening along the first direction is located within the second dielectric wall of the second initial semiconductor structure, and the etching opening is located between the removed second active portion and the retained second active portion. Based on the etching opening, the second dielectric wall of the first dielectric layer and the second initial semiconductor structure is etched until the power rails in the first semiconductor structure are exposed, forming a second trench; The second trench is filled to form the conductive channel.

11. The method according to claim 10, characterized in that, The process of filling the second trench to form the conductive channel includes: An insulating material is deposited on the first dielectric layer to form a second isolation layer; the second isolation layer at least covers the sidewalls of the second trench and the exposed power rails; Etch a portion of the second isolation layer covering the power rail to expose the power rail; Metallic material is deposited within the second trench where the second isolation layer is formed to form the conductive channel.

12. The method according to claim 9, characterized in that, The formation of a conductive channel within the second initial semiconductor structure includes: After fin cutting the target active structure, the bottom of the first trench is etched until the first trench and the power rail in the first semiconductor structure have an overlap height in the first direction. The first trench is filled to form the conductive channel.

13. The method according to claim 12, characterized in that, The process of filling the first trench to form the conductive channel includes: The first trench is filled to form a sacrificial filler layer; the top surface of the sacrificial filler layer is flush with the opening of the first trench. The second initial semiconductor structure is processed using front-end technology until a gate cut-off structure is formed. Remove the sacrificial fill layer within the first trench; Etch a portion of the trench wall within the first trench until the power rail and the second dielectric wall are exposed; Metal material is deposited in the first trench to form the conductive channel.

14. The method according to claim 13, characterized in that, The method further includes: A first dielectric layer is formed based on a second initial semiconductor structure having the conductive channels formed thereon; A portion of the first dielectric layer is etched to form a first via; the first via connects the conductive channel and the power supply metal structure within the second initial semiconductor structure. Metal material is deposited in the first through hole to form a first coupled metal structure.

15. The method according to any one of claims 9 to 14, characterized in that, The method further includes: After forming a first dielectric layer within the second initial semiconductor structure, a portion of the first dielectric layer is etched to form a plurality of second vias; the second vias connect the second gate metal structure of each of the second transistors in the second standard cell to the second source / drain metal structure of another second transistor. Metallic material is deposited in the second through-hole to form a second coupled metallic structure.

16. A memory, characterized in that, include: The semiconductor device as described in any one of claims 1 to 7.

17. An electronic device, characterized in that, include: The circuit board and the memory as described in claim 16, wherein the memory is disposed on the circuit board.

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