Packaging method of superconducting quantum chip and packaged superconducting quantum chip

Abstract

The application discloses a packaging method and a packaged superconducting quantum chip. The packaging method comprises the following steps: providing a first substrate and a second substrate; preparing a first superconducting metal pattern and a Josephson junction on the one side surface of the first substrate in sequence to form a superconducting quantum chip; wherein the first superconducting metal pattern comprises a first transmission line, a first pad, a first electrode and a second electrode; the Josephson junction is located between the first electrode and the second electrode and is electrically connected with the first electrode and the second electrode to form a quantum bit; preparing a second superconducting metal pattern on the one side surface of the second substrate to form a packaging substrate; and aligning and welding the first pad and the second pad by using a flip-chip process to package the superconducting quantum chip by using the packaging substrate. By using the method, the superconducting quantum chip is packaged by using a superconducting packaging substrate, energy dissipation is reduced, the performance and heat conductivity of the superconducting quantum chip are improved, the superconducting quantum chip is easy to integrate, and the cost is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of superconducting quantum chip packaging, and particularly relates to a superconducting quantum chip packaging method and a packaged superconducting quantum chip. BACKGROUND

[0002] Superconducting quantum has developed rapidly in the past two decades, and many breakthroughs have been made in quantum chips, which provides the possibility for fault-tolerant quantum computing. For superconducting quantum chips, coplanar waveguide structure is currently used to read and control bit information by using microwave measurement and control technology. Since the pads of the superconducting quantum chip are small, in order to ensure the accuracy of the signal of the superconducting quantum chip during reading and control, the packaging of the superconducting quantum chip has become a problem of concern today.

[0003] Figure 1 A structure diagram for packaging a superconducting quantum chip provided by the prior art is shown in FIG. 1, Figure 1 As shown in FIG. 1, the existing packaging method for the superconducting quantum chip 1 mainly packages the superconducting quantum chip 1 with a PCB board 2, Figure 1 The orange block in the middle represents the pads of the PCB board 2, and the yellow block represents the pads of the superconducting quantum chip 1. When the superconducting quantum chip 1 is packaged, the pads 11 of the superconducting quantum chip 1 are electrically connected to the pads 21 of the PCB board 2 by means of aluminum wire 3 bonding, and then electrically connected to the copper wire and the peripheral pads 22 of the PCB board 2, which are pre-set on the PCB board 2. The peripheral pads 22 of the PCB board 2 are connected to the external control system for signal connection. However, the PCB board 2 is usually made of organic materials such as multi-layer resin, so the thermal conductivity of the superconducting quantum chip 1 packaged by the PCB board 2 is poor, and a large signal delay is generated when the superconducting quantum chip 1 is read and controlled by the PCB board 2, thereby increasing the electrical dissipation. In addition, due to the difference in material and process between the superconducting quantum chip 1 and the PCB board 2, the superconducting quantum chip 1 and the PCB board 2 need to be prepared by different preparation processes on different production lines, which reduces the process integration and increases the production cost. SUMMARY

[0004] The present application provides a superconducting quantum chip packaging method and a packaged superconducting quantum chip, which realizes the packaging of the superconducting quantum chip by using a superconducting packaging substrate, reduces energy dissipation, improves the performance and thermal conductivity of the superconducting quantum chip, and is easy to integrate and low in cost.

[0005] In a first aspect, the present application provides a superconducting quantum chip packaging method, comprising:

[0006] providing a first substrate and a second substrate;

[0007] A first superconducting metal pattern and a Josephson junction are sequentially fabricated on one side surface of a first substrate to form a superconducting quantum chip. The first superconducting metal pattern includes a first transmission line, a first pad, a first electrode, and a second electrode. The Josephson junction is located between the first electrode and the second electrode and is electrically connected to the first electrode and the second electrode to form a quantum bit. The first transmission line includes a readout cavity, a readout line, and a control line. The first ends of the readout cavity and the control line are both coupled to the quantum bit. The second end of the readout cavity is coupled to the first end of the readout line. The second ends of the readout line and the control line are both electrically connected to the first pad, and the first pad is located in the peripheral region of the first substrate.

[0008] A second superconducting metal pattern is prepared on one side surface of the second substrate to form an encapsulation substrate; wherein, the second superconducting metal pattern includes a second transmission line, a second pad and a third pad; the second pad corresponds one-to-one with the first pad, the second pad is electrically connected to the third pad through the second transmission line, and the third pad is located in the peripheral area of ​​the second substrate;

[0009] A flip-chip bonding process is used to align and bond the first and second pads to encapsulate the superconducting quantum chip using a packaging substrate.

[0010] Optionally, a first superconducting metal pattern and a Josephson junction are sequentially fabricated on one side surface of the first substrate to form a superconducting quantum chip, including:

[0011] A first superconducting metal layer and a first photoresist layer are sequentially deposited on one side of the first substrate.

[0012] The first photoresist layer is patterned to expose part of the first superconducting metal layer;

[0013] Remove the first photoresist layer and the exposed portion of the first superconducting metal layer to form a first superconducting metal pattern;

[0014] A Josephson junction is prepared between the first electrode and the second electrode.

[0015] Optionally, a Josephson junction is fabricated between the first and second electrodes, including:

[0016] A third superconducting metal pattern is prepared on the surface of the first superconducting metal pattern on the side away from the first substrate; the third superconducting metal pattern partially covers the first electrode.

[0017] An oxide layer is prepared on the surface of the third superconducting metal pattern on the side away from the first substrate;

[0018] A fourth superconducting metal pattern is prepared on the surface of the oxide layer away from the first substrate; the fourth superconducting metal pattern covers part of the second electrode, and there is an overlapping region between the fourth superconducting metal pattern and the third superconducting metal pattern, and the overlapping region forms a Josephson junction.

[0019] Optionally, a third superconducting metal pattern is prepared on the surface of the first superconducting metal layer away from the first substrate, including:

[0020] A second photoresist layer and a third photoresist layer are formed on the surface of the first superconducting metal pattern away from the first substrate;

[0021] The second and third photoresist layers are patterned using an electron beam lithography process to form a first opening and a second opening; the orthographic projection of the first opening on the first substrate overlaps with the first electrode portion, and the orthographic projection of the second opening on the first substrate overlaps with the second electrode portion.

[0022] The first substrate is tilted to a first preset angle with a first tilting axis. The first tilting axis is parallel to the extension direction of the second opening. The first preset angle is the angle between the first substrate and the first direction. The first direction is perpendicular to the evaporation direction.

[0023] A third superconducting metal pattern was formed by vacuum evaporation within the first opening.

[0024] A fourth superconducting metal pattern is fabricated on the surface of the oxide layer away from the first substrate, including:

[0025] The first substrate is rotated to a second preset angle about a first rotation axis; the first rotation axis is parallel to the thickness direction of the first substrate, and the second preset angle is the angle between the first substrate and the first direction;

[0026] The first substrate is tilted to a third preset angle with a second tilting axis, the second tilting axis being parallel to the extension direction of the first opening, and the third preset angle being the angle between the first substrate and the first direction;

[0027] A fourth superconducting metal pattern is formed by vacuum evaporation at a third preset angle within the first opening.

[0028] The second and third photoresist layers are removed using a stripping process to form a Josephson junction.

[0029] Optionally, an oxide layer is prepared on the surface of the third superconducting metal pattern away from the first substrate, including:

[0030] The surface of the third superconducting metal pattern away from the first substrate is oxidized to form an oxide layer.

[0031] Optionally, a second superconducting metal pattern is prepared on one side surface of the second substrate to form a packaging substrate, including:

[0032] A fourth superconducting metal layer and a fourth photoresist layer are sequentially formed on one side surface of the second substrate;

[0033] The fourth photoresist layer is patterned to expose part of the fourth superconducting metal layer;

[0034] The fourth photoresist layer and the exposed portion of the fourth superconducting metal layer are removed to form a second superconducting metal pattern.

[0035] Optionally, before forming the encapsulation substrate, a second superconducting metal pattern is prepared on one side surface of the second substrate, and the process further includes:

[0036] A drilling process is used to drill holes on the second substrate to form a first through hole and a second through hole. The first through hole corresponds one-to-one with a portion of the first pad, and the second through hole is located in the outer area of ​​the second substrate and corresponds one-to-one with a portion of the third pad.

[0037] The first through hole and the second through hole are metallized to deposit a conductive layer on the inner wall of the first through hole and the second through hole, thereby forming the first metallized through hole and the second metallized through hole;

[0038] A fifth superconducting metal layer and a fifth photoresist layer are sequentially deposited on the other side of the second substrate.

[0039] The fifth photoresist layer is patterned to form a third transmission line, a fourth pad, and a fifth pad. The fourth pad corresponds one-to-one with the first metallized via, and the fifth pad corresponds one-to-one with the second metallized via. The fourth pad and the fifth pad are electrically connected through the third transmission line.

[0040] In a second aspect, the present invention provides a packaged superconducting quantum chip, comprising: at least one superconducting quantum chip and a packaging substrate;

[0041] The superconducting quantum chip includes a first substrate, a first superconducting metal pattern and a Josephson junction located on one side surface of the first substrate; the first superconducting metal pattern includes a first transmission line, a first pad, a first electrode and a second electrode; the Josephson junction is located between the first electrode and the second electrode and is electrically connected to the first electrode and the second electrode to form a quantum bit; the first transmission line includes a readout cavity, a readout line and a control line, the first ends of the readout cavity and the control line are both coupled to the quantum bit, the second end of the readout cavity is coupled to the first end of the readout line, the second end of the readout line and the second end of the control line are both electrically connected to the first pad, and the first pad is located in the peripheral region of the first substrate;

[0042] The packaging substrate includes a second substrate and a second superconducting metal pattern located on one side surface of the second substrate; the second superconducting metal pattern includes a second transmission line, a second pad and a third pad; the second pad corresponds one-to-one with the first pad, the second pad is electrically connected to the third pad through the second transmission line, and the third pad is located in the peripheral area of ​​the second substrate;

[0043] At least one superconducting quantum chip has its first and second pads aligned and soldered using a flip-chip bonding process to encapsulate the superconducting quantum chip using a packaging substrate.

[0044] Optionally, the Josephson junction includes a third superconducting metal pattern, an oxide layer on the third superconducting metal pattern, and a fourth superconducting metal pattern on the oxide layer. The third superconducting metal pattern partially covers the first electrode, and the fourth superconducting metal pattern partially covers the second electrode. The fourth superconducting metal pattern and the third superconducting metal pattern have an overlapping region, and the overlapping region forms the Josephson junction.

[0045] Optionally, the packaging substrate may further include: a first metallized via, a second metallized via, a third transmission line, a fourth pad, and a fifth pad;

[0046] The first metallized via corresponds to a portion of the first pad and the fourth pad, respectively. The second metallized via is located in the outer region of the packaging substrate and corresponds to a portion of the third pad and the fifth pad, respectively. The fourth pad and the fifth pad are electrically connected through the third transmission line.

[0047] The technical solution of this invention involves providing a first substrate and a second substrate; sequentially fabricating a first superconducting metal pattern and a Josephson junction on one side of the first substrate to form a superconducting quantum chip; fabricating a second superconducting metal pattern on one side of the second substrate to form a packaging substrate; and aligning and bonding the first and second pads using a flip-chip bonding process to encapsulate the superconducting quantum chip using the packaging substrate. This method achieves the encapsulation of a superconducting quantum chip using a packaging substrate formed from superconducting metal materials, reducing energy dissipation, improving the performance and thermal conductivity of the superconducting quantum chip, and offering advantages such as easy integration and low cost.

[0048] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 A schematic diagram of a packaged superconducting quantum chip provided by existing technology;

[0051] Figure 2A flowchart illustrating a packaging method for a superconducting quantum chip according to Embodiment 1 of the present invention;

[0052] Figure 3 This is a process flow diagram of a superconducting quantum chip packaging provided in Embodiment 1 of the present invention;

[0053] Figure 4 This is a partial enlarged view of a Josephson knot provided in Embodiment 1 of the present invention;

[0054] Figure 5 This is a cross-sectional view of a superconducting quantum chip package provided in Embodiment 1 of the present invention;

[0055] Figure 6 This is a schematic diagram of another packaged superconducting quantum chip provided in Embodiment 1 of the present invention;

[0056] Figure 7 A flowchart illustrating a packaging method for a superconducting quantum chip according to Embodiment 2 of the present invention;

[0057] Figure 8 A flowchart illustrating a packaging method for a superconducting quantum chip according to Embodiment 3 of the present invention;

[0058] Figure 9 This is a schematic diagram of a first preset angle and a third preset angle provided in Embodiment 3 of the present invention;

[0059] Figure 10 This is a schematic diagram of a second preset angle provided in Embodiment 3 of the present invention;

[0060] Figure 11 A flowchart illustrating a packaging method for a superconducting quantum chip according to Embodiment 4 of the present invention;

[0061] Figure 12 This is a schematic diagram of a packaged superconducting quantum chip provided in Embodiment 5 of the present invention. Detailed Implementation

[0062] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0063] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] Example 1

[0065] Figure 2 This is a flowchart of a packaging method for a superconducting quantum chip provided in Embodiment 1 of the present invention. Figure 3 This is a process flow diagram of a superconducting quantum chip packaging fabrication method provided in Embodiment 1 of the present invention. Figure 4 This is a partially enlarged view of a Josephson knot provided in Embodiment 1 of the present invention. Figure 5 This is a cross-sectional view of a superconducting quantum chip package according to Embodiment 1 of the present invention. This embodiment is applicable to the packaging of superconducting quantum chips to achieve precise signal control and signal readout of the qubits in the superconducting quantum chip. Figures 2 to 5 As shown, the encapsulation method includes:

[0066] S110 provides a first substrate and a second substrate.

[0067] Among them, reference Figure 3 In Figure a), the first substrate 11 is the substrate for preparing the superconducting quantum chip 1, and the second substrate 21 is the substrate for preparing the packaging substrate 2. In this embodiment, the materials of the first substrate 11 and the second substrate 21 may include sapphire or silicon, etc., which can be determined according to the actual situation and are not limited here.

[0068] S120. A first superconducting metal pattern and a Josephson junction are sequentially fabricated on one side of the first substrate to form a superconducting quantum chip.

[0069] Among them, reference Figure 3Figure b) shows that the first superconducting metal pattern 12 is a structure formed by patterning a superconducting metal layer. The Josephson junction 13, also known as a superconducting tunnel junction, includes two superconducting metal bodies and a very thin barrier layer located between them. This thin barrier layer can be an oxide layer. In this embodiment, the first superconducting metal pattern 12 includes a first transmission line 121, a first pad 122, a first electrode 123, and a second electrode 124. The first electrode 123 and the second electrode 124 can be two electrodes of a capacitor. The first electrode 123 can be a positive electrode, and the second electrode 124 can be a negative electrode, or vice versa; no limitation is made here. (See reference...) Figure 4 Two protruding electrodes are provided on the first electrode 123, and one protruding electrode is provided on the second electrode 124. The Josephson junction 13 is located between the first electrode 123 and the second electrode 124, and is electrically connected to both electrodes 123 and 124. That is, the Josephson junction 13 is electrically connected to the two protrusions of the first electrode 123 and the one protrusion of the second electrode 124, respectively, to achieve signal conduction and form a quantum bit 14. The first transmission line 121 includes a read cavity 1211, a read line 1212, and a control line 1213. The first ends of the read cavity 1211 and the control line 1213 are both coupled to the quantum bit 14. The second end of the read cavity 1211 is coupled to the first end of the read line 1212. The second ends of the read line 1212 and the control line 1213 are both electrically connected to the first pad 122, and the first pad 122 is located in the peripheral region of the first substrate 11. Quantum bit 14 is used to store microwave photons in a quantum state. Control line 1213 is electrically connected to the first pad 122, so the control signal for regulating quantum bit 14 can be transmitted to control line 1213 of the superconducting quantum chip 1. Control line 1213 is used to output control pulses to regulate quantum bit 14. Readout cavity 1211 is used to read the quantum state of the microwave photons after regulation by quantum bit 14, for example, by changing the frequency of the quantum bit. Readout line 1212 is used to transmit the quantum state of the quantum bit read by readout cavity 1211. Readout line 1212 is electrically connected to the first pad 122, so the quantum state of quantum bit 14 read by readout cavity 1211 can be transmitted to an external control device through the first pad 122 so that the user can observe the changes in the quantum bit. In addition, the material of superconducting quantum chip 1 can be a superconducting metal material. For example, the material of superconducting quantum chip 1 may include, but is not limited to, aluminum (Al), tantalum (Ta), niobium (Nb), and titanium nitride (TiN).

[0070] Understandable Figure 3Figure b) shows a top view of the superconducting quantum chip 1, so the position of the first substrate 11 is not shown. In fact, the first substrate 11 is located below the first superconducting metal pattern 12 and the Josephson junction 13, that is, the first superconducting metal pattern 12 and the Josephson junction 13 are formed on one side of the first substrate 11.

[0071] Specifically, in fabricating the superconducting quantum chip 1, a superconducting metal layer and a photoresist layer can be deposited on one side of the surface of the first substrate 11. The formed photoresist layer is then patterned using exposure, development, and removal methods, ultimately forming a first superconducting metal pattern 12 on one side of the first substrate 11. After forming the first superconducting metal pattern 12, a Josephson junction 13 can be formed between the first electrode 123 and the second electrode 124 in the first superconducting metal pattern 12 through processes such as vapor deposition. After fabricating the first superconducting metal pattern 12 and the Josephson junction 13, the superconducting quantum chip 1 is fabricated.

[0072] S130. A second superconducting metal pattern is prepared on one side surface of the second substrate to form an encapsulation substrate.

[0073] The second superconducting metal pattern 22 includes a second transmission line 221, a second pad 222 and a third pad 223. The second pad 222 corresponds one-to-one with the first pad 122. The second pad 222 is electrically connected to the third pad 223 through the second transmission line 221, and the third pad 223 is located in the peripheral area of ​​the second substrate 21.

[0074] The encapsulation substrate 2 is used to encapsulate the superconducting quantum chip 1. The second pad 222 is used for electrical connection to the first pad 122 of the superconducting quantum chip 1. The third pad 223 is used for electrical connection between the superconducting quantum chip 1 and an external control device. The second transmission line 221 is used for electrical connection between the first pad 122 and the second pad 222, so that the quantum state signal of the qubit 14 in the superconducting quantum chip 1 can communicate normally with the external control device. The material of the second superconducting metal pattern 22 can be a superconducting metal material; for example, the material of the second superconducting metal pattern 22 may include, but is not limited to, aluminum (Al), tantalum (Ta), niobium (Nb), and titanium nitride (TiN).

[0075] For details, please refer to Figure 3 As shown in Figure c), when preparing the packaging substrate 2, a superconducting metal layer and a photoresist layer can be deposited on one side of the surface of the second substrate 21, and the formed photoresist layer can be patterned. The patterning method can include processes such as exposure and development. After removing the photoresist layer, a second superconducting metal pattern 22 can be finally formed on one side of the surface of the second substrate 21. The formed second superconducting metal pattern 22 includes a second transmission line 221, a second pad 222 and a third pad 223. That is, the formed second superconducting metal pattern 22 is the packaging substrate 2.

[0076] S140. The first and second pads are aligned and soldered using a flip-chip bonding process to encapsulate the superconducting quantum chip using a packaging substrate.

[0077] Flip-chip bonding is a technique that vertically interconnects circuits on two chips using bonding pads under certain pressure and temperature. Flip-chip bonding effectively solves the wiring problem for the control circuitry of the centrally located qubit 14, making large-scale superconducting qubit 14 wiring possible. In this embodiment, the material used in the flip-chip bonding process may include indium.

[0078] For details, please refer to Figure 3 d) diagram and Figure 5 After the superconducting quantum chip 1 and the packaging substrate 2 are fabricated, they need to be packaged. In this embodiment, a flip-chip bonding process can be used to align and bond the first pad 122 of the superconducting quantum chip 1 and the second pad 222 of the packaging substrate 2. After the bonding is completed, it indicates that the superconducting quantum chip 1 and the packaging substrate 2 are connected accordingly, and normal signal transmission can be realized. Therefore, the packaging of the superconducting quantum chip 1 is achieved.

[0079] The technical solution of this invention involves providing a first substrate and a second substrate; sequentially fabricating a first superconducting metal pattern and a Josephson junction on one side of the first substrate to form a superconducting quantum chip; fabricating a second superconducting metal pattern on one side of the second substrate to form a packaging substrate; and aligning and soldering the first and second pads using a flip-chip bonding process to encapsulate the superconducting quantum chip using the packaging substrate. This method achieves the encapsulation of a superconducting quantum chip using a packaging substrate formed from superconducting metal materials, reducing energy dissipation, improving the performance and thermal conductivity of the superconducting quantum chip, and offering advantages such as easy integration and low cost.

[0080] In another specific embodiment, Figure 6 This is a schematic diagram of another packaged superconducting quantum chip provided in Embodiment 1 of the present invention, with reference to... Figure 2 and Figure 6As shown, optionally, before forming the packaging substrate, a second transmission line, a second pad, and a third pad are prepared on one side surface of the second substrate, the method further includes: drilling holes in the second substrate using a drilling process to form a first through-hole and a second through-hole, wherein the first through-hole corresponds one-to-one with a portion of the first pad, the second through-hole is located in the peripheral region of the second substrate, and the second through-hole corresponds one-to-one with a portion of the third pad; metallizing the first through-hole and the second through-hole to deposit a conductive layer on the inner wall of the first through-hole and the second through-hole to form a first metallized through-hole and a second metallized through-hole; sequentially depositing a fifth superconducting metal layer and a fifth photoresist layer on the other side surface of the second substrate; patterning the fifth photoresist layer to form a third transmission line, a fourth pad, and a fifth pad, wherein the fourth pad corresponds one-to-one with the first metallized through-hole, the fifth pad corresponds one-to-one with the second metallized through-hole, and the fourth pad and the fifth pad are electrically connected through the third transmission line.

[0081] The drilling process involves using a laser or mechanical drilling tool to create cylindrical holes in the second substrate 21. In this embodiment, the drilling process may include, but is not limited to, laser drilling or mechanical drilling. The first metallized via 23 and the second metallized via 24 are both formed in the second substrate 21 by depositing a metallized thin film within the via using magnetron sputtering or atomic layer deposition. The material of the metallized thin film may include, but is not limited to, aluminum (Al), tantalum (Ta), niobium (Nb), and titanium nitride (TiN), to ensure that the via can conduct signals normally. The third transmission line 25 is used to electrically connect the fourth pad 26 and the fifth pad 28 to ensure normal signal transmission.

[0082] Specifically, when the superconducting quantum chip 1 has many pins, i.e., many pads need to be connected externally, to ensure that the second transmission line 221 does not cross and cause signal interference, some of the first pads 122 of the superconducting quantum chip 1 can be connected to the back side of the packaging substrate 2. In this embodiment, a drilling process can be used to drill holes in the second substrate 21 at positions corresponding to some of the first pads 122 to form first through-holes, and holes can also be drilled at positions corresponding to some of the third pads 223 to form second through-holes. That is, the formed first through-holes correspond one-to-one with some of the first pads 122, the second through-holes are located in the peripheral area of ​​the second substrate 21, and the second through-holes correspond one-to-one with some of the third pads 223. After forming the first and second through-holes, metallization is performed in the first and second through-holes 24 to form a conductive layer on the inner wall of the first and second through-holes, i.e., the first metallized through-hole 23 and the second metallized through-hole 24, so that the signal can be transmitted normally in the first metallized through-hole 23 and the second metallized through-hole 24. After the first metallized via 23 and the second metallized via 24 are formed, pads and transmission lines are fabricated on both sides of the second substrate 21. Specifically, a second pad 222, a third pad 223, and a second transmission line 221 are fabricated on one side of the second substrate 21. The specific fabrication process can be referred to the above embodiment and will not be repeated here. On the other side of the second substrate 21, a third transmission line 25, a fourth pad 26, and a fifth pad 28 are fabricated. Specifically, a fifth superconducting metal layer and a fifth photoresist layer can be sequentially deposited on the other side of the second substrate 21. By patterning the fifth photoresist layer, that is, by exposing and developing the fifth photoresist layer according to a preset pattern, a portion of the fifth superconducting metal layer can be exposed. The exposed portion of the fifth superconducting metal layer is etched using a dry etching or wet etching process to remove the exposed portion of the fifth superconducting metal layer. After etching part of the fifth superconducting metal layer, the fifth photoresist layer can be removed by processes such as stripping. The remaining structure becomes the third transmission line 25, the fourth pad 26 and the fifth pad 28. In this way, normal signal transmission can still be achieved when the superconducting quantum chip 1 has multiple pins.

[0083] Example 2

[0084] Figure 7 This is a flowchart of a packaging method for a superconducting quantum chip according to Embodiment 2 of the present invention. This embodiment refines the specific implementation of S120 in the above embodiment, in which a first superconducting metal pattern and a Josephson junction are sequentially prepared on one side of the first substrate to form a superconducting quantum chip, and refines it as follows:

[0085] A first superconducting metal layer and a first photoresist layer are sequentially deposited on one side of the first substrate.

[0086] The first photoresist layer is patterned to expose part of the first superconducting metal layer;

[0087] Remove the first photoresist layer and the exposed portion of the first superconducting metal layer to form a first superconducting metal pattern;

[0088] A Josephson junction is prepared between the first electrode and the second electrode.

[0089] like Figure 3 and Figure 7 As shown, the encapsulation method includes:

[0090] S210 provides a first substrate and a second substrate.

[0091] S220, a first superconducting metal layer and a first photoresist layer are sequentially deposited on one side of the first substrate.

[0092] Specifically, when fabricating the first superconducting metal pattern 12, a deposition can be performed on one side of the first substrate 11 to form a first superconducting metal layer of a certain thickness on that side. The deposition method can include, but is not limited to, magnetron sputtering. After forming the first superconducting metal layer, a first photoresist layer of a certain thickness can be deposited on the side of the first superconducting metal layer away from the first substrate 11. The material of the first photoresist can include, but is not limited to, AZ5214.

[0093] S230. Pattern the first photoresist layer to expose part of the first superconducting metal layer.

[0094] Specifically, after forming a first superconducting metal layer and a first photoresist layer on one side of the first substrate 11, the first photoresist layer can be patterned. The patterning method can be to expose and develop the first photoresist layer according to a preset pattern to expose the part of the first superconducting metal layer that needs to be removed.

[0095] S240: Remove the first photoresist layer and the exposed portion of the first superconducting metal layer to form a first superconducting metal pattern.

[0096] Specifically, after exposing a portion of the first superconducting metal layer, the remaining first photoresist layer and the exposed first superconducting metal layer need to be removed. This can be done using dry etching or wet etching processes to etch the exposed portion of the first superconducting metal layer, leaving the remaining portion protected by the first photoresist layer. After etching the portion of the first superconducting metal layer, the first photoresist layer also needs to be removed. The removal of the first photoresist layer can be achieved, but is not limited to, by a stripping process. After removing the first photoresist layer, the first superconducting metal layer structure remaining on one side of the first substrate 11 is the first superconducting metal pattern 12, which includes the first transmission line 121, the first pad 122, the first electrode 123, and the second electrode 124.

[0097] S250, a Josephson junction is prepared between the first electrode and the second electrode.

[0098] After the first superconducting metal pattern 12 is formed, a Josephson junction 13 with a three-layer structure can be formed between the first electrode 123 and the second electrode 124 of the first superconducting metal pattern 12 by sequential deposition. The Josephson junction 13, the first superconducting metal pattern 12, and the first substrate 11 together form the superconducting quantum chip 1. In addition, the Josephson junction 13 and the first electrode 123 and the second electrode 124 connected on both sides can form a qubit 14, providing a basis for subsequent signal modulation and readout of the qubit 14.

[0099] S260. A second superconducting metal pattern is prepared on one side surface of the second substrate to form an encapsulation substrate.

[0100] S270. The first and second pads are aligned and soldered using a flip-chip bonding process to encapsulate the superconducting quantum chip using a packaging substrate.

[0101] The technical solution of this invention involves depositing a first superconducting metal layer on one side of a first substrate; patterning the first superconducting metal layer to form a first transmission line, a first pad, a first electrode, and a second electrode; and fabricating a Josephson junction between the first and second electrodes. Using this method, a superconducting quantum chip is fabricated.

[0102] Example 3

[0103] Figure 8 This is a flowchart of a packaging method for a superconducting quantum chip provided in Embodiment 3 of the present invention. Figure 9 This is a schematic diagram of a first preset angle and a third preset angle provided in Embodiment 3 of the present invention. Figure 10 This is a schematic diagram of a second preset angle provided in Embodiment 3 of the present invention. This embodiment refines the specific implementation of S250 in the above embodiment, which involves fabricating a Josephson junction between the first and second electrodes, and can be further refined as follows:

[0104] A third superconducting metal pattern is prepared on the surface of the first superconducting metal pattern on the side away from the first substrate; the third superconducting metal pattern partially covers the first electrode.

[0105] An oxide layer is prepared on the surface of the third superconducting metal pattern on the side away from the first substrate;

[0106] A fourth superconducting metal pattern is prepared on the surface of the oxide layer away from the first substrate; the fourth superconducting metal pattern covers part of the second electrode, and there is an overlapping region between the fourth superconducting metal pattern and the third superconducting metal pattern, and the overlapping region forms a Josephson junction.

[0107] refer to Figure 3 , Figure 4 , Figures 8 to 10 As shown, the encapsulation method includes:

[0108] S310 provides a first substrate and a second substrate.

[0109] S320. A first superconducting metal layer and a first photoresist layer are sequentially deposited on one side of the first substrate.

[0110] S330. Pattern the first photoresist layer to expose part of the first superconducting metal layer.

[0111] S340: Remove the first photoresist layer and the exposed portion of the first superconducting metal layer to form a first superconducting metal pattern.

[0112] S350. A third superconducting metal pattern is prepared on the surface of the first superconducting metal pattern away from the first substrate.

[0113] This step can be further broken down as follows: forming a second photoresist layer and a third photoresist layer on the surface of the first superconducting metal pattern away from the first substrate; patterning the second and third photoresist layers using an electron beam lithography process to form a first opening and a second opening; the orthographic projection of the first opening on the first substrate overlaps with the first electrode portion, and the orthographic projection of the second opening on the first substrate overlaps with the second electrode portion; tilting the first substrate to a first preset angle with a first tilt axis, the first tilt axis being parallel to the extension direction of the second opening, the first preset angle being the angle between the first substrate and a first direction, the first direction being perpendicular to the evaporation direction; and evaporating a third superconducting metal pattern within the first opening using a vacuum evaporation process.

[0114] The second and third photoresist layers refer to etch-resistant thin film materials whose solubility changes upon irradiation or radiation by ultraviolet light, electron beams, ion beams, or X-rays. The formation methods of the second and third photoresist layers may include, but are not limited to, coating methods. The material of the second photoresist layer may include, but is not limited to, polymethyl methacrylate (PMMA), and the material of the third photoresist layer may include, but is not limited to, methacrylic acid (MAA). Electron beam exposure refers to the process of using an electron beam to prepare the desired pattern on a surface. Vacuum evaporation refers to the process of placing the material to be formed into a film in a vacuum for evaporation or sublimation to form a metal film layer of a certain thickness on the substrate surface.

[0115] Specifically, after forming the first superconducting metal pattern 12, a Josephson junction 13 needs to be fabricated between the first electrode 123 and the second electrode 124. This can be achieved by coating a second photoresist layer and a third photoresist layer onto the surface of the first superconducting metal pattern 12 away from the first substrate 11. After forming the second and third photoresist layers, an electron beam lithography process is used to pattern the second and third photoresist layers. This involves exposure and development processes according to a preset pattern to remove the exposed portions of the second and third photoresist layers. The resulting structure includes a first opening and a second opening, with the orthographic projection of the first opening onto the first substrate 11 partially overlapping the first electrode 123. (See reference...) Figure 4 The area formed by the two purple areas on the left and right and the line connecting them, and the second opening's orthogonal projection on the first substrate 11 partially overlaps with the second electrode 124, can be referenced. Figure 4 The area formed by the purple border at the bottom center and the vertical line. It can be understood that the shape of the second opening is essentially similar to the first opening, only the angle is different. Figure 4 Only a portion of the second opening structure is shown as an example; in reality, a region electrically connected to the second electrode may also exist at the symmetrical upper position below the purple area. After forming the first and second openings, a Josephson junction 13 needs to be fabricated within the first and second openings. In this embodiment, the first substrate 11 can be tilted to a first preset angle θ1 along a first tilt axis, wherein the first tilt axis is parallel to the extension direction of the second opening, and the first preset angle θ1 is the angle between the first substrate 11 and a first direction X, which is perpendicular to the evaporation direction. That is, the first preset angle θ1 is the angle between the first substrate 11 and the horizontal direction, for example, the first preset angle θ1 can be 45° or 60°. After tilting the first substrate 11 to the first preset angle θ1, a vacuum evaporation process can be used to deposit a second superconducting metal layer on the surface of the first substrate 11 at the first preset angle θ1. It is understandable that when the evaporation is performed at the first preset angle θ1, the second superconducting metal layer formed will be deposited inside the first opening and on the sidewalls of the second and third photoresist layers located on the second opening, but will not be deposited inside the second opening, so as to ensure that only the third superconducting metal pattern is formed.

[0116] It is understandable that before the third superconducting metal pattern is formed by vacuum evaporation at a first preset angle θ1 on the surface of the first substrate 11 and the first superconducting metal pattern 12, the first electrode 123 and the second electrode 124 are exposed to air, and the superconducting metal will undergo an oxidation reaction with the air, generating an oxide layer between the first electrode 123 and the second electrode 124. Therefore, in order to ensure that the third superconducting metal pattern is electrically connected to the first electrode 123, it is necessary to remove the oxide layer generated on the first electrode 123 and the second electrode 124 in advance. The specific removal method may include, but is not limited to, bombardment removal using an ion beam bombardment process in an argon ion chamber.

[0117] S360. An oxide layer is prepared on the surface of the third superconducting metal pattern on the side away from the first substrate.

[0118] This step can be further refined as follows: oxidize the surface of the third superconducting metal pattern on the side away from the first substrate to form an oxide layer.

[0119] The oxide layer is a thin film located in the middle of Josephson junction 13.

[0120] Specifically, after the third superconducting metal pattern is fabricated, the surface of the third superconducting metal pattern away from the first substrate 11 needs to be oxidized. This oxidation can be performed within an oxidation chamber. After oxidation, a thin oxide layer will be formed on the third superconducting metal pattern. It can be understood that during the formation of the oxide layer, in addition to forming an oxide layer on the surface of the third superconducting metal pattern, an oxide layer will also be formed on the surface of the third photoresist layer away from the first substrate 11. More precisely, an oxide layer is also formed on the surface of a portion of the second superconducting metal layer on the third photoresist layer.

[0121] S370. A fourth superconducting metal pattern is prepared on the surface of the oxide layer away from the first substrate. The fourth superconducting metal pattern covers part of the second electrode. The fourth superconducting metal pattern and the third superconducting metal pattern have an overlapping region, and the overlapping region forms a Josephson junction.

[0122] This step can be further broken down as follows: rotating the first substrate to a second preset angle using a first rotation axis; the first rotation axis is parallel to the thickness direction of the first substrate, and the second preset angle is the angle between the first substrate and the first direction; tilting the first substrate to a third preset angle using a second tilt axis, the second tilt axis being parallel to the extension direction of the first opening, and the third preset angle being the angle between the first substrate and the first direction; using a vacuum evaporation process to deposit a fourth superconducting metal pattern within the first opening at the third preset angle; and using a lift-off process to remove the second and third photoresist layers to form a Josephson junction.

[0123] The lift-off process involves obtaining a patterned photoresist structure or a metal mask on the first substrate 11 using photolithography, depositing a target coating layer on the mask using a coating process, and then dissolving the photoresist using a stripping solution or lift-off solution to obtain the Josephson junction 13. For example, the lift-off process can be a lift-off process.

[0124] Specifically, after the oxide layer is formed, a third layer structure of the Josephson junction 13, namely the fourth superconducting metal pattern, needs to be fabricated on the surface of the oxide layer away from the first substrate 11. In this embodiment, when the first substrate 11 returns from the oxide chamber to the evaporation chamber, since the first substrate 11 still maintains the state it was in during the first evaporation, and the fourth superconducting metal pattern formed during the second evaporation is located in a different direction from the first superconducting metal pattern formed during the first evaporation, in order to ensure that the Josephson junction 13 is normally conductive, the first substrate 11 needs to be rotated first when forming the fourth superconducting metal pattern on the oxide layer. This ensures that the second opening of the first substrate 11 after rotation is consistent with the direction of the first opening during the first evaporation. In this embodiment, the first substrate 11 can be rotated to a second preset angle Ф around a first rotation axis; the first rotation axis is parallel to the thickness direction of the first substrate 11, as shown in the reference. Figure 9 The solid line segment perpendicular to the first substrate 11, and the second preset angle Ф is the angle between the first substrate 11 and the first direction X, referenced. Figure 10As shown, for example, the second preset angle Ф can be 90°. After rotating the first substrate 11, in order to perform vapor deposition on the second opening, the first substrate 11 also needs to be tilted, that is, tilted to the third preset angle θ2 with the second tilt axis. The second tilt axis is parallel to the extension direction of the first opening. The third preset angle θ2 is the angle between the first substrate 11 and the first direction X. For example, the third preset angle θ2 can be 45° or 60°. After tilting the first substrate 11 to the first preset angle θ1, a third superconducting metal layer can be formed by vacuum vapor deposition on the surface of the oxide layer away from the first substrate 11 at the second preset angle θ2. The formed third superconducting metal layer includes a fourth superconducting metal pattern and a portion of the third superconducting metal layer located on the surface of the second superconducting metal layer away from the first substrate 11. It is understood that when using vacuum evaporation at a third preset angle θ2, the third superconducting metal layer can be deposited within the second opening, but not within the first opening. Instead, it is deposited onto the sidewalls of the second and third photoresist layers located on the first opening. The formed third superconducting metal layer includes a fourth superconducting metal pattern located within the second opening, as well as portions of the third superconducting metal layer located on the surface and sidewalls of the third photoresist layer. After the fourth superconducting metal pattern is formed, a lift-off process is used to remove the second and third photoresist layers, as well as portions of the second and third superconducting metal layers located on the second and third photoresist layers, to retain the Josephson junction 13 between the first superconducting metal pattern 12 and the first electrode 123 and the second electrode 124 on the first substrate 11. In this configuration, the first electrode 123 and the second electrode 124, together with the Josephson junction 13, can form a quantum bit 14. When the control pulse signal generated by the control line 1213 is transmitted to the quantum bit 14, the quantum state of the quantum bit 14 will undergo certain changes according to the control pulse signal, such as frequency changes. This change can be read through the readout cavity 1211 and the readout line 1212 to ultimately read the quantum state, thereby achieving precise control of the quantum bit 14.

[0125] S380. A second superconducting metal pattern is prepared on one side surface of the second substrate to form an encapsulation substrate.

[0126] S390: The first and second pads are aligned and soldered using a flip-chip bonding process to encapsulate the superconducting quantum chip using a packaging substrate.

[0127] The technical solution of this invention involves fabricating a third superconducting metal pattern on the surface of a first superconducting metal pattern away from the first substrate; the third superconducting metal pattern partially covering the first electrode; an oxide layer fabricated on the surface of the third superconducting metal pattern away from the first substrate; and a fourth superconducting metal pattern fabricated on the surface of the oxide layer away from the first substrate. The fourth superconducting metal pattern partially covers the second electrode, and the fourth and third superconducting metal patterns overlap, forming a Josephson junction. Using this method, the Josephson junction is fabricated, providing a foundation for subsequent signal modulation and readout of the qubits formed by the Josephson junction and the first and second electrodes.

[0128] Example 4

[0129] Figure 11 This is a flowchart of a packaging method for a superconducting quantum chip provided in Embodiment 4 of the present invention. This embodiment refines the specific implementation of S130 in the above embodiment, which involves preparing a second superconducting metal pattern on one side of the second substrate to form a packaging substrate, as follows:

[0130] A fourth superconducting metal layer and a fourth photoresist layer are sequentially deposited on one side of the second substrate.

[0131] The fourth photoresist layer is patterned to expose part of the fourth superconducting metal layer;

[0132] The fourth photoresist layer and the exposed portion of the fourth superconducting metal layer are removed to form a second superconducting metal pattern, thereby forming a packaging substrate.

[0133] refer to Figure 3 and Figure 11 As shown, the encapsulation method includes:

[0134] S410 provides a first substrate and a second substrate.

[0135] S420. A first superconducting metal pattern and a Josephson junction are sequentially fabricated on one side of the first substrate to form a superconducting quantum chip.

[0136] S430, a fourth superconducting metal layer and a fourth photoresist layer are sequentially formed on one side of the second substrate.

[0137] Specifically, when preparing the packaging substrate 2, a fourth superconducting metal layer of a certain thickness can be deposited on one side of the surface of the second substrate 21. The deposition method can include, but is not limited to, magnetron sputtering. After the fourth superconducting metal layer is deposited, a fourth photoresist layer of a certain thickness is formed on the side of the fourth superconducting metal layer away from the second substrate 21. The method of forming the fourth photoresist layer can include, but is not limited to, coating.

[0138] S440: Pattern the fourth photoresist layer to expose part of the fourth superconducting metal layer.

[0139] Specifically, after the fourth photoresist layer is formed on one side of the second substrate 21, the fourth photoresist layer can be patterned, that is, the fourth photoresist layer can be exposed and developed according to the preset pattern to expose the part of the fourth superconducting metal layer that needs to be removed.

[0140] S450, remove the fourth photoresist layer and the exposed portion of the fourth superconducting metal layer to form a packaging substrate.

[0141] Specifically, after exposing part of the fourth superconducting metal layer, the remaining fourth photoresist layer and the exposed fourth superconducting metal layer need to be removed. This can be done using dry etching or wet etching processes to etch the exposed portion of the fourth superconducting metal layer, leaving the remaining portion protected by the fourth photoresist layer. After etching the portion of the fourth superconducting metal layer, the fourth photoresist layer also needs to be removed. The removal of the fourth photoresist layer can be achieved, but is not limited to, using a stripping process. After removing the fourth photoresist layer, the fourth superconducting metal layer structure remaining on one side of the second substrate 21 is the second superconducting metal pattern 22, which includes the second transmission line 221, the second pad 222, and the third pad 223. The second superconducting metal pattern 22 and the second substrate 21 form the packaging substrate 2.

[0142] S460 uses a flip-chip bonding process to align and solder the first and second pads to encapsulate the superconducting quantum chip using a packaging substrate.

[0143] The technical solution of this invention involves sequentially depositing a fourth superconducting metal layer and a fourth photoresist layer on one side of a second substrate; patterning the fourth photoresist layer to expose a portion of the fourth superconducting metal layer; and removing the fourth photoresist layer and the exposed portion of the fourth superconducting metal layer to form a packaging substrate. Using this method, a packaging substrate of superconducting metal is fabricated, providing a foundation for packaging superconducting quantum chips using this substrate. Furthermore, the fabrication process is simple and cost-effective.

[0144] Example 5

[0145] refer to Figure 4 and Figure 5As shown, the encapsulated superconducting quantum chip 1 includes at least one superconducting quantum chip 1 and an encapsulation substrate 2; the superconducting quantum chip 1 includes a first substrate 11, and a first superconducting metal pattern 12 and a Josephson junction 13 located on one side surface of the first substrate 11; the first superconducting metal pattern 12 includes a first transmission line 121, a first pad 122, a first electrode 123, and a second electrode 124; the Josephson junction 13 is located between the first electrode 123 and the second electrode 124, and is electrically connected to the first electrode 123 and the second electrode 124 to form a quantum bit 14; the first transmission line 121 includes a read cavity 1211, a read line 1212, and a control line 1213, the first ends of the read cavity 1211 and the control line 1213 are both coupled to the quantum bit 14, and the second end of the read cavity 1211 is coupled to the first end of the read line 1212. The first substrate 11 is located in the peripheral region of the first substrate 11. The encapsulation substrate 2 includes a second substrate 21 and a second superconducting metal pattern 22 located on one side surface of the second substrate 21. The second superconducting metal pattern 22 includes a second transmission line 221, a second pad 222 and a third pad 223. The second pad 222 corresponds one-to-one with the first pad 122. The second pad 222 is electrically connected to the third pad 223 through the second transmission line 221 and the third pad 223 is located in the peripheral region of the second substrate 21. The first pad 122 and the second pad 222 of at least one superconducting quantum chip 1 are aligned and soldered using a flip-chip bonding process to encapsulate at least one superconducting quantum chip 1 using the encapsulation substrate 2.

[0146] The superconducting quantum chip 1 is based on the electronic circuitry of a superconducting Josephson junction 13. It can be flexibly constructed using semiconductor micro / nano processes and is considered one of the most promising and practically valuable quantum chips. It needs to operate in an extremely low-temperature environment to avoid heat interference with the quantum state, thus exhibiting quantum effects and allowing for better manipulation of these effects. The encapsulation substrate 2 is used to encapsulate the superconducting quantum chip 1, enabling precise control of signals within it. In this embodiment, the superconducting quantum chip 1 includes a first substrate 11, a first superconducting metal pattern 12, and a Josephson junction 13 located on one side of the first substrate 11. The Josephson junction 13, also known as a superconducting tunnel junction, comprises two weakly connected superconducting metal bodies. This weak connection can be composed of a thin insulating layer, a short section of non-superconducting metal, or a narrow portion that weakens the superconductivity of the contact point. The first superconducting metal pattern 12 includes a first transmission line 121, a first pad 122, a first electrode 123, and a second electrode 124. The first transmission line 121 and the first pad 122 are used to enable signal transmission between an external control device and the superconducting quantum chip 1. The first electrode 123 and the second electrode 124 can be two electrodes of a capacitor. The first electrode 123 can be a positive electrode and the second electrode 124 can be a negative electrode, or vice versa; no limitation is made here. A Josephson junction 13 is located between the first electrode 123 and the second electrode 124 and is electrically connected to the first electrode 123 and the second electrode 124. The first electrode 123, the second electrode 124, and the Josephson junction 13 form a quantum bit 14. The first transmission line 121 includes a reading cavity 1211, a reading line 1212, and a control line 1213. The first ends of both the reading cavity 1211 and the control line 1213 are coupled to the qubit 14. The second end of the reading cavity 1211 is coupled to the first end of the reading line 1212. The second ends of both the reading line 1212 and the control line 1213 are electrically connected to a first pad 122, which is located in the peripheral region of the first substrate 11. In this embodiment, the control line 1213 can be used to output control pulses to regulate the qubit 14. The control line 1213 may include XY control lines and Z control lines to regulate the qubit 14 in the X, Y, and Z directions. The reading cavity 1211 is used to read the quantum state of the microwave photon after regulation of the qubit 14, for example, it can read the frequency change of the qubit 14. The reading line 1212 is used to transmit the quantum state of the qubit 14 read by the reading cavity 1211. The encapsulation substrate 2 is used to encapsulate the superconducting quantum chip 1. The second pad 222 is used for electrical connection with the first pad 122 of the superconducting quantum chip 1. The third pad 223 is used for electrical connection between the superconducting quantum chip 1 and an external control device.The second transmission line 221 is used to electrically connect the first pad 122 and the second pad 222 so that the quantum state signal of the quantum bit 14 in the superconducting quantum chip 1 can communicate normally with the external control device.

[0147] Specifically, when signal modulation is performed on the superconducting quantum chip 1, the first pad 122 and the second pad 222 of at least one superconducting quantum chip 1 can be aligned and soldered using a flip-chip bonding process, so as to encapsulate at least one superconducting quantum chip 1 using the encapsulation substrate 2. An external control device sends a control signal, which can be transmitted to the second pad 222 via the third pad 223 and the second transmission line 221 of the packaging substrate 2. This signal is then transmitted to the control line 1213 of the superconducting quantum chip 1 via the second pad 222. Upon receiving the control signal, the control line 1213 outputs a corresponding control pulse signal and couples it to the quantum bit 14. Upon receiving the control pulse signal, the quantum state of the quantum bit 14 undergoes a change. The readout cavity 1211 can couple and transmit this change through the readout line 1212, and then through the first pad 122, the second pad 222 of the packaging substrate 2, the second transmission line 221, and the third pad 223 to the external control device. This allows for observation of the quantum state changes of the quantum bit 14 corresponding to different control pulse signals, thus enabling precise control of the quantum bit 14.

[0148] It is understandable that when the control signal emitted by the external control device changes, after the control signal is transmitted to the control line 1213, the control line 1213 will output different control pulse signals according to the changing control signal, so that the quantum state of the quantum bit 14 changes accordingly, thereby achieving precise control of the quantum bit 14 in the superconducting quantum chip 1.

[0149] in addition, Figure 12 This is a schematic diagram of another packaged superconducting quantum chip provided in Embodiment 5 of the present invention, with reference to... Figure 12As shown, if the superconducting quantum chip 1 is square and the encapsulation substrate 2 is circular, when encapsulating the superconducting quantum chip 1, since the diameter of the encapsulation substrate 2 is much larger than the side length of the superconducting quantum chip 1 (for example, if the side length of a superconducting quantum chip 1 is 1 cm, the diameter of the encapsulation substrate 2 can be 4 inches, or 10.16 cm), one or more superconducting quantum chips 1 can be placed on one encapsulation substrate 2. That is, in the thickness direction of the first substrate 11, the orthographic projection of the encapsulation substrate 2 in the thickness direction of the first substrate 11 covers the orthographic projection of at least one superconducting quantum chip 1 in the thickness direction of the first substrate 11. This allows multiple superconducting quantum chips 1 to be encapsulated using one encapsulation substrate 2, greatly reducing production costs. It is understandable that, to meet practical needs and facilitate integration, in addition to encapsulating multiple superconducting quantum chips 1, other different chips can also be encapsulated on the encapsulation substrate 2, integrating all chips onto the encapsulation substrate 2, thus greatly saving production costs.

[0150] The technical solution of this invention involves aligning and bonding the first and second pads of at least one superconducting quantum chip using a flip-chip bonding process. This encapsulates the superconducting quantum chip using a packaging substrate. When signal modulation is applied to the superconducting quantum chip, the modulation signal sent by an external control device can be transmitted through the third pad and the second transmission line of the packaging substrate to the second pad, and then through the second pad to the control line of the superconducting quantum chip. Upon receiving the modulation signal, the control line outputs a control pulse signal and couples it to the qubit. Upon receiving the control pulse signal, the quantum state of the qubit changes accordingly. After this change, the readout cavity couples and transmits the change in the quantum state signal of the qubit through the readout line, and then transmits it to the external control device through the first pad, the second pad of the packaging substrate, the second transmission line, and the third pad. Using this structure, by encapsulating the superconducting quantum chip and the packaging substrate, the changes in the quantum state of the qubit corresponding to different control pulse signals can be observed more intuitively and conveniently, achieving precise modulation of the qubit.

[0151] Optional, see reference Figure 3 and Figure 4 The Josephson junction 13 includes a third superconducting metal pattern, an oxide layer on the third superconducting metal pattern, and a fourth superconducting metal pattern on the oxide layer. The third superconducting metal pattern partially covers the first electrode 123, and the fourth superconducting metal pattern partially covers the second electrode 124. The fourth superconducting metal pattern and the third superconducting metal pattern have an overlapping region, and the overlapping region forms a Josephson junction.

[0152] The Josephson junction 13 comprises a three-layer structure: the first layer is a third superconducting metal pattern electrically connected to the first electrode 123; the second layer is an oxide layer on the third superconducting metal pattern; and the third layer is a fourth superconducting metal pattern on the oxide layer. In this embodiment, the third superconducting metal pattern partially covers the first electrode 123, and the fourth superconducting metal pattern partially covers the second electrode 124. The fourth and third superconducting metal patterns overlap, forming a Josephson junction. This allows control pulse signals to be transmitted sequentially through the first electrode 123, the third superconducting metal pattern, the oxide layer, and the fourth superconducting metal pattern to the second electrode 124, thereby controlling the qubits 14 in the superconducting quantum chip 1.

[0153] Optional, see reference Figure 6 As shown, the packaging substrate further includes: a first metallized via 23, a second metallized via 24, a third transmission line 25, a fourth pad 26, and a fifth pad 28; the first metallized via 23 corresponds one-to-one with a portion of the first pad 122 and the fourth pad 26, the second metallized via 24 is located in the peripheral area of ​​the packaging substrate 2, and the second metallized via 24 corresponds one-to-one with a portion of the third pad 223 and the fifth pad 28, and the fourth pad 26 and the fifth pad 28 are electrically connected through the third transmission line 25.

[0154] Specifically, the first metallized via 23 and the second metallized via 24 are formed by depositing a metallized thin film inside the via using magnetron sputtering or atomic beam deposition after the via is formed in the second substrate 21, so that the via can conduct signals normally. The third transmission line 25 is used to electrically connect the fourth pad 26 and the fifth pad 28 to ensure normal signal transmission.

[0155] Specifically, when the superconducting quantum chip 1 has a large number of pins, i.e., a large number of pads need to be connected externally, in order to ensure that the second transmission line 221 does not cross and cause signal interference, some of the pads of the superconducting quantum chip 1 can be connected to the back side of the packaging substrate 2. In this embodiment, a first metallized via 23, a second metallized via 24, a third transmission line 25, a fourth pad 26, and a fifth pad 28 are provided on the packaging substrate 2. The first metallized via 23 is located between a portion of the first pad 122 and the fourth pad 26, and is configured in a one-to-one correspondence with a portion of the first pad 122 and the fourth pad 26. A second metallized via 24 is disposed between a portion of the third pad 223 and the fifth pad 28, corresponding one-to-one with the portions of the third pad 223 and the fifth pad 28. The fourth pad 26 and the fifth pad 28 are electrically connected via a third transmission line 25. The second metallized via 24 is located in the peripheral area of ​​the packaging substrate 2 for electrical connection with external control equipment. This allows a portion of the signal from the superconducting quantum chip 1 to be transmitted to the back side of the packaging substrate 2 via the corresponding portion of the first pad 122 and the corresponding first metallized via 23, and then to the fifth pad 28 via the fourth pad 26 and the third transmission line 25 on the back side of the packaging substrate 2. Finally, the signal is transmitted to the third pad 223 via the fifth pad 28 and the second metallized via 24, ultimately enabling normal signal output. Similarly, the transmission path from the external control settings to the superconducting quantum chip 1 is the reverse of the above path and will not be described further here.

[0156] For example, if there are 32 first pads 122 on the periphery of the superconducting quantum chip 1, then when setting the pads and vias on the packaging substrate 2, an odd number of second pads 222 can be set on one side of the packaging substrate 2. For example, the second pads 222 corresponding to the 1st, 3rd, 5th, etc., odd-numbered first pads 122 can be set on one side, that is, the signals of the odd-numbered first pads 122 on the superconducting quantum chip 1 can be transmitted through the second transmission line 221 and the third pad 223. For even-numbered first pads 122, such as the 2nd, 4th, 6th, etc., a first metallized via 23 can be set on the packaging substrate 2 at the corresponding position, so that the control pulse signal can be transmitted to the third pad 223 through the first metallized via 23, the fourth pad 26, the third transmission line 25, the fifth pad 28, and the second metallized via 24.

[0157] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0158] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A packaging method for a superconducting quantum chip, characterized in that, include: Provide a first substrate and a second substrate; A first superconducting metal pattern and a Josephson junction are sequentially fabricated on one side surface of the first substrate to form a superconducting quantum chip. The first superconducting metal pattern includes a first transmission line, a first pad, a first electrode, and a second electrode. The Josephson junction is located between the first electrode and the second electrode and is electrically connected to both electrodes to form a quantum bit. The first transmission line includes a readout cavity, a readout line, and a control line. The first ends of the readout cavity and the control line are coupled to the quantum bit. The second end of the readout cavity is coupled to the first end of the readout line. The second ends of the readout line and the control line are electrically connected to the first pad, and the first pad is located in the peripheral region of the first substrate. A second superconducting metal pattern is formed on one side surface of the second substrate to form an encapsulation substrate; wherein, the second superconducting metal pattern includes a second transmission line, a second pad and a third pad; the second pad corresponds one-to-one with the first pad, the second pad is electrically connected to the third pad through the second transmission line, and the third pad is located in the peripheral area of ​​the second substrate; The first pad and the second pad are aligned and soldered using a flip-chip bonding process to encapsulate the superconducting quantum chip using the packaging substrate; A first superconducting metal pattern and a Josephson junction are sequentially fabricated on one side of the first substrate to form a superconducting quantum chip, comprising: A first superconducting metal layer and a first photoresist layer are sequentially formed on one side surface of the first substrate; The first photoresist layer is patterned to expose part of the first superconducting metal layer; Remove the first photoresist layer and the exposed portion of the first superconducting metal layer to form the first superconducting metal pattern; A third superconducting metal pattern is prepared on the surface of the first superconducting metal pattern on the side away from the first substrate; the third superconducting metal pattern partially covers the first electrode. An oxide layer is prepared on the surface of the third superconducting metal pattern on the side away from the first substrate; A fourth superconducting metal pattern is prepared on the surface of the oxide layer away from the first substrate; the fourth superconducting metal pattern covers a portion of the second electrode, and there is an overlapping region between the fourth superconducting metal pattern and the third superconducting metal pattern, and the overlapping region forms the Josephson junction.

2. The packaging method according to claim 1, characterized in that, Fabricating a third superconducting metal pattern on the surface of the first superconducting metal pattern away from the first substrate includes: A second photoresist layer and a third photoresist layer are formed on the surface of the first superconducting metal pattern away from the first substrate; The second photoresist layer and the third photoresist layer are patterned using an electron beam lithography process to form a first opening and a second opening; the orthographic projection of the first opening on the first substrate overlaps with the first electrode portion, and the orthographic projection of the second opening on the first substrate overlaps with the second electrode portion. The first substrate is tilted to a first preset angle with a first tilting axis, the first tilting axis being parallel to the extension direction of the second opening, the first preset angle being the angle between the first substrate and a first direction, and the first direction being perpendicular to the evaporation direction; The third superconducting metal pattern is formed by vacuum evaporation within the first opening. A fourth superconducting metal pattern is fabricated on the surface of the oxide layer away from the first substrate, including: The first substrate is rotated to a second preset angle about a first rotation axis; the first rotation axis is parallel to the thickness direction of the first substrate, and the second preset angle is the angle between the first substrate and the first direction; The first substrate is tilted to a third preset angle with a second tilting axis, the second tilting axis being parallel to the extension direction of the first opening, and the third preset angle being the angle between the first substrate and the first direction; The fourth superconducting metal pattern is formed by vacuum evaporation at the third preset angle within the first opening. The second and third photoresist layers are removed using a stripping process to form the Josephson junction.

3. The packaging method according to claim 1, characterized in that, An oxide layer is prepared on the surface of the third superconducting metal pattern on the side away from the first substrate, including: The surface of the third superconducting metal pattern away from the first substrate is oxidized to form the oxide layer.

4. The packaging method according to claim 1, characterized in that, A second superconducting metal pattern is fabricated on one side surface of the second substrate to form a packaging substrate, including: A fourth superconducting metal layer and a fourth photoresist layer are sequentially formed on one side surface of the second substrate; The fourth photoresist layer is patterned to expose part of the fourth superconducting metal layer; The fourth photoresist layer and the exposed portion of the fourth superconducting metal layer are removed to form the second superconducting metal pattern.

5. The packaging method according to claim 1, characterized in that, Before forming the encapsulation substrate, a second superconducting metal pattern is prepared on one side surface of the second substrate, which further includes: A drilling process is used to drill holes in the second substrate to form a first through hole and a second through hole. The first through hole corresponds one-to-one with a portion of the first pad, and the second through hole is located in the peripheral area of ​​the second substrate and corresponds one-to-one with a portion of the third pad. The first through hole and the second through hole are metallized to deposit a conductive layer on the inner wall of the first through hole and the second through hole, thereby forming the first metallized through hole and the second metallized through hole; A fifth superconducting metal layer and a fifth photoresist layer are sequentially deposited on the other side surface of the second substrate; The fifth photoresist layer is patterned to form a third transmission line, a fourth pad, and a fifth pad. The fourth pad corresponds one-to-one with the first metallized via, and the fifth pad corresponds one-to-one with the second metallized via. The fourth pad and the fifth pad are electrically connected through the third transmission line.

6. A packaged superconducting quantum chip, characterized in that, A packaging method for performing the superconducting quantum chip according to any one of claims 1-5, comprising: at least one superconducting quantum chip and a packaging substrate; The superconducting quantum chip includes a first substrate, a first superconducting metal pattern and a Josephson junction located on one side surface of the first substrate; the first superconducting metal pattern includes a first transmission line, a first pad, a first electrode and a second electrode; the Josephson junction is located between the first electrode and the second electrode and is electrically connected to the first electrode and the second electrode to form a quantum bit; the first transmission line includes a readout cavity, a readout line and a control line, the first ends of the readout cavity and the control line are both coupled to the quantum bit, the second end of the readout cavity is coupled to the first end of the readout line, the second end of the readout line and the second end of the control line are both electrically connected to the first pad, and the first pad is located in the peripheral region of the first substrate; The packaging substrate includes a second substrate and a second superconducting metal pattern located on one side surface of the second substrate; the second superconducting metal pattern includes a second transmission line, a second pad and a third pad; the second pad corresponds one-to-one with the first pad, the second pad is electrically connected to the third pad through the second transmission line, and the third pad is located in the peripheral area of ​​the second substrate; The first and second pads of at least one of the superconducting quantum chips are aligned and soldered using a flip-chip bonding process to encapsulate at least one of the superconducting quantum chips using the packaging substrate.

7. The encapsulated superconducting quantum chip according to claim 6, characterized in that, The Josephson junction includes a third superconducting metal pattern, an oxide layer on the third superconducting metal pattern, and a fourth superconducting metal pattern on the oxide layer. The third superconducting metal pattern partially covers the first electrode, and the fourth superconducting metal pattern partially covers the second electrode. The fourth superconducting metal pattern and the third superconducting metal pattern have an overlapping region, and the overlapping region forms the Josephson junction.

8. The encapsulated superconducting quantum chip according to claim 6, characterized in that, The packaging substrate further includes: a first metallized through-hole, a second metallized through-hole, a third transmission line, a fourth pad, and a fifth pad; The first metallized via corresponds one-to-one with a portion of the first pad and the fourth pad, the second metallized via is located in the peripheral area of ​​the packaging substrate, and the second metallized via corresponds one-to-one with a portion of the third pad and the fifth pad, the fourth pad and the fifth pad are electrically connected through the third transmission line.

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