A piezoresistive pressure sensor and a method for manufacturing the same

Abstract

The present invention belongs to the field of micro-electromechanical systems, and provides a piezoresistive pressure sensor and a preparation method thereof. The sensor is made of a 5-layer SOI silicon wafer 100 and an ordinary silicon wafer 200. The preparation method comprises the following steps: S02: etching the first structural layer of the 5-layer SOI silicon wafer to form an island structure; S03: oxidizing the upper and lower surfaces of the ordinary silicon wafer to form an oxide film, and after double-sided photolithography, etching both sides simultaneously to form a through hole; S03: bonding the first structural layer of the 5-layer SOI silicon wafer to the ordinary silicon wafer; S04: removing the substrate layer and the second buried oxide layer of the 5-layer SOI silicon wafer; S05: making a varistor on the second structural layer of the 5-layer SOI silicon wafer. The processing technology is simple, the chip utilization rate is high, the cost is low, and it is suitable for processing low-range and medium-high-range pressure sensors. The piezoresistive pressure sensor of the present invention has high sensitivity and good high temperature resistance.

Description

Technical Field

[0001] The present invention relates to the field of micro-electromechanical systems, and in particular to a method for preparing a piezoresistive pressure sensor. Background Art

[0002] MEMS pressure sensors are widely used in the fields of automobiles, aerospace, military, medical and health care, etc. Among them, MEMS piezoresistive pressure sensors are the most widely used type of pressure sensors due to their simple structure and processing technology and easy signal extraction. Sensitivity and linearity are two important technical indicators of pressure sensors. For traditional C-type silicon cup structure pressure sensors, the sensitivity is generally improved by thinning the thickness of the sensitive film, but this method will lead to increased nonlinearity. Therefore, this flat film structure is not suitable for low-range pressure sensors and is generally used in medium and high-range pressure sensors.

[0003] In order to solve this problem, an island membrane structure pressure sensor has been developed. The island membrane structure can obtain higher sensitivity and reduce nonlinearity than the flat membrane structure at the same membrane thickness. In addition, in order to increase the operating temperature of the pressure sensor, an SOI island membrane structure pressure sensor has been developed. Due to production process limitations, the preparation of pressure sensors with this structure is subject to many restrictions, including but not limited to: 1) Dry etching requires multiple layers of masks and multiple etchings, which affects the etching efficiency; 2) After wet etching, the side wall and the bottom of the cavity will form an angle greater than 90°, which is not conducive to reducing the chip area. The utilization rate of the silicon wafer is low, which also limits the application of this process in small-volume pressure sensors. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a piezoresistive pressure sensor and a preparation method thereof, which is made of a 5-layer SOI silicon wafer and a common silicon wafer, has a simple processing technology and low cost.

[0005] In a first aspect, the present invention provides a method for preparing a piezoresistive pressure sensor, wherein the piezoresistive pressure sensor is made of a 5-layer SOI silicon wafer and a common silicon wafer, wherein the 5-layer SOI silicon wafer includes a first structural layer, a first buried oxide layer, a second structural layer, a second buried oxide layer and a substrate layer arranged in sequence from top to bottom.

[0006] The preparation method comprises the following steps:

[0007] S01: Etching the first structure layer of a 5-layer SOI silicon wafer to form an island structure;

[0008] S02: After the upper and lower surfaces of the ordinary silicon wafer are oxidized to form an oxide film, double-sided photolithography is performed to form an etching pattern of the through hole, and double-sided etching is performed to form the through hole simultaneously;

[0009] S03: bonding the first structure layer of the five-layer SOI silicon wafer with the island structure to the common silicon wafer with the through hole;

[0010] S04: removing the substrate layer and the second buried oxide layer of the 5-layer SOI silicon wafer;

[0011] S05: Fabricate a varistor on the second structure layer of the 5-layer SOI silicon wafer.

[0012] Furthermore, step S01 includes the following steps: after forming an etching pattern of the island structure on the first structure layer by photolithography, forming the island structure by dry etching or wet etching.

[0013] In some embodiments, in step S04, the substrate layer and the second buried oxide layer are removed by dry etching.

[0014] Furthermore, the bonding connection method in step S03 is silicon-silicon bonding or gold-silicon bonding.

[0015] Furthermore, the thickness of the first structural layer 11 is 50-150 μm;

[0016] Furthermore, the thickness of the second structural layer 13 is 2 μm-5 μm.

[0017] Furthermore, after step S05, the method further includes:

[0018] Step S06: depositing a fourth insulating layer on the second structural layer;

[0019] Step S07: after photolithography is performed to form an etching pattern of a lead hole on the fourth insulating layer, the fourth insulating layer is etched to form a first lead hole.

[0020] Furthermore, after step S07, the method further includes:

[0021] Step S08: depositing a passivation layer on the fourth insulating layer;

[0022] Step S09: after photolithography is performed to form an etching pattern of a lead hole on the passivation layer, the passivation layer is etched to form a second lead hole.

[0023] Furthermore, after step S09, the method further includes step S10: manufacturing electrode leads on the passivation layer.

[0024] In a second aspect, the present invention further provides a piezoresistive pressure sensor, which is prepared by the preparation method of the first aspect. The piezoresistive pressure sensor comprises a piezoresistive layer, a silicon island layer and a base layer arranged in sequence from top to bottom, the piezoresistive layer is provided with a piezoresistor, the silicon island layer is provided with an island structure, and the base layer is provided with a through hole. Among them, the piezoresistive layer is made of the second structural layer of a 5-layer SOI silicon wafer; the silicon island layer is made of the first structural layer of a 5-layer SOI silicon wafer, and the base layer is made of an ordinary silicon wafer.

[0025] The features and advantages of the present invention include: forming an island structure on the first structural layer of a 5-layer SOI silicon wafer, and making a varistor on the second structural layer. Since the thickness of the first structural layer and the second structural layer of the 5-layer SOI silicon wafer can be customized, the thickness of the structural layer used to make the island structure and the structural layer used to make the varistor can be controlled, so that the thickness of the sensitive film can be controlled. Since the thinner first structural layer can be customized, it is possible to avoid multi-layer masking and etching to remove excess structural layer thickness or silicon wafer thickness during the dry etching process of the island structure. The island structure can also be processed by wet etching, which is particularly suitable for the production of small-volume pressure sensors; and since the thinner second structural layer can be customized, the high temperature resistance of the pressure sensor can be improved; and since the thickness of the first structural layer and the second structural layer can be customized, the thickness of the sensitive film can be controlled. This method can be applied to the processing of low-range and medium-high-range pressure sensors at the same time.

[0026] The method for preparing the piezoresistive pressure sensor of the present invention has a simple processing technology, high chip utilization rate, low cost, and is suitable for processing low-range and medium-high-range pressure sensors. The piezoresistive pressure sensor of the present invention has high sensitivity and good high temperature resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 It is a schematic diagram of the structure of a 5-layer SOI silicon wafer;

[0029] Figure 2 It is a schematic diagram of the structure of a common silicon wafer;

[0030] Figure 3 It is a schematic diagram of the structure after an island structure is formed on the first structure layer of a 5-layer SOI silicon wafer;

[0031] Figure 4 This is a schematic diagram of the structure after a through hole is formed on a common silicon wafer;

[0032] Figure 5 It is a schematic diagram of the structure after bonding 5-layer SOI silicon wafer and ordinary silicon wafer;

[0033] Figure 6 It is a schematic diagram of the structure after removing the substrate layer and the second buried oxide layer;

[0034] Figure 7 It is a schematic diagram of the structure after the varistor is manufactured on the second structural layer;

[0035] Figure 8 is a schematic diagram of a structure after a fourth insulating layer is deposited on the second structural layer;

[0036] Fig. 9 is a schematic diagram of a structure after a passivation layer is deposited on the fourth insulating layer;

[0037] Fig.10 It is a schematic diagram of the structure after electrode leads are made on the passivation layer;

[0038] Fig.11 Schematic diagram of the structure of a piezoresistive pressure sensor.

[0039] Description of reference numerals:

[0040] 100-5-layer SOI silicon wafer, 11-first structural layer, 112-island structure, 12-first buried oxide layer, 13-second structural layer, 14-second buried oxide layer, 15-substrate layer;

[0041] 200-ordinary silicon wafer, 21-oxide film, 22-through hole;

[0042] 300-Varistor;

[0043] 410 - fourth insulating layer, 412 - first lead hole; 420 - passivation layer, 422 - second lead hole;

[0044] 500-electrode lead;

[0045] 600 - piezoresistive pressure sensor, 610 - piezoresistive layer, 620 - silicon island layer, 630 - base layer, 641 - first insulating layer, 642 - second insulating layer, 643 - third insulating layer. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0047] See also Figure 1 , Figure 2 and Fig.10 The present invention provides a method for preparing a piezoresistive pressure sensor, which uses a 5-layer SOI silicon wafer and a common silicon wafer to prepare a piezoresistive pressure sensor 600.

[0048] The 5-layer SOI silicon wafer includes a first structure layer 11, a first buried oxide layer 12, a second structure layer 13, a second buried oxide layer 14 and a substrate layer 15. The material of the first structure layer 11 is (100) N type with a resistivity of 1~10Ω·cm, and the material of the second structure layer 13 is (100) N type with a resistivity of 1~5Ω·cm. An island structure is made on the first structure layer 11, and a varistor 300 is made on the second structure layer 13. In order to avoid interference from environmental factors on the test, the height of the silicon island is generally only tens of microns; in order to ensure the sensitivity of the sensor, the thickness of the sensitive film needs to be controlled to a few microns; and the total thickness of the SOI silicon wafer is generally not less than 200μm. Therefore, the three structure layers of the 5-layer SOI silicon wafer are designed so that the thickness of the substrate layer 15 is the thickest and the thickness of the second structure layer 13 is the thinnest. The thickness of the first structure layer 11 is customized according to the thickness of the silicon island, and the thickness of the second structure layer 13 is customized according to the thickness of the sensitive film. For example, in a 500μm 5-layer SOI silicon wafer, the thickness of the first structure layer 11 is about 0~100μm thicker than the thickness of the silicon island. When the thickness of the silicon island is 50μm, the thickness of the first structure layer 11 is customized to be 50~150μm; the thickness of the second structure layer 13 is customized to be 2μm~5μm.

[0049] The method for preparing the piezoresistive pressure sensor of the present invention is as follows: firstly, island structures are respectively made on the first structural layers of the 5-layer SOI silicon wafer, and through holes are processed on the ordinary silicon wafer; then, the first structural layers of the 5-layer SOI silicon wafer are bonded to the ordinary silicon wafer; then, the substrate layer and the second buried oxide layer of the 5-layer SOI silicon wafer are removed; and then, a varistor is made on the second structural layer of the 5-layer SOI silicon wafer. Specifically, it includes steps S01 to S05.

[0050] Step S01: See Figure 1 and Figure 3 , a 5-layer SOI silicon wafer 100 is used to etch an island structure 112 on the first structure layer 11. Specifically, after an etching pattern of the island structure is formed on the first structure layer 11 by photolithography, the island structure 112 is formed by dry or wet etching.

[0051] Step S02: See Figure 2 and Figure 4 , a common silicon wafer 200 is used, and after the upper and lower surfaces thereof are oxidized to form an oxide film 21, after the etching pattern of the through hole is formed by double-sided photolithography, the through hole 22 is formed by etching on both sides simultaneously. Specifically, the through hole 22 can be formed by wet etching. Etching on the upper and lower surfaces of the common silicon wafer 200 simultaneously can reduce the processing time. The through hole 22 formed has the largest opening at the upper and lower surfaces, and the opening gradually decreases as it extends inward, and the opening in the middle of the silicon wafer is the smallest.

[0052] Step S03: Clean the 5-layer SOI silicon wafer 100 processed in step S01 and the common silicon wafer 200 processed in step S02, and then bond the first structure layer 11 with the island structure 112 of the 5-layer SOI silicon wafer 100 to the common silicon wafer 200 with the through hole 22. Figure 5 Specifically, the bonding connection can be performed by using bonding methods such as silicon-silicon bonding and gold-silicon bonding.

[0053] Step S04: removing the substrate layer 15 and the second buried oxide layer 14 of the 5-layer SOI silicon wafer 100, such as Figure 6 Preferably, the substrate layer 15 and the second buried oxide layer 14 are removed by dry etching.

[0054] Step S05: Make four varistors 300 on the second structural layer 13, such as Figure 7 Specifically, the specific material of the second structure layer 13 can be (100) N type with a resistivity of 1-5Ω·cm, and the varistor 300 can be formed by performing a high-dose concentrated boron doping process on the second structure layer 13. More specifically, the second structure layer 13 can be doped with a high dose of concentrated boron by an ion implantation process or a high-temperature diffusion process.

[0055] Among them, step S01 and step S02 do not have a sequence and can be performed simultaneously. In the above manufacturing method, the 5-layer SOI silicon wafer 100 is first bonded to the ordinary silicon wafer 200, and then the substrate layer 15 and the second buried oxide layer 14 in the 5-layer SOI are removed, so that the ordinary silicon wafer 200 can support the first structure layer and the second structure layer in the 5-layer SOI silicon wafer 100, which is convenient for the subsequent use of a dry etching process to remove the substrate layer 15 and the second buried oxide layer 14.

[0056] Since the thickness of the first structural layer 11 and the second structural layer 13 of the 5-layer SOI silicon wafer can be customized, the thickness of the structural layer used to make the island structure and the structural layer used to make the varistor can be controlled. The thinner first structural layer 11 can be customized according to the thickness of the island structure, so it is possible to avoid removing excess structural layer thickness or silicon wafer thickness through multi-layer masking and etching during the dry etching process of the island structure; at the same time, since the first structural layer 11 is relatively thin, an island structure that meets the requirements can also be obtained through wet etching, which is particularly suitable for the production of small-volume pressure sensors. In addition, since the thinner second structural layer 13 can be customized, the consistency of the sensitive film thickness is good, which can improve the sensitivity and high temperature resistance of the pressure sensor. The processing method of the present invention has a simple process; at the same time, the chip utilization rate obtained by the processing method is high and the cost is low.

[0057] See also Figure 8, after step S05, the method further includes step S06: depositing a fourth insulating layer 410 on the second structure layer 13. Specifically, in some implementations, silicon dioxide or silicon nitride is deposited on the second structure layer 13 by thermal oxidation or chemical vapor deposition, and in other implementations, silicon dioxide is first deposited on the second structure layer 13, and then silicon nitride is deposited on the surface of silicon dioxide.

[0058] Continue to see Figure 8 , after step S06, the method further includes step S07: after photolithography forms an etching pattern of the lead hole on the fourth insulating layer 410, etching the fourth insulating layer 410 to form the first lead hole 412. Specifically, firstly, a photoresist is coated on the fourth insulating layer 410, and then photolithography is performed to form an etching pattern of the lead hole, and then the fourth insulating layer 410 in the lead hole area is wet-etched to remove, thereby forming the first lead hole 412, and then the photoresist of the fourth insulating layer 410 is removed.

[0059] See also Fig. 9 , after step S07, the method further includes step S08: depositing a passivation layer 420 on the fourth insulating layer 410. Specifically, the passivation layer 420 is deposited by chemical vapor deposition, for example, the passivation layer 420 is prepared by plasma chemical vapor deposition. The passivation layer 420 can protect the sensor.

[0060] Continue to see Fig. 9 , after step S08, the method further includes step S09: after photolithography forms an etching pattern of the lead hole on the passivation layer 420, etching the passivation layer 420 to form a second lead hole 422. Specifically, firstly, a photoresist is coated on the passivation layer 420, and then photolithography is performed to form an etching pattern of the lead hole, and then the passivation layer 420 in the lead hole area is wet-etched to remove, thereby forming the second lead hole 422, and then the photoresist on the passivation layer 420 is removed.

[0061] The first lead hole 412 and the second lead hole 422 are aligned to form a lead hole of the varistor 300 .

[0062] See also Fig.10 , after step S09, the method further includes step S10: manufacturing electrode leads 500 on the passivation layer 420. Specifically, in some embodiments, a metal layer is manufactured on the surface of the passivation layer 420, for example, the metal layer is manufactured by metal sputtering, and then the metal layer surface is photolithographically processed to form an etched pattern of the electrode leads, and then the metal layer is etched to form the electrode leads 500.

[0063] Then, alloying is performed to form an ohmic contact, and dicing is performed to obtain a MEMS piezoresistive pressure sensor. The four piezoresistors 300 of the piezoresistive pressure sensor are interconnected through electrode leads 500 to form a Wheatstone bridge.

[0064] See also Fig.11The piezoresistive pressure sensor prepared by the preparation method of the present invention comprises a piezoresistive layer 610, a third insulating layer 643, a silicon island layer 620, a second insulating layer 642, a base layer 630 and a first insulating layer 641 arranged in sequence from top to bottom. The piezoresistive layer 610 is provided with a plurality of varistors 300, the silicon island layer 620 is provided with an island structure 112, and the base layer 630 is provided with a through hole 22; the thickness of the piezoresistive layer 610 is less than the thickness of the silicon island layer 620, and the thickness of the silicon island layer 620 is less than the thickness of the base layer 630. The island structure 112 is aligned with the through hole 22, and the through hole 22 is configured to accommodate the island structure 112. The island structure 112 can move into the through hole 22 under the action of an external force without interfering with the through hole wall. The openings at both ends of the through hole 22 are large, the opening in the middle is small, and the opening gradually decreases as it extends inward from the end surface. After the silicon island layer 620 forms a back cavity structure, the remaining portion inside the back cavity becomes an island structure 112. A plurality of varistors 300 are dispersedly arranged in the stress concentration area, for example Fig.11 Schematic position. In some embodiments, the lower surface of the island structure 112 is flush with the lower surface of the peripheral structure surrounding the island structure 112. Among them, the varistor layer 610 is made of the second structure layer 13 of the 5-layer SOI silicon wafer 100, the silicon island layer 620 is made of the first structure layer 11 of the 5-layer SOI silicon wafer 100, the base layer 630 is made of the ordinary silicon wafer 200, the third insulating layer 643 corresponds to the first buried oxide layer 12 of the 5-layer SOI silicon wafer 100, and the first insulating layer 641 and the second insulating layer 642 are oxide films 21 formed after the upper and lower surfaces of the ordinary silicon wafer 200 are oxidized. In some embodiments, the thickness of the silicon island layer 620 is greater than the thickness of the island structure 112, and the thickness of the varistor layer 610 is equal to the thickness of the varistor 300.

[0065] Continue to see Fig.11 In some embodiments, the piezoresistive pressure sensor further includes a fourth insulating layer 410 and a passivation layer 420 sequentially deposited on the varistor layer 610, and lead holes are provided in the passivation layer 420 and the fourth insulating layer 410, and an electrode lead 500 is provided on the passivation layer 420, and the electrode lead 500 extends from the lead hole to be electrically connected to the varistor 300.

[0066] The piezoresistive pressure sensor of the present invention has high sensitivity, good high temperature resistance, is suitable for mass production and has low cost.

[0067] The above are only several embodiments of the present disclosure. Those skilled in the art may make various changes or modifications to the embodiments of the present disclosure based on the contents disclosed in the application documents without departing from the spirit and scope of the present disclosure.

Claims

1. A method for preparing a piezoresistive pressure sensor, characterized in that: The piezoresistive pressure sensor is made of a five-layer SOI silicon wafer (100) and a common silicon wafer (200), wherein the five-layer SOI silicon wafer (100) comprises a first structural layer (11), a first buried oxide layer (12), a second structural layer (13), a second buried oxide layer (14) and a substrate layer (15) arranged in sequence from top to bottom, wherein the thickness of the first structural layer (11) is 50 to 150 μm, and the thickness of the second structural layer (13) is 2 to 5 μm, and the preparation method comprises the following steps: S01: etching the first structure layer (11) of the 5-layer SOI silicon wafer (100) to form an island structure (112); S02: after oxidizing the upper and lower surfaces of a common silicon wafer (200) to form an oxide film (21), double-sided photolithography is performed to form an etching pattern of a through hole, and double-sided etching is performed simultaneously to form a through hole (22); S03: bonding and connecting the first structure layer (11) of the five-layer SOI silicon wafer (100) having the island structure (112) and the common silicon wafer (200) having the through hole (22); S04: removing the substrate layer (15) and the second buried oxide layer (14) of the 5-layer SOI silicon wafer (100); S05: manufacturing a varistor (300) on the second structure layer (13) of the 5-layer SOI silicon wafer (100).

2. The method for preparing a piezoresistive pressure sensor according to claim 1, characterized in that: Step S01 comprises the following steps: after photolithography is performed on the first structural layer (11) to form an etching pattern of an island structure, dry or wet etching is performed to form an island structure (112).

3. The method for preparing a piezoresistive pressure sensor according to claim 2, characterized in that: In step S04, the substrate layer (15) and the second buried oxide layer (14) are removed by dry etching.

4. The method for preparing a piezoresistive pressure sensor according to claim 3, characterized in that: The bonding connection method in step S03 is silicon-silicon bonding or gold-silicon bonding.

5. The method for preparing a piezoresistive pressure sensor according to any one of claims 1 to 4, characterized in that: After step S05, the method further includes: Step S06: depositing a fourth insulating layer (410) on the second structural layer (13); Step S07: after photolithography is performed on the fourth insulating layer (410) to form an etching pattern of a lead hole, the fourth insulating layer (410) is etched to form a first lead hole (412).

6. The method for preparing a piezoresistive pressure sensor according to claim 5, characterized in that: After step S07, the method further includes: Step S08: depositing a passivation layer (420) on the fourth insulating layer (410); Step S09: after photolithography is performed on the passivation layer (420) to form an etching pattern of a lead hole, the passivation layer (420) is etched to form a second lead hole (422).

7. The method for preparing a piezoresistive pressure sensor according to claim 6, characterized in that: After step S09, the method further includes step S10: manufacturing electrode leads (500) on the passivation layer (420).

8. A piezoresistive pressure sensor manufactured by the method according to any one of claims 1 to 7, characterized in that: The invention comprises a varistor layer (610), a silicon island layer (620) and a base layer (630) which are arranged in sequence from top to bottom, wherein the varistor layer (610) is provided with a varistor (300), the silicon island layer (620) is provided with an island structure (112), and the base layer (630) is provided with a through hole (22); The varistor layer (610) is made from the second structural layer (13) of the five-layer SOI silicon wafer (100); the silicon island layer (620) is made from the first structural layer (11) of the five-layer SOI silicon wafer (100); and the base layer (630) is made from the common silicon wafer (200).

Images