Display module and display device

Abstract

The application discloses a display module and a display device. The display module comprises a display panel and a driving chip. The driving chip comprises a plurality of chip pins, and the plurality of chip pins comprise test pins. The driving chip is bound with the display panel to form at least two test binding units. Each test binding unit comprises at least two groups of test pins and first binding pads which are connected correspondingly. The first binding pads are arranged on a non-display area of the display panel. The display panel further comprises a test pad unit and a first gating circuit. The test pad unit is connected with the first binding pads and the test pins in each test binding unit through the first gating circuit to form a binding impedance test loop. According to the above scheme, one test pad unit can form a binding impedance test loop with different test binding units, so that the number of test pad units can be reduced, the space occupied by the test pad units can be reduced, and the layout of other signal lines can be facilitated.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a display module and a display device. BACKGROUND

[0002] In current display technology, a driving chip driving a display panel to work needs to be bonded with the display panel. Before the display panel is shipped, the reliability of the bonding connection between the driving chip and the display panel is tested to avoid the shipment of products with poor bonding connection. In the prior art, a large number of bonding pads are used for the bonding test, which occupies a large amount of wiring space of the display panel and affects the wiring effect. SUMMARY

[0003] Therefore, the present application provides a display module and a display device to reduce the space occupied by the test pad unit and facilitate the layout of other signal wires.

[0004] In a first aspect, embodiments of the present application provide a display module, comprising:

[0005] a display panel, the display panel comprising a display area and a non-display area surrounding at least part of the display area;

[0006] a driving chip, the driving chip comprising a plurality of chip pins, the plurality of chip pins comprising test pins; the driving chip is bonded with the display panel to form at least two test bonding units, each test bonding unit comprising at least two groups of corresponding bonded test pins and first bonding pads, the first bonding pads being arranged in the non-display area of the display panel;

[0007] the display panel further comprises a test pad unit and a first gating circuit, the test pad unit is electrically connected to each test bonding unit through the first gating circuit, and the test pad unit is connected to the first bonding pads and the test pins in each test bonding unit through the first gating circuit to form a bonding impedance test loop.

[0008] In a second aspect, embodiments of the present application provide a display device comprising the display module of the first aspect of the present application.

[0009] The display module provided by the embodiment of the present application is provided with a test pad unit and a first gating circuit, the test pad unit is electrically connected with each test binding unit through the first gating circuit, and the test pad unit is connected with the first binding pad and the test pin in each test binding unit through the first gating circuit to form a binding impedance test loop. Under the gating effect of the first gating circuit, one test pad unit can form a binding impedance test loop with different test binding units, thereby reducing the number of test pad units, reducing the space occupied by the test pad units, leaving more layout space for other signal lines, and further reducing the wiring layout difficulty and improving the wiring effect. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A structural schematic diagram of a display module in a related art is provided for the embodiment of the present application.

[0011] Figure 2 A structural schematic diagram of a display module is provided for the embodiment of the present application.

[0012] Figure 3 A structural schematic diagram of a display module is provided for the embodiment of the present application. Figure 2 An enlarged structural schematic diagram at A.

[0013] Figure 4 A structural schematic diagram of a display module is provided for the embodiment of the present application. Figure 3 A sectional structural schematic diagram along the direction of B-B'.

[0014] Figure 5 A structural schematic diagram of another display module is provided for the embodiment of the present application.

[0015] Figure 6 A structural schematic diagram of still another display module is provided for the embodiment of the present application.

[0016] Figure 7 A structural schematic diagram of still another display module is provided for the embodiment of the present application.

[0017] Figure 8 A structural schematic diagram of still another display module is provided for the embodiment of the present application. Figure 7 A sectional structural schematic diagram along the direction of C-C'.

[0018] Figure 9 A structural schematic diagram of still another display module is provided for the embodiment of the present application.

[0019] Figure 10 A structural schematic diagram of still another display module is provided for the embodiment of the present application. Figure 9 A sectional structural schematic diagram along the direction of D-D'.

[0020] Figure 11 A structural schematic diagram of still another display module is provided for the embodiment of the present application.

[0021] Figure 12Yet another structural schematic diagram of a display module provided by an embodiment of the present application is shown in FIG. 6.

[0022] Figure 13 Yet another structural schematic diagram of a display module provided by an embodiment of the present application is shown in FIG. 6.

[0023] Figure 14 A structural schematic diagram of a display device provided by an embodiment of the present application is shown in FIG. 7. DETAILED DESCRIPTION

[0024] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended for the purpose of interpretation of the present application and are not intended to limit the present application. In addition, it should be noted that only the parts related to the present application are shown in the accompanying drawings for the purpose of description.

[0025] The terms used in the embodiments of the present application are merely intended for the purpose of description of specific embodiments and are not intended to limit the present application. It should be noted that "have", "contain", "include" and the like described in the present application are all open-ended terms, i.e., when a module is described as "having", "containing" or "including" a first element, a second element and / or a third element, it means that the module includes other elements in addition to the first element, the second element and / or the third element. The orientation terms such as "upper", "lower", "left", "right" and the like described in the embodiments of the present application are described in the angle shown in the accompanying drawings and should not be understood as limiting the embodiments of the present application.

[0026] In addition, it should be understood in the context that when one element is mentioned to be formed "on" or "under" another element, it can be directly formed "on" or "under" the other element or indirectly formed "on" or "under" the other element through an intermediate element. The terms "first", "second" and the like are merely used for the purpose of description and do not represent any order, quantity or importance, but are merely used to distinguish different components. In addition, the ordinal terms "first", "second" and "third" in the present application are not intended to limit the specific order, but merely to distinguish the parts. In the present application, when layer A and layer B are described as "disposed in the same layer", it means that layer A and layer B are made of the same material and by the same process. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0027] Figure 1 A structural schematic diagram of a display module in a related art provided by an embodiment of the present application is shown in FIG. 5. Figure 1In the related art, when performing a binding impedance test, the test pins 21 on the driving chip 2 and the test pads 40 are in a one-to-one correspondence. For example, to measure the binding of the 4 test pins 21 on the left side and the 4 test pins 21 on the right side of the driving chip 2, 8 test pads 40 are arranged on the display panel, and the test pads 40 are connected to the test pins 21 one by one to transmit test signals to the test pins 21, so as to determine the binding impedance of the test pins 21 according to the test signals, and determine whether the test pins 21 are normally bound according to the binding impedance. The test pads 40 are formed on the display panel, and the inventors find that, according to the above arrangement of the test pads 40, the test pads 40 will occupy a large space of the frame of the display panel, thereby squeezing the arrangement space of other lines, increasing the difficulty of line arrangement, and affecting the line arrangement effect.

[0028] Based on the defects of the above related art, the present application provides a display module, comprising:

[0029] a display panel, the display panel comprising a display area and a non-display area surrounding at least part of the display area;

[0030] a driving chip, the driving chip comprising a plurality of chip pins, the plurality of chip pins comprising test pins; the driving chip is bound with the display panel to form at least two test binding units, each test binding unit comprising at least two groups of test pins and first binding pads connected correspondingly, and the first binding pads are arranged on the non-display area of the display panel;

[0031] The display panel further comprises a test pad unit and a first gating circuit, the test pad unit is electrically connected to each test binding unit through the first gating circuit, and the test pad unit is connected to the first binding pads and the test pins in each test binding unit through the first gating circuit to form a binding impedance test loop.

[0032] Through the above technical solution, under the gating action of the first gating circuit, one test pad unit can form a binding impedance test loop with different test binding units, thereby reducing the number of test pad units and the space occupied by the test pad units, leaving more layout space for other signal lines, thereby reducing the difficulty of line arrangement and improving the wiring effect.

[0033] The above is the core idea of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0034] Figure 2 A structural schematic diagram of a display module provided by the embodiment of the present application, Figure 3 is provided.Figure 2 An enlarged structural schematic view at A, Figure 4 As Figure 3 An enlarged structural schematic view at A, Figures 2 to 4 In the embodiment of the present application, the display module comprises: a display panel 1, the display panel 1 comprising a display area AA and a non-display area NA surrounding at least part of the display area AA; a driving chip 2, the driving chip 2 comprising a plurality of chip pins 20, the plurality of chip pins 20 comprising test pins 21; the driving chip 2 is bound with the display panel 1 to form at least two test binding units 3, the test binding unit 3 comprising at least two groups of corresponding binding connection test pins 21 and first binding pads 11, the first binding pads 11 being arranged on the non-display area NA of the display panel 1; the display panel 1 further comprises test pad units 4 and first gating circuits 5, the test pad units 4 being electrically connected with each test binding unit 3 through the first gating circuits 5, and the test pad units 4 being connected with the first binding pads 11 and the test pins 21 in each test binding unit 3 through the first gating circuits 5 to form a binding impedance test loop.

[0035] As Figures 2 to 4 shown, the display module comprises a display panel 1 and a driving chip 2 bound with the display panel 1, and the driving chip 2 is bound to the non-display area NA of the display panel 1. The driving chip 2 is exemplarily shown as being bound in the non-display area NA on the lower side of the display panel 1, but is not limited thereto. The driving chip 2 is used to provide various signals required for display to the display panel 1.

[0036] In the embodiment of the present application, the display panel 1 can be provided with a plurality of chip binding pads 10, and the chip pins 20 in the driving chip 2 are connected with the chip binding pads 10 through anisotropic conductive adhesive, so as to realize the binding of the driving chip 2 and the display panel 1. Figure 3 In the embodiment of the present application, the display panel 1 can be provided with a plurality of chip binding pads 10, and the chip pins 20 in the driving chip 2 are connected with the chip binding pads 10 through anisotropic conductive adhesive, so as to realize the binding of the driving chip 2 and the display panel 1. Figure 4 In the cross-sectional view, only the chip pins 20 and the chip binding pads 10 are shown, and the structures such as the driving chip 2 are not shown.

[0037] Continuing to refer to Figures 2 to 4 The chip pins 20 comprise at least two test pins 21, the chip binding pads 10 comprise at least two first binding pads 11, and the test pins 21 and the first binding pads 11 are correspondingly bound to form the test binding unit 3. The test pins 21 and the first binding pads 11 in the test binding unit 3 are used for binding impedance test.

[0038] Further, as Figures 2 to 4As shown, the non-display area NA of the display panel 1 further includes a test pad unit 4, which can include a test pad 40, and is used to receive an impedance test signal during a binding impedance test. The test pad unit 4 can be located on the side of the driving chip 2 away from the display area AA. It is worth mentioning that in the embodiment of the present application, a first gating circuit 5 is further arranged in the display panel 1, and the first gating circuit 5, the test pad unit 4 and the driving chip 2 can be arranged in the non-display area NA on the same side of the display panel 1. The test pad unit 4 is connected to the at least two test binding units 3 through the first gating circuit 5. The first gating circuit 5 has a gating function, and the test pad unit 4 and the test binding unit 3 are connected through the first gating circuit 5, so that one test pad unit 4 can be connected to different test binding units 3. Thus, one test pad unit 4 can form a binding impedance test loop with different test binding units 3 in time division mode. The binding impedance test loop includes the test pad 40 in the test pad unit 4, the first gating circuit 5, and the chip pin 20 and the first binding pad 11 in the test binding unit 3 gated by the first gating circuit 5.

[0039] In this arrangement, under the gating action of the first gating circuit, one test pad unit can form a binding impedance test loop with different test binding units, thereby reducing the number of test pad units, i.e., reducing the number of test pads, reducing the space occupied by the test pad unit, leaving more space for other signal wiring, and thus reducing the wiring layout difficulty and improving the wiring effect.

[0040] In this arrangement, under the gating action of the first gating circuit, one test pad unit can form a binding impedance test loop with different test binding units, thereby reducing the number of test pad units, i.e., reducing the number of test pads, reducing the space occupied by the test pad unit, leaving more space for other signal wiring, and thus reducing the wiring layout difficulty and improving the wiring effect.

[0041] The display module provided by the embodiment of the present application includes a test pad unit and a first gating circuit. The test pad unit is electrically connected to each test binding unit through the first gating circuit, and the test pad unit is connected to the first binding pad and the test pin in each test binding unit through the first gating circuit to form a binding impedance test loop. Under the gating action of the first gating circuit, one test pad unit can form a binding impedance test loop with different test binding units, thereby reducing the number of test pad units, reducing the space occupied by the test pad unit, leaving more space for other signal wiring, and thus reducing the wiring layout difficulty and improving the wiring effect.

[0042] Optionally, Figure 5 Another structure diagram of the display module provided by the embodiment of the present application can be combined with reference to Figures 2 to 5In a possible embodiment, the at least two test binding units 3 include at least one first test binding unit 31 and at least one second test binding unit 32; the first gating circuit 5 includes a first gating unit 51 and a second gating unit 52, the test pad unit 4 is electrically connected to the first test binding unit 31 through the first gating unit 51 and is electrically connected to the second test binding unit 32 through the second gating unit 52; the display module includes a first test stage and a second test stage, in the first test stage, the test pad unit 4 is gated to the first test binding unit 31 by using the first gating unit 51, and the first binding pad 11 in the test pad unit 4 and the first test binding unit 31 is connected to the test pin 21 to form a first binding impedance test loop; in the second test stage, the test pad unit 4 is gated to the second test binding unit 32 by using the second gating unit 52, and the first binding pad 11 in the test pad unit 4 and the second test binding unit 32 is connected to the test pin 21 to form a second binding impedance test loop.

[0043] As shown in Figures 2 to 5 , in the embodiment, the test binding unit 3 can be divided into the first test binding unit 31 and the second test binding unit 32, the first test binding unit 31 and the second test binding unit 32 refer to two different test binding units 3 connected to the same test pad 40 in the test pad unit 4.

[0044] Specifically, the test pad unit 4 can be connected to one end of the first gating unit 51 through a wire, the other end of the first gating unit 51 is connected to the first test binding unit 31 through a wire; the test pad unit 4 is also connected to one end of the second gating unit 52 through a wire, the other end of the second gating unit 52 is connected to the second test binding unit 32 through a wire, and the above wires can be connection wires in the display panel 1.

[0045] In this arrangement, the binding test process of the display panel 1 and the driving chip 2 can include a first test stage and a second test stage. In the first test stage, as shown in Figure 2 , the first gating unit 51 is gated, so that the test pad unit 4 is connected to the first test binding unit 31, and the test pin 21 and the first binding pad 11 in the test pad unit 4, the first gating unit 51 and the first test binding unit 31 are connected to form a first binding impedance test loop; the binding impedance of the first binding pad 11 and the test pin 21 in the first test binding unit 31 is detected by using the first binding impedance test loop. In the second test stage, as shown in Figure 5As shown, the first gating unit 51 is gated, so that the test pad unit 4 is connected with the second test binding unit 32, and the test pin 21 in the test pad unit 4, the second gating unit 52, the second test binding unit 32 and the first binding pad 11 form a second binding impedance test loop in communication; the binding impedance of the first binding pad 11 and the test pin 21 in the second test binding unit 32 is detected by using the second binding impedance test loop. Figure 2 and Figure 5 In the above embodiments, the dashed line in the gating unit indicates that the gating unit is turned on, and the cross line indicates that the gating unit is turned off.

[0046] Optionally, Figure 6 Another structure schematic diagram of a display module provided by the embodiment of the present application is provided, which can be referred to Figure 6 In the possible embodiment, the test pad unit 4 includes a test pad 40, the first gating unit 51 includes a first switch K1, the test pad 40 is electrically connected with the first binding pad 11 in the first test binding unit 31 through the first switch K1; the second gating unit 52 includes a second switch K2, the test pad 40 is electrically connected with the first binding pad 11 in the second test binding unit 32 through the second switch K2; the control end of the first switch K1 is connected to the first test control end 6, and the control end of the second switch K2 is connected to the second test control end 7; in the first test stage, the first switch K1 is turned on according to the effective level signal transmitted by the first test control end 6, and the second switch K2 is turned off according to the ineffective level signal transmitted by the second test control end 7; in the second test stage, the first switch K1 is turned off according to the ineffective level signal transmitted by the first test control end 6, and the second switch K2 is turned on according to the effective level signal transmitted by the second test control end 7.

[0047] As shown in the figure, Figure 6 As shown, the number of test pads 40 in the test pad unit 4 can be the same as the number of first binding pads 11 in the test binding unit 3 connected with the test pad unit 4, for example, the figure shows that one test binding unit 3 includes two first binding pads 11, and the test pad unit 4 can include two test pads 40, which is not limited in practice.

[0048] The gating unit can be composed of switching elements, which include but are not limited to transistors. The first gating unit 51 includes first switches K1, and the number of the first switches K1 can be the same as the number of the test pads 40 in the test pad unit 4. The test pads 40 are connected to the first ends of the first switches K1 through wires, and the second ends of the first switches K1 are connected to the corresponding first bonding pads 11 in the first test bonding unit 31 through wires. Correspondingly, the second gating unit 52 includes second switches K2, and the number of the second switches K2 can be the same as the number of the test pads 40 in the test pad unit 4. The test pads 40 are connected to the first ends of the second switches K2 through wires, and the second ends of the second switches K2 are connected to the corresponding first bonding pads 11 in the second test bonding unit 32 through wires.

[0049] Further, the first switches K1 and the second switches K2 each include a control end. The control end of the first switch K1 is electrically connected to the first test control end 6 to receive a test control signal sent by the first test control end 6 and turn on or off in response to the test control signal. When the first switch K1 is turned on, the test pad unit 4 is in communication with the first test bonding unit 31, and when the first switch K1 is turned off, the test pad unit 4 is disconnected from the first test bonding unit 31. The control end of the second switch K2 is electrically connected to the second test control end 7 to receive a test control signal sent by the second test control end 7 and turn on or off in response to the test control signal. When the second switch K2 is turned on, the test pad unit 4 is in communication with the first test bonding unit 31, and when the second switch K2 is turned off, the test pad unit 4 is disconnected from the second test bonding unit 32.

[0050] Specifically, in the first test phase, the first test control end 6 sends an effective level signal to the first switch K1, and the first switch K1 turns on in response to the effective level signal. At the same time, the second test control end 7 sends an ineffective level signal to the second switch K2, and the second switch K2 remains in the off state in response to the ineffective level signal, so that the test signal in the test pad unit 4 is transmitted to the first test bonding unit 31. In the second test phase, the second test control end 7 sends an effective level signal to the second switch K2, and the second switch K2 turns on in response to the effective level signal. At the same time, the first test control end 6 sends an ineffective level signal to the first switch K1, and the first switch K1 remains in the off state in response to the ineffective level signal, so that the test signal in the test pad unit 4 is transmitted to the second test bonding unit 32.

[0051] Optionally, with reference to Figure 6 the control ends of the first switches K1 in the same first gating unit 51 are connected to the same first test control end 6; and the control ends of the second switches K2 in the same second gating unit 52 are connected to the same second test control end 7.

[0052] In the embodiment, the control terminals of all the first switches K1 in the same first gating unit 51 are connected to the same first test control terminal 6, and the test control signals are sent to the plurality of first switches K1 by the same first test control terminal 6; the control terminals of all the second switches K2 in the same second gating unit 52 are connected to the same second test control terminal 7, and the test control signals are sent to the plurality of second switches K2 by the same second test control terminal 7. In this way, the control timing of different first switches K1 in the same first gating unit 51 is the same, and in the first test stage, all the first switches K1 in the same first gating unit 51 are turned on synchronously; the control timing of different second switches K2 in the same second gating unit 52 is the same, and in the second test stage, all the second switches K2 in the same second gating unit 52 are turned on synchronously, thereby improving the synchronization of the on or off of the switching elements in the same gating unit.

[0053] Of course, in other embodiments not shown, the control terminals of the first switches K1 in the same first gating unit 51 can be connected to different first test control terminals 6, and the control terminals of the second switches K2 in the same second gating unit 52 can be connected to different second test control terminals 7, so that each first switch K1 (second switch K2) is controlled by a corresponding test control terminal, thereby improving the flexibility of the control of the first switch K1 (second switch K2).

[0054] It should be noted that the resistances of the switching elements and the connection wires can be different, and the addition of the first gating circuit 5 in the communication path between the test pad unit 4 and the test bonding unit 3 can cause the bonding impedance between the first bonding pad 11 and the test pin 21 to be different from the bonding impedance when the first gating circuit 5 is not set. Based on this, the embodiment of the present application proposes that in the bonding impedance test stage, the resistance part of the first switch K1 (second switch K2) can be compensated, that is, the influence of the resistance of the switching element on the bonding impedance is removed, so as to ensure the accuracy of the bonding impedance test.

[0055] Further, the above embodiment can be further combined with the following embodiments. Figure 6 In possible embodiments, the at least two test bonding units 3 include at least two first test bonding units 31 and at least two second test bonding units 32; the number of the first gating units 51 is the same as the number of the first test bonding units 31, and the number of the second gating units 52 is the same as the number of the second test bonding units 32; the control terminals of the first switches K1 in each first gating unit 51 are connected to the same first test control terminal 6, and the control terminals of the second switches K2 in each second gating unit 52 are connected to the same second test control terminal 7.

[0056] For example, the first test control terminal 6 can be connected to the first test control terminal 6 of the first test bonding unit 31, and the second test control terminal 7 can be connected to the second test control terminal 7 of the second test bonding unit 32. Figure 6As shown, the first test binding unit 31 and the second test binding unit 32 connected with the same test pad unit 4 can be defined as a test binding group 33. In the embodiment of the present application, the display module can include at least two test binding groups 33. Correspondingly, the first gating circuit 5 includes at least two first gating units 51 and at least two second gating units 52, and each test binding group 33 is provided with a first gating unit 51 and a second gating unit 52, that is, the first gating unit 51 is connected with the first test binding unit 31 one by one, and the second gating unit 52 is connected with the second test binding unit 32 one by one.

[0057] In the embodiment, the number of test pad units 4 is the same as the number of test binding groups 33, and one test pad unit 4 is connected with the first test binding unit 31 and the second test binding unit 32 in one test binding group 33. Specifically, one test pad unit 4 is connected with one first test binding unit 31 through the corresponding first gating unit 51, and is connected with one second test binding unit 32 through the corresponding second gating unit 52.

[0058] Reference Figure 6 In the embodiment, the first switch K1 in the plurality of first gating units 51 is connected to the same first test control end 6, and the second switch K2 in the plurality of second gating units 52 is connected to the same second test control end 7. In this way, the control timing of the plurality of first switches K1 in the first gating circuit 5 is the same, and the control timing of the plurality of second switches K2 in the first gating circuit 5 is the same. In the first test stage, the test pad unit 4 can be used to simultaneously test the binding impedance of all first test binding units 31 in the display module; in the second test stage, the test pad unit 4 can be used to simultaneously test the binding impedance of all second test binding units 32 in the display module. The display module has high binding impedance test efficiency.

[0059] Reference Figure 6 In the possible embodiment, the at least two test binding units 3 include two first test binding units 31 and two second test binding units 32; the two first test binding units 31 are respectively close to the two opposite side edges of the driving chip 2 along the first direction X, and the two second test binding units 32 are respectively close to the two opposite side edges of the driving chip 2 along the first direction X; the first direction X is parallel to the arrangement direction of the chip pins 20 in the driving chip 2; the display panel 1 includes two test pad units 4, one test pad unit 4 is connected with one first test binding unit 31 through the corresponding first gating unit 51, and is connected with one second test binding unit 32 through the corresponding second gating unit 52.

[0060] As Figure 6As shown, the test pins 21 can be part of the chip pins 20 located on both sides of the chip pins 20 in the arrangement direction of the chip pins 20, corresponding to the bound chip bond pads 10 as the first bond pads 11. In the direction shown in the figure, the first direction X is the left-right direction, and the two groups of corresponding bound chip pins 20 and first bond pads 11 near the one side edge (for example, the left side edge) of the driving chip 2 along the first direction X form a first test binding unit 31, and the other two groups of corresponding bound chip pins 20 and first bond pads 11 form a second test binding unit 32; the two groups of corresponding bound chip pins 20 and first bond pads 11 near the other side edge (for example, the right side edge) of the driving chip 2 along the first direction X form a first test binding unit 31, and the other two groups of corresponding bound chip pins 20 and first bond pads 11 form a second test binding unit 32. That is, the display panel 1 is provided with two groups of test binding groups 33, and the two groups of test binding groups 33 are respectively near the two side edges of the driving chip 2 along the first direction X, in other words, the driving chip 2 is provided with the first test binding unit 31 and the second test binding unit 32 along any side edge of the first direction X.

[0061] Further, referring to Figure 6 , the test pad unit 4 can include a first test pad unit 41 and a second test pad unit 42, the first test pad unit 41 can be near one side edge (for example, the left side edge) of the driving chip 2 along the first direction X, and the second test pad unit 42 can be near the other side edge (for example, the right side edge) of the driving chip 2 along the first direction X. The first test pad unit 41 is connected to a group of test binding groups 33 (including a first test binding unit 31 and a second test binding unit 32) through a group of first gating units 51 and second gating units 52; the second test pad unit 42 is connected to another group of test binding groups 33 (including a first test binding unit 31 and a second test binding unit 32) through another group of first gating units 51 and second gating units 52.

[0062] In this configuration, the bonding impedance of the bonding units 3 at both edges of the driver chip 2 can be tested using two test pad units 4. Considering that the driver chip 2 is typically a regular shape (mostly rectangular), if uneven force occurs during the pressing of the driver chip 2 and the display panel 1, resulting in poor bonding, this is most likely to occur at the two edges of the driver chip 2 along the first direction X. Therefore, in this embodiment, two first test bonding units 31 are respectively located near the opposite edges of the driver chip 2 along the first direction X, and two second test bonding units 32 are respectively located near the opposite edges of the driver chip 2 along the first direction X. This allows for testing of the bonding status of the driver chip 2 at the two edges along the first direction X, thus meeting the requirement of improving the reliability of the evaluation results without significantly increasing costs or occupying too many chip pins 20.

[0063] Optional, you can continue to refer to Figure 6 In some embodiments, the chip pin 20 further includes a first control pin 201 and a second control pin 202. The first control pin 201 serves as a first test control terminal 6 and is electrically connected to the control terminal of the first switch K1. The second control pin 202 serves as a second test control terminal 7 and is electrically connected to the control terminal of the second switch K2.

[0064] like Figure 6 As shown, the first control pin 201 and the second control pin 202 can be any chip pin 20 other than the test pin 21. As mentioned above, the test pin 21 is a chip pin 20 along the two edges of the first direction X, so the first control pin 201 and the second control pin 202 can be located between the two test pins 21. During the bonding impedance test stage, the first control pin 201 can be used as the first test control terminal 6 to transmit the test control signal to the first switch K1; the second control pin 202 can be used as the second test control terminal 7 to transmit the test control signal to the second switch K2. During the normal use stage after the display module leaves the factory, the first control pin 201 and the second control pin 202 can be used normally as signal transmission pins of the driver chip 2.

[0065] With this setup, there is no need to set up the first test control terminal 6 and the second test control terminal 7 separately, saving the process of the first test control terminal 6 and the second test control terminal 7, and also not taking up extra space in the display panel 1.

[0066] The first control pin 201 and the second control pin 202 are both bound to the corresponding chip binding pad 10, and the corresponding chip binding pad 10 can be connected with the control binding pad (not shown in the figure) through the wire (not shown in the figure) in the display panel 1. In the binding impedance test stage, the test equipment can be used to provide the test control signal to the control binding pad through the program setting, so as to transmit the test control signal to the first gating circuit 5 through the first control pin 201 and the second control pin 202.

[0067] Optionally, Figure 7 Another structure schematic diagram of a display module provided by an embodiment of the present application is provided, Figure 8 is Figure 7 The structure schematic diagram of the section along the C-C' direction can be referred to Figure 7 and Figure 8 In some other embodiments, the display module further comprises a flexible circuit board 8, and the flexible circuit board 8 is bound to the non-display area NA, and the first test control end 6 and the second test control end 7 are integrated in the flexible circuit board 8.

[0068] As shown in Figure 7 and Figure 8 The flexible circuit board 8 can be bound to the side of the driving chip 2 away from the display area AA, for example, a second binding pad 12 can also be arranged in the display panel 1, and the second binding pad 12 is located on the side of the chip binding pad 10 away from the display area AA. The flexible circuit board 8 can comprise a third binding pad 13, and the third binding pad 13 can be connected with the second binding pad 12 through the anisotropic conductive adhesive, so as to realize the binding of the flexible circuit board 8 and the display panel 1.

[0069] In the embodiment, the first test control end 6 and the second test control end 7 can be arranged in the flexible circuit board 8. For example, part of the third binding pad 13 can be reused as the first test control end 6 and the second test control end 7 (as shown in the figure), or the first test control end 6 and the second test control end 7 are respectively electrically connected with the corresponding third binding pad 13; the control end of the first switch K1 of the first gating unit 51 and the control end of the second switch K2 of the second gating unit 52 are respectively electrically connected with the corresponding second binding pad 12. In the binding impedance test stage, the test equipment can be used to provide the test control signal to the first test control end 6 and the second test control end 7, so as to transmit the test control signal to the first gating circuit 5 through the flexible circuit board 8.

[0070] At least part of the second binding pad 12 can be electrically connected with the chip binding pad 10 through the wire (not shown in the figure) in the display panel 1, so as to realize the electrical connection between the flexible circuit board 8 and the driving chip 2, so that the driving chip 2 can receive the electrical signal from the flexible circuit board 8.

[0071] Optionally, the above description can be continued with reference toFigure 6 The display panel 1 further comprises a first test control signal line 14 and a second test control signal line 15, both of which are located on the side of the driving chip 2 away from the display area AA; the control end of the first switch K1 is electrically connected with the first test control end 6 through the first test control signal line 14, and the control end of the second switch K2 is electrically connected with the second test control end 7 through the second test control signal line 15.

[0072] As shown in Figure 6 , the first test control signal line 14 is used to connect the first test control end 6 and the control end of the plurality of first switches K1, and the second test control signal line 15 is used to connect the second test control end 7 and the control end of the plurality of second switches K2. The first test control signal line 14 and the second test control signal line 15 can be the above-mentioned signal lines in the display panel 1. In order to ensure the connection effect of the driving chip 2 and the signal lines in the display area AA of the display panel 1, the driving chip 2 is generally bound in the non-display area NA close to the display area AA, so that the space on the side of the driving chip 2 away from the display area AA is larger. Therefore, in the embodiment, the first test control signal line 14 and the second test control signal line 15 can be arranged in the non-display area NA on the side of the driving chip 2 away from the display area AA, so as to leave enough arrangement space for the first test control signal line 14 and the second test control signal line 15.

[0073] Optionally, taking the multiplexing of the chip pin 20 of the driving chip 2 as the first test control end 6 and the second test control end 7 as an example, the first test control signal line 14 and the second test control signal line 15 can each comprise a plurality of parts extending along a first direction X and a second direction Y, respectively, the second direction Y intersects the first direction X, and the specific arrangement manner of the first test control signal line 14 and the second test control signal line 15 is not limited, which can be set according to actual needs by those skilled in the art.

[0074] Optionally, in some embodiments, the test pin 21 in the first test binding unit 31 is a signal input pin of the driving chip 2, and the test pin 21 in the second test binding unit 32 is a signal output pin of the driving chip 2.

[0075] The signal input pins of the driving chip 2 refer to the chip pins 20 corresponding to the chip bonding pads 10 connected with the flexible circuit board 8, and the signal output pins refer to the chip pins 20 corresponding to the chip bonding pads 10 connected with the signal lines in the display area AA. The plurality of signal input pins are arranged along the first direction X to form a signal input pin group, and the plurality of signal output pins are arranged along the first direction X to form a signal output pin group. The signal input pin group can be located on the side away from the display area AA of the signal output pin group, that is, the signal output pins are closer to the display area AA, and the signal input pins are closer to the flexible circuit board 8.

[0076] In the embodiment, part of the signal input pins of the driving chip 2 serve as the test pins 21 in the first test bonding unit 31, and part of the signal output pins of the driving chip 2 serve as the test pins 21 in the second test bonding unit 32. In the first test stage, the bonding impedance test is performed on the signal input pins of the driving chip 2 and the corresponding first bonding pads 11; and in the second test stage, the bonding impedance test is performed on the signal output pins of the driving chip 2 and the corresponding first bonding pads 11. Thus, the bonding of the signal input pins and the bonding of the signal output pins are tested respectively by using one test pad unit 4, so as to ensure the comprehensiveness and accuracy of the bonding impedance test.

[0077] Optionally, continuing to refer to Figure 6 In the same test bonding unit 3, the first bonding pads 11 include input bonding pads 111 and output bonding pads 112, the test pins 21 include first test pins 211 and second test pins 212, the input bonding pads 111 are bonded with the first test pins 211, the output bonding pads 112 are bonded with the second test pins 212, and the first test pins 211 and the second test pins 212 are short-circuited; the test pad unit 4 includes input test pads 411 and output test pads 412, the input test pads 411 are connected with the input bonding pads 111 in the test bonding unit 3 through the first gating circuit 5, the output test pads 412 are connected with the output bonding pads 112 in the test bonding unit 3 through the first gating circuit 5, and the input test pads 411, the input bonding pads 111, the first test pins 211, the second test pins 212, the output bonding pads 112 and the output test pads 412 are connected to form a bonding impedance test loop.

[0078] Specifically, in the embodiment, the test binding unit 3 can include two groups of corresponding binding connection test pins 21 and first binding pads 11, which are respectively corresponding binding first test pins 211 and input binding pads 111, and corresponding binding second test pins 212 and output binding pads 112. Among them, the first test pin 211 and the second test pin 212 are short-circuited, that is, the first test pin 211 and the second test pin 212 are directly electrically connected in the driving chip 2.

[0079] Correspondingly, the test pad unit 4 can include an input test pad 411 and an output test pad 412, the input test pad 411 is connected with the input binding pad 111 through the first gating circuit 5, and the output test pad 412 is connected with the output binding pad 112 through the first gating circuit 5. In the binding impedance test stage, when part of the test pad unit 4 and the test binding unit 3 are gated by the first gating circuit 5, the gated input test pad 411, the input binding pad 111, the first test pin 211, the second test pin 212, the output binding pad 112 and the output test pad 412 are sequentially connected to form a binding impedance test loop. The binding impedance of the test binding unit 3 can be calculated by the change of the electrical signal on the input test pad 411 and the output test pad 412.

[0080] It should be noted that any one of the first binding pads 11 in the same test binding unit 3 can be an input binding pad 111, and the corresponding binding test pin 21 can be a first test pin 211; the other first binding pad 11 is an output binding pad 112, and the corresponding binding test pin 21 can be a second test pin 212. Any one of the test pads 40 in the same test pad unit 4 can be an input test pad 411, and the other test pad 40 can be an output test pad 412. It is only necessary to ensure that the input test pad 411 is connected with the input binding pad 111, and the output test pad 412 is connected with the output binding pad 112; the impedance test signal enters the binding impedance test loop from the input test pad 411 and is output from the output test pad 412.

[0081] For example, the above-mentioned embodiment can be continued with reference to Figure 6For example, two first test binding units 31 are respectively close to two opposite side edges of the driving chip 2 along the first direction X, and two second test binding units 32 are respectively close to two opposite side edges of the driving chip 2 along the first direction X, the display panel 1 can include 4 input binding pads 111 and 4 output binding pads 112. Correspondingly, the display panel 1 can include two test pad units 4, two first gating units 51 and two second gating units 52, each test pad unit 4 includes the input test pad 411 and the output test pad 412, each first gating unit 51 includes two first switches K1, and each second gating unit 52 includes two second switches K2, that is, the display panel 1 includes 4 first switches K1 and 4 second switches K2. For the two test binding units 3 close to the left side edge of the driving chip 2 along the first direction X, in one first test binding unit 31, the input binding pad 111 is connected with the input test pad 411 through one first switch K1, and the output test pad 412 is connected with the output test pad 412 through another first switch K1; in one second test binding unit 32, the input binding pad 111 is connected with the input test pad 411 through one second switch K2, and the output test pad 412 is connected with the output test pad 412 through another second switch K2; the two test binding units 3 are connected with the first test pad unit 41 through the first switch K1 and the second switch K2. The two test binding units 3 close to the other side edge of the driving chip 2 along the first direction X are also connected with the second test pad unit 42 in the above connection mode, and the application will not be described in detail.

[0082] Further, the control ends of the 4 first switches K1 can be connected to one first test control end 6, and the control ends of the 4 second switches K2 can be connected to one second test control end 7. In the first test stage, the first test control end 6 is provided with an effective level signal and the second test control end 7 is provided with an ineffective level signal through a program, the first switch K1 is turned on and the second switch K2 is turned off; the input test pad 411, the output test pad 412, the input binding pad 111 and the output binding pad 112 in the first test pad unit 41 are connected to form a first binding impedance test loop, and then the binding condition of the signal input pin of the driving chip 2 is tested. In the second test stage, the second test control end 7 is provided with an effective level signal and the first test control end 6 is provided with an ineffective level signal through a program, the second switch K2 is turned on and the first switch K1 is turned off; the input test pad 411, the output test pad 412, the input binding pad 111 and the output binding pad 112 in the second test pad unit 42 are connected to form a second binding impedance test loop, and then the binding condition of the signal output pin of the driving chip 2 is tested.

[0083] It is to be noted that, for the first switch K1 (second switch K2) connecting the input test pad 411 and the input binding pad 111, the first end of the first switch K1 (second switch K2) is the input end thereof, and the second end is the output end thereof; for the first switch K1 (second switch K2) connecting the output test pad 412 and the output binding pad 112, the first end of the first switch K1 (second switch K2) is the output end thereof, and the second end is the input end thereof; in one binding impedance test loop, the test signal is transmitted to the input binding pad 111 in sequence through the input test pad 411, the first end of one of the first switches K1 (second switches K2), and the second end, and then is transmitted to the output test pad 412 in sequence through the first test pin 211, the second test pin 212, the output binding pad 112, the second end of the other first switch K1 (second switch K2), and the first end.

[0084] In the above scheme, only 4 test pads 40 need to be arranged in the display panel 1, and the space occupied is less, and signals can be provided to the test pads 40 by using 4 test probes. The above binding impedance test can be performed at the same time as the display module lighting test, thereby improving the production line efficiency.

[0085] Optionally, Figure 9 Another structure diagram of a display module provided by an embodiment of the present application can be referred to Figure 9 The display module further comprises a flexible circuit board 8, and the flexible circuit board 8 is bound to the non-display area NA; the display panel 1 comprises a plurality of second binding pads 12, the flexible circuit board 8 comprises a plurality of third binding pads 13, the second binding pads 12 and the third binding pads 13 are correspondingly bound, and part of the second binding pads 12 constitute the test pad unit 4.

[0086] The binding mode of the flexible circuit board 8 and the display panel 1 is described above in all the embodiments, and will not be described again here. In this embodiment, part of the second binding pads 12 can be used as the test pads 40, thereby constituting the test pad unit 4. Specifically, the second binding pads 12 can comprise first sub-binding pads 121 and second sub-binding pads 122, the first sub-binding pads 121 are the test pads 40 in the test pad unit 4, and the second sub-binding pads 122 are directly connected to the corresponding chip binding pads 10 through the wires in the display panel 1, thereby realizing the electrical connection between the flexible circuit board 8 and the driving chip 2.

[0087] Specifically, the first sub-binding pads 121 can be located on both sides of the second sub-binding pads 122 along the first direction X, and along the second direction Y, the second sub-binding pads 122 can overlap the driving chip 2. In this way, the first sub-binding pads 121 are used as the test pads 40 and connected to the test binding unit 3 located at the edge of the driving chip 2, and the switch elements and wires and the like between the test pads 40 and the test binding unit 3 are arranged more simply.

[0088] Optionally, Figure 10 For Figure 9 The cross-sectional structure along the D-D' direction is shown in Figure 9 And Figure 10 In possible embodiments, at least one first test binding pad 123 is included in the second binding pad 12, at least one second test binding pad 133 is included in the third binding pad 13, and the first test binding pad 123 and the second test binding pad 133 correspondingly bind to form a test binding structure 18; the first test binding pad 123 in the two test binding structures 18 is electrically connected, so that the two test binding structures 18 are connected to form a third binding impedance test loop.

[0089] As Figure 9 And Figure 10 shown, in addition to the first sub-binding pad 121 and the second sub-binding pad 122 described above, the second binding pad 12 can also include a first test binding pad 123, and the number of the first test binding pad 123 is not limited. The third binding pad 13 corresponding to the first test binding pad 123 is a second test binding pad 133, and the first test binding pad 123 and the second test binding pad 133 form a test binding structure 18, which is used to test the binding impedance between the flexible circuit board 8 and the display panel 1, so as to detect the binding condition of the two.

[0090] Specifically, the impedance test phase of the display panel 1 can also include a third test phase, in which the first test binding pad 123 in different test binding structures 18 can be connected, and the connected first test binding pad 123 and the corresponding second test binding pad 133 form a third binding impedance test loop. The binding impedance of the test binding structure 18 can be calculated by transmitting an impedance test signal to the second test binding pad 133 and detecting the signal output by the other second test binding pad 133, so as to detect the binding condition of the flexible circuit board 8 and the display panel 1 using the third binding impedance test loop.

[0091] Among them, the third test phase can be executed simultaneously with any one of the first test phase and the second test phase, or the third test phase can be executed alone, and the embodiments of the present application do not limit this.

[0092] In this embodiment, part of the second binding pad 12 is used as a test binding structure 18 to test the binding impedance of the flexible circuit board 8, so as to determine whether the flexible circuit board 8 is normally bound in the binding impedance test phase, and to ensure normal signal transmission between the flexible circuit board 8 and the driving chip 2 when the display panel 1 is applied subsequently.

[0093] Figure 9In the shown embodiment, the two test bonding pads 123 are shorted by a wire in the display panel 1 to form the two test bonding structures 18 electrically connected, which is not limited thereto. In this arrangement, in the third test stage, the test equipment transmits an impedance test signal to the second test bonding pad 133 in the two test bonding structures 18 electrically connected, so as to detect the bonding impedance of the flexible circuit board 8 and the display panel 1.

[0094] Figure 11 Another structural schematic diagram of the display module provided by the embodiment of the present application can be referred to Figure 11 In some embodiments, the display panel 1 can further include a second gating circuit 16, the first end and the second end of the second gating circuit 16 are respectively connected to different first test bonding pads 123, and the control end of the second gating circuit 16 is connected to the third test control end 17; the second gating circuit 16 is gated according to the control signal of the third test control end 17.

[0095] Figure 11 The shown embodiment is different from Figure 9 The difference between the shown embodiment and Figure 11 In the shown embodiment, the second gating circuit 16 is arranged in the display panel 1, and the first test bonding pads 123 in different test bonding structures 18 are gated by the second gating circuit 16.

[0096] Specifically, the second gating circuit 16 can include a third switch K3, the first end (or the second end) of the third switch K3 can be the first end of the second gating circuit 16, and the second end (or the first end) of the third switch K3 can be the second end of the second gating circuit 16, that is, the first end and the second end of the third switch K3 are connected between different first test bonding pads 123. The control end of the third switch K3 can be the control end of the second gating circuit 16 and be connected to the third test control end 17. In the third test stage, the test equipment can provide an effective level signal to the third test control end 17 through a program, and the third switch K3 is turned on in response to the effective level signal, so as to make the different first test bonding pads 123 connected; in other test periods, an ineffective level signal can be provided to the third test control end 17 through a program, and the third switch K3 is turned off in response to the ineffective level signal, so as to make the different first test bonding pads 123 disconnected.

[0097] In the second gating circuit 16, the number of the third switch K3 is not limited, Figure 11 In the shown embodiment, one third switch K3 and one third test control end 17 are exemplarily shown, and the connection between the two test bonding structures 18 can be realized by one third test control end 17 and the corresponding third switch K3, which is not limited thereto.

[0098] Further optionally, as shown in Figure 11 The plurality of second bonding pads 12 are arranged along a first direction X, which is parallel to the arrangement direction of the chip pins 20 in the driving chip 2. The second bonding pads 12 include two first test bonding pads 123, which are respectively located on two sides of the test pad unit 4 along the first direction X.

[0099] The second bonding pads 12 are also arranged along the first direction X. In this embodiment, the two second bonding pads 12 located at the outermost sides along the first direction X can be used as the first test bonding pads 123, and the corresponding bonded third bonding pads 13 can be used as the second test bonding pads 133. That is, the display module includes two test bonding structures 18, which are close to the two side edges of the flexible circuit board 8 along the first direction X.

[0100] In this arrangement, in the third test stage, the test bonding structures 18 close to the two side edges of the flexible circuit board 8 along the first direction X are connected by the second gating circuit 16, so that the bonding state of the flexible circuit board 8 at the two side edges along the first direction X can be tested. This can meet the detection requirements of bonding reliability, and does not occupy many second bonding pads 12 (third bonding pads 13).

[0101] Figure 12 Another structure diagram of a display module provided by an embodiment of the present application is shown in Figure 12 In the embodiment shown, the second gating circuit 16 includes two third switches K3, which are respectively connected to different third test control ends 17. Specifically, the display module can include three first test bonding pads 123 and corresponding second test bonding pads 133, so as to form three test bonding structures 18, which are respectively a first sub-test bonding structure 181, a second sub-test bonding structure 182, and a third sub-test bonding structure 183. Correspondingly, the third switch K3 can include a first sub-switch K31 and a second sub-switch K32, and the third test control end 17 can include a first sub-test control end 171 and a second sub-test control end 172. The first sub-test bonding structure 181 and the second sub-test bonding structure 182 are respectively close to the two side edges of the flexible circuit board (not shown in the figure) along the first direction X, and the third sub-test bonding structure 183 is located in the middle region of the flexible circuit board along the first direction X. The first end of the first sub-switch K31 can be connected to the first sub-test bonding structure 181, the second end can be connected to the second sub-test bonding structure 182, and the control end of the first sub-switch K31 is connected to the first sub-test control end 171. The first end of the second sub-switch K32 can be connected to the first sub-test bonding structure 181, the second end can be connected to the third sub-test bonding structure 183, and the control end of the second sub-switch K32 is connected to the second sub-test control end 172.

[0102] The third test stage can include a first sub-test stage and a second sub-test stage. In the first sub-test stage, the first sub-test control terminal 171 can transmit an effective level signal to the first sub-switch K31, and the second sub-test control terminal 172 can transmit an ineffective level signal to the second sub-switch K32. The first sub-switch K31 can connect the first sub-test binding structure 181 and the second sub-test binding structure 182 to form a third binding impedance test loop. At this time, the detection is the binding state of the two side edges of the flexible circuit board. In the second sub-test stage, the second sub-test control terminal 172 can transmit an effective level signal to the second sub-switch K32, and the first sub-test control terminal 171 can transmit an ineffective level signal to the first sub-switch K31. The second sub-switch K32 can connect the first sub-test binding structure 181 and the third sub-test binding structure 183 to form a third binding impedance test loop. At this time, the detection is the binding state of the side edge and the middle of the flexible circuit board. In this way, the detection of the binding state of different positions of the flexible circuit board can be realized.

[0103] Compared with directly short-circuiting between the two first test binding pads 123, the two first test binding pads 123 are gated by the second gating circuit 16, which can improve the flexibility of the connection between different test binding structures 18, thereby meeting the detection needs of different binding positions of the flexible circuit board and the display panel 1.

[0104] Continuing to refer to Figure 11 The driving chip 2 further includes a third control pin 203, which is electrically connected to the control terminal of the second gating circuit 16 as the third test control terminal 17.

[0105] The third control pin 203 can be another chip pin 20 except the test pin 21, the first control pin 201, and the second control pin 202. The third control pin 203 can be located between the two side test pins 21. In the binding impedance test stage, the third control pin 203 can be used as the third test control terminal 17 to transmit a test control signal to the third switch K3. In the normal use stage after the display module is shipped, the third control pin 203 can normally serve as a signal transmission pin of the driving chip 2.

[0106] Of course, in other embodiments, the third test control terminal 17 can also be a third binding pad 13 on the flexible circuit board 8. For example, the third binding pad 13 except the third binding pad 13 bound with the test pad 40 in the test pad unit 4 and the second test binding pad 133 can be provided by the flexible circuit board 8 to provide the test control signal required by the second gating circuit 16.

[0107] Figure 13This is a schematic diagram of another display module provided in an embodiment of the present invention, which can be referred to. Figure 13 In a possible embodiment, the flexible circuit board 8 may further include a plurality of first test points 81, the first test points 81 being electrically connected to the third bonding pads 13 corresponding to the test pad units 4, the first test points 81 being in contact with test probes for receiving first impedance test signals; and / or, the flexible circuit board 8 may further include at least two second test points 82, the second test points 82 being electrically connected to the second test bonding pads 133, the second test points 82 being in contact with test probes for receiving second impedance test signals.

[0108] like Figure 13 As shown, in some embodiments, multiple test points may be provided on the flexible circuit board 8, which are the copper leakage test pads on the flexible circuit board 8. The test points may include a first test point 81 and / or a second test point 82. The first test point 81 is connected to the first portion of the third bonding pad 13 via a trace within the flexible circuit board 8, and the second bonding pad 12 corresponding to the first portion of the third bonding pad 13 is the test pad in the test pad unit 4. In the first test stage and the second test stage, a first impedance test signal can be transmitted to the first test point 81 using the test probes of the test equipment, thereby transmitting the first impedance test signal to the first bonding impedance test circuit or the second bonding impedance test circuit to detect the bonding state of the driver chip 2.

[0109] The second test point 82 is connected to the second part of the third bonding pad 13 via a trace within the flexible circuit board 8. The second part of the third bonding pad 13 is the second test bonding pad 133. In the third testing phase, a second impedance test signal can be transmitted to the second test point 82 using the test probes of the test equipment, thereby transmitting the second impedance test signal to the third impedance test circuit to detect the bonding state of the flexible circuit board 8. The first impedance test signal may be the same as or different from the second impedance test signal; this embodiment of the invention does not limit this.

[0110] Figure 13 In the illustrated embodiment, the flexible circuit board 8 is provided with a first test point 81 and a second test point 82. However, this is not a limitation; in other embodiments, the flexible circuit board 8 may only have the first test point 81 or only the second test point 82, or the test points may be omitted entirely. Before bonding the flexible circuit board 8, a test probe directly contacts the second bonding pad 12 to detect the bonding status of the driver chip 2 and / or the flexible circuit board 8.

[0111] It is understood that the number of first test points 81 can be the same as the number of test pads 40, and the number of second test points 82 can be the same as the number of test bonding structures 18. In some embodiments, the number of first test points 81 in the flexible circuit can be 4, which are respectively connected to the 4 test pads 40 in the test pad unit 4; the number of second test points 82 can be 2, which are respectively connected to the two test bonding structures 18. The number of test points used for bonding impedance testing on the flexible circuit board 8 is reduced, thereby reducing the occupation of test points on the surface of the flexible circuit board 8. The space saved can be used to lay out other structures, which is more conducive to the layout of traces in the flexible circuit board 8.

[0112] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 14 As shown, the display device includes the display module 100 provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention has the corresponding beneficial effects of the display module provided in the embodiments of the present invention, which will not be elaborated here. For example, the display device can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and the embodiments of the present invention do not limit it to this.

[0113] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display module, characterized by The display module comprises: a display panel, comprising a display area and a non-display area surrounding at least part of the display area; a driving chip, comprising a plurality of chip pins, the plurality of chip pins comprising test pins; the driving chip is bonded with the display panel to form at least two test bonding units, each test bonding unit comprising at least two groups of corresponding bonded test pins and first bonding pads, the first bonding pads being arranged on the non-display area of the display panel; the display panel further comprises a test pad unit and a first gating circuit, the test pad unit being electrically connected to each test bonding unit through the first gating circuit, the test pad unit being connected to the first bonding pads and the test pins in each test bonding unit through the first gating circuit to form a bonding impedance test loop; one test pad unit can form the bonding impedance test loop with different test bonding units respectively; the display module further comprises a flexible circuit board, the flexible circuit board being bonded to the non-display area; the display panel comprises a plurality of second bonding pads, the flexible circuit board comprises a plurality of third bonding pads, the second bonding pads and the third bonding pads being correspondingly bonded, part of the second bonding pads constituting the test pad unit; at least one first test bonding pad is included in the second bonding pads, at least one second test bonding pad is included in the third bonding pads, the first test bonding pad and the second test bonding pad being correspondingly bonded to form a test bonding structure; the first test bonding pads in two test bonding structures are electrically connected to enable two test bonding structures to be connected to form a third bonding impedance test loop.

2. The display module of claim 1, wherein, At least two test bonding units comprise at least one first test bonding unit and at least one second test bonding unit; the first gating circuit comprises a first gating unit and a second gating unit, the test pad unit being electrically connected to the first test bonding unit through the first gating unit and being electrically connected to the second test bonding unit through the second gating unit; the display module comprises a first test stage and a second test stage, in the first test stage, the test pad unit and the first test bonding unit are gated by the first gating unit, the first bonding pads in the test pad unit and the first test bonding unit being connected to the test pins to form a first bonding impedance test loop; in the second test stage, the test pad unit and the second test bonding unit are gated by the second gating unit, the first bonding pads in the test pad unit and the second test bonding unit being connected to the test pins to form a second bonding impedance test loop.

3. The display module of claim 2, wherein, the test pad unit comprises a test pad, the first gating unit comprises a first switch, the test pad being correspondingly electrically connected to the first bonding pads in the first test bonding unit through the first switch. The second gating unit includes a second switch, and the test pad is electrically connected to the first bonding pad in the second test bonding unit via the second switch; The control terminal of the first switch is connected to the first test control terminal, and the control terminal of the second switch is connected to the second test control terminal. In the first test phase, the first switch is turned on according to the valid level signal transmitted by the first test control terminal, and the second switch is turned off according to the invalid level signal transmitted by the second test control terminal; in the second test phase, the first switch is turned off according to the invalid level signal transmitted by the first test control terminal, and the second switch is turned on according to the valid level signal transmitted by the second test control terminal.

4. The display module of claim 3, wherein, The control terminals of each first switch in the same first gating unit are connected to the same first test control terminal; the control terminals of each second switch in the same second gating unit are connected to the same second test control terminal.

5. The display module of claim 3, wherein, The at least two test binding units include at least two first test binding units and at least two second test binding units; The number of the first gating units is the same as the number of the first test binding units, the number of the second gating units is the same as the number of the second test binding units, the control terminal of the first switch in each of the first gating units is connected to the same first test control terminal, and the control terminal of the second switch in each of the second gating units is connected to the same second test control terminal.

6. The display module of claim 5, wherein, At least two of the test binding units include two first test binding units and two second test binding units; The two first test bonding units are respectively located near the two opposite edges of the driver chip along the first direction, and the two second test bonding units are respectively located near the two opposite edges of the driver chip along the first direction; the first direction is parallel to the arrangement direction of the chip pins in the driver chip; The display panel includes two test pad units. One test pad unit is connected to a first test bonding unit through a corresponding first gating unit, and is connected to a second test bonding unit through a corresponding second gating unit.

7. The display module of claim 3, wherein, The chip pins also include a first control pin and a second control pin. The first control pin serves as the first test control terminal and is electrically connected to the control terminal of the first switch. The second control pin serves as the second test control terminal and is electrically connected to the control terminal of the second switch.

8. The display module of claim 3, wherein, The display module also includes a flexible circuit board, which is bonded to the non-display area, and the first test control terminal and the second test control terminal are integrated within the flexible circuit board.

9. The display module of claim 7 or 8, wherein, The display panel further includes a first test control signal line and a second test control signal line, both of which are located on the side of the driver chip away from the display area. The control terminal of the first switch is electrically connected to the first test control terminal via the first test control signal line, and the control terminal of the second switch is electrically connected to the second test control terminal via the second test control signal line.

10. The display module of claim 2, wherein, The test pin in the first test bonding unit is the signal input pin of the driver chip, and the test pin in the second test bonding unit is the signal output pin of the driver chip.

11. The display module of claim 1, wherein, In the same test bonding unit, the first bonding pad includes an input bonding pad and an output bonding pad, the test pin includes a first test pin and a second test pin, the input bonding pad is bonded to the first test pin, the output bonding pad is bonded to the second test pin, and the first test pin and the second test pin are shorted. The test pad unit includes an input test pad and an output test pad. The input test pad is connected to the input bonding pad in the test bonding unit through the first gating circuit. The output test pad is connected to the output bonding pad in the test bonding unit through the first gating circuit. The input test pad, the input bonding pad, the first test pin, the second test pin, the output bonding pad, and the output test pad are connected to form the bonding impedance test loop.

12. The display module of claim 1, wherein, The display panel further includes a second gating circuit, the first end and the second end of the second gating circuit are respectively connected to different first test bonding pads, and the control end of the second gating circuit is connected to a third test control end. The second selection circuit selects two of the first test bonding pads according to the control signal of the third test control terminal.

13. The display module of claim 12, wherein, The driver chip also includes a third control pin, which serves as the third test control terminal and is electrically connected to the control terminal of the second gating circuit.

14. The display module of claim 12, wherein, Multiple second bonding pads are arranged along a first direction, which is parallel to the arrangement direction of the chip pins in the driver chip; The second bonding pad includes two first test bonding pads, which are located on both sides of the test pad unit along the first direction.

15. The display module of claim 1, wherein, The flexible circuit board also includes a plurality of first test points, the first test points being electrically connected to the third bonding pads corresponding to the test pad units, and the first test points being in contact with test probes for receiving first impedance test signals. And / or, The flexible circuit board further includes at least two second test points, which are electrically connected to the second test bonding pads and are in contact with test probes to receive second impedance test signals.

16. A display device comprising: include: The display module according to any one of claims 1-15.

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