Dual-gate semiconductor device with timing difference and preparation method thereof

Abstract

The present invention provides a dual-gate semiconductor device with a timing difference and a method for preparing the same. The device comprises: a body having an emitter, a base region, and a collector, the base region including a transmission layer group and an auxiliary layer group, the transmission layer group being connected to the emitter, and the auxiliary layer group being connected to the collector; a precursor gate and an accelerating gate; when the device is in an operating state, the precursor gate and the accelerating gate simultaneously receive a positive voltage; when the device switches from the operating state to the off state, the accelerating gate first switches to a negative voltage to form a hole inversion channel, through which hole current is conducted; and the precursor gate then switches to a negative voltage to complete the shutdown. The present invention can create an additional hole inversion channel within the device by controlling the switching order of the precursor gate and the accelerating gate voltages, thereby conducting away the tail current present when the device is turned off in a short time. Compared to conventional semiconductor devices, the device has a significantly reduced shutdown time and a significantly increased device operating frequency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a dual-gate semiconductor device with a timing difference and a preparation method thereof. Background Art

[0002] The insulated-gate bipolar transistor (IGBT) is an important power semiconductor device that plays a key role in power electronics. Combining the high input impedance of a MOSFET with the high current-carrying capability of a BJT, the IGBT offers high voltage capability, high power density, and high switching speed. These characteristics make the IGBT an indispensable component in high-power applications such as power converters, motor drives, and inverters.

[0003] However, IGBTs present several technical challenges during switching. As a bipolar device, the hole current in the IGBT causes a conductivity modulation effect. While this reduces device conduction losses and increases current density, it also requires the hole current to be discharged during the device's turn-off phase, resulting in a tail current phenomenon. The presence of this tail current not only reduces device switching speed but also limits the application of IGBTs in high-frequency applications.

[0004] To overcome the above technical challenges, researchers have proposed a variety of methods to improve IGBT performance, such as improving manufacturing processes and adopting new materials. However, these methods generally have problems such as high R&D costs and limited scope of application. Therefore, how to reduce the impact of tail current by optimizing the device structure provides a new idea for solving the above problems. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the problem of tail current limiting the switching speed of the device in the prior art and provide a dual-gate semiconductor device with timing difference and a preparation method thereof.

[0006] In order to solve the above technical problems, the present invention provides a dual-gate semiconductor device with a timing difference, which includes: a body, an emitter and a collector are provided on opposite sides of the body, a base region is between the emitter and the collector, the base region includes a transmission layer group and an auxiliary layer group, the transmission layer group and the auxiliary layer group are respectively arranged on opposite sides of the base region, wherein the transmission layer group is connected to the emitter, and the auxiliary layer group is connected to the collector; a pioneer gate and an acceleration gate, the pioneer gate and the acceleration gate are arranged at intervals inside the base region; when the device is in an operating state, the pioneer gate and the acceleration gate obtain a positive voltage at the same time, when the device is switched from the operating state to the off state, the acceleration gate is first switched to a negative voltage to form a hole inversion channel, and the hole current is extracted through the hole inversion channel; the pioneer gate is then switched to a negative voltage to complete the shutdown; the transmission layer group includes N + layer, p-body layer and charge separation layer, wherein the N + layer connects the emitter, the N + A connecting groove is provided between the N layer and the p-body layer, and the connecting groove penetrates the N + layer, and extending into at least a portion of the p-body layer.

[0007] In one embodiment of the present invention, the auxiliary layer group includes an N-Buffer layer and a P + layer, wherein the P + The layer is connected to the collector, and the N-Buffer layer is spaced apart from the charge separation layer.

[0008] In one embodiment of the present invention, the precursor gate and the accelerating gate substrates are made of polysilicon, and the emitter and the collector are both made of metal-based materials.

[0009] In one embodiment of the present invention, a gate oxide layer is provided between the precursor gate and the acceleration gate and the body.

[0010] The present invention also provides a method for preparing a dual-gate semiconductor device with a timing difference, which is used to prepare the above-mentioned dual-gate semiconductor device with a timing difference, and specifically includes the following steps: S1, preparing a pioneer gate and an acceleration gate arranged at intervals inside the body after etching; S2, injecting a transmission layer substrate into the interior of the body from the first surface to form a transmission layer group; S3, depositing an emitter on the surface of the transmission layer group; S4, injecting an auxiliary layer substrate into the interior of the body from the second surface to form an auxiliary layer group, wherein the first surface and the second surface are respectively arranged on opposite sides of the body; S5, depositing a collector on the surface of the auxiliary layer group to complete the preparation of the target device.

[0011] In one embodiment of the present invention, step S1 is specifically as follows: S11, trench etching the body to form a trench structure; S12, preparing a gate oxide layer in the trench; S13, filling the trench with polysilicon to form the pioneer gate and the acceleration gate.

[0012] In one embodiment of the present invention, step S2 is specifically as follows: S21, sequentially preparing a charge separation layer, a p-body layer and an N-body layer from the inside to the outside of the body; + layer, wherein the N + layer close to the first surface; S22, in the N + A connecting groove is prepared between the N layer and the p-body layer, so that the connecting groove passes through the N + layer, and extending into at least a portion of the p-body layer.

[0013] In one embodiment of the present invention, step S3 specifically includes: + The metal deposition process is performed on the surface of the layer to prepare the emitter on the first surface; Step S4 is specifically: preparing the N-Buffer layer and the P- + layer, wherein the P + The layer is close to the second surface; Step S5 is specifically: + The surface of the layer is subjected to metal deposition processing to prepare the collector on the second surface to complete the preparation of the target device.

[0014] The above technical solution of the present invention has the following advantages over the prior art:

[0015] The dual-gate semiconductor device with timing difference and the preparation method thereof described in the present invention have a pioneer gate and an accelerating gate arranged at intervals within the body, thereby being able to produce an additional hole inversion channel in the internal components of the device by controlling the order of switching the pioneer gate and accelerating gate voltages, thereby being able to extract the tail current existing when the device is turned off in a short time. At this time, the tail current is completely suppressed, thereby reducing the charge carrier concentration, which helps to cut off the current flow process. Based on this, compared with conventional semiconductor devices, the device shutdown time of this application is significantly reduced, and the device usage frequency is greatly improved, which gives it a broader use prospect in this field. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0017] Figure 1 1 is a schematic structural diagram of a dual-gate semiconductor device with timing difference in a preferred embodiment of the present invention;

[0018] Figure 2 yes Figure 1 A structural schematic diagram of a dual-gate semiconductor device with timing difference from another perspective is shown.

[0019] Description of the reference numerals in the specification: 100, body; 110, emitter; 120, base region; 121, transmission layer group; 1211, N + layer; 1212, p-body layer; 1213, charge separation layer; 1214, connecting groove; 122, auxiliary layer group; 1221, N-Buffer layer; 1222, P + layer; 130, collector; 200, pioneer gate; 300, accelerating gate; 400, gate oxide layer. DETAILED DESCRIPTION

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention.

[0021] Example 1

[0022] See also Figure 1 and Figure 2 As shown, this embodiment provides a dual-gate semiconductor device with a timing difference, which includes: a body 100, an emitter 110 and a collector 130 are provided on opposite sides of the body 100, a base region 120 is located between the emitter 110 and the collector 130, and the base region 120 includes a transmission layer group 121 and an auxiliary layer group 122, wherein the transmission layer group 121 and the auxiliary layer group 122 are respectively provided on opposite sides of the base region 120, wherein the transmission layer group 121 is connected to the emitter 110, and the auxiliary layer group 122 is connected to the emitter 110. The collector 130 is connected; a pioneer gate 200 and an accelerating gate 300 are arranged at intervals inside the base region 120; when the device is in an operating state, the pioneer gate 200 and the accelerating gate 300 simultaneously obtain a positive voltage; when the device is switched from an operating state to an off state, the accelerating gate 300 is first switched to a negative voltage to form a hole inversion channel, and the hole current is extracted through the hole inversion channel; the pioneer gate 200 is then switched to a negative voltage to complete the shutdown.

[0023] The dual-gate semiconductor device with a timing difference described in the present invention has a pioneer gate 200 and an accelerating gate 300 arranged at intervals within the main body 100, thereby being able to generate additional hole inversion channels in the internal components of the device by controlling the order of voltage switching of the pioneer gate 200 and the accelerating gate 300, thereby being able to extract the tail current existing when the device is turned off in a short time. At this time, the tail current is completely suppressed, thereby reducing the charge carrier concentration, which helps to cut off the current flow process. Based on this, compared with conventional semiconductor devices, the device shutdown time of the present application is significantly reduced, and the device usage frequency is greatly improved, which gives it a broader use prospect in this field.

[0024] by Figure 1 The illustrated dual-gate semiconductor device with timing difference serves as a reference. In this embodiment, the emitter 110 and collector 130 are located on opposite sides of the body 100 in the height direction. The channel gate and accelerating gate 300 are spaced apart along all directions. When the device is in operation, both the precursor gate 200 and the accelerating gate 300 receive a positive voltage, which excites electron-hole pairs in the base region 120 (channel), thereby forming a conductive channel. Furthermore, electrons primarily flow within the base region 120, forming a current, while holes are pushed toward the collector 130. Correspondingly, when the device transitions from the operating state to the off state, the precursor gate 200 maintains a positive voltage, while the accelerating gate 300 preferentially applies a negative voltage. The negative voltage applied to the accelerating gate 300 forms a hole inversion channel, accelerating the removal of holes from the channel. It is worth noting that holes are one of the charge carriers. Their removal reduces the charge carrier concentration in the channel, thereby helping to cut off the current flow. Therefore, the rapid sweeping out of holes helps to quickly turn off the device. In addition, when the device is turned off, if the hole current cannot be swept out quickly, it will cause reverse conduction, which will slow down the device shutdown speed and generate additional losses. Therefore, accelerating the sweeping out speed of the hole current can reduce this reverse conduction loss. Furthermore, shortening the turn-off time can reduce the power loss of the device during the switching process and reduce the thermal stress of the device, which helps to improve the reliability and life of the device.

[0025] In this embodiment, the precursor gate 200 and the accelerating gate 300 are made of polysilicon, and the emitter 110 and the collector 130 are made of metal-based materials, and the present invention does not impose any specific restrictions on their types. Figure 1As shown, the pioneer gate 200 and the accelerating gate 300 are both provided with a gate oxide layer between the main body 100, and the base material thereof is preferably silicon oxide (SiO2), which is used as an insulating layer to isolate the pioneer gate 200, the accelerating gate 300 and the collector 130, thereby preventing electrons from being directly injected from the gate into the collector 130, thereby avoiding rapid failure of the device.

[0026] See also Figure 1 As shown, in this embodiment, the transmission layer group 121 includes N + layer 1211, p-body layer 1212 and charge separation layer 1213, wherein the N + Layer 1211 is connected to the emitter 110. Further, the N + A connecting groove 1214 is provided between the layer 1211 and the p-body layer 1212. The connecting groove 1214 penetrates the N + The auxiliary layer group 122 includes an N-Buffer layer 1221 and a P-body layer 1212 connected to each other, thereby improving the on- and off-state characteristics of the device and improving its switching performance. + Layer 1222, wherein the P + Layer 1222 is connected to the collector 130, and the N-Buffer layer 1221 is spaced apart from the charge separation layer 1213. Specifically, in the above structure, the N+ region helps to improve the emission efficiency of carriers (electrons or holes); the P-body region provides additional carrier injection, thereby improving the current carrying capacity and switching characteristics of the device; the charge separation layer 1213 separates the charges to form a conductive channel; the purpose of the N-Buffer layer 1221 is to reduce the change in base current caused by the change in the collector 130 current, thereby improving the stability and driving capability of the transistor; + Layer 1222 is used to form specific electrodes or regions to improve carrier injection efficiency and device performance.

[0027] Example 2

[0028] This embodiment provides a method for preparing a dual-gate semiconductor device with a timing difference, which is used to prepare the dual-gate semiconductor device with a timing difference described in the first embodiment, and specifically includes the following steps:

[0029] S1. Preparing the precursor gate 200 and the accelerating gate 300 spaced apart inside the etched body 100. In this embodiment, step S1 is specifically as follows:

[0030] S11, performing trench etching on the body 100 to form a trench structure;

[0031] S12, preparing a gate oxide layer in the trench;

[0032] S13, filling the trench with polysilicon to form the precursor gate 200 and the accelerating gate 300

[0033] S2, injecting a transmission layer base material from the first surface of the body 100 into the interior thereof to form a transmission layer assembly 121; in this embodiment, step S2 is specifically as follows:

[0034] S21, sequentially preparing the charge separation layer 1213, the p-body layer 1212 and the N + Layer 1211, wherein the N + Layer 1211 is close to the first surface;

[0035] S22, in the N + A connecting groove 1214 is formed between the layer 1211 and the p-body layer 1212, so that the connecting groove 1214 passes through the N + layer 1211 and extending into at least a portion of the p-body layer 1212

[0036] S3, depositing the emitter 110 on the surface of the transmission layer group 121; in this embodiment, step S3 is specifically as follows: + The surface of the layer 1211 is subjected to a metal deposition process to prepare the emitter 110 on the first surface.

[0037] S4, injecting an auxiliary layer substrate into the interior of the body 100 from the second surface thereof to form an auxiliary layer group 122, wherein the first surface and the second surface are respectively arranged on opposite sides of the body 100; in this embodiment, the N-Buffer layer 1221 and the P-Buffer layer 1222 are sequentially prepared from the interior of the body 100 to the exterior thereof. + Layer 1222, wherein the P + Layer 1222 is adjacent to the second surface.

[0038] S5, depositing the collector electrode 130 on the surface of the auxiliary layer group 122 to complete the preparation of the target device; in this embodiment, + The surface of the layer 1222 is subjected to metal deposition processing to prepare the collector electrode 130 on the second surface, thereby completing the preparation of the target device.

[0039] In summary, the dual-gate semiconductor device with timing difference and the preparation method thereof described in the present invention have a pioneer gate 200 and an accelerating gate 300 spaced apart in the main body 100, thereby being able to generate an additional hole inversion channel in the internal components of the device by controlling the order of voltage switching of the pioneer gate 200 and the accelerating gate 300, thereby being able to extract the tail current existing when the device is turned off in a short time. At this time, the tail current is completely suppressed, thereby reducing the charge carrier concentration, which helps to cut off the current flow process. Based on this, compared with conventional semiconductor devices, the device shutdown time of this application is significantly reduced, and the device usage frequency is greatly improved, which gives it a broader use prospect in this field.

[0040] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A dual-gate semiconductor device with timing difference, characterized in that: include: A body, wherein an emitter and a collector are provided on opposite sides of the body, a base region is located between the emitter and the collector, and the base region includes a transmission layer group and an auxiliary layer group, wherein the transmission layer group and the auxiliary layer group are respectively provided on opposite sides of the base region, wherein the transmission layer group is connected to the emitter, and the auxiliary layer group is connected to the collector; A pioneer gate and an accelerating gate, wherein the pioneer gate and the accelerating gate are spaced apart and arranged inside the base region; When the device is in the working state, the precursor gate and the accelerating gate simultaneously obtain positive voltages. When the device is switched from the working state to the off state, the accelerating gate is first switched to a negative voltage to form a hole inversion channel, through which the hole current is extracted; the precursor gate is then switched to a negative voltage to complete the shutdown; the transmission layer group includes N + layer, p-body layer and charge separation layer, wherein the N + layer connects the emitter, the N + A connecting groove is provided between the N layer and the p-body layer, and the connecting groove penetrates the N + layer, and extending into at least a portion of the p-body layer.

2. The dual-gate semiconductor device with timing difference according to claim 1, wherein: The auxiliary layer group includes an N-Buffer layer and a P + layer, wherein the P + The layer is connected to the collector, and the N-Buffer layer is spaced apart from the charge separation layer.

3. The dual-gate semiconductor device with timing difference according to claim 1, wherein: The precursor gate and the accelerating gate substrates are made of polysilicon, and the emitter and the collector are both made of metal-based materials.

4. The dual-gate semiconductor device with timing difference according to claim 1, wherein: The precursor gate and the accelerating gate are both provided with a gate oxide layer between the body.

5. A method for preparing a dual-gate semiconductor device with timing difference, characterized in that: The method for preparing the dual-gate semiconductor device with timing difference according to any one of claims 1 to 4 comprises the following steps: S1, preparing a pioneer gate and an accelerating gate arranged at intervals inside the etched body; S2. Injecting a transmission layer base material from the first surface of the body into the interior thereof to form a transmission layer assembly; S3, depositing an emitter on the surface of the transmission layer group; S4, injecting an auxiliary layer substrate into the interior of the main body from the second surface thereof to form an auxiliary layer group, wherein the first surface and the second surface are respectively disposed on opposite sides of the main body; S5. Depositing a collector electrode on the surface of the auxiliary layer group to complete the preparation of the target device.

6. The method for preparing a dual-gate semiconductor device with timing difference according to claim 5, wherein: Step S1 is specifically as follows: S11, performing trench etching on the body to form a trench structure; S12, preparing a gate oxide layer in the trench; S13, filling the trench with polysilicon to form the pioneer gate and the accelerating gate.

7. The method for preparing a dual-gate semiconductor device with timing difference according to claim 5, wherein: Step S2 is specifically as follows: S21, sequentially preparing a charge separation layer, a p-body layer and an N-body layer from the inside to the outside of the body. + layer, wherein the N + layer adjacent to said first surface; S22, in the N + A connecting groove is prepared between the N layer and the p-body layer, so that the connecting groove passes through the N + layer, and extending into at least a portion of the p-body layer.

8. The method for preparing a dual-gate semiconductor device with timing difference according to claim 5, wherein: Step S3 is specifically as follows: + performing a metal deposition process on the surface of the layer to prepare the emitter on the first surface; Step S4 is specifically as follows: preparing N-Buffer layer and P- + layer, wherein the P + a layer adjacent to said second surface; Step S5 is specifically as follows: + The surface of the layer is subjected to metal deposition processing to prepare the collector on the second surface to complete the preparation of the target device.

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