Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a source, a drain, a gate, a channel structure, a support layer and a gate dielectric layer. The drain and the source are arranged in a vertical direction. The gate is arranged between the drain and the source. The channel structure is partially arranged in the gate and connects the drain and the source. The support layer is arranged on the sidewall of the channel structure. The gate dielectric layer is partially arranged between the channel structure and the gate in a horizontal direction and partially arranged between the support layer and the gate. Thus, the gate dielectric layer can be arranged around the gate by the arrangement of the support layer, and the operation performance of the semiconductor device is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and more particularly, to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] The technology of semiconductor integrated circuits has been growing over time, with each new generation of manufacturing process producing products with smaller and more complex circuit designs than the previous generation. Functional components on each wafer area must be increased in number and density due to product innovation requirements, of course, the geometry of each component needs to be smaller and smaller. Since the traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing process is difficult to continue to shrink, the industry has proposed to replace the traditional planar transistor component with a three-dimensional or non-planar transistor component, thereby reducing the geometry of the transistor component or / and improving the operating performance of the transistor element. SUMMARY

[0003] The purpose of the present application is to provide a semiconductor device and a method of manufacturing the same, which additionally provides a support layer on the sidewall of the channel structure, so that the gate dielectric layer is arranged around the gate, thereby improving the structural stability and operating performance of the semiconductor device, to solve the problem of lack of stability in the structure of the semiconductor device and poor operating performance in the related art.

[0004] To achieve the above-mentioned purpose, one embodiment of the present application provides a semiconductor device, comprising a source, a drain, a gate, a channel structure, a support layer, and a gate dielectric layer. The drain and the source are arranged in a vertical direction, and the gate is arranged between the drain and the source. The channel structure is partially arranged in the gate and connects the drain and the source. The support layer is arranged on the sidewall of the channel structure. The gate dielectric layer is partially arranged in a horizontal direction between the channel structure and the gate, and partially arranged between the support layer and the gate.

[0005] To achieve the above-mentioned purpose, one embodiment of the present application provides a method of manufacturing a semiconductor device, comprising the following steps. Form a stack of a source, a gate, and a drain in a vertical direction. Form a channel structure between the drain and the source, the channel structure being partially arranged in the gate and connecting the drain and the source. Form a support layer on the sidewall of the channel structure. Form a gate dielectric layer between the channel structure and the gate, the gate dielectric layer also being partially arranged between the support layer and the gate.

[0006] The semiconductor device of the present application includes a source, a drain, a gate, a channel structure, a support layer, and a gate dielectric layer. The drain and the source are stacked in a vertical direction, and the gate is disposed between the drain and the source. Part of the channel structure is disposed in the gate and connects the drain and the source. The support layer is disposed on the sidewall of the channel structure. Part of the gate dielectric layer is disposed between the channel structure and the gate in a horizontal direction, and part of the gate dielectric layer is disposed between the support layer and the gate. By disposing the support layer, the gate dielectric layer can be disposed around the gate, effectively improving the operating performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of the some embodiments. It will be appreciated that all drawings are schematic and for purposes of illustration support and are not relative to scale. Identical reference numerals in different drawings represent identical or corresponding features.

[0008] Figure 1 A cross-sectional view of a semiconductor device according to a first embodiment of the present application is shown.

[0009] Figures 2 to 11 A cross-sectional view of a semiconductor device according to a first embodiment of the present application is shown.

[0010] Wherein:

[0011] Figure 2 A top view of a semiconductor device after forming a support material layer is shown.

[0012] Figure 3 A cross-sectional view of a semiconductor device after forming a support material layer is shown.

[0013] Figure 4 A top view of a semiconductor device after forming a channel hole is shown.

[0014] Figure 5 A cross-sectional view of a semiconductor device after forming a channel hole is shown.

[0015] Figure 6 A cross-sectional view of a semiconductor device after forming a channel structure is shown.

[0016] Figure 7 A cross-sectional view of a semiconductor device after removing a sacrificial layer is shown.

[0017] Figure 8 A cross-sectional view of a semiconductor device after forming an electrode material layer is shown.

[0018] Figure 9 A cross-sectional view of a semiconductor device after forming a gate is shown.

[0019] Figure 10 Fig. 2 is a top view of a semiconductor device after forming an insulating spacer;

[0020] Figure 11 Fig. 3 is a cross-sectional view of the semiconductor device after forming the insulating spacer.

[0021] Figure 12 Fig. 4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present application.

[0022] In the drawings, the following reference numerals are used:

[0023] 10, 20 semiconductor device

[0024] 100 dielectric layer

[0025] 102, 106, 136, 142 metal barrier layer

[0026] 104, 138, 144 electrode layer

[0027] 108 bottom semiconductor layer

[0028] 110 bottom dielectric layer

[0029] 112 first dielectric layer

[0030] 112a first dielectric material layer

[0031] 114 second dielectric layer

[0032] 114a second dielectric material layer

[0033] 116 sacrificial layer

[0034] 118 fill layer

[0035] 120 channel layer

[0036] 122 insulating layer

[0037] 124 first semiconductor layer

[0038] 126 second semiconductor layer

[0039] 130 support layer

[0040] 130a support material layer

[0041] 132 first gate dielectric layer

[0042] 132a first gate dielectric material layer

[0043] 134 second gate dielectric layer

[0044] 134a second gate dielectric material layer

[0045] 136, 236 metal barrier layer

[0046] 136a electrode barrier material layer

[0047] 138, 238 electrode layer

[0048] 138a electrode material layer

[0049] 140, 240 insulating spacer

[0050] 146 top dielectric layer

[0051] 236a recess

[0052] 238a recess

[0053] 240a, 240b protrusion

[0054] D1 vertical direction

[0055] D2 horizontal direction

[0056] D3 horizontal direction

[0057] DE drain

[0058] GE gate

[0059] GD gate dielectric layer

[0060] OP via hole

[0061] R1, R2, R3 through hole

[0062] SE source

[0063] SS channel structure

[0064] V1 void DETAILED DESCRIPTION

[0065] In order to enable a person skilled in the art to further understand the present application, several preferred embodiments of the present application are listed below, and the technical solutions of the present application and the effects to be achieved are described in detail with reference to the accompanying drawings. A person skilled in the art can refer to the following embodiments without departing from the spirit of the present application, and replace, reorganize, mix the features in several different embodiments to complete other embodiments.

[0066] Please refer to Figure 1 , as shown, Figure 1This is a schematic cross-sectional view of the semiconductor device 10 according to the first embodiment of the present invention. Figure 1 As shown, the semiconductor device 10 includes a source SE, a drain DE, a gate GE, a channel structure SS, a support layer 130, and a gate dielectric layer GD. The source SE and drain DE are stacked in the vertical direction D1, and the gate GE is located above the source SE and disposed between the source SE and drain DE. The channel structure SS is partially disposed within the gate GE and is also disposed in the vertical direction D1 between the source SE and drain DE, electrically connecting the source SE and drain DE. It should be noted that the support layer 130 is disposed on a portion of the sidewall of the channel structure SS, while the gate dielectric layer GD covers the support layer 130, such that a portion of the gate dielectric layer GD is disposed in the horizontal direction D2 / D3 between the channel structure SS and the gate GE, while another portion of the gate dielectric layer GD is disposed in the vertical direction D1 between the support layer 130 and the gate GE. Therefore, by means of the support layer 130, the gate dielectric layer GD covering the sidewall of the support layer 130 can be arranged around the gate GE, improving the structural stability of the gate GE and the channel structure SS, thereby improving the operating performance of the semiconductor device 10.

[0067] Furthermore, the semiconductor device 10 also includes a bottom dielectric layer 110 and an insulating space 140 sequentially disposed between the source SE and the drain GE, which may include, for example, the same or different insulating material as the support layer 130. In one embodiment, the bottom dielectric layer 110, the insulating space 140, and the support layer 130 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulating materials. For example, when the insulating space 140 includes, for example, silicon oxide, silicon oxynitride, etc., the bottom dielectric layer 110 and the support layer 130 may include, for example, silicon nitride, silicon carbonitride, etc., but this is not a limitation. In another embodiment, the support layer 130 may also be selected to include the same material as the insulating space 140, such as silicon oxide, silicon oxynitride, etc. Preferably, the bottom dielectric layer 110 includes a first dielectric layer 112 and a second dielectric layer 114 sequentially disposed, for example, each including different insulating materials. The first dielectric layer 112 preferably comprises the same material as the insulating space 140, such as silicon oxide, while the second dielectric layer 114 preferably comprises the same material as the support layer 130, such as silicon nitride, but is not limited thereto.

[0068] The gate GE is disposed within the insulating gap 140, and the bottom of the insulating gap 140 extends further into the bottom dielectric layer 110, having a bottom surface lower than the gate dielectric layer GD. Thus, the channel structure SS, partially disposed within the gate GE, is also partially disposed within the bottom dielectric layer 110 between the source SE and the gate GE, and has a bottom surface flush with the bottom dielectric layer 110. Figure 1The gate dielectric layer GD is configured to effectively isolate the gate GE and its adjacent components, and to optimize the structure and function of the gate GE. It is noted that the gate dielectric layer GD is in physical contact with the upper surface, the lower surface and the sidewall of the side of the gate GE, and is also in physical contact with the sidewall and the lower surface of the support layer 130, such that the gate dielectric layer GD is also partially disposed between the support layer 130 and the insulating spacer 140 in the horizontal direction D2 / D3, and is also partially disposed below the gate GE in the vertical direction Dl, between the gate GE and the bottom dielectric layer 110. That is, the gate dielectric layer GD generally presents a ladle-shaped cross section as shown in Figure 1 In an embodiment, the gate dielectric layer GD includes a first gate dielectric layer 132 and a second gate dielectric layer 134 disposed in sequence between the channel structure SS and the gate GE in the horizontal direction D2 / D3, wherein the first gate dielectric layer 132 and the second gate dielectric layer 134, for example, include different dielectric materials or high dielectric constant dielectric materials, respectively.

[0069] As further shown in Figure 1 The semiconductor device 10 further includes a dielectric layer 100, a bottom semiconductor layer 108, a channel opening OP, and a top dielectric layer 146. The aforementioned source SE, drain DE, gate GE, channel structure SS, support layer 130, and gate dielectric layer GD, etc. are disposed on the dielectric layer 100, and the dielectric layer 100 is disposed on a substrate (not shown), which includes, but is not limited to, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or other suitable materials. Those skilled in the art should understand that various active components and / or passive components can be further formed on or in the substrate according to actual device requirements, without being limited to the aforementioned components.

[0070] Specifically, the bottom semiconductor layer 108 is disposed between the source SE and the bottom dielectric layer 110 in the vertical direction D1, while the via hole OP penetrates the support layer 130 and the bottom dielectric layer 110 in the vertical direction D1 to expose the bottom semiconductor layer 108 from the bottom thereof. Thus, the bottom surface of the channel structure SS disposed in the via hole OP physically contacts the bottom semiconductor layer 108. The channel structure SS in detail includes the channel layer 120 and the insulating layer 122 stacked in sequence in the horizontal direction D2 / D3, wherein the channel layer 120 further includes the first semiconductor layer 124 and the second semiconductor layer 126, and the insulating layer 122 can be used to indirectly control the composition of the channel structure SS and / or support the channel structure SS. The second semiconductor layer 126 is disposed between the insulating layer 122 and the drain DE in the vertical direction D1, and the first semiconductor layer 124 is disposed around the second semiconductor layer 126 and the insulating layer 122 in the horizontal direction D2 / D3, and has a U-shaped cross-section as shown in Figure 1 In an embodiment, the bottom semiconductor layer 108, the first semiconductor layer 124, and the second semiconductor layer 126, for example, each include a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide (IZO), aluminum zinc oxide (AZO), or indium gallium zinc oxide (IGZO), but are not limited thereto. Moreover, the materials of the bottom semiconductor layer 108, the first semiconductor layer 124, and the second semiconductor layer 126 can be the same as or different from each other. In another embodiment, the dielectric layer 100 and the insulating layer 122, for example, each include a dielectric material or a high dielectric constant dielectric material, and preferably each include silicon oxide, but are not limited thereto.

[0071] On the other hand, the top dielectric layer 146 is disposed on the insulating spacer 140, such that the insulating spacer 140 is sandwiched between the bottom dielectric layer 110 and the top dielectric layer 146 in the vertical direction D1, and the drain electrode DE is disposed in the top dielectric layer 146, but not limited thereto. In detail, the source electrode SE, the gate electrode GE and the drain electrode DE each include a composite layer structure, for example. The source electrode SE preferably includes the metal barrier layer 102, the electrode layer 104 and the metal barrier layer 106, which are sequentially stacked in the vertical direction D1, for example. The gate electrode GE includes the metal barrier layer 136 and the electrode layer 138, which are sequentially disposed on the gate dielectric layer GD in the horizontal direction D2 / D3. The drain electrode DE includes the metal barrier layer 142 and the electrode layer 144, which are sequentially stacked in the vertical direction D1. In an embodiment, the metal barrier layer 102, the metal barrier layer 106, the metal barrier layer 136 and the metal barrier layer 142 include titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or other suitable metal barrier materials, for example, and the materials of the metal barrier layer 102, the metal barrier layer 106, the metal barrier layer 136 and the metal barrier layer 142 can be the same as or different from each other, and preferably all include titanium nitride, but not limited thereto. In addition, the electrode layer 104, the electrode layer 138 and the electrode layer 144 each include copper (Cu), aluminum (Al), tungsten (W) or other suitable low-resistance metal materials, and the materials of the electrode layer 104, the electrode layer 138 and the electrode layer 144 can be the same as or different from each other, and preferably all include tungsten, but not limited thereto. In other embodiments, the metal barrier layer 102, the metal barrier layer 106, the metal barrier layer 136 and / or the metal barrier layer 142 can be selectively omitted or have a composite film according to actual device requirements, but not limited thereto.

[0072] In this configuration, the channel structure SS of the semiconductor device 10 presents a columnar cross-section extending along the vertical direction D1. Furthermore, by means of the first semiconductor layer 124 of the channel layer 120, the second semiconductor layer 126 and the bottom semiconductor layer 108 are physically in contact, so that when a threshold voltage is applied to the gate GE, the drain DE and the source SE are electrically connected. The drain DE, the gate dielectric layer GD, the gate GE, the channel structure SS, and the source SE together form a three-dimensional transistor assembly, making the channel structure SS a vertical channel structure of the three-dimensional transistor assembly, while the gate GE surrounding the outside of the channel structure SS achieves an effect similar to a gate-all-around (GAA). According to the semiconductor device 10 of this embodiment, with the aid of a support layer 130 additionally disposed on the channel structure SS, the gate dielectric layer GD covering the support layer 130 is located between the gate GE and the channel structure SS in the horizontal direction D2 / D3, and partially located between the support layer 130 and the gate GE, and partially located between the gate GE and the bottom dielectric layer 110 in the vertical direction D1, and generally presents a spoon-shaped cross-section. Thus, the gate dielectric layer GD is disposed around the gate GE to improve the structural stability and component performance of the gate GE and the channel structure SS, and the semiconductor device 10 has a relatively short channel length, thereby improving its operational performance.

[0073] To enable those skilled in the art to easily understand and implement the semiconductor device of the present invention, the following will further describe the manufacturing method of the semiconductor device of the present invention.

[0074] Please see Figures 2 to 11 The diagram shown is a schematic representation of a method for fabricating a semiconductor device 10 according to an embodiment of the present invention. First, as... Figure 2 and Figure 3As shown, another film formation fabrication process, such as by a chemical vapor deposition process, a physical vapor deposition process, or other suitable means, is performed to form the fill layer 118 within the via Rl. Then, a dry etching fabrication process is performed with a mask (not shown) to partially remove the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a in the region 120, forming at least one through-hole OP in the vertical direction Dl through the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a, while exposing the bottom semiconductor layer 108 from a bottom portion of the at least one through-hole OP. Also, the support layer 130 on the outer sidewall of the at least one through-hole OP is formed simultaneously with the formation of the at least one through-hole OP, and the first dielectric layer 112 and the second dielectric layer 114 are formed sequentially between the bottom semiconductor layer 108 and the fill layer 118, and the mask is completely removed. The first dielectric layer 112 and the second dielectric layer 114 collectively form the bottom dielectric layer 110 of the semiconductor device 10. In one embodiment, the fill layer 118, for example, includes a dielectric material different from the support material layer 130a and the sacrificial layer 116, and preferably includes tetraethoxysilane (TEOS), but is not limited thereto.

[0075] As shown, another film formation fabrication process, such as by a chemical vapor deposition process, a physical vapor deposition process, or other suitable means, is performed to form the fill layer 118 within the via Rl. Then, a dry etching fabrication process is performed with a mask (not shown) to partially remove the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a in the region 120, forming at least one through-hole OP in the vertical direction Dl through the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a, while exposing the bottom semiconductor layer 108 from a bottom portion of the at least one through-hole OP. Also, the support layer 130 on the outer sidewall of the at least one through-hole OP is formed simultaneously with the formation of the at least one through-hole OP, and the first dielectric layer 112 and the second dielectric layer 114 are formed sequentially between the bottom semiconductor layer 108 and the fill layer 118, and the mask is completely removed. The first dielectric layer 112 and the second dielectric layer 114 collectively form the bottom dielectric layer 110 of the semiconductor device 10. In one embodiment, the fill layer 118, for example, includes a dielectric material different from the support material layer 130a and the sacrificial layer 116, and preferably includes tetraethoxysilane (TEOS), but is not limited thereto. Figure 4 and Figure 5 As shown, another film formation fabrication process, such as by a chemical vapor deposition process, a physical vapor deposition process, or other suitable means, is performed to form the fill layer 118 within the via Rl. Then, a dry etching fabrication process is performed with a mask (not shown) to partially remove the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a in the region 120, forming at least one through-hole OP in the vertical direction Dl through the support material layer 130a, the sacrificial layer 116, the first dielectric material layer 112a, and the second dielectric material layer 114a, while exposing the bottom semiconductor layer 108 from a bottom portion of the at least one through-hole OP. Also, the support layer 130 on the outer sidewall of the at least one through-hole OP is formed simultaneously with the formation of the at least one through-hole OP, and the first dielectric layer 112 and the second dielectric layer 114 are formed sequentially between the bottom semiconductor layer 108 and the fill layer 118, and the mask is completely removed. The first dielectric layer 112 and the second dielectric layer 114 collectively form the bottom dielectric layer 110 of the semiconductor device 10. In one embodiment, the fill layer 118, for example, includes a dielectric material different from the support material layer 130a and the sacrificial layer 116, and preferably includes tetraethoxysilane (TEOS), but is not limited thereto. Figure 3

[0076] As​Figure 6 As shown, a channel structure SS is formed within at least one channel hole OP. The formation of the channel structure SS includes, but is not limited to, the following steps. First, a film fabrication process, such as chemical vapor deposition, physical vapor deposition, or other suitable methods, is performed again to form a first semiconductor material layer (not shown), partially located within and partially located outside the at least one channel hole OP, such that the first semiconductor material layer conformally covers the top surface of the support layer 130 and the fill layer 118, and the sidewalls of the support layer 130, the sacrificial layer 116, and the bottom dielectric layer 110, physically contacting the bottom semiconductor layer 108. Then, an insulating material layer (not shown) is formed, at least filling the at least one channel hole OP. Next, the insulating material layer is partially removed until the at least one channel hole OP is not completely filled, forming an insulating layer 122 with its top surface lower than the bottom surface of the support layer 130. Then, a second semiconductor material layer (not shown) is formed, filling the remaining space of the at least one channel hole OP and further covering the top surface of the support layer 130 and the fill layer 118.

[0077] Then, a planarization process, such as chemical mechanical polishing or other suitable methods, is performed to simultaneously remove the second semiconductor material layer and the first semiconductor material layer formed outside at least one channel hole OP, forming a second semiconductor layer 126 and a first semiconductor layer 124. Thus, the second semiconductor layer 126, the insulating layer 122, and the first semiconductor layer 124 formed within at least one channel hole OP together form the channel structure SS of the semiconductor device 10, wherein a support layer 130 is formed on the sidewall of the upper half of the channel structure SS and has a top surface flush with the channel structure SS, such as... Figure 6 As shown. In one embodiment, the first semiconductor material layer and the second semiconductor material layer include, for example, doped polycrystalline silicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, preferably both of which include the same semiconductor material as the bottom semiconductor layer 108, but are not limited thereto. The insulating material layer includes, for example, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, preferably both of which include silicon oxide, but are not limited thereto.

[0078] like Figure 7 As shown, a wet etching process is performed to simultaneously remove... Figure 6 The etching process selects filler layer 118 and sacrificial layer 116 with similar ratios to form through-hole R2, partially exposing the second dielectric layer 114. Since the support layer 130 is formed on the sidewall of the upper half of the channel structure SS, through-hole R2 has a smaller diameter at the top and a larger diameter at the bottom, thus presenting a shape similar to... Figure 7The bottle-like cross-section is shown, but is not limited thereto. Also, a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable process is performed to sequentially form a first gate dielectric material layer 132a partially formed within the via R2 and partially formed outside the via R2, and a second gate dielectric material layer 134a. In one embodiment, the first gate dielectric material layer 132a and the second gate dielectric material layer 134a include, for example, different dielectric materials or high dielectric constant dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or the like, but are not limited thereto.

[0079] As shown in FIG. 1C, a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable process is performed to form an electrode barrier material layer 136a partially formed within the via R2 and partially formed outside the via R2, and then an electrode material layer 138a is formed to fill the via R2 and further cover the top surface of the support layer 130 and the channel structure SS. Figure 8 As shown in FIG. 1C, a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable process is performed to form an electrode barrier material layer 136a partially formed within the via R2 and partially formed outside the via R2, and then an electrode material layer 138a is formed to fill the via R2 and further cover the top surface of the support layer 130 and the channel structure SS.

[0080] As shown in FIG. 1C, a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable process is performed to form an electrode barrier material layer 136a partially formed within the via R2 and partially formed outside the via R2, and then an electrode material layer 138a is formed to fill the via R2 and further cover the top surface of the support layer 130 and the channel structure SS. Figure 9 As shown in FIG. 1C, a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable process is performed to form an electrode barrier material layer 136a partially formed within the via R2 and partially formed outside the via R2, and then an electrode material layer 138a is formed to fill the via R2 and further cover the top surface of the support layer 130 and the channel structure SS. Figure 8The electrode material layer 138a, the electrode barrier material layer 136a, the second gate dielectric material layer 134a and the first gate dielectric material layer 132a formed outside the via R2 expose the bottom surface of the support layer 130. Then, the etching process is performed again with the support layer 130, to partially remove the electrode material layer 138a, the electrode barrier material layer 136a, the second gate dielectric material layer 134a and the first gate dielectric material layer 132a formed at the bottom of the via R2, and the second dielectric layer 114 underneath, to form a via R3 with a top surface lower than the top surface of the bottom dielectric layer 110. Also, the metal barrier layer 136, the electrode layer 138, the first gate dielectric layer 132 and the second gate dielectric layer 134 are formed simultaneously on both sides of the via R3. Thus, the metal barrier layer 136 and the electrode layer 138 together form the gate electrode GE of the semiconductor device 10, while the first gate dielectric layer 132 and the second gate dielectric layer 134 together form the gate dielectric GD of the semiconductor device 10. It is noted that the fabrication method of the present embodiment is to first form the channel structure SS with a columnar cross-section in the vertical direction D1, and the support layer 130 on the upper half of the sidewall of the channel structure SS, and then form the gate dielectric GD and the gate electrode GE. In this operation, the fabrication of the gate electrode GE does not require the formation of an additional etching mask, but is performed by the etching process with the support layer 130, and the subsequently formed gate dielectric GD can also conformally cover the support layer 130 and the lower half of the sidewall of the channel structure SS, so that the gate dielectric GD is arranged around the gate electrode GE, and presents a ladle-shaped cross-section as shown in Figure 9 Thus, the gate dielectric GD is fabricated after the formation of the channel structure SS, so that the structural damage can be effectively avoided, and the device stability is optimized. Furthermore, the gate dielectric GD is located between the gate electrode GE and the channel structure SS in the horizontal direction D2 / D3, and is partially located between the support layer 130 and the gate electrode GE, and partially located between the gate electrode GE and the bottom dielectric layer 110 in the vertical direction D1, so that the structural stability and the component performance of the gate electrode GE are optimized.

[0081] As shown in Figure 10 and Figure 11 The deposition fabrication process such as the chemical vapor deposition process, the physical vapor deposition process or other suitable methods is performed again to form a dielectric material layer (not shown) partially formed inside the via R3 and partially formed outside the via R3, and then the planarization fabrication process such as the chemical mechanical polishing process or other suitable methods is performed to remove the dielectric material layer formed outside the via R3, to form the insulating spacer 140 with a bottom surface lower than the gate dielectric GD. Then, the drain DE is formed on the channel structure SS and the support layer 130, and the top dielectric layer 146 is formed, to form the semiconductor device 10 as shown inFigure 1 The semiconductor device 10 shown is completed by the manufacturing method of the embodiment. Figures 5 to 11 The structures not mentioned in the embodiment are the same as those in the first embodiment, and will not be repeated. Figure 1 The description is consistent with the first embodiment, and will not be repeated.

[0082] According to the manufacturing method of the embodiment, the channel structure SS is formed in advance before the manufacturing of the gate GE, and the support layer 130 is additionally formed on the sidewall of the channel structure SS, so that the manufacturing of the gate GE is performed by the etching process of the support layer 130, and the subsequently formed gate dielectric layer GD is arranged around the gate GE, thereby being able to be conformally covered on the support layer 130 and the lower half sidewall of the channel structure SS, and presenting a ladle-shaped cross section. In this way, the gate dielectric layer GD is located between the gate GE and the channel structure SS in the horizontal direction D2 / D3, and is partially located between the support layer 130 and the gate GE and partially located between the gate GE and the bottom dielectric layer 110 in the vertical direction D1, thereby providing the gate GE with more optimized structural stability and component performance. Accordingly, the semiconductor device 10 manufactured by the manufacturing method of the embodiment has the gate GE and the channel structure SS with more optimized component performance, thereby improving the operation performance of the semiconductor device 10.

[0083] Those skilled in the art of the present application should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and the manufacturing method thereof of the present application can also have other forms or can be achieved by other means, and are not limited to the foregoing. Further embodiments or variations of the semiconductor device and the manufacturing method thereof of the present application will be described below. In order to simplify the description, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeated. In addition, the same components in the embodiments of the present application are marked with the same reference numerals for mutual reference between the embodiments.

[0084] Please refer to Figure 12 shown, Figure 12 is a cross-sectional schematic view of a semiconductor device 20 of a second embodiment of the present application. The structure of the semiconductor device 20 of the embodiment is generally the same as that of the semiconductor device 10 of the first embodiment described above, and also includes a source SE, a drain DE, a gate GE, a channel structure SS, a support layer 130, and a gate dielectric layer GD, etc. The same parts will not be repeated here. The main difference between the semiconductor device 20 of the embodiment and the first embodiment described above is that, when the via R3 as shown in the first embodiment is formed, Figure 9 The etching degree of the electrode material layer 138a and the electrode barrier material layer 136a is caused to be different by adjusting the process conditions of the electrode material layer 138a and the electrode barrier material layer 136a, and at least one recessed portion 236a, 238a is formed on the gate GE, which is recessed towards the channel structure SS.

[0085] Specifically, in one embodiment, the etch selectivity ratio of the electrode barrier material layer 136a relative to the electrode material layer 138a is adjusted such that the electrode barrier material layer 136a is etched to a relatively greater extent than the electrode material layer 138a, thereby forming a metal barrier layer 236 having recesses 236a, as shown on the left side. Figure 12 The recesses 236a are formed, for example, between the electrode layer 138 and the support layer 130, or between the bottom dielectric layer 110 and the electrode layer 138, in the vertical direction Dl, at the end of the gate electrode GE. Thus, the subsequently formed insulating spacer 240 has a protrusion 240a that fills the recess 236a at the end of the gate electrode GE. In another embodiment, the etch selectivity ratio of the electrode material layer 138a relative to the electrode barrier material layer 136a is adjusted such that the electrode material layer 138a is etched to a relatively greater extent than the electrode barrier material layer 136a, thereby forming an electrode layer 238 having recesses 238a, as shown on the right side. Figure 12 The recesses 238a are formed, for example, at the middle of the gate electrode GE in the vertical direction Dl, such that the subsequently formed insulating spacer 240 has a protrusion 240b that fills the recess 238a at the middle of the gate electrode GE.

[0086] In this operation, the semiconductor device 20 fabricated by the fabrication method of the present embodiment is also capable of having the gate dielectric layer GD formed on the sidewall of the support layer 130 wrapped around the gate electrode GE, thereby improving the structural stability of the gate electrode GE and the channel structure SS, and thus improving the operational performance of the semiconductor device 20.

[0087] In summary, the semiconductor device and the fabrication method thereof of the present embodiment forms the channel structure in advance before fabricating the gate electrode, and additionally forms the support layer on the sidewall of the channel structure, such that the fabrication of the gate electrode is performed by etching the support layer, and the subsequently formed gate dielectric layer can be wrapped around the gate electrode, thereby being conformally formed on the sidewall of the lower half of the support layer and the channel structure, and presenting a ladle-shaped cross section. Thus, the gate dielectric layer can provide the gate electrode with relatively optimized structural stability and component performance, thereby improving the operational performance of the semiconductor device of the present embodiment.

[0088] The preferred embodiments of the present application have been described above with the aid of drawing figures, and are not limited to those embodiments; instead, they will include any modifications and variations of the present application that occur to those skilled in the field of the present application, which modifications and variations are within the scope of the present application as defined by the following claims. Any reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A semiconductor device, characterized by, Comprising: a source electrode; a drain electrode, the source electrode and the drain electrode being disposed in a vertical direction; a gate electrode disposed between the source electrode and the drain electrode; an insulating spacer disposed between adjacent drain electrodes; a channel structure partially disposed within the gate electrode and connecting the drain electrode and the source electrode; a support layer disposed on a sidewall of the channel structure; and a gate dielectric layer partially disposed between the channel structure and the gate electrode in a horizontal direction and partially disposed between the support layer and the gate electrode; the gate dielectric layer physically contacts a lower surface and a sidewall of the support layer. the gate dielectric layer physically contacts an upper surface, a lower surface, and a sidewall of the gate electrode.

2. The semiconductor device according to claim 1, wherein Further comprising:

3. The semiconductor device of claim 1, wherein an insulating spacer disposed between the drain electrode and the source electrode, wherein the gate dielectric layer is further partially disposed between the support layer and the insulating spacer. the insulating spacer and the support layer comprise different materials.

4. The semiconductor device according to claim 3, wherein a bottom surface of the insulating spacer is lower than a bottom surface of the gate dielectric layer.

5. The semiconductor device of claim 3, wherein the insulating spacer comprises at least one protrusion protruding toward the gate electrode.

6. The semiconductor device of claim 3, wherein the gate electrode comprises at least one recessed portion recessed toward the channel structure.

7. The semiconductor device of claim 1, wherein the at least one recessed portion is disposed at an end portion of the gate electrode in the vertical direction.

8. The semiconductor device of claim 7, wherein, the at least one recessed portion is disposed at a middle portion of the gate electrode in the vertical direction.

9. The semiconductor device of claim 7, wherein, Further comprising:

10. The semiconductor device of claim 1, wherein a bottom dielectric layer disposed between the source electrode and the gate electrode, wherein the channel structure is further partially disposed within the bottom dielectric layer, and the bottom dielectric layer and the support layer comprise the same material. the gate dielectric layer is further partially disposed between the gate electrode and the bottom dielectric layer in the vertical direction.

11. The semiconductor device of claim 10, wherein, Comprising:

12. A method of fabricating a semiconductor device, characterized by, sequentially forming a source electrode, a gate electrode, and a drain electrode in a vertical direction; forming an insulating spacer between adjacent drain electrodes; forming a channel structure between the drain electrode and the source electrode, the channel structure being partially within the gate electrode and connecting the drain electrode and the source electrode; forming a support layer on a sidewall of the channel structure; and forming a gate dielectric layer between the channel structure and the gate electrode, the gate dielectric layer being further partially disposed between the support layer and the gate electrode; the gate dielectric layer physically contacts a lower surface and a sidewall of the support layer. forming the gate dielectric layer and the gate electrode after forming the channel structure and the support layer. Further comprising:

13. The method of fabricating a semiconductor device according to Claim 12, wherein forming an insulating spacer between the drain electrode and the source electrode, wherein the gate dielectric layer is further partially disposed between the support layer and the insulating spacer.

14. The method of fabricating a semiconductor device according to Claim 12, wherein the insulating spacer comprises at least one protrusion protruding toward the gate electrode. the gate electrode comprises at least one recessed portion recessed toward the channel structure.

15. The method of fabricating a semiconductor device according to Claim 14, wherein Further comprising:

16. The method of fabricating a semiconductor device according to Claim 12, wherein forming a bottom dielectric layer between the source electrode and the gate electrode in the vertical direction, wherein the channel structure is further partially disposed within the bottom dielectric layer.

17. The method of fabricating a semiconductor device according to Claim 14, wherein forming the channel structure further comprises: forming a sacrificial layer and a support material layer sequentially stacked on the bottom dielectric layer; 18. The method of fabricating a semiconductor device according to Claim 17, wherein ​ ​ partially removing the support material layer, the sacrificial layer and the bottom dielectric layer to form a via hole through the support material layer, the sacrificial layer and the bottom dielectric layer; forming the channel structure in the via hole; and completely removing the sacrificial layer after the channel structure is formed.

19. The method of fabricating a semiconductor device according to Claim 18, wherein The sacrificial layer and the support material layer comprise different insulating materials, and the sacrificial layer and the insulating spacer comprise the same insulating material.

20. A semiconductor device, characterized by comprising: Comprise: a source electrode; a drain electrode, the source electrode and the drain electrode being arranged in a vertical direction; a gate electrode, arranged between the source electrode and the drain electrode; an insulating spacer, arranged between adjacent drain electrodes; a channel structure, partially arranged in the gate electrode and connecting the drain electrode and the source electrode; a support layer, arranged on a sidewall of the channel structure; and a gate dielectric layer, partially arranged in a horizontal direction between the channel structure and the gate electrode, and partially arranged between the support layer and the gate electrode. The gate electrode comprises at least one recessed portion recessed towards the channel structure. Comprise:

21. A semiconductor device, characterized by comprising: a source electrode; a drain electrode, the source electrode and the drain electrode being arranged in a vertical direction; a gate electrode, arranged between the source electrode and the drain electrode; an insulating spacer, arranged between adjacent drain electrodes; a channel structure, partially arranged in the gate electrode and connecting the drain electrode and the source electrode; a support layer, arranged on a sidewall of the channel structure; and a gate dielectric layer, partially arranged in a horizontal direction between the channel structure and the gate electrode, and partially arranged between the support layer and the gate electrode. a bottom dielectric layer, arranged between the source electrode and the gate electrode, wherein the channel structure is also partially arranged in the bottom dielectric layer, and the bottom dielectric layer and the support layer comprise the same material. ​ ​

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