A relaxation oscillator with comparator delay elimination

Abstract

The present invention discloses a relaxation oscillator for eliminating comparator delay, comprising: a reference generation circuit for dividing a power supply VDD to generate a reference voltage; a capacitor charging and discharging circuit for charging via a resistor connected to the power supply VDD and discharging via a switch connected to a common ground VSS; a peak sampling circuit connected to the capacitor charging and discharging circuit for collecting the peak voltage of the capacitor when it is charged; a dynamic reference voltage generation circuit for providing a dynamic reference voltage to the comparator; and a clock generation circuit for providing a clock drive to switches in the capacitor charging and discharging circuit and the peak sampling circuit. The present invention samples the peak voltage of the capacitor charge via the peak sampling circuit, provides the dynamic reference voltage to the comparator via the dynamic reference voltage generation circuit, and utilizes a negative feedback mechanism to clamp the peak voltage of the capacitor charge to a set reference voltage, thereby eliminating the influence of the comparator delay on the oscillator frequency.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, in particular to a relaxation oscillator with comparator delay elimination. Background Art

[0002] The relaxation oscillator has the advantages of simple circuit structure, small footprint, easy integration and low power consumption, so it is widely used in on-chip integration. Figure 1 As shown, it mainly realizes the oscillation of the circuit by cyclically charging and discharging capacitors C1 and C2, and its oscillation period is Where VREF is the reference voltage, IC is the capacitor charging current, and Td is the comparator delay time.

[0003] With the development of fields such as communications and the Internet of Things, higher precision requirements have been put forward for oscillators. At present, the output accuracy of traditional relaxation oscillators is largely limited by the delay of the comparator, because VREF and IC can be corrected by digital adjustment and other methods, while the comparator delay time Td will be affected by process, temperature and other conditions. Therefore, it can only be reduced to a negligible level by increasing power consumption, but this approach does not conform to the low-power development trend of integrated circuits. For this reason, scholars have proposed many methods to solve the problem of comparator delay, such as average voltage negative feedback and other methods, but these methods usually require at least two comparators. In comparison, the present invention only requires one comparator, thereby achieving the purpose of optimizing circuit area and reducing comparator power consumption. Summary of the Invention

[0004] An object of the present invention is to provide a relaxation oscillator with comparator delay elimination to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a relaxation oscillator with comparator delay elimination, comprising:

[0006] A reference generating circuit divides the power supply VDD to generate a reference voltage;

[0007] The capacitor charging and discharging circuit is charged through a resistor connected to the power supply VDD and discharged through a switch connected to the common ground VSS;

[0008] A peak sampling circuit is connected to the capacitor charging and discharging circuit to collect the peak voltage when the capacitor is charging;

[0009] A dynamic reference voltage generating circuit, used for providing a dynamic reference voltage to the comparator;

[0010] And a clock generating circuit is used to provide clock drive to switches in the capacitor charging and discharging circuit and the peak sampling circuit.

[0011] Furthermore, the reference generation circuit includes resistors RO1 and RO2 connected in series, which divide the power supply VDD to generate a reference voltage VREF; the capacitor charging and discharging circuit includes a charging circuit, a first discharging circuit and a second discharging circuit.

[0012] Furthermore, the charging circuit includes a negative temperature coefficient resistor Rpoly, a positive temperature coefficient resistor Rdif, switches SW1 and SW3; the first discharge circuit includes a switch SW2 and a variable capacitor CO1, and the discharge of CO1 is controlled by a signal DISC1; the second discharge circuit includes a switch SW4 and a variable capacitor CO2, and the discharge of CO2 is controlled by a signal DISC2. The power supply VDD charges the capacitor through the series-connected Rpoly and Rdif, and the capacitor voltage is VCAP. The SW1 and SW3 are used to determine the charging of CO1 and CO2, respectively.

[0013] Furthermore, the peak sampling circuit includes switches SW5, SW6 and capacitor CO3, one end of the switch SW5 is connected to the first discharge circuit, and the other end is connected to the capacitor CO3; one end of the switch SW6 is connected to the second discharge circuit, and the other end is connected to the capacitor CO3; the sampling clock signals of the peak sampling circuit are S1 and S2, and the sampled output voltage is VPEAK.

[0014] Furthermore, the dynamic reference voltage generating circuit includes an amplifier OTA and a capacitor CO4, the reference voltage VREF is connected to the same-direction end of the amplifier OTA, the sampled output voltage VPEAK is connected to the reverse end of OTA, and the amplifier OTA amplifies the difference between VREF and VPEAK to generate a dynamic reference voltage D_VPEAK.

[0015] Furthermore, the clock generating circuit includes a frequency divider circuit composed of a comparator COMP, a Schmitt trigger, an inverter, and a D flip-flop, and a timing signal generating circuit composed of a gate circuit such as an inverter;

[0016] VCAP is connected to the same-direction end of COMP, and D_VPEAK is connected to the reverse end of COMP. COMP compares VCAP and D_VPEAK to generate a clock. After being shaped by the Schmitt trigger, inverter, and D flip-flop, CLKIN is generated to drive the timing signal generation circuit. The timing signal generation circuit then performs logical operations to generate CLK, ICLK, S1, S2, DISC1, and DISC2 signals.

[0017] Furthermore, the CLK and ICLK are generated by CLKIN through non-overlapping clocks, S1 is generated by performing a phase-OR operation on CLK and CLK after a period of delay, namely CLK_DEL1; DISC1 is generated by performing a phase-OR operation on CLK and CLK after two periods of delay, namely CLK_DEL2; S2 is generated by performing a phase-OR operation on ICLK and ICLK after a period of delay, namely ICLK_DEL1; DISC2 is generated by performing a phase-OR operation on ICLK and ICLK after two periods of delay, namely ICLK_DEL2.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The present invention samples the peak voltage of capacitor charging through a peak sampling circuit, provides a dynamic reference voltage to the comparator through a dynamic reference voltage generation circuit, and utilizes a negative feedback mechanism to clamp the peak voltage of capacitor charging to a set reference voltage to eliminate the influence of comparator delay on the oscillator frequency. It does not need to increase power consumption to reduce the delay time of the comparator. Compared with other current methods for eliminating comparator delay, the present invention only requires one comparator, thereby achieving the purpose of optimizing circuit area and reducing comparator power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is the schematic diagram of the traditional relaxation oscillator circuit;

[0021] Figure 2 A schematic diagram of a relaxation oscillator circuit for comparator delay elimination according to the present invention;

[0022] Figure 3 The schematic diagram of the timing signal generating circuit of the present invention;

[0023] Figure 4 Schematic diagram of the timing signal waveform of the present invention;

[0024] Figure 5 This is a diagram showing the capacitor charging peak clamping effect of the present invention. DETAILED DESCRIPTION

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0026] like Figure 2 As shown, a relaxation oscillator with comparator delay elimination includes:

[0027] A reference generating circuit divides the power supply VDD to generate a reference voltage;

[0028] The capacitor charging and discharging circuit is charged through a resistor connected to the power supply VDD and discharged through a switch connected to the common ground VSS;

[0029] A peak sampling circuit is connected to the capacitor charging and discharging circuit to collect the peak voltage when the capacitor is charging;

[0030] A dynamic reference voltage generating circuit, used for providing a dynamic reference voltage to the comparator;

[0031] The clock generation circuit is used to provide clock drive for switches in the capacitor charging and discharging circuit and the peak sampling circuit. In this embodiment, the reference generation circuit includes resistors RO1 and RO2 connected in series, which divide the power supply VDD to generate a reference voltage VREF; the capacitor charging and discharging circuit includes a charging circuit, a first discharge circuit, and a second discharge circuit.

[0032] In this embodiment, the charging circuit includes a negative temperature coefficient resistor Rpoly, a positive temperature coefficient resistor Rdif, and switches SW1 and SW3. The first discharge circuit includes a switch SW2 and a variable capacitor CO1, and the discharge of CO1 is controlled by a signal DISC1. The second discharge circuit includes a switch SW4 and a variable capacitor CO2, and the discharge of CO2 is controlled by a signal DISC2. The power supply VDD charges the capacitors through the series connection Rpoly and Rdif, and the capacitor voltage is VCAP. The charging of CO1 and CO2 is controlled by switches SW1 and SW3.

[0033] In this embodiment, the peak sampling circuit includes switches SW5, SW6 and capacitor CO3. One end of the switch SW5 is connected to the first discharge circuit, and the other end is connected to the capacitor CO3. One end of the switch SW6 is connected to the second discharge circuit, and the other end is connected to the capacitor CO3. The sampling clock signals of the peak sampling circuit are S1 and S2, and the sampled output voltage is VPEAK.

[0034] In this embodiment, the dynamic reference voltage generating circuit includes an amplifier OTA and a capacitor CO4. The reference voltage VREF is connected to the positive terminal of the amplifier OTA, and the sampled output voltage VPEAK is connected to the negative terminal of the OTA. The amplifier OTA amplifies the difference between VREF and VPEAK to generate a dynamic reference voltage D_VPEAK.

[0035] In this embodiment, the clock generation circuit includes a divide-by-two frequency circuit composed of a comparator COMP, a Schmitt trigger, an inverter, and a D flip-flop, and a timing signal generation circuit composed of a gate circuit such as an inverter;

[0036] VCAP is connected to the same-direction end of COMP, and D_VPEAK is connected to the reverse end of COMP. COMP compares VCAP and D_VPEAK to generate a clock. After being shaped by the Schmitt trigger, inverter, and D flip-flop, CLKIN is generated to drive the timing signal generation circuit. The timing signal generation circuit then performs logical operations to generate CLK, ICLK, S1, S2, DISC1, and DISC2 signals.

[0037] The above timing signals CLK, ICLK, S1, S2, DISC1, and DISC2 are generated by the timing generation circuit, and its schematic diagram is as follows: Figure 3 As shown, CLK and ICLK are generated by CLKIN through non-overlapping clocks, which can prevent SW1 and SW3 from being turned on at the same time. S1 is generated by the phase-OR operation of CLK and CLK after a period of delay, namely CLK_DEL1. The delay time of CLK determines the sampling time of the peak sampling circuit. DISC1 is generated by the phase-OR operation of CLK and CLK after two periods of delay, namely CLK_DEL2. S2 is generated by the phase-OR operation of ICLK and ICLK after a period of delay, namely ICLK_DEL1. The delay time of ICLK also determines the sampling time of the peak sampling circuit. DISC2 is generated by the phase-OR operation of ICLK and ICLK after two periods of delay, namely ICLK_DEL2. The final waveform diagram is shown as follows: Figure 4 shown.

[0038] The working principle of this embodiment is as follows:

[0039] Resistors RO1 and RO2 connected in series divide the power supply VDD to generate a reference voltage VREF.

[0040] When the circuit is not enabled, switches SW7 and SW8 are closed, the dynamic reference voltage D_VPEAK and the sampled output voltage VPEAK are initialized to VREF, the comparator COMP output is clamped to "0", CLKIN and CLK are reset to "0", and the charging circuit charges the variable capacitor CO2 to "1" through SW3.

[0041] After the circuit is enabled, switches SW7 and SW8 are disconnected, the comparator output will instantly jump to "1", and CLKIN will instantly jump to "1".

[0042] When CLK jumps to "1", DISC1 jumps to "0", and the charging circuit charges variable capacitor CO1 through SW1. The comparator output instantly jumps to "0". Due to the divide-by-two circuit composed of the D flip-flop, CLKIN remains "1". When ICLK jumps to "0", SW3 turns off, and CO2 stops charging. When S2 jumps to "1", the sampling circuit samples the CO2 voltage.

[0043] After a period of time, S2 jumps to "0", the sampling circuit stops sampling the CO2 voltage, and the OTA adjusts the dynamic reference voltage D_VREF. If the collected voltage is greater than VREF, D_VREF will decrease. The next time the capacitor voltage VCAP only needs to reach the reduced D_VREF comparator to achieve a flip, thereby increasing the circuit's oscillation frequency, otherwise the oscillation frequency will be reduced.

[0044] After a period of time, DISC2 jumps to "1", the switch SW4 is turned on, and CO2 is discharged until it is discharged to VSS.

[0045] When CO1 is charged to the first adjusted D_VREF, the comparator output will instantly jump to "1" and CLKIN will instantly jump to "0".

[0046] When CLK jumps to "0", DISC2 jumps to "0", and the charging circuit charges CO2 through SW3. The comparator output will instantly jump to "0". Due to the divide-by-two circuit composed of the D flip-flop, CLKIN remains "0". When CLK is "0", SW1 is turned off, and CO1 stops charging. When S1 jumps to "1", the sampling circuit samples the CO1 voltage.

[0047] After a period of time, S1 jumps to "0", the sampling circuit stops sampling the CO2 voltage, and the OTA adjusts the dynamic reference voltage D_VREF for the second time.

[0048] After a period of time, DISC1 jumps to "1", the switch SW2 is turned on, and CO1 is discharged until it is discharged to VSS.

[0049] CO1 and CO2 charge and discharge repeatedly to keep the circuit working properly.

[0050] The peak clamping effect of the capacitor charging in the circuit is as follows: Figure 5 As shown, the OTA repeatedly adjusts the dynamic reference voltage D_VREF according to the output voltage of the sampling circuit, so that the output voltage of the sampling circuit is equal to the reference voltage VREF, and finally the charging peak voltage of the capacitor is clamped at VREF.

[0051] The expression for the time t required for the capacitor to charge to VREF can be obtained by the three-element method:

[0052]

[0053] Simplified, we get:

[0054]

[0055] Where Req is the equivalent resistance of the negative temperature coefficient resistor Rpoly and the positive temperature coefficient resistor Rdif in the capacitor charging branch.

[0056] Because VREF is generated by dividing the power supply VDD by the series resistors RO1 and RO2, if RO1 / (RO1+RO2)=N, then t can be rewritten as:

[0057]

[0058] From the expression, we can see that the time t required to charge the capacitor has nothing to do with VDD.

[0059] Therefore, the oscillation period T of the oscillator is:

[0060]

[0061] It can be seen that the oscillator's oscillation period is independent of the comparator's delay time, but is only related to the resistance ratio of RO1 and RO2, the resistors Rdif and Rpoly in the capacitor charging branch, and the size of the variable capacitors CO1 and CO2. The negative temperature coefficient resistor Rpoly and the positive temperature coefficient resistor Rdif can be weighted and added together to offset the temperature drift of the capacitor, ultimately achieving temperature compensation for the oscillator's output frequency. The oscillator's oscillation frequency can also be adjusted by adjusting the size of the variable capacitors CO1 and CO2, thus correcting process deviations.

[0062] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A relaxation oscillator with comparator delay cancellation, characterized in that: include: A reference generating circuit for dividing the power supply VDD to generate a reference voltage; a capacitor charging and discharging circuit connected to the reference generating circuit, and charging and discharging the capacitor by the current output by the reference generating circuit; A peak sampling circuit is connected to the capacitor charging and discharging circuit to sample the peak voltage of the capacitor charging; A dynamic reference voltage generating circuit, used for providing a dynamic reference voltage to the comparator; and a clock generation circuit for clamping the peak voltage of the capacitor charge to a set reference voltage using a negative feedback mechanism based on the generated dynamic reference voltage, so as to eliminate the influence of the comparator delay on the oscillator frequency; The reference generation circuit includes resistors RO1 and RO2 connected in series, which divide the power supply VDD to generate a reference voltage VREF; the capacitor charging and discharging circuit includes a charging circuit, a first discharging circuit and a second discharging circuit; the charging circuit includes a negative temperature coefficient resistor Rpoly, a positive temperature coefficient resistor Rdif, switches SW1 and SW3; the first discharging circuit includes a switch SW2 and a variable capacitor CO1, and the discharge of CO1 is controlled by a signal DISC1; the second discharging circuit includes a switch SW4 and a variable capacitor CO2, and the discharge of CO2 is controlled by a signal DISC2. The power supply VDD charges the capacitor through the series Rpoly and Rdif, and the capacitor voltage is VCAP. The SW1 and SW3 are respectively used to CO1 and CO2 are charged; the peak sampling circuit includes switches SW5, SW6 and capacitor CO3, one end of the switch SW5 is connected to the first discharge circuit, and the other end is connected to the capacitor CO3; one end of the switch SW6 is connected to the second discharge circuit, and the other end is connected to the capacitor CO3; the sampling clock signals of the peak sampling circuit are S1 and S2, and the sampling output voltage is VPEAK; the dynamic reference voltage generation circuit includes an amplifier OTA and a capacitor CO4, the reference voltage VREF is connected to the same-direction terminal of the amplifier OTA, and the sampling output voltage VPEAK is connected to the reverse terminal of OTA, and the amplifier OTA amplifies the difference between VREF and VPEAK to generate a dynamic reference voltage D_VPEAK.

2. The relaxation oscillator with comparator delay elimination according to claim 1, wherein: The clock generating circuit includes a frequency divider circuit composed of a comparator COMP, a Schmitt trigger, an inverter, and a D flip-flop, and a timing circuit TIMING composed of an inverter, a NAND gate, and a NOR gate; VCAP is connected to the same-direction end of COMP, and D_VPEAK is connected to the reverse end of COMP. COMP compares VCAP and D_VPEAK to generate a clock. After being shaped by the Schmitt trigger, inverter, and D flip-flop, CLKIN is generated to drive the TIMING circuit. The logical operation of the TIMING circuit generates CLK, ICLK, S1, S2, DISC1, and DISC2 signals.

3. The relaxation oscillator with comparator delay elimination according to claim 2, wherein: The CLK and ICLK are generated by CLKIN through non-overlapping clocks, S1 is generated by the phase OR operation of CLK and CLK after a period of delay, namely CLK_DEL1; DISC1 is generated by the phase OR operation of CLK and CLK after two periods of delay, namely CLK_DEL2; S2 is generated by the phase OR operation of ICLK and ICLK after a period of delay, namely ICLK_DEL1; DISC2 is generated by the phase OR operation of ICLK and ICLK after two periods of delay, namely ICLK_DEL2.

Images