Array substrate, display panel, alignment film printing plate and alignment film printing device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel, an alignment film printing plate and an alignment film printing device, and relate to the technical field of display, and are used for improving the display quality of the display panel. The array substrate comprises a substrate, a pixel circuit layer, a common voltage connecting part and a first alignment film; wherein the pixel circuit layer comprises a pixel circuit and a first signal line connected with the pixel circuit; a first via hole is arranged in the pixel circuit layer, the first via hole is located in a peripheral area, and the first signal line passes through the first via hole; the common voltage connecting part is arranged on a side of the pixel circuit layer away from the substrate, and is arranged in a frame glue area; the first alignment film is arranged on a side of the pixel circuit layer away from the substrate; the first alignment film is located in a display area, a peripheral area and a frame glue area, the first alignment film covers the first signal line in the first via hole, and covers the common voltage connecting part; the thickness of the first alignment film located in the frame glue area is less than the thickness of the first alignment film located in the display area. The display panel is used for displaying an image.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, an alignment film printing plate, and an alignment film printing apparatus. Background Technology

[0002] Liquid crystal display (LCD) panels are increasingly widely used due to their advantages such as low power consumption, miniaturization, and thinness. Therefore, improving the display quality of LCD panels is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] The purpose of this disclosure is to provide an array substrate, a display panel, an alignment film printing plate, and an alignment film printing apparatus for improving the display quality of the display panel.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, an array substrate is provided. The array substrate includes a substrate, a pixel circuit layer, a common voltage connection portion, and a first alignment film. The array substrate includes a display area, a peripheral area, and a frame adhesive area, with the peripheral area surrounding the display area and the frame adhesive area surrounding the peripheral area. The pixel circuit layer is disposed on one side of the substrate; the pixel circuit layer includes a pixel circuit and a first signal line connected to the pixel circuit; a first via is provided in the pixel circuit layer, the first via is located in the peripheral area, and the first signal line passes through the first via; the common voltage connection portion is disposed on the side of the pixel circuit layer away from the substrate and in the frame adhesive area; the common voltage connection portion is used to transmit a common voltage signal; the first alignment film is disposed on the side of the pixel circuit layer away from the substrate; the first alignment film is located in the display area, the peripheral area, and the frame adhesive area, and covers the first signal line in the first via and the common voltage connection portion; the thickness of the first alignment film located in the frame adhesive area is less than the thickness of the first alignment film located in the display area.

[0006] The display panel used in the array substrate also includes a color filter substrate opposite to the array substrate, on which a common electrode layer is disposed; the display panel also includes a frame adhesive and a conductive structure disposed in the frame adhesive, one end of the conductive structure is connected to a common voltage connection portion on the array substrate, and the other end passes through the frame adhesive and is connected to the common electrode layer on the color filter substrate, so that the array substrate can transmit a common voltage to the common electrode layer.

[0007] In the aforementioned array substrate, the first alignment film is disposed in the display area, the peripheral area, and the frame adhesive area. Since the first alignment film covers the first signal line in the first via and the edge of the first alignment film is located in the frame adhesive area, and the edge of the first alignment film is far from the first via, the water vapor and impurity ions adsorbed by the first alignment film will not enter the first via and react with the more active metal in the first signal line to form a galvanic cell reaction (especially when the first signal line is used to transmit low-voltage signals). Consequently, the more active metal in the first signal line will not lose electrons and be oxidized, thus avoiding adverse phenomena such as open circuits in the first signal line.

[0008] To cover the first signal line in the first via in the peripheral area, the first alignment film may extend from the peripheral area to the frame adhesive area. Since the thickness of the first alignment film in the frame adhesive area is less than that in the display area (i.e., the thickness of the first alignment film in the frame adhesive area is smaller), this avoids the problem of poor electrical connection reliability between the conductive structure and the common voltage connection portion caused by the first alignment film existing in the frame adhesive area and covering the common voltage connection portion. In this embodiment, the thickness of the first alignment film in the frame adhesive area is small. The smaller the thickness of the first alignment film, the stronger its conductivity. Therefore, the electrical connection reliability between the common voltage connection portion and the conductive structure in the array substrate is improved, thereby increasing the yield of the array substrate.

[0009] In some embodiments, the common voltage connection includes a plurality of connection sub-parts with gaps between them; the first alignment film covers the plurality of connection sub-parts and the gap region between them.

[0010] In some embodiments, the thickness of the first alignment film covering the plurality of connector sub-parts is less than the thickness of the first alignment film covering the gap region between the plurality of connector sub-parts.

[0011] In some embodiments, in the frame adhesive area, the surface of the pixel circuit layer away from the substrate is provided with a plurality of protrusions; the plurality of connecting sub-parts are located on the side of the plurality of protrusions away from the substrate, and the gap region between the plurality of connecting sub-parts corresponds to the gap region between the plurality of protrusions.

[0012] In some embodiments, the pixel circuit layer includes at least one metal layer and at least one inorganic insulating layer alternately stacked; in the thickness direction of the substrate, the thickness of at least one metal layer corresponding to the region of the plurality of protrusions is greater than the thickness of the metal layer in the display area; and / or, in the thickness direction of the substrate, the thickness of at least one inorganic insulating layer corresponding to the region of the plurality of protrusions is greater than the thickness of the inorganic insulating layer in the display area.

[0013] In some embodiments, the method further includes: an organic insulating layer disposed between the pixel circuit layer and the first alignment film; the organic insulating layer is located in the display area, the peripheral area and the frame adhesive area; in the frame adhesive area, the surface of the organic insulating layer away from the substrate is provided with a plurality of grooves, the plurality of connecting sub-parts are located around the plurality of grooves, and the gap regions between the plurality of connecting sub-parts correspond to the plurality of grooves.

[0014] In some embodiments, the connecting sub-parts are elongated and the plurality of connecting sub-parts are arranged at intervals along a preset direction, the preset direction being a direction parallel to the substrate; or, the plurality of connecting sub-parts are arranged in multiple rows and columns; or, the plurality of connecting sub-parts are arranged in a grid pattern with mutual intersection.

[0015] In some embodiments, the thickness of the first alignment film located in the display area is equal to the thickness of the first alignment film located in the peripheral area.

[0016] In some embodiments, the first signal line is used to transmit a frame start pulse signal or a clock signal.

[0017] On the other hand, a display panel is provided. The display panel includes: an array substrate, a color filter substrate, a liquid crystal layer, and a frame adhesive as described in any of the above embodiments. The color filter substrate and the array substrate are disposed opposite to each other; the color filter substrate includes a common electrode layer; the liquid crystal layer is disposed between the color filter substrate and the array substrate; the frame adhesive connects the array substrate and the color filter substrate and surrounds the liquid crystal layer; the frame adhesive has a conductive structure, one end of which is connected to a common voltage connection portion in the array substrate, and the other end of which is connected to the common electrode layer.

[0018] The above-described display panel has the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here.

[0019] On the other hand, an alignment film printing plate is provided. The alignment film printing plate includes a base layer and a pattern layer stacked together, wherein the surface of the pattern layer away from the base layer is provided with a plurality of protrusions; the alignment film printing plate includes a first region and a second region surrounding the first region; the percentage of the total area of ​​the bottom of the protrusions in the second region to the total area of ​​the second region is greater than the percentage of the total area of ​​the bottom of the protrusions in the first region to the total area of ​​the first region.

[0020] On the other hand, an alignment film printing apparatus is provided. The alignment film printing apparatus includes: an alignment film printing plate as described in the above embodiments, and a printing roller, the alignment film printing plate being disposed on the printing roller. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0023] Figure 2 This is a structural diagram of a display device according to some embodiments;

[0024] Figure 3 This is a structural diagram of a display panel according to some embodiments;

[0025] Figure 4 This is a structural diagram of an array substrate according to some embodiments;

[0026] Figure 5 This is a structural diagram of another display panel provided according to some embodiments;

[0027] Figure 6 This is a structural diagram of another display panel provided according to some embodiments;

[0028] Figure 7 This is a structural diagram of a common voltage connection according to some embodiments;

[0029] Figure 8 This is a structural diagram of another common voltage connection provided according to some embodiments;

[0030] Figure 9 This is a structural diagram of another common voltage connection provided according to some embodiments;

[0031] Figure 10 This is a structural diagram of another array substrate provided according to some embodiments;

[0032] Figure 11 This is a structural diagram of another array substrate provided according to some embodiments;

[0033] Figure 12 This is a structural diagram of another array substrate provided according to some embodiments;

[0034] Figure 13 This is a structural diagram of another array substrate provided according to some embodiments;

[0035] Figure 14 This is a structural diagram of an alignment film printing plate provided according to some embodiments;

[0036] Figure 15 This is a structural diagram of an alignment film printing plate provided according to some embodiments;

[0037] Figure 16 This is a structural diagram of an alignment film printing plate and an array substrate according to some embodiments;

[0038] Figure 17 This is a structural diagram of the protrusion in the first region of an alignment film printing plate according to some embodiments;

[0039] Figure 18 This is a structural diagram of the protrusion in the second region of an alignment film printing plate according to some embodiments;

[0040] Figure 19 This is a structural diagram of a motherboard for an array substrate according to some embodiments;

[0041] Figure 20 This is a structural diagram of an alignment film printing apparatus according to some embodiments;

[0042] Figure 21 This is a flowchart of a method for fabricating an array substrate according to some embodiments. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0046] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0047] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0048] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0049] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0050] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0051] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0052] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0053] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0054] like Figure 1 As shown, embodiments of this disclosure provide a display device 1000, which is a product with image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0055] For example, the display device 1000 can be any product or component with display functionality, such as a television, laptop, tablet, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, camera view display (e.g., a rearview camera display in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, or flight display. Figure 1 As shown, the display device 1000 can be a mobile phone.

[0056] From the perspective of the light emission type of the display device 1000, the display device 1000 can be a thin-film transistor liquid crystal display (TFT-LCD) device. From the perspective of the form of the display device 1000, the display device 1000 can be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. The embodiments of this disclosure do not specifically limit this. The following uses a rectangular and flat display device 1000 as an example to illustrate some embodiments of this disclosure, but the implementation of this disclosure is not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0057] refer to Figure 2 The display device 1000 includes a display panel 1001 and a circuit board PCB. The display panel 1001 includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA is the area on the display panel 1001 used to display images. The peripheral area BB can be used to house a first signal line L1. The first signal line L1 can be used to transmit low-voltage signals, such as clock signals, frame start pulse signals, etc., and can also be used to transmit other signals. The circuit board PCB can be located on one side of the peripheral area BB and is connected to the first signal line L1. The circuit board PCB transmits the signals required by the display panel 1001 to the display area AA through the first signal line L1.

[0058] The structure of the display panel 1001 will be described in detail below.

[0059] refer to Figure 3 The display panel 1001 includes an array substrate 1, a color filter substrate 2, a liquid crystal layer 3, and a frame adhesive J. The color filter substrate 2 is disposed opposite to the array substrate 1, and the liquid crystal layer 3 is disposed between the color filter substrate 2 and the array substrate 1; the frame adhesive J connects the array substrate 1 and the color filter substrate 2 and surrounds the liquid crystal layer 3.

[0060] Among them, in conjunction with reference Figure 3 and Figure 4 The array substrate 1 includes a display area AA, a peripheral area BB, and a frame adhesive area CC. The peripheral area BB surrounds the display area AA, and the frame adhesive area CC surrounds the peripheral area BB.

[0061] refer to Figure 3 The array substrate 1 includes a substrate 100, a pixel circuit layer 120, a pixel electrode layer 130, and a first alignment film M1.

[0062] The structure of substrate 100 can be varied, and the specific configuration can be selected according to actual needs. The substrate can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a polymethyl methacrylate (PMMA) substrate. Alternatively, the substrate can be a flexible substrate. For example, the flexible substrate can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0063] A pixel circuit layer 120 is disposed on one side of the substrate 100. The pixel circuit layer 120 includes multiple conductive layers and multiple insulating layers located between adjacent conductive layers. The multiple conductive layers are configured to form a pixel circuit L2 and multiple signal lines for driving the pixel circuit L2. The multiple signal lines may be a first signal line L1. The multiple conductive layers may include, for example, a semiconductor layer ACT, a gate conductive layer GT, and a source / drain conductive layer SD sequentially disposed along a direction perpendicular to and away from the substrate 100. Of course, the pixel circuit layer 120 may also include other conductive layers, such as a second source / drain conductive layer, which is not specifically limited here.

[0064] The aforementioned conductive layers form multiple thin-film transistors (TFTs). Each TFT may include a semiconductor pattern 101 located in the semiconductor layer ACT, a gate electrode 102 located in the gate conductive layer GT, and a source electrode 103 and a drain electrode 104 located in the source-drain conductive layer SD. The multiple TFTs are interconnected to form a pixel circuit L2, which is connected to a first signal line L1. A first via g is also provided in the pixel circuit layer 120, located in the peripheral region BB, through which the first signal line L1 passes. Thus, the circuit board PCB can transmit a driving signal to the pixel circuit L2 via the first signal line L1.

[0065] The aforementioned insulating layers may include, for example, a gate insulating layer GI located between the semiconductor layer ACT and the gate conductive layer GT, an interlayer dielectric layer ILD located between the gate conductive layer GT and the source / drain conductive layer SD, and a passivation layer PVX located between the source / drain conductive layer SD and the pixel electrode layer 130. Of course, the pixel circuit layer 120 may also include other insulating film layers, which will not be described in detail here.

[0066] A pixel electrode layer 130 is disposed on the side of the pixel circuit layer 120 away from the substrate 100. The pixel electrode layer 130 includes a plurality of first electrodes 131 disposed in the display area AA and a common voltage connection portion Q disposed in the frame adhesive area CC. The first electrodes 131 are connected to the pixel circuit L2. After the circuit board PCB transmits a driving signal to the pixel circuit L2 through the first signal line L1, the pixel circuit L2 can provide a pixel voltage to the first electrodes 131. In some embodiments, the plurality of first electrodes 131 and the common voltage connection portion Q can be fabricated in the same layer and with the same material. Among the plurality of first electrodes 131, one first electrode 131 corresponds to one sub-pixel.

[0067] The first alignment film M1 is disposed on the side of the pixel circuit layer 120 away from the substrate 100; the first alignment film M1 is located in the display area AA. (Reference) Figure 3 The color filter substrate 2 includes a substrate 200, a color filter layer 201, a common electrode layer 202, and a second alignment film M2, which are stacked sequentially. A conductive structure D is provided in the sealant J. One end of the conductive structure D is connected to a common voltage connection portion Q in the array substrate 1, and the other end of the conductive structure D is connected to the common electrode layer 202. The conductive structure D is used to conduct electricity between the array substrate 1 and the color filter substrate 2, thereby forming a driving electric field for the liquid crystal layer 3 in the display panel 1001.

[0068] The circuit board (PCB) is also connected to a common voltage connection part Q. The PCB can transmit a common voltage signal to the common voltage connection part Q, which transmits the common voltage signal to the common electrode layer 202 of the color filter substrate 2 through the conductive structure D. In this way, the voltage difference generated between the common electrode layer 202 and the first electrode 131 can drive the liquid crystal molecules to deflect and achieve grayscale adjustment.

[0069] In some embodiments, the conductive structure D may be made of gold spheres, or other materials that can conduct electricity.

[0070] In some embodiments, the frame adhesive J includes not only the conductive structure D, but also supporting silicon or plastic balls.

[0071] The first alignment film M1 and the second alignment film M2 are configured to impart orientation to the liquid crystal in the liquid crystal layer 3, enabling the liquid crystal to align in the same direction, form a pretilt angle, and return to its initial state after the electric field disappears. Therefore, an alignment film needs to be provided in the display area AA of the display panel 1001, in conjunction with a reference. Figure 3 and Figure 4 When the first alignment film M1 is disposed in the display area AA of the array substrate 1, the first alignment film M1 will also expand outward to part of the peripheral area BB due to the fluidity of the alignment liquid, covering part of the first via g in the peripheral area BB.

[0072] Since the first alignment film M1 and the second alignment film M2 have the ability to adsorb water vapor and impurity ions, especially in the array substrate 1, it can be referred to Figure 4 Water vapor and impurity ions adsorbed at the edge of the first alignment film M1 can easily enter the first via g. When the first signal line L1 is a low-voltage signal line, the more active metal in the low-voltage signal line is in a low-voltage state and is prone to undergo a galvanic cell reaction with water vapor and impurity ions, causing the more active metal in the low-voltage signal line to lose electrons and be oxidized. This leads to open circuits and other defects in the first signal line L1 in the array substrate 1, resulting in display abnormalities in the display panel 1001.

[0073] Therefore, refer to Figure 4 The first via g in the peripheral area BB can be covered to prevent the first alignment film M1 from adsorbing moisture and impurity ions and entering the first via g. However, covering the first via g in the peripheral area BB, especially for the display panel 1001 with a narrow bezel, will cause the first alignment film M1 to expand from the peripheral area BB to the frame adhesive area CC. This results in the first alignment film M1 in the frame adhesive area CC being too thick. Since the first alignment film M1 is an insulating material, the electrical connection reliability between the common voltage connection part Q in the frame adhesive area CC and the conductive structure D in the frame adhesive J is reduced. This, in turn, reduces the electrical connection reliability between the common voltage connection part Q and the color filter substrate 2, causing display abnormalities and crosstalk in the display panel 1001.

[0074] To address the aforementioned technical problems, this embodiment provides an array substrate 1, with reference to... Figure 5 The first alignment film M1 is located in the display area AA, the peripheral area BB and the frame adhesive area CC. The orthographic projection of the first alignment film M1 on the substrate 100 covers the orthographic projection of the first via g on the substrate 100. The thickness of the first alignment film M1 located in the frame adhesive area CC is less than the thickness of the first alignment film M1 located in the display area AA.

[0075] In this embodiment, the array substrate 1 has a first alignment film M1 disposed in the display area AA, the peripheral area BB, and the frame adhesive area CC. Since the first alignment film M1 covers the first signal line L1 in the first via g, and the edge of the first alignment film M1 is located in the frame adhesive area CC, the edge of the first alignment film M1 is far from the first via g. Therefore, the water vapor and impurity ions adsorbed by the first alignment film M1 will not enter the first via g and react with the more active metal in the first signal line L1 to form a galvanic cell reaction (especially when the first signal line L1 is used to transmit low-voltage signals). As a result, the more active metal in the first signal line L1 will not lose electrons and be oxidized, thus avoiding the adverse phenomena such as open circuit in the first signal line L1.

[0076] To cover the first signal line L1 in the first via g in the peripheral area BB, the first alignment film M1 may extend from the peripheral area BB to the frame adhesive area CC. Since the thickness of the first alignment film M1 in the frame adhesive area CC is less than the thickness of the first alignment film M1 in the display area AA, that is, the thickness of the first alignment film M1 in the frame adhesive area CC is smaller, this avoids the problem of poor electrical connection reliability between the conductive structure D and the common voltage connection portion Q caused by the first alignment film M1 existing in the frame adhesive area CC and covering the common voltage connection portion Q. In this embodiment, the thickness of the first alignment film M1 in the frame adhesive area CC is small. The smaller the thickness of the first alignment film M1, the stronger its conductivity. Therefore, the electrical connection reliability between the common voltage connection portion Q and the conductive structure D in the array substrate 1 is improved, thereby improving the yield of the array substrate 1.

[0077] In some embodiments, reference Figure 7 The common voltage connection part Q includes multiple connection sub-parts q, and there is a gap V between the multiple connection sub-parts q.

[0078] For example, the connecting sub-parts q are elongated, and multiple connecting sub-parts q are arranged at intervals along a preset direction, which is parallel to the substrate 100; or, multiple connecting sub-parts q are arranged in multiple rows and columns; or, multiple connecting sub-parts q are arranged in a grid pattern with each other intersecting.

[0079] For example, refer to Figure 7 The connecting sub-parts q are elongated, and multiple connecting sub-parts q are arranged at intervals along a preset direction, which is parallel to the substrate 100. In the frame adhesive area CC, the multiple connecting sub-parts q can be evenly spaced, which also helps to improve the stability and uniformity of signal transmission between the common voltage connection part Q of the array substrate 1 and the color filter substrate 2.

[0080] For example, refer to Figure 8 Multiple connection sub-parts q are arranged in multiple rows and columns. The multiple connection sub-parts q can be evenly distributed on the side of the pixel circuit layer 120 away from the substrate 100, which helps to improve the stability and uniformity of signal transmission between the common voltage connection part Q of the array substrate 1 and the color filter substrate 2.

[0081] For example, refer to Figure 9 Multiple connecting sub-parts q are arranged in a grid pattern, which increases the electrical connection area between the common voltage connecting part Q and the color filter substrate 2, thereby improving the reliability of the electrical connection between the array substrate 1 and the color filter substrate 2.

[0082] In some embodiments, reference Figure 10The first alignment film M1 covers multiple connecting sub-parts q and the gap regions between them. The common voltage connection Q includes multiple connecting sub-parts q, ensuring a conductive point between the common voltage connection Q and the color filter substrate 2 at each location in the frame adhesive area CC. A gap V exists between the multiple connecting sub-parts q. This arrangement is designed so that, due to the fluidity of the alignment liquid during the formation of the first alignment film M1, the liquid flows from the surface of the connecting sub-parts q to the gap V between them. This results in the thickness of the first alignment film M1 covering the multiple connecting sub-parts q being less than the thickness of the first alignment film M1 covering the gap regions between them. In some cases, the alignment liquid may even flow entirely to the gap V between the connecting sub-parts q, meaning the surface of the connecting sub-parts q may not have the first alignment film M1. This improves the electrical connection reliability between the common voltage connection Q of the array substrate 1 and the color filter substrate 2.

[0083] In some embodiments, continue to refer to Figure 10 The thickness of the first alignment film M1 covering the multiple connecting sub-parts q is less than the thickness of the first alignment film M1 covering the gap region between the multiple connecting sub-parts q. That is, the thickness of the first alignment film M1 between the multiple connecting sub-parts q and the conductive structure D in the frame adhesive J is thin, which improves the electrical connection reliability between the common voltage connection part Q of the array substrate 1 and the color filter substrate 2.

[0084] In some embodiments, reference Figure 11 In the frame adhesive area CC, the pixel circuit layer 120 has multiple protrusions T on its surface away from the substrate 100; multiple connecting sub-parts q are located on the side of the multiple protrusions T away from the substrate 100, and the gap area between the multiple connecting sub-parts q corresponds to the gap area between the multiple protrusions T. With this configuration, since the alignment liquid is fluid during the formation of the first alignment film M1, and because the area around the protrusions T is concave, there is a height difference between the surface of the protrusions T and the area around the protrusions T, the alignment liquid flows from the surface of the protrusions T to the concave area around the protrusions T. Furthermore, since the multiple connecting sub-parts q are located on the side of the multiple protrusions T away from the substrate 100, the thickness of the first alignment film M1 finally formed, covering the multiple connecting sub-parts q, is less than the thickness of the first alignment film M1 covering the gap area between the multiple connecting sub-parts q, further improving the electrical connection reliability between the common voltage connection portion Q of the array substrate 1 and the color filter substrate 2.

[0085] Continue to refer to Figure 11The pixel circuit layer 120 includes at least one metal layer K and at least one inorganic insulating layer w alternately stacked. In the thickness direction of the substrate 100, the thickness of the region corresponding to the plurality of protrusions T of the at least one metal layer K is greater than the thickness of the metal layer K in the display area AA; and / or, in the thickness direction of the substrate 100, the thickness of the region corresponding to the plurality of protrusions T of the at least one inorganic insulating layer w is greater than the thickness of the inorganic insulating layer w in the display area AA. Since the protrusions are formed directly using the metal layer K and the inorganic insulating layer w in the pixel circuit layer 120, it is unnecessary to add an additional film layer for forming the protrusions T, thus simplifying the fabrication process of the array substrate 1.

[0086] For example, refer to Figure 11 In the thickness direction of the substrate 100, the thickness of at least one metal layer K corresponding to the region of multiple protrusions T is greater than the thickness of the metal layer K in the display area AA. The at least one metal layer K can be one or more of the gate conductive layer GT and the source / drain conductive layer SD.

[0087] For example, in the thickness direction of the substrate 100, the thickness of the area of ​​the gate conductive layer GT corresponding to the multiple protrusions T is greater than the thickness of the gate conductive layer GT in the display area AA.

[0088] For example, in the thickness direction of the substrate 100, the thickness of the region corresponding to the multiple protrusions T of the source / drain conductive layer SD is greater than the thickness of the source / drain conductive layer SD in the display area AA.

[0089] For example, in the thickness direction of the substrate 100, the thickness of the regions corresponding to the multiple protrusions T of the source / drain conductive layer SD and the gate conductive layer GT is greater than the thickness of the source / drain conductive layer SD and the gate conductive layer GT in the display area AA.

[0090] Figure 11 The diagram illustrates the process using metal layer K as the source and drain conductive layer SD.

[0091] For example, refer to Figure 12 In the thickness direction of the substrate 100, the thickness of at least one inorganic insulating layer w corresponding to the region of the plurality of protrusions T is greater than the thickness of the inorganic insulating layer w in the display area AA. The at least one inorganic insulating layer w may be one or more of the gate insulating layer GI, the interlayer dielectric layer ILD, and the passivation layer PVX.

[0092] For example, refer to Figure 12 In the thickness direction of the substrate 100, the thickness of the passivation layer PVX corresponding to the region of multiple protrusions T is greater than the thickness of the passivation layer PVX in the display area AA.

[0093] For example, in the thickness direction of the substrate 100, the thickness of the area of ​​the gate insulating layer GI corresponding to the plurality of protrusions T is greater than the thickness of the gate insulating layer GI in the display area AA.

[0094] For example, in the thickness direction of the substrate 100, the thickness of the region corresponding to the multiple protrusions T of the interlayer dielectric layer (ILD) is greater than the thickness of the interlayer dielectric layer (ILD) in the display area AA.

[0095] In some embodiments, reference Figure 13 The array substrate 1 further includes an organic insulating layer ORG, disposed between the pixel circuit layer 120 and the first alignment film M1. Specifically, the organic insulating layer ORG is disposed between the pixel circuit layer 120 and the pixel electrode layer 130. The organic insulating layer ORG is located in the display area AA, the peripheral area BB and the frame adhesive area CC. In the frame adhesive area CC, the surface of the organic insulating layer ORG away from the substrate 100 is provided with a plurality of grooves U, a plurality of connecting sub-parts q are located around the plurality of grooves U, and the gap area between the plurality of connecting sub-parts q corresponds to the plurality of grooves U. With this configuration, since the alignment liquid is fluid during the formation of the first alignment film M1, and since multiple grooves U are provided on the surface of the organic insulating layer ORG away from the substrate 100 in the frame adhesive area CC, the alignment liquid will flow from the surface of the organic insulating layer ORG away from the substrate 100 to the groove U area. Moreover, multiple connecting sub-parts q are located around the multiple grooves U. Therefore, the thickness of the first alignment film M1 that is finally formed, covering the multiple connecting sub-parts q, is less than the thickness of the first alignment film M1 that covers the gap area between the multiple connecting sub-parts q, which further improves the electrical connection reliability between the common voltage connection part Q of the array substrate 1 and the color filter substrate 2.

[0096] Furthermore, since the organic insulating layer ORG is disposed between the pixel circuit layer 120 and the pixel electrode layer 130, the organic insulating layer ORG increases the distance between the pixel electrode layer 130 and the metal layer in the pixel circuit layer 120. For example, it increases the distance between the pixel electrode layer 130 and the source / drain conductive layer SD, or between the pixel electrode layer 130 and the gate conductive layer GT. According to the capacitance formula c = εs / d (where c represents capacitance, d represents the distance between the pixel electrode layer 130 and the metal layer in the pixel circuit layer 120, d represents the overlap area between the pixel electrode layer 130 and the metal layer in the pixel circuit layer 120, and ε represents the dielectric constant of the organic insulating layer ORG), the organic insulating layer ORG reduces the dielectric capacitance between the pixel electrode layer 130 and the metal layer in the pixel circuit layer 120.

[0097] In some embodiments, continue to refer to Figure 6The thickness of the first alignment film M1 located in the display area AA is equal to the thickness of the first alignment film M1 located in the peripheral area BB. This ensures that the thickness of the first alignment film M1 in the display area AA and the peripheral area BB are uniform, preventing uneven brightness display in the display panel 1001 due to fluctuations in the thickness of the first alignment film M1.

[0098] In some embodiments, the first signal line L1 is used to transmit a frame-open pulse signal or a clock signal. In other embodiments, the first signal line L1 also includes other signals for transmitting low voltage.

[0099] Another embodiment of the present invention also provides a display panel 1001, see reference. Figure 6 This includes: the array substrate 1 provided in any of the above embodiments.

[0100] In some embodiments, continue to refer to Figure 6 In the color filter substrate 2, the second alignment film M2 is located in the display area AA, the peripheral area BB, and the frame adhesive area CC. The thickness of the second alignment film M2 located in the frame adhesive area CC is less than the thickness of the second alignment film M2 located in the display area AA. In this way, the second alignment film M2 in the color filter substrate 2 and the first alignment film M1 in the array substrate 1 can be fabricated using the same alignment film printing plate, eliminating the need for an additional alignment film printing plate and thus saving costs.

[0101] The technical solution of the present invention can be widely used in various display panels 1001, such as TN (Twisted Nematic) display panels and VA (Vertical Alignment) display panels, all of which are applicable to the above solution.

[0102] Another embodiment of the present invention also provides an alignment film printing plate (APR), see reference. Figure 14 It includes a base layer Y1 and a pattern layer Y2 stacked together. The surface of the pattern layer Y2 away from the base layer Y1 has multiple protrusions C, and the recessed areas between adjacent protrusions C are used to support the alignment liquid Pi; Reference Figure 15 The alignment film printing plate (APR) includes a first region Q1 and a second region Q2 surrounding the first region Q1. The percentage of the total area of ​​the bottom of the protrusions C in the second region Q2 relative to the total area of ​​the second region Q2 is greater than the percentage of the total area of ​​the bottom of the protrusions C in the first region Q1 relative to the total area of ​​the first region Q1. Thus, per unit area, the alignment liquid carried by the alignment film printing plate APR in the first region Q1 is greater than the alignment liquid carried by the alignment film printing plate APR in the second region Q2. (Reference) Figure 16Since the first region Q1 corresponds to the display region AA and the peripheral region BB in the array substrate 1, and the second region Q2 corresponds to the frame adhesive region CC in the array substrate 1, when the first alignment film M1 is formed on the side of the pixel circuit layer 120 away from the substrate 100, the thickness of the first alignment film M1 formed in the frame adhesive region CC is less than the thickness of the first alignment film M1 located in the display region AA and the peripheral region BB.

[0103] The statement that "the percentage of the total area of ​​the bottom of the protrusion C in the second region Q2 to the total area of ​​the second region Q2 is greater than the percentage of the total area of ​​the bottom of the protrusion C in the first region Q1 to the total area of ​​the first region Q1" can mean that, when the density of the protrusion C in the first region Q1 and the second region Q2 is equal, the size of the protrusion C per unit area in the second region Q2 is greater than the size of the protrusion C per unit area in the first region Q1.

[0104] The statement that "the percentage of the total area of ​​the bottom of the protrusion C in the second region Q2 to the total area of ​​the second region Q2 is greater than the percentage of the total area of ​​the bottom of the protrusion C in the first region Q1 to the total area of ​​the first region Q1" can also be, in conjunction with reference to... Figure 17 and Figure 18 When the protrusions C in the first region Q1 and the second region Q2 are of equal size, the density of the protrusions C in the second region Q2 is greater than the density of the protrusions C in the first region Q1.

[0105] It should be noted that the density of protrusions C refers to the number of protrusions C per unit area of ​​alignment film printing plate (APR).

[0106] For example, the total area of ​​the bottom of the protrusion C in the first region Q1 accounts for 20%, 22%, 23%, or 25% of the total area of ​​the first region Q1. Within this range, the thickness of the first alignment film M1 formed in the display area AA and the peripheral area BB is... For example and The total area of ​​the bottom of the protrusion C in the second region Q2 accounts for 30%, 32%, 33%, or 35% of the total area of ​​the second region Q2. Within this range, the thickness of the first alignment film M1 in the frame region CC is... For example or The thickness of the first alignment film M1 in the frame region CC is less than or equal to Within this range, the reliability of the electrical connection between the common voltage connection part Q and the conductive structure D (gold ball), that is, with the color filter substrate 2, can be improved.

[0107] It should be noted that the size or density of the protrusions C in the first region Q1 and the second region Q2 can be designed according to the required thickness of the first alignment film M1 and the conductivity of the conductive structure D (gold ball). As long as the first alignment film M1 located in the frame region CC can improve the electrical connection reliability between the common voltage connection part Q and the conductive structure D (gold ball) and improve the reliability of the array substrate 1, it is acceptable.

[0108] In some embodiments, continue to refer to Figure 14 The alignment film printing plate APR also includes an adhesive layer Y3, which is disposed between the base layer Y1 and the pattern layer Y2 and is configured to bond the base layer Y1 and the pattern layer Y2 together.

[0109] In some embodiments, continue to refer to Figure 15 The alignment film printing plate APR includes a third region Q3, which surrounds the second region Q2. It should be noted that, as referenced... Figure 19 To improve the fabrication efficiency of the array substrate 1, the array substrate 1 can be formed in an array on a large-area mother plate M. A dicing channel G is provided on the mother plate M between adjacent array substrates 1. Then, the mother plate M, which has formed multiple array substrates 1, is cut along the dicing channel G to form several independent array substrates 1. Therefore, when the first alignment film M1 is formed on the side of the pixel circuit layer 120 away from the substrate 100, the third region Q3 corresponds to the dicing channel G in the mother plate M. The percentage of the total area of ​​the protrusions C in the third region Q3 to the total area of ​​the third region Q3 can be equal to the percentage of the total area of ​​the protrusions C in the first region Q1 to the total area of ​​the first region Q1, or it can be equal to the percentage of the total area of ​​the protrusions C in the second region Q2 to the total area of ​​the second region Q2. The protrusions C in the third region Q3 prevent cracks from forming in the first alignment film M1 due to vibrations in the alignment film printing plate APR during its formation.

[0110] In some embodiments, the area corresponding to the common voltage connection portion Q of the alignment film printing plate APR and the array substrate 1 may not be provided with alignment liquid. In this way, there is no first alignment film M1 between the connection portion q and the conductive structure D, which can improve the electrical connection reliability between the common voltage connection portion Q of the array substrate 1 and the color filter substrate 2.

[0111] Another embodiment of the present invention also provides an alignment film printing apparatus 10, see reference. Figure 20 ,include:

[0112] The alignment film printing plate APR and the printing roller 11 described in the previous embodiment are provided on the printing roller 11.

[0113] Continue to refer to Figure 20The alignment film printing apparatus 10 further includes: a machine base 12, a liquid sprayer 13, a doctor blade 14, and a transfer roller 15. The machine base 12 is used to fix the array substrate 1 to be printed; the liquid sprayer 13 is used to drop alignment liquid onto the transfer roller 15; the doctor blade 14 is used to spread the alignment liquid onto the transfer roller 15; the transfer roller 15 is used to supply alignment liquid to the alignment film printing plate APR when in contact with it; and the printing roller 11 is used to drive the alignment film printing plate APR to roll on the array substrate 1 to be printed.

[0114] The alignment liquid is evenly dripped onto the transfer roller 15 through the sprayer 13. As the transfer roller 15 rotates, the doctor blade 14 scrapes the alignment liquid evenly on the transfer roller 15, thus distributing the alignment liquid evenly on the transfer roller 15. The transfer roller 15 transfers the alignment liquid on the transfer roller 15 to the alignment film printing plate APR set on the printing roller 11 through contact with the printing roller 11 during rotation. During the rotation of the printing roller 11, the alignment liquid stored in the alignment film printing plate APR is transferred to the array substrate 1 to be printed by pressing it. During the printing process, the machine 12 moves the array substrate 1 to be printed.

[0115] Embodiments of the present invention also provide a method for fabricating an array substrate 1, see reference. Figure 21 This includes the following steps:

[0116] Step S1: Reference Figure 6 A pixel circuit layer 120 is formed on the substrate 100. The pixel circuit layer 120 includes a pixel circuit L2 and a first signal line L1 connected to the pixel circuit L2. A first via g is provided in the pixel circuit layer 120. The first via g is located in the peripheral area BB of the array substrate 1, and the first signal line L1 passes through the first via g.

[0117] Step S2: Continue to refer to Figure 6 A common voltage connection portion Q is formed on the side of the pixel circuit layer 120 away from the substrate 100. The common voltage connection portion Q is disposed in the frame adhesive area CC of the array substrate 1 and is used to transmit a common voltage signal. The first electrode 131 is connected to the pixel circuit L2.

[0118] Here, in the step of forming a common voltage connection portion Q on the side of the pixel circuit layer 120 away from the substrate 100, a first electrode 131 is also formed on the side of the pixel circuit layer 120 away from the substrate 100. The first electrode 131 is located in the display area AA of the array substrate 1, and the common voltage connection portion Q and the first electrode 131 form the pixel electrode layer 130.

[0119] Step S3: Continue to refer to Figure 6 Using the alignment film printing apparatus 10 provided in the above embodiments, a first alignment film M1 is formed on the side of the pixel circuit layer 120 away from the substrate 100.

[0120] Here, the first region Q1 of the alignment film printing plate APR in the alignment film printing apparatus 10 corresponds to the display area AA and the peripheral area BB in the array substrate 1, and the second region Q2 of the alignment film printing plate APR in the alignment film printing apparatus 10 corresponds to the frame adhesive area CC in the array substrate 1. Since the volume of alignment liquid carried by the alignment film printing plate APR per unit area in the first region Q1 is greater than the volume of alignment liquid carried by the alignment film printing plate APR per unit area in the second region Q2, when the first alignment film M1 is formed on the side of the pixel circuit layer 120 away from the substrate 100, the thickness of the first alignment film M1 formed in the frame adhesive area CC is less than the thickness of the first alignment film M1 located in the display area AA and the peripheral area BB. This can improve the reliability of the electrical connection between the common voltage connection portion Q of the array substrate 1 and the color filter substrate 2.

[0121] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising a display area, a peripheral area, and a frame adhesive area, wherein the peripheral area surrounds the display area, and the frame adhesive area surrounds the peripheral area, characterized in that, The array substrate includes: Substrate; A pixel circuit layer is disposed on one side of the substrate; the pixel circuit layer includes a pixel circuit and a first signal line connected to the pixel circuit; a first via is provided in the pixel circuit layer, the first via is located in the peripheral area, and the first signal line passes through the first via; A common voltage connection portion is disposed on the side of the pixel circuit layer away from the substrate and in the frame adhesive area; the common voltage connection portion is used to transmit a common voltage signal; A first alignment film is disposed on the side of the pixel circuit layer away from the substrate; the first alignment film is located in the display area, the peripheral area and the frame adhesive area, the first alignment film covers the first signal line in the first via and covers the common voltage connection portion; the thickness of the first alignment film located in the frame adhesive area is less than the thickness of the first alignment film located in the display area; The common voltage connection includes multiple connection sub-parts with gaps between them; the first alignment film covers the multiple connection sub-parts and the gap regions between them. In the frame adhesive area, the pixel circuit layer has a plurality of protrusions on the surface away from the substrate; the plurality of connecting sub-parts are located on the side of the plurality of protrusions away from the substrate, and the gap area between the plurality of connecting sub-parts corresponds to the gap area between the plurality of protrusions.

2. The array substrate according to claim 1, characterized in that, The thickness of the first alignment film covering the plurality of connecting sub-parts is less than the thickness of the first alignment film covering the gap region between the plurality of connecting sub-parts.

3. The array substrate according to claim 1, characterized in that, The pixel circuit layer includes at least one metal layer and at least one inorganic insulating layer that are alternately stacked; In the thickness direction of the substrate, the thickness of at least one of the metal layers corresponding to the regions of the plurality of protrusions is greater than the thickness of the metal layer in the display area; And / or, In the thickness direction of the substrate, the thickness of at least one inorganic insulating layer corresponding to the region of the plurality of protrusions is greater than the thickness of the inorganic insulating layer in the display area.

4. The array substrate according to claim 1 or 2, characterized in that, Also includes: An organic insulating layer is disposed between the pixel circuit layer and the first alignment film; the organic insulating layer is located in the display area, the peripheral area and the frame adhesive area; In the frame adhesive area, the surface of the organic insulating layer away from the substrate is provided with a plurality of grooves, the plurality of connectors are located around the plurality of grooves, and the gap area between the plurality of connectors corresponds to the plurality of grooves.

5. The array substrate according to claim 1 or 2, characterized in that, The connecting sub-parts are elongated strips, and the plurality of connecting sub-parts are arranged at intervals along a preset direction, the preset direction being a direction parallel to the substrate; or, The plurality of connecting sub-parts are arranged in multiple rows and columns; or... The multiple connecting sub-parts are arranged in a grid pattern, intersecting each other.

6. The array substrate according to claim 1 or 2, characterized in that, The thickness of the first alignment film located in the display area is equal to the thickness of the first alignment film located in the peripheral area.

7. The array substrate according to claim 1 or 2, characterized in that, The first signal line is used to transmit a frame start pulse signal or a clock signal.

8. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 7; A color filter substrate is disposed opposite to the array substrate; the color filter substrate includes a common electrode layer. A liquid crystal layer is disposed between the color filter substrate and the array substrate; A frame adhesive connects the array substrate and the color filter substrate and surrounds the liquid crystal layer; the frame adhesive has a conductive structure, one end of which is connected to a common voltage connection portion in the array substrate, and the other end of which is connected to the common electrode layer.

9. An alignment film printing plate for manufacturing an array substrate as described in any one of claims 1 to 7, characterized in that, It includes a base layer and a graphic layer stacked together, wherein the surface of the graphic layer away from the base layer has multiple protrusions; The alignment film printing plate includes a first region and a second region surrounding the first region; the percentage of the total area of ​​the bottom of the protrusions in the second region to the total area of ​​the second region is greater than the percentage of the total area of ​​the bottom of the protrusions in the first region to the total area of ​​the first region. Wherein, the first region corresponds to the display area and the peripheral area of ​​the array substrate, the second region corresponds to the frame adhesive area of ​​the array substrate, and the alignment film printing plate is configured such that the thickness of the first alignment film formed in the frame adhesive area is less than the thickness of the first alignment film formed in the display area and the peripheral area.

10. An alignment film printing apparatus, characterized in that, include: The alignment film printing plate as described in claim 9; A printing roller, on which the alignment film printing plate is disposed.

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