A multi-dimensional simulation VCSEL chip fault point early warning system

Abstract

The present application provides a multi-dimensional simulation VCSEL chip fault point warning system, which relates to the field of semiconductor laser technology, including: a chip structure acquisition module for obtaining chip structure information of a target VCSEL chip; a finite element analysis module for generating a finite element simulation model; a failure mode acquisition module for collecting chip failure modes; a failure simulation module for establishing a failure decision warning device; a multi-dimensional monitoring module for collecting multi-dimensional monitoring data; a failure warning module for performing chip failure mode identification and fault warning decision-making, and outputting warning signals. This application can solve the technical problem in the prior art that it is difficult to effectively distinguish between reversible failure modes and irreversible failure modes, resulting in difficulty in making targeted warning decisions in a timely manner when the chip is working abnormally, so as to achieve accurate recovery of reversible failures, while preventing irreversible damage in advance and ensuring the technical effect of safe chip operation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor laser technology, and in particular to a multi-dimensional simulated VCSEL chip fault point early warning system. Background Art

[0002] With the development of electronic devices, optical communication technology and photonic devices, vertical cavity surface emitting lasers (VCSEL chips) are increasingly used in optical communication, optical interconnection, sensing and 3D imaging. VCSEL has the advantages of high efficiency, low power consumption and array integration, so it has attracted wide attention in application scenarios such as data centers, high-speed network transmission and lidar.

[0003] At present, VCSEL chips often face the challenge of performance degradation or failure under high-frequency and long-term working environments. Especially under harsh working conditions such as high temperature and high current density, the chip is prone to problems such as thermal damage, electrode damage or resonant cavity attenuation. These failure problems will not only affect the stability and working life of VCSEL, but may also cause serious system failures and increase maintenance costs. Although the existing technology has alleviated some failure problems by improving heat dissipation design and optimizing electrode materials, it is still difficult to fully prevent and monitor chip failures in practical applications.

[0004] In particular, most of the current failure monitoring technologies rely on threshold judgments of multi-dimensional parameters, which makes it difficult to effectively distinguish between reversible failure modes and irreversible failure modes, resulting in difficulty in making targeted recovery or shutdown decisions in a timely manner when the chip operates abnormally. Summary of the invention

[0005] The purpose of this application is to provide a multi-dimensional simulated VCSEL chip fault point warning system to solve the technical problem in the prior art that it is difficult to effectively distinguish between reversible failure modes and irreversible failure modes, resulting in difficulty in making targeted warning decisions in a timely manner when the chip is working abnormally.

[0006] In view of the above problems, the present application provides a multi-dimensional simulation VCSEL chip fault point warning system, including: a chip structure acquisition module, used to obtain chip structure information of a target VCSEL chip, wherein the chip structure information includes active layer information, resonant cavity information and electrode information; a finite element analysis module, used to perform finite element modeling based on the active layer information, the resonant cavity information and the electrode information to generate a finite element simulation model; a failure mode acquisition module, used to collect chip failure modes of the target VCSEL chip, wherein the chip failure modes include reversible failure modes and irreversible failure modes; a failure simulation module, used to call the finite element simulation model to perform chip failure simulation for the reversible failure mode and the irreversible failure mode, and establish a failure decision warning device; a multi-dimensional monitoring module, used to deploy micro multi-dimensional sensors for the active layer structure, resonant cavity structure and electrode structure of the target VCSEL chip, and collect multi-dimensional monitoring data; a failure warning module, used to perform chip failure mode identification and fault warning decision on the multi-dimensional monitoring data through the failure decision warning device, and output a warning signal.

[0007] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0008] A chip structure acquisition module is used to acquire chip structure information of a target VCSEL chip, wherein the chip structure information includes active layer information, resonant cavity information and electrode information; a finite element analysis module is used to perform finite element modeling based on the active layer information, the resonant cavity information and the electrode information to generate a finite element simulation model; a failure mode acquisition module is used to acquire chip failure modes of the target VCSEL chip, wherein the chip failure modes include reversible failure modes and irreversible failure modes; a failure simulation module is used to call the finite element simulation model to perform chip failure simulation for the reversible failure mode and the irreversible failure mode, and establish a failure decision early warning device; a multi-dimensional monitoring module is used to deploy micro multi-dimensional sensors for the active layer structure, resonant cavity structure and electrode structure of the target VCSEL chip to collect multi-dimensional monitoring data; a failure early warning module is used to perform chip failure mode identification and fault early warning decision on the multi-dimensional monitoring data through the failure decision early warning device, and output an early warning signal. By obtaining the structural information of the target VCSEL chip and analyzing the reversible and irreversible failure modes based on the finite element simulation model, combined with the real-time monitoring data collected by the multi-dimensional sensor, the failure mode of the chip can be accurately identified, and then the failure decision warning device can be used to issue a real-time fault warning, so as to accurately recover from reversible failures and prevent irreversible damage in advance, thereby ensuring the technical effect of safe chip operation.

[0009] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented according to the contents of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are specifically cited below. It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easy to understand through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0011] Figure 1 This is a schematic diagram of the structure of a multi-dimensional simulated VCSEL chip fault point warning system for this application;

[0012] Figure 2 This is a schematic diagram of the process of generating a failure decision warning device in a multi-dimensional simulation VCSEL chip fault point warning system of the present application.

[0013] Description of reference numerals:

[0014] Chip structure acquisition module 11, finite element analysis module 12, failure mode acquisition module 13, failure simulation module 14, multi-dimensional monitoring module 15, failure warning module 16. DETAILED DESCRIPTION

[0015] This application provides a multi-dimensional simulated VCSEL chip fault point warning system to solve the technical problem in the prior art that it is difficult to effectively distinguish between reversible failure modes and irreversible failure modes, resulting in difficulty in making targeted warning decisions in a timely manner when the chip is working abnormally. By obtaining the structural information of the target VCSEL chip and analyzing the reversible and irreversible failure modes based on the finite element simulation model, combined with the real-time monitoring data collected by the multi-dimensional sensor, the failure mode of the chip can be accurately identified, and then the failure decision warning device can be used to perform real-time fault warning, so as to achieve accurate recovery of reversible failures, and at the same time prevent irreversible damage in advance to ensure the technical effect of safe chip operation.

[0016] Below, the technical solutions in the present application will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments of the present application. It should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application. It should also be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, rather than all of them.

[0017] Please see attached Figure 1 , the present application provides a multi-dimensional simulation VCSEL chip fault point early warning system, including:

[0018] The chip structure acquisition module 11 is used to acquire chip structure information of a target VCSEL chip, wherein the chip structure information includes active layer information, resonant cavity information and electrode information.

[0019] Specifically, the target VCSEL chip refers to any VCSEL chip for which fault point warning is to be carried out. The chip structure information of the target VCSEL chip includes active layer information, resonant cavity information and electrode information. The active layer is responsible for generating light signals, which can be understood as a small laser transmitter that converts the energy of electrons into photons to form a laser beam. Therefore, the active layer information includes material composition, thickness, and luminescent characteristics. The resonant cavity allows light to be repeatedly reflected and amplified in the chip, ultimately enhancing the laser output. The resonant cavity information includes its length, the reflectivity of the reflector, and the matching degree with the wavelength of light. The electrode provides current to the chip to drive the active layer to work. The electrode information includes the layout, material, and current supply mode.

[0020] For example, in a VCSEL chip, the active layer is made of gallium arsenide with a thickness of 5 microns; the resonant cavity is 8 microns long with a reflectivity of 99%; the electrodes are made of indium tin oxide (ITO) and are arranged at the upper and lower ends of the chip. This information can help build a complete chip model and prepare for subsequent simulations.

[0021] The finite element analysis module 12 is used to perform finite element modeling based on the active layer information, the resonant cavity information and the electrode information to generate a finite element simulation model.

[0022] Specifically, finite element modeling is an existing numerical analysis method that decomposes complex physical systems into smaller, manageable units, each of which can calculate its physical properties separately. In this way, the behavior of the entire system can be analyzed more efficiently. In VCSEL chips, finite element modeling can help simulate the stress distribution, thermal effects and optical performance of the chip under different working conditions. Specifically, based on the active layer information, the active layer is divided into many small units and given specific physical properties, such as the refractive index, optical gain and conductivity of the material, which will affect the transmission and amplification of light in the chip. Next, the resonant cavity information will be used to model the reflection and resonance behavior of light. Parameters such as the length of the resonant cavity and the reflectivity of the reflector will directly affect the number of reflections of the light beam inside the chip and the output efficiency of the laser. By performing finite element division on the resonant cavity, the behavior of light waves, such as diffraction and interference of the light beam, can be accurately simulated. Finally, the electrode information will be used to construct a model of the electric field distribution. By analyzing the arrangement, material and current distribution of the electrodes, the process of how the current flows through the active layer and drives the emission of photons can be simulated.

[0023] For example, when conducting finite element modeling on a VCSEL chip, the active layer material is gallium arsenide, the resonant cavity length is 10 microns, and the electrode is indium tin oxide, this information is input into the finite element modeling software, and the entire chip structure is decomposed into thousands of small units through fine mesh division. Based on the material properties and structural parameters of each unit, a comprehensive simulation of the optical, electrical and thermal characteristics is performed to generate a complete finite element simulation model. This lays the foundation for subsequent chip failure analysis and can also provide guidance for chip design optimization.

[0024] The failure mode acquisition module 13 is used to acquire the chip failure mode of the target VCSEL chip, wherein the chip failure mode includes a reversible failure mode and an irreversible failure mode.

[0025] Specifically, failure modes refer to abnormal conditions that may occur during the operation of a chip, which manifests as failure of certain functions or performance of the chip. The collection of failure modes usually relies on actual test data, historical fault records, and monitoring of specific parameters inside the chip, such as current, voltage, temperature, etc. Among them, reversible failure modes refer to those failures that can be recovered through external intervention or chip self-repair. Such failures usually do not cause permanent damage to the chip. For example, when the chip temperature is too high, the laser output power may temporarily drop, but by dissipating heat or reducing the operating current, the chip can return to normal working state. Such failure modes are reversible because the failure does not cause irreparable physical damage.

[0026] In contrast, irreversible failure modes refer to failures that cause permanent damage to the chip, which usually results in physical destruction of the active layer or resonant cavity. For example, overheating of the electrode may cause the connection point between the electrode and the active layer to burn out. This damage cannot be restored by simple repair measures and is an irreversible failure mode.

[0027] To illustrate this process more clearly, for example, when testing a certain VCSEL chip, it was found that after running in a high temperature environment for a period of time, the laser output power dropped by 20%. After cooling, the chip resumed normal output, which is a typical manifestation of a reversible failure mode. However, if the chip works at high temperature, causing irreparable damage to the material structure of the active layer and completely losing the laser output, then this failure mode is an irreversible failure mode.

[0028] In the process of collecting these failure modes, it is necessary not only to record the conditions for the occurrence of each failure, but also to understand the transformation process and trigger points, which provides basic information for subsequent simulation models and early warning systems, and facilitates the effective identification and prediction of potential failures of VCSEL chips.

[0029] The failure simulation module 14 is used to call the finite element simulation model to perform chip failure simulation for the reversible failure mode and the irreversible failure mode, and establish a failure decision early warning device.

[0030] Specifically, for reversible failure modes, the finite element simulation model simulates how external intervention or chip repair can help restore the chip to normal working state when a temporary failure occurs. For example, when the chip temperature is too high, through finite element simulation, we can predict whether reducing the current or enhancing heat dissipation measures can restore the chip to normal state. The characteristic of reversible failure modes is that these failures are temporary and certain measures can be taken to restore the chip to a stable working state.

[0031] For irreversible failure modes, the simulation model will simulate situations that cause permanent damage to the chip. For example, when the chip is in a high voltage or high temperature environment for a long time, the simulation can predict the specific circumstances in which the active layer or electrode will be irreparably damaged. Once these failures occur, they cannot be recovered by any external means, and will eventually lead to complete failure of the chip. Through simulation analysis, these key failure modes can be identified in advance and early warning thresholds can be set for them.

[0032] Next, based on these simulation results, a failure decision early warning device was built. The core function of the failure decision early warning device is to integrate data from multi-dimensional sensors, monitor the operating status of the chip in real time, and perform failure identification and fault prediction based on simulation results. For reversible failure modes, the failure decision early warning device will make a judgment. Once it detects that the chip's operating status is close to the failure boundary, it will immediately issue a warning signal and recommend repair measures (such as reducing temperature or current). For irreversible failure modes, the failure decision early warning device will identify irrecoverable fault points based on the current state of the chip, and promptly trigger protection mechanisms such as emergency shutdown to prevent more serious damage.

[0033] For example, assuming that a certain VCSEL chip is running at high current, the simulation model predicts that it will experience reversible failure (such as decreased light output) when it exceeds 85°C, and irreversible failure (such as damage to the active layer) at 105°C. The early warning device sends a warning signal when the temperature approaches 85°C and prompts cooling measures. When the temperature continues to rise and approaches 105°C, the early warning device will trigger an emergency shutdown to prevent irreversible damage. In this way, the failure decision early warning device can effectively combine the finite element simulation results to monitor and predict the failure behavior of the chip in real time, thereby minimizing irreparable damage to the chip, extending its service life and ensuring its stable operation.

[0034] The multi-dimensional monitoring module 15 is used to deploy micro multi-dimensional sensors for the active layer structure, resonant cavity structure and electrode structure of the target VCSEL chip to collect multi-dimensional monitoring data.

[0035] Specifically, micro multi-dimensional sensors are deployed on the active layer structure, resonant cavity structure and electrode structure of the target VCSEL chip to collect multi-dimensional monitoring data generated during the operation of the chip. These data will provide basic support for subsequent failure mode identification and fault warning decisions. Micro multi-dimensional sensors are a type of small and versatile sensors that can simultaneously monitor data in multiple dimensions, such as temperature, stress, current, voltage, light output and other parameters. The purpose of deploying these sensors is to obtain real-time operating status information of each key structure of the chip, thereby providing real-time data support for the early warning system. For example, multi-dimensional sensors are deployed on a VCSEL chip, including temperature sensors, current sensors and optical sensors. When the chip starts working, the temperature sensor shows that the temperature of the active layer has risen to 80°C, the current sensor shows that the electrode current fluctuates greatly, and the optical sensor detects a slight decrease in light output. Through the real-time collection and analysis of these data, it can be preliminarily judged that the chip is approaching the critical point of reversible failure, and a warning signal can be issued in time to remind the user to take measures to reduce the temperature or current to prevent the failure from further deteriorating.

[0036] The failure warning module 16 is used to perform chip failure mode recognition and fault warning decision on the multi-dimensional monitoring data through the failure decision warning device, and output a warning signal.

[0037] Specifically, the multi-dimensional monitoring data is collected by micro sensors deployed on the target VCSEL chip, covering information in multiple dimensions such as temperature, stress, light output, and current, reflecting the real-time status of the chip during operation, and has high timeliness and accuracy. After receiving the multi-dimensional monitoring data, the failure decision early warning device automatically analyzes the failure mode and first distinguishes two types of failure modes: reversible failure mode and irreversible failure mode. The failure decision early warning device can identify the type of failure that the chip may currently face based on the characteristics of temperature, light output, and current fluctuations in the multi-dimensional monitoring data. For example, when it is detected that the temperature of the active layer rises sharply but is still within the tolerance range of the chip, and the optical output power decreases, it will be judged as a reversible failure mode and corresponding early warning suggestions will be given, such as reducing the operating current or enhancing heat dissipation. If the monitoring data shows that the chip temperature has exceeded its upper tolerance limit and the optical output power drops rapidly, it will be judged as an irreversible failure mode, which may trigger a more urgent protection mechanism.

[0038] Next, a fault warning decision is made based on the identified failure mode. For reversible failure modes, a prompt signal is output, and corrective measures are recommended, such as adjusting operating parameters, reducing power, or enhancing heat dissipation to help the chip return to normal. For irreversible failure modes, a more serious warning is issued, and it is recommended to shut down or turn off the power immediately to avoid permanent damage to the chip. The early warning signal is the final result of the output and can be presented in different ways. For example, the early warning signal can trigger an alarm light, buzzer, or email to notify the operator through the control system. When a reversible failure mode is identified, the severity of the signal is low, reminding the operator to pay attention and make timely adjustments. When an irreversible failure mode is identified, the severity of the early warning signal will increase, indicating that urgent processing is required.

[0039] For example, the operating temperature of a certain VCSEL chip suddenly rose to 85°C, and the optical output power dropped by 10%. After analyzing the multi-dimensional monitoring data, the failure decision early warning device identified that this was a reversible failure mode, and output a warning signal suggesting that the operating current be reduced immediately. After taking cooling measures, the chip temperature returned to the normal range and the light output also returned to normal levels. If the temperature further rises to 105°C and the light output drops sharply, the failure decision early warning device will determine that this is an irreversible failure mode and immediately trigger a shutdown signal to prevent further damage to the chip. In this way, the failure decision early warning device, combined with multi-dimensional monitoring data, can promptly identify the failure mode of the chip and make corresponding early warning decisions, helping to avoid major failures and extend the service life of the chip.

[0040] Further, as attached Figure 2 As shown, the failure simulation module 14 in the multi-dimensional simulation VCSEL chip fault point early warning system is also used for:

[0041] For the reversible failure mode, the finite element simulation model is called to perform reversible behavior identification and fault recovery decision testing, and a reversible integrated decision maker is trained; for the irreversible failure mode, the finite element simulation model is called to perform irreversible behavior identification and an irreversible limit stop predictor is trained; the reversible integrated decision maker and the irreversible limit stop predictor are connected in parallel to generate the failure decision early warning device.

[0042] Specifically, for reversible failure modes and irreversible failure modes, a finite element simulation model is used for simulation analysis, and the reversible integrated decision maker and the irreversible limit stop predictor are trained respectively, and the two are connected in parallel to finally generate a complete failure decision warning device. The specific steps are described in detail as follows.

[0043] First, for reversible failure modes, the finite element simulation model is called to perform reversible behavior identification and fault recovery decision testing, simulating the behavior of the chip under different failure scenarios and identifying which parameter changes can enable the chip to recover from the failed state. For example, when the chip temperature rises to a certain critical point, the finite element simulation model will simulate the recovery effect after cooling or reducing the current, thereby predicting the chip's recovery ability. Next, based on these simulation results, the reversible integrated decision maker is trained. The role of the reversible integrated decision maker is to integrate different reversible failure modes together to generate a model that can make recovery decisions in actual operation. For example, through multiple simulation tests of parameters such as temperature, stress, and light output, the decision maker can determine when it is necessary to reduce the current and when it is necessary to increase heat dissipation and other repair operations. In this way, when encountering similar situations in actual operation, it can make quick recovery decisions to help the chip return to normal.

[0044] On the other hand, for irreversible failure modes, finite element simulation models are also called to identify irreversible behaviors. Irreversible failure modes refer to failures that cause permanent damage to the chip, which usually cannot be repaired by external intervention. Through simulation, the destructive behavior of the chip under extreme conditions such as high temperature and high pressure can be simulated, and the key failure boundaries can be identified. For example, when the electrode is overheated and burned, the simulation model will analyze the changes in current and the damage process of the electrode material. These data will be used to train the irreversible limit stop predictor. The irreversible limit stop predictor identifies whether the critical point of irreversible damage has been reached based on the current state of the chip. When irreversible failure is detected, an emergency shutdown or other protection mechanism is immediately triggered to prevent the chip from suffering further damage. For example, when it is monitored that the chip temperature has reached the irreparable limit temperature, a shutdown signal will be directly triggered to avoid greater losses.

[0045] Finally, the reversible integrated decision maker and the irreversible limit stop predictor are connected in parallel to generate a complete failure decision warning device. This parallel connection method can ensure the simultaneous monitoring of reversible and irreversible failure modes. Specifically, the warning device can first determine whether the fault is a reversible failure mode based on real-time monitoring data. If so, the reversible integrated decision maker is called to provide a repair plan; if an irreversible failure signal is detected, the irreversible limit stop predictor is immediately called for emergency shutdown or other protection operations, to achieve comprehensive monitoring of the chip, respond to different types of faults in a timely manner, ensure that the chip operates in the best state, and minimize permanent damage to the chip caused by irreversible failure.

[0046] Furthermore, the multi-dimensional simulation VCSEL chip fault point early warning system also includes a decision optimization module, and the decision optimization module is used to:

[0047] For the reversible failure mode, a reversible failure multidimensional data set is collected; based on the reversible failure multidimensional data set, mode transition probability identification is performed to generate a mode transition probability set, wherein the mode transition probability is the probability of the reversible failure mode transforming into the irreversible failure mode; based on the mode transition probability set, target reversible failure multidimensional data with a transition probability greater than a preset threshold is extracted, and the boundary range of the failure data is determined after outlier data is deleted; based on the failure data boundary range, the reversible integrated decision maker and the irreversible stop predictor are optimized.

[0048] Specifically, collecting a reversible failure multidimensional data set refers to collecting and monitoring data on the reversible failure mode of the target VCSEL chip from multiple dimensions (such as temperature, current, light output, etc.). For example, when the chip temperature gradually rises to a certain level, the light output will be observed to gradually decrease, and then the light output will return to normal by cooling or reducing the current. These data cover the entire process from chip failure to recovery and have multidimensional characteristics. Next, based on the reversible failure multidimensional data set, the mode transition probability is identified, that is, the possibility of the reversible failure mode turning into an irreversible failure mode is calculated. The mode transition probability indicates the risk of the chip in the reversible failure state evolving into an irreversible failure under different conditions. For example, when the temperature exceeds 90°C, there is a 10% probability that the chip will be irreversibly damaged, but if the temperature reaches 105°C, this probability rises to 80%. Through these data, it is possible to identify under which conditions the failure mode is more likely to turn from reversible to irreversible, thereby generating a mode transition probability set.

[0049] Then, based on the mode transition probability set, data with a transition probability greater than a preset threshold is extracted from the reversible failure multidimensional data set to form the target reversible failure multidimensional data. This means that the focus is on those situations in which there is a high risk of turning into irreversible failure in the reversible failure mode. For example, if we set the threshold to 50%, then the failure mode with a transition probability exceeding 50% will be extracted for further analysis. Outlier data deletion, that is, removing those data points that obviously deviate from the normal range, these data may be outliers caused by special circumstances or noise, and do not represent the actual failure process. Specifically, it is a common technical means for technicians in this field to delete outliers through existing methods. For example, the target reversible failure multidimensional data can be multi-classified through the isolation forest method, and outlier data with only one data in the classification result can be identified and deleted. By deleting outlier data, the boundary range of failure data can be determined more accurately, that is, it is defined under which conditions the chip state is close to irreversible failure.

[0050] Finally, based on the failure data boundary range, the reversible integrated decision maker and the irreversible limit stop predictor are optimized. The purpose of the optimization is to improve the recognition accuracy of reversible failure modes and irreversible failure modes. Specifically, even if the monitoring data of the chip meets the failure data boundary range, there is a higher probability of turning into an irreversible failure in this case. Therefore, the state that meets the failure data boundary range is directly identified as an irreversible failure mode, and shutdown protection is performed. In this way, the reversible integrated decision maker and the irreversible limit stop predictor are optimized, and the shutdown protection is triggered at the critical point where irreversible failure is about to occur.

[0051] For example, in a certain test, when the temperature of the chip exceeds 95°C, the probability of it turning into an irreversible failure reaches 80%. These high-risk failure data are extracted, and 95°C is determined as the critical failure boundary through the cleaning of outlier data. Based on this result, the reversible integrated decision maker and irreversible limit stop predictor are optimized to identify the irreversible failure mode when the temperature reaches 95°C, trigger the shutdown signal in advance, prevent the chip from suffering irreversible damage, effectively prevent the occurrence of irreversible failure, and ensure the reliability and service life of the chip.

[0052] Furthermore, the decision optimization module in the multi-dimensional simulation VCSEL chip fault point early warning system is also used for:

[0053] Based on the reversible integrated decision maker, reversible recovery decisions are made on the reversible failure multidimensional data set to generate multiple groups of recovery decisions; based on the reversible failure multidimensional data set and the reversible failure multidimensional data set, a first reversible failure multidimensional data set and a first recovery decision with a corresponding relationship are extracted; with the first reversible failure multidimensional data set and the first recovery decision as constraints, a chip fault record database is traversed to count the first mode transition probability; and the first mode transition probability is added to the mode transition probability set.

[0054] Specifically, the reversible integrated decision maker is a model for identifying and making decisions on reversible failure modes constructed in the above steps. When analyzing the reversible failure multidimensional data set, the reversible integrated decision maker will make a series of reversible recovery decisions based on different failure conditions (such as temperature, current, light output, etc.). These decisions point to a set of measures that can help the chip recover to a normal working state. For example, if the chip temperature is too high, the decision maker will suggest reducing the current or increasing the heat dissipation so that the chip light output returns to a normal level, thereby generating multiple sets of recovery decisions, which have a corresponding relationship with the reversible failure multidimensional data set. Next, the first reversible failure multidimensional data set and the first recovery decision with a corresponding relationship are extracted from the reversible failure multidimensional data set and the multiple sets of recovery decisions, that is, the recovery scheme corresponding to each set of reversible failure data is found, for example, when the temperature rises to a certain value, the current adjustment measures for the chip to recover to a normal state, these data will be organized into the first reversible failure multidimensional data set and the first recovery decision. For example, when the temperature of a VCSEL chip rises to 90°C and the light output decreases, historical records show that the light output can be effectively restored by reducing the current to 8mA. This is a corresponding relationship.

[0055] With the first reversible failure multidimensional data set and the first recovery decision as constraints, the chip fault record database is traversed and analyzed to find fault records under similar failure conditions and to count the mode transition probabilities under these conditions. The mode transition probability indicates the possibility of the chip changing from a reversible failure mode to an irreversible failure mode under reversible failure conditions. For example, through analysis, when the temperature exceeds 95°C, the current is reduced according to the first recovery decision to resume work, but there is still a probability of changing to an irreversible failure mode in subsequent operation. The proportion of data that changes to an irreversible failure mode is counted as the first mode transition probability. Finally, the first mode transition probability is added to the mode transition probability set to further improve the prediction ability of the failure mode, accurately determine when the chip may change from a reversible failure mode to an irreversible failure mode, and take corresponding protective measures at the right time to more accurately evaluate the risk of chip failure transition, thereby improving the overall fault warning accuracy and decision-making efficiency.

[0056] Furthermore, the failure simulation module 14 in the multi-dimensional simulation VCSEL chip fault point early warning system is also used for:

[0057] Extract the first reversible mode and the first reversible recovery parameter type in the reversible failure mode, and load them through the finite element simulation model to generate a first reversible behavior data set; take the first reversible recovery parameter type as the control test target, perform multiple tests through the finite element simulation model, and generate a first effective recovery decision set; perform decision tree training based on the first reversible behavior data set and the first effective recovery decision set to generate a first reversible decision tree; add the first reversible decision tree into the reversible integrated decision maker.

[0058] Specifically, the first reversible mode refers to any failure mode in the reversible failure mode. The characteristic of the reversible failure mode is that the chip can be restored to a normal working state through appropriate external intervention or chip self-adjustment. The first reversible recovery parameter type refers to the key parameters related to the failure mode, which control the chip to recover from a failed state to a normal state. For example, if the first reversible mode is a decrease in laser output caused by excessive temperature, then the first reversible recovery parameter type may be the operating current or the heat dissipation efficiency. It can be determined specifically in combination with historical experience data. Next, the first reversible mode and the first reversible recovery parameter type are input into the finite element simulation model for simulation loading. The finite element simulation model simulates the performance of the chip under different working conditions and collects multidimensional data about the failure mode, such as temperature, current, etc., so as to generate a first reversible behavior data set.

[0059] Further, the first reversible recovery parameter type is used as the control test target, and the parameters corresponding to the first reversible recovery parameter type are continuously adjusted and tested multiple times using the finite element simulation model to generate the first effective recovery decision set. The purpose of the test is to determine which recovery measures can effectively restore the chip from the failure state under different conditions. For example, by simulating and analyzing different current values, heat dissipation efficiency and ambient temperature, the optimal recovery scheme can be found. After each test, the corresponding recovery effect is recorded, and the adjustment strategy that can restore the reversible failure mode to the normal mode is used as an effective recovery decision, thereby generating the first effective recovery decision set. After having the first reversible behavior data set and the first effective recovery decision set, the first reversible decision tree is generated through decision tree training. The decision tree is a commonly used machine learning algorithm that can generate a decision path based on the input and output relationship in the data set to quickly determine the best decision under future input conditions. In this process, different parameter combinations are analyzed and a logical structure is formed to make quick decisions when encountering similar failure situations in the future. For example, if the temperature exceeds 85°C and the current is greater than 10mA, the decision tree may recommend reducing the current to 8mA and enabling additional heat dissipation measures. Finally, the first reversible decision tree will be added to the reversible integrated decision maker. The reversible integrated decision maker integrates these different decision trees together for automated fault recovery decisions in actual chip operation. In this way, when the chip encounters a similar reversible failure mode in the future, a recovery plan can be made immediately based on the decision tree to reduce losses and downtime.

[0060] For example, when testing a VCSEL chip, the light output decreases when the temperature is too high. Through simulation analysis, we found that when the temperature reaches 90°C, if the operating current is reduced to 8mA and the fan speed is increased, the chip's light output can be restored to normal levels. Therefore, these recovery parameters are used as training data to generate a decision tree. When it is detected that the temperature rises to 90°C, the current will be automatically reduced and the fan will be started according to the decision tree recommendations, thereby quickly restoring the normal working state of the chip. In this way, timely and accurate recovery decisions can be made for the reversible failure mode of the VCSEL chip, thereby ensuring the long-term stable operation of the chip.

[0061] Furthermore, the failure simulation module 14 in the multi-dimensional simulation VCSEL chip fault point early warning system is also used for:

[0062] The irreversible failure mode is loaded through the finite element simulation model to generate an irreversible behavior data set; irreversible identification boundary conditions are determined based on the irreversible behavior data set; and the irreversible limited stop predictor is constructed based on the irreversible identification boundary conditions as a limited identification standard.

[0063] Specifically, the finite element simulation model is used to simulate and load the irreversible failure mode of the target VCSEL chip. The irreversible failure mode refers to the type of failure that will cause permanent damage to the chip and cannot be repaired once it occurs. For example, if the chip is exposed to excessively high temperatures, excessive currents or stress conditions for a long time, it may cause damage to the internal material structure or electrodes, and these damages are irreversible. Through simulation, the response of the chip under extreme conditions is simulated, and the failure process of the chip under different conditions is captured, thereby generating an irreversible behavior data set. This data set contains the performance details of the chip under irreversible failure mode, such as material decomposition caused by temperature exceeding the limit, permanent degradation of the resonant cavity, etc. Next, the irreversible identification boundary conditions are extracted from the irreversible behavior data set. These boundary conditions are key indicators and critical values ​​for identifying the impending irreversible failure of the chip. For example, the simulation results may show that when the chip temperature exceeds 110°C or the current reaches a certain limit value, the chip material will begin to degrade, or the electrode will be permanently damaged. By analyzing these critical conditions, the failure boundary of the chip can be defined, which helps to quickly identify the impending irreversible failure in actual operation.

[0064] Then, the irreversible identification boundary condition is used as the limited identification standard to construct an irreversible stop limit predictor. The function of the irreversible stop limit predictor is to monitor key parameters (such as temperature, current, stress, etc.) in real time during the operation of the chip. Once it is detected that these parameters reach the irreversible identification boundary condition, a shutdown signal is immediately issued to prevent the chip from suffering further damage. For example, through finite element simulation, it is found that when the temperature of the VCSEL chip exceeds 105°C, the electrode material will be permanently damaged, causing the chip to be unable to continue to work normally. 105°C is set as the irreversible identification boundary condition. When the chip's temperature sensor detects that the temperature is close to or exceeds this critical value, the irreversible stop limit predictor will immediately issue a shutdown command to protect the chip from further damage, which helps to extend the service life of the chip and significantly reduce the significant losses caused by irreversible failures.

[0065] Furthermore, the failure warning module 16 in the multi-dimensional simulation VCSEL chip fault point warning system is also used for:

[0066] The multi-dimensional monitoring data are respectively input into the reversible integrated decision maker and the irreversible limited stop predictor in the failure decision warning device to trigger the decision maker warning; the target failure mode and the target fault warning decision are obtained by the output result of the triggering decision maker; the warning signal is generated by the target failure mode and the target fault warning decision.

[0067] Specifically, the multi-dimensional monitoring data includes data in multiple dimensions such as temperature, current, voltage, and light output, which reflect the working status of the VCSEL chip in real time. These monitoring data are input into the reversible integrated decision maker and the irreversible limit stop predictor respectively. The reversible integrated decision maker is specifically used to identify reversible failure modes. By analyzing the monitoring data, it can detect whether the chip has entered a fault state that can be restored by external intervention. At the same time, the irreversible limit stop predictor is used to identify irreversible failure modes and determine whether the chip is about to have an irreversible permanent failure based on the monitoring data. For example, suppose that the temperature of the chip gradually rises to 95°C and the current fluctuation becomes unstable. At this time, the reversible integrated decision maker will determine whether the failure mode is a reversible state and whether normal operation can be restored by reducing the current or increasing heat dissipation. The irreversible limit stop predictor will evaluate whether the temperature has approached or exceeded the critical point of irreversible failure. If it is close to the critical point, the emergency shutdown mechanism will be triggered.

[0068] When the decision maker warning is triggered, the current target failure mode and target fault warning decision are obtained according to the output of the decision maker. The target failure mode refers to the specific failure mode identified, which is a reversible failure mode or an irreversible failure mode. The target fault warning decision is the countermeasures recommended by the system after the target failure mode is identified. For example, if the reversible integrated decision maker determines that it is a reversible failure mode, the warning decision may be to reduce the operating current or increase the heat dissipation. If the irreversible limit stop predictor detects that the chip is close to the irreversible failure critical value, the warning decision may be to shut down immediately to prevent further damage to the chip.

[0069] Next, based on the target failure mode and target fault warning decision identified above, a warning signal is generated and output. The warning signal can be conveyed in different ways, such as an alarm light, buzzer or email in the control system to notify the operator. When the warning signal is issued, corresponding actions can be taken according to the warning signal, such as adjusting the working parameters of the chip or starting the emergency shutdown program. Thus, the real-time feedback of multi-dimensional monitoring data is used to accurately identify the failure mode of the chip and generate the corresponding warning signal, thereby avoiding the occurrence of major failures and extending the service life of the chip.

[0070] In summary, the multi-dimensional simulation VCSEL chip fault point warning system provided by the present application has the following technical effects:

[0071] A chip structure acquisition module is used to acquire chip structure information of a target VCSEL chip, wherein the chip structure information includes active layer information, resonant cavity information and electrode information; a finite element analysis module is used to perform finite element modeling based on the active layer information, the resonant cavity information and the electrode information to generate a finite element simulation model; a failure mode acquisition module is used to acquire chip failure modes of the target VCSEL chip, wherein the chip failure modes include reversible failure modes and irreversible failure modes; a failure simulation module is used to call the finite element simulation model to perform chip failure simulation for the reversible failure mode and the irreversible failure mode, and establish a failure decision early warning device; a multi-dimensional monitoring module is used to deploy micro multi-dimensional sensors for the active layer structure, resonant cavity structure and electrode structure of the target VCSEL chip to collect multi-dimensional monitoring data; a failure early warning module is used to perform chip failure mode identification and fault early warning decision on the multi-dimensional monitoring data through the failure decision early warning device, and output an early warning signal. By obtaining the structural information of the target VCSEL chip and analyzing the reversible and irreversible failure modes based on the finite element simulation model, combined with the real-time monitoring data collected by the multi-dimensional sensor, the failure mode of the chip can be accurately identified, and then the failure decision warning device can be used to issue a real-time fault warning, so as to accurately recover from reversible failures and prevent irreversible damage in advance, thereby ensuring the technical effect of safe chip operation.

[0072] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0073] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the present application and its equivalent technology, the present application is also intended to include these modifications and variations.

Claims

1. A multi-dimensional simulation VCSEL chip fault point early warning system, characterized in that: include: A chip structure acquisition module, used to acquire chip structure information of a target VCSEL chip, wherein the chip structure information includes active layer information, resonant cavity information and electrode information; A finite element analysis module, used for performing finite element modeling based on the active layer information, the resonant cavity information and the electrode information to generate a finite element simulation model; A failure mode acquisition module, used to acquire chip failure modes of the target VCSEL chip, wherein the chip failure modes include reversible failure modes and irreversible failure modes; A failure simulation module, for calling the finite element simulation model to perform chip failure simulation for the reversible failure mode and the irreversible failure mode, and establishing a failure decision early warning device; A multi-dimensional monitoring module, used to deploy micro multi-dimensional sensors for the active layer structure, resonant cavity structure and electrode structure of the target VCSEL chip to collect multi-dimensional monitoring data; A failure warning module, used to perform chip failure mode recognition and fault warning decision on the multi-dimensional monitoring data through the failure decision warning device, and output a warning signal; The failure simulation module is also used for: For the reversible failure mode, calling the finite element simulation model to perform reversible behavior identification and fault recovery decision testing, and training a reversible integrated decision maker; For the irreversible failure mode, calling the finite element simulation model to perform irreversible behavior identification and train an irreversible stop predictor; The reversible integrated decision maker and the irreversible limited stop predictor are connected in parallel to generate the failure decision early warning device.

2. A multi-dimensional simulation VCSEL chip fault point early warning system as claimed in claim 1, characterized in that: The reversible failure mode is a failure mode that is restored to a normal working state through external intervention or self-repair; the irreversible failure mode is a failure mode that causes permanent damage to the target VCSEL chip.

3. A multi-dimensional simulation VCSEL chip fault point early warning system as claimed in claim 1, characterized in that: It also includes a decision optimization module, which is used to: For the reversible failure mode, collecting a reversible failure multidimensional data set; Based on the reversible failure multidimensional data set, mode transition probability identification is performed to generate a mode transition probability set, wherein the mode transition probability is the probability of the reversible failure mode transforming into the irreversible failure mode; Extracting target reversible failure multidimensional data with a transition probability greater than a preset threshold based on the pattern transition probability set, and determining the boundary range of the failure data after deleting outlier data; The reversible integrated decision maker and the irreversible limited stop predictor are optimized based on the failure data boundary range.

4. A multi-dimensional simulation VCSEL chip fault point early warning system as claimed in claim 3, characterized in that: The decision optimization module is also used to: Perform reversible recovery decisions on the reversibly failed multidimensional data set based on the reversible integrated decision maker to generate multiple groups of recovery decisions; extracting a first reversible failure multidimensional data set and a first recovery decision having a corresponding relationship based on the reversible failure multidimensional data set and the reversible failure multidimensional data set; Taking the first reversible failure multidimensional data set and the first recovery decision as constraints, traverse the chip fault record database to count the first mode transition probability; The first mode transition probability is added to the mode transition probability set.

5. A multi-dimensional simulation VCSEL chip fault point early warning system as claimed in claim 1, characterized in that: The failure simulation module is also used for: Extracting a first reversible mode and a first reversible recovery parameter type from the reversible failure mode, and loading them through the finite element simulation model to generate a first reversible behavior data set; Taking the first reversible recovery parameter type as a control test target, performing multiple tests through the finite element simulation model to generate a first effective recovery decision set; Performing decision tree training based on the first reversible behavior data set and the first effective recovery decision set to generate a first reversible decision tree; The first reversible decision tree is added into the reversible integrated decider.

6. A multi-dimensional simulation VCSEL chip fault point early warning system as claimed in claim 1, characterized in that: The failure simulation module is also used for: Loading the irreversible failure mode through the finite element simulation model to generate an irreversible behavior data set; determining irreversible identification boundary conditions using the irreversible behavior data set; The irreversible limited stop predictor is constructed by taking the irreversible identification boundary condition as a limiting identification standard.

7. A multi-dimensional simulation VCSEL chip fault point early warning system as claimed in claim 1, characterized in that: The failure warning module is also used for: The multi-dimensional monitoring data are respectively input into the reversible integrated decision maker and the irreversible limited stop predictor in the failure decision early warning device to trigger the decision maker early warning; The output result of the triggering decision maker is used to obtain the target failure mode and target fault warning decision; The warning signal is generated based on the target failure mode and the target fault warning decision.

Images