Fast simulation method of quantum transport-thermal transport-thermal stress coupling in three-dimensional nanodevices

Abstract

The application discloses a quantum transport-thermal transport-thermal stress coupling fast simulation method in a three-dimensional nano device. By solving the quantum transport equation, the heat conduction equation and the solid mechanics balance equation in the coupling mode space, the three-dimensional nano semiconductor device is simulated fast, and the calculation amount of solving the three-dimensional quantum transport equation is reduced. The method comprises the following steps: (1) using the non-equilibrium Green function method, solving the three-dimensional quantum transport equation in the coupling mode space while considering the thermal stress and the phonon scattering effect; (2) using the current density spectrum to calculate the heat source distribution and the current respectively; (3) based on the numerical method and the heat source distribution, solving the heat conduction equation and the solid mechanics balance equation to obtain the temperature distribution and the thermal stress distribution; (4) converting the thermal stress to the mode space, and substituting the temperature distribution and the thermal stress distribution into the quantum transport equation, and repeating steps (1)-(4) until convergence. The application provides a simulation method for the design and optimization of the three-dimensional nano semiconductor device.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of multi-physical field modeling and simulation of nano semiconductor electronic devices, and relates to a quantum transport-thermal transport-thermal stress coupling fast simulation method in a three-dimensional nano device. BACKGROUND

[0002] Gate-all-around transistors (GAA-FETs) are used in 3nm technology nodes due to their high drive current, high integration density and strong gate control ability. However, due to the fact that the channel of the GAA-FET is surrounded by a low thermal conductivity gate oxide layer, the self-heating effect (SHE) of the GAA-FET is serious. This may further cause thermal stress and affect the performance of the device.

[0003] At present, research has been conducted on the electro-thermal effect of GAA-FETs, such as the influence of process variability (M.G. Pala et al., "Increase of self-heating effects in nanodevices induced by surface roughness: A full-quantum study", Journal of Applied Physics 2015), device geometry (W. Kwon, C et al., "Electrothermal Modeling of Multi-Nanosheet FETs With Various Layouts", IEEE Transactions on Electron Devices 2024) and interfacial thermal resistance (S. Venkateswarlu et al., "Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around Nanosheet FET", IEEE Transactions on Electron Devices 2020) on the self-heating effect of GAA-FETs.

[0004] On the other hand, the effect of stress on FET has been studied. A two-dimensional model is established for FinFET to study the effect of SHE-induced thermal stress on carrier transport (Huali Duan et al., "Theoretical Study of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in p-Type Ultrathin Body-FinFET by Multiphysics Simulation", IEEE Transactions on Electron Devices 2023). The stress introduced by stress engineering can change the threshold voltage, band structure and carrier mobility of the device to improve the performance of the device (Yoon et al., "Bandgap Engineering and Strain Effects of Core-Shell Tunneling Field-Effect Transistors," IEEE Transactions on Electron Devices, 2017.).

[0005] However, there is almost no research on the thermodynamic effect in three-dimensional nanoscale semiconductor devices at present. Because the GAA-FET structure is three-dimensional, the coupling process of quantum transport, heat transport and thermal stress inside it is more complex and the calculation is more complex than that of two-dimensional structure. In addition, three-dimensional GAA-FET has been widely used in today's 3nm node circuits. Therefore, it is necessary to develop an efficient fast simulation method for three-dimensional nanoscale semiconductor devices with multi-physical coupling, and to study the multi-physical field coupling mechanism in three-dimensional nanoscale semiconductor devices to guide device and circuit design.

[0006] The present application solves three-dimensional quantum transport equations, heat conduction equations and solid mechanics equilibrium equations in the coupling mode space by numerical method to simulate, and gives a fast simulation method for three-dimensional nanoscale semiconductor device quantum transport, heat and thermal stress coupling effect, wherein the heat source distribution is calculated from the current density energy spectrum considering electron-phonon microscopic interaction. This method is suitable for most three-dimensional nanoscale semiconductor electronic devices including all-around gate field effect transistor (GAA-FET). SUMMARY

[0007] In view of the deficiencies in the prior art, the present application provides a three-dimensional nanoscale semiconductor device quantum transport-heat transport-thermal stress coupling fast simulation method.

[0008] The technical scheme adopted by the present application is as follows:

[0009] A rapid simulation method for quantum transport-thermal transport-thermal stress coupling in three-dimensional nanodevices mainly includes:

[0010] Transform the thermal stress and Hamiltonian in the real space of the device into the coupled mode space;

[0011] Based on the non-equilibrium Green's function method, in the coupled mode space, and considering the phonon scattering effect based on the self-consistent Born approximation method, the interaction between charge carriers and phonons is simulated using the self-consistent Born approximation and the phonon deformation potential method. The current density energy spectrum is obtained by self-consistently solving the three-dimensional quantum transport equation and the Poisson equation.

[0012] Calculation of heat source distribution from current density energy spectrum;

[0013] Based on the heat source distribution, the temperature distribution and thermal stress distribution in real space are obtained by numerically solving the heat conduction equation and the solid mechanics equilibrium equation.

[0014] The thermal stress distribution in real space is then transformed to coupled mode space, and the above steps are repeated iteratively until convergence.

[0015] In the above technical solution, the conversion to the coupled mode space further includes: constructing a mode space rotation matrix based on the eigenvector of the Hamiltonian of the device cross-section considering electric potential and thermal stress; first converting the Hamiltonian of the real space cross-section of the three-dimensional nanodevice, the coupling Hamiltonian between different cross-sections in the real space of the device, the electric potential distribution in the real space of the device, and the strain Hamiltonian of the device from the real space to the k space; and then combining the rotation matrix from the k space to the mode space to obtain the characteristic equation of the cross-section considering thermal stress in the coupled mode space.

[0016] Furthermore, the characteristic equation of the cross section considering thermal stress in the coupled mode space is obtained as follows:

[0017]

[0018] Where E is energy and ψ is the carrier wavefunction. Cross-section of the device The k-space Hamiltonian, Let be the coupling Hamiltonian between different cross-sections in the k-space of the device. This represents the k-space potential distribution inside the device. Let be the strain Hamiltonian in the k-space of the device. Let be the rotation matrix from k-space to modulus space corresponding to the cross-section of the device. It is an Hermitian operator.

[0019] Furthermore, the rotation matrix from k-space to modulus space corresponding to the device cross-section Specifically:

[0020]

[0021] where, ψ i is the wave function, i∈1,2,…,N m , N m is the number of selected modes, represents the eigenvector of the wave function.

[0022] Further, the non-equilibrium Green's function method specifically comprises: simulating the interaction between the carrier and the phonon by using the self-consistent Born approximation and the phonon deformation potential method in the coupled mode space.

[0023] Further, the calculation of the heat source distribution from the current density energy spectrum specifically comprises:

[0024]

[0025] where, is the heat source distribution of the device cross section , E is the energy, q is the point charge constant, is the current density energy spectrum in the coupled mode space from the cross section to the cross section .

[0026] Further, the convergence requirement is that the current, the hole density, the electric potential, the thermal stress and the temperature change between two iterations are all less than the preset tolerances, and the preset tolerances can be set according to experience or specific needs.

[0027] Compared with the prior art, the present application has the following beneficial effects:

[0028] 1. The present application provides a three-dimensional nano semiconductor device quantum transport-thermal transport-thermal stress coupling effect simulation method, which is helpful for the design optimization of three-dimensional semiconductor devices, and provides guidance for the research of the multi-physical field coupling mechanism in the circuit and system, and can analyze the influence of thermal transport and thermal stress on the device, including: analyzing the influence of thermal stress on the effective mass of the carrier according to the E-k dispersion relation of the device channel material; analyzing the influence of thermal stress on the state density of the device channel material, further researching the influence of thermal stress on the carrier distribution in the device; analyzing the influence of thermal stress on the current density energy spectrum, further analyzing the influence of thermal stress on the on-current of the device, etc.

[0029] 2. The present application provides a method for converting thermal stress to the coupled mode space, so as to simultaneously and quickly solve the quantum transport equation, the heat conduction equation and the solid mechanics equilibrium equation in the three-dimensional coupled mode space.

[0030] 3. This invention provides a method for simulating the electrothermal effects of nanoscale semiconductor devices across scales. The current density energy spectrum is calculated considering microscopic carrier-phonon interactions, and the microscopic heat source is obtained from the current density energy spectrum. The microscopic heat source is substituted into the heat conduction equation to solve for the temperature distribution in macroscopic structural regions including the substrate, dielectric, and metal, thereby achieving cross-scale simulation.

[0031] 4. This invention can study the effects of self-heating and self-heating-induced thermal stress on the quantum transport properties of three-dimensional nano-semiconductor devices, while previous studies have mostly focused on the effects of strain engineering on device properties, or the effects of thermal stress on quantum transport properties in two-dimensional nano-semiconductor devices. Attached Figure Description

[0032] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0033] Figure 1 This invention provides a typical three-dimensional nanotransistor structure, namely a gate all-around transistor (GAA-FET) structure, wherein Figure (a) is the 3D structure, and Figures (b) and (c) are its XZ and YZ cross-sectional views, respectively, and the red dot is the origin of the device.

[0034] Figure 2 (a) Current density energy spectrum considering phonon-hole interaction provided by the present invention; Figure 2 (b) is the device heat source distribution calculated from the current density energy spectrum provided by the present invention.

[0035] Figure 3 This is a temperature distribution diagram of the device operating in the on-state in an embodiment of the present invention; Figure 3 (a) is a three-dimensional temperature distribution diagram of the device; Figure 3 (b) shows the temperature distribution across the YZ cross section (x = 22 nm); Figure 3 (c) shows the temperature distribution across the XZ cross section (y = 20 nm); Figure 3 (d) shows the temperature distribution at the midpoint of the cross-section of the channel along the transport direction.

[0036] Figure 4 Figure (a) shows the thermal stress distribution of the device in the on-state in this embodiment of the invention, where (a)-(c) correspond to the normal thermal stress σ of the XZ section, respectively. xx σ yy and σ zz The distribution of thermal stress is shown in Figure (d), which is the thermal stress distribution at the midpoint of the channel section, including σ. xx σ yy σ zz σ yz σzx and σ xy six components.

[0037] Figure 5 is the valence band structure of the embodiment of the present application under the condition of considering and not considering thermal stress (x = 15 nm).

[0038] Figure 6 is the change of the hole effective mass in the embodiment of the present application; (a)-(c) hole effective mass at the top of subbands 1, 2, 3 in the

[100] /

[001] direction under the condition of considering and not considering thermal stress; (d)-(f) hole effective mass at the top of subbands 1, 2, 3 in the

[111] / [-110] direction under the condition of considering and not considering thermal stress. Note: subbands 1, 2, 3 in the

[100] /

[001] direction are the 9th, 25th and 38th subbands of the valence band respectively. Subbands 1, 2, 3 in the

[111] / [-110] direction are the 15th, 30th and 50th subbands of the valence band respectively. (g) influence of thermal stress on the hole effective mass of subbands 1, 2, 3 in the

[100] /

[001] direction; (h) influence of thermal stress on the hole effective mass of subbands 1, 2, 3 in the

[111] / [-110] direction.

[0039] Figure 7 is the influence of thermal stress on the state density of the channel material in the embodiment of the present application. (a) and (b) are the state density of the channel material in the

[100] and

[111] directions respectively without thermal stress; (c) and (d) are the state density of the channel material in the

[100] and

[111] directions respectively with thermal stress. (e) and (f) are the change of the state density of the channel material in the

[100] and

[111] directions respectively caused by thermal stress.

[0040] Figure 8 is the influence of thermal stress on the hole density of the device in the

[100] channel orientation in the embodiment of the present application. (a) cross-sectional average hole density along the transport direction under the condition of considering and not considering thermal stress; (b) hole density distribution in the channel cross-section under the condition of considering thermal stress (x = 27 nm); (c) hole density distribution in the channel cross-section under the condition of not considering thermal stress (x = 27 nm); (d) change of hole density distribution in the channel cross-section caused by thermal stress (x = 27 nm).

[0041] Figure 9The influence of thermal stress on the hole density of the device with

[111] channel orientation in the embodiment of the present application. (a) The cross-sectional average hole density along the transport direction in the case of considering and not considering thermal stress; (b) The hole density distribution of the channel cross-section (x = 27 nm) in the case of considering thermal stress; (c) The hole density distribution of the channel cross-section (x = 27 nm) in the case of not considering thermal stress; (d) The change of the hole density distribution of the channel cross-section (x = 27 nm) caused by thermal stress.

[0042] Figure 10 The influence of thermal stress on the current density spectrum of the device in the embodiment of the present application. (a) and (b) are the current density spectra of the device in the

[100] and

[111] crystal orientations without thermal stress, respectively; (c) and (d) are the current density spectra of the device in the

[100] and

[111] crystal orientations with thermal stress, respectively; (e) and (f) are the changes of the current density spectra of the device caused by thermal stress in the

[100] and

[111] crystal orientations, respectively.

[0043] Figure 11 (a) is the I-V characteristic curve of the device in different crystal orientations in the embodiment of the present application in the case of considering and not considering thermal stress. D -V G The transfer characteristic curve; Fig. (b) is the change of the on-state current caused by thermal stress under different gate voltages; Fig. (c) is the percentage change of the on-state current caused by thermal stress under different gate voltages. DETAILED DESCRIPTION

[0044] The present application will be described in detail below with specific embodiments. The following examples will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present application. These all belong to the protection scope of the present application.

[0045] In the following examples, a typical three-dimensional nanometer semiconductor electronic device is selected, and a p-type fully wrapped gate transistor (GAA-FET) is taken as an example to describe the quantum transport-thermal-thermal stress coupling fast simulation method of the three-dimensional nanometer device of the present application. However, the quantum transport-thermal-thermal stress coupling fast simulation method of the three-dimensional nanometer semiconductor device proposed by the present application is not only suitable for fully wrapped gate transistors, but also suitable for most nanometer scale semiconductor electronic devices that require three-dimensional modeling analysis.

[0046] According to a specific example of the present application, Table I is a pseudo code table for modeling and simulation of the multi-physical field coupling effect of the three-dimensional nanometer semiconductor device provided by the present application. The quantum transport-thermal-thermal stress coupling effect simulation method of the three-dimensional nanometer semiconductor device in this example includes the following steps:

[0047] Step 1: After transforming the thermal stress in the device real space and the Hamiltonian to the coupled mode space, the quantum transport equation and Poisson equation are solved self-consistently in the coupled mode space based on the non-equilibrium Green's function method, and the current density spectrum is obtained. The heat source distribution is calculated according to the results. The governing equations used are listed in Table 2.

[0048] Step 2: Based on the heat source distribution, the heat conduction equation and the solid mechanics equilibrium equation are solved by numerical method to obtain the internal temperature distribution and thermal stress distribution of the device.

[0049] Step 3: The above thermal stress is introduced into the strain Hamiltonian and transformed into the mode space. Steps 1 and 2 are repeated iteratively until the current density converges, with the requirement that the changes in current density, hole density, electric potential, thermal stress and temperature between two iterations are less than the preset tolerance.

[0050] Table I

[0051]

[0052] Table 2 Governing equations in the model

[0053]

[0054] The symbols and terms appearing in the text are listed in Table 3.

[0055] Table 3 Symbols and terms appearing in the text

[0056]

[0057] As shown in Figure 2 (a) is the current density spectrum of the transistor when V G = V D = -0.7V, and Fig. (b) is the internal heat source distribution curve of the device calculated according to the current density spectrum. Figure 3 is the temperature distribution of the transistor in the on state, where the hot spot is located near the channel-drain and drain extension region interface, and the highest temperature is about 395K. Figure 4 is the thermal stress distribution of the transistor in the on state, where the shear stress component is much smaller than the normal stress component. Figure 5 is the E-k x dispersion relationship comparison chart, which shows that thermal stress can cause changes in the energy band structure of the channel semiconductor material. Figure 6 is the effect of thermal stress on the effective mass of holes at the top of each subband along the transport direction for different crystal orientations. Figure 7 is the effect of thermal stress on the state density of the channel material of the device along the transport direction for different crystal orientations, and the results show that thermal stress increases the state density of the

[100] crystal orientation channel at the red arrow and decreases it at the black arrow; the analysis of

[111] is similar.Figure 8 With Figure 9 respectively, the effect of thermal stress on the average hole density of the cross section of the device along the transport direction for different crystal orientations. The results show that thermal stress increases the hole density at the channel for both crystal orientations. Figure 10 respectively, the effect of thermal stress on the current density energy spectrum of the device along the transport direction in the on state. The thermal stress increases the current density energy spectrum of the

[100] crystal orientation between [-0.2, 0.2] eV. The thermal stress decreases the current density energy spectrum of the

[111] crystal orientation between [-0.2, 0.2] eV and increases it between [0.2, 0.8] eV. Figure 11 respectively, the effect of thermal stress on the current density energy spectrum of the device along the transport direction in the on state. The thermal stress increases the current density energy spectrum of the

[100] crystal orientation between [-0.2, 0.2] eV. The thermal stress decreases the current density energy spectrum of the

[111] crystal orientation between [-0.2, 0.2] eV and increases it between [0.2, 0.8] eV. D -V G respectively, the effect of thermal stress on the current density energy spectrum of the device along the transport direction in the on state. The thermal stress increases the current density energy spectrum of the

[100] crystal orientation between [-0.2, 0.2] eV. The thermal stress decreases the current density energy spectrum of the

[111] crystal orientation between [-0.2, 0.2] eV and increases it between [0.2, 0.8] eV.

[0058] Based on the results of the multi-physics coupling simulation, thermal stress can lead to an increase or decrease in the on-state current, depending on the crystal orientation configuration of the channel semiconductor material. Similarly, thermal stress can change the hole density distribution in the channel in the on state, thereby changing the gate capacitance of the device.

[0059] The specific embodiments of the present application are described above. It should be understood that the present application is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essential content of the present application. In the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A method for fast simulation of quantum transport-thermal transport-thermal stress coupling in three-dimensional nanodevices, characterized in that, The method comprises the following steps: 1) converting the real space Hamiltonian of a three-dimensional nano device and a thermal stress distribution into a coupled mode space; The conversion into the coupled mode space comprises: constructing a mode space rotation matrix based on an eigenvector of a device cross-section Hamiltonian considering an electric potential and a thermal stress; converting the cross-section Hamiltonian of the three-dimensional nano device, a coupling Hamiltonian between different cross-sections in a device real space, a device internal real space electric potential distribution, and a device strain Hamiltonian from the real space to a k space, and then combining the k space with a rotation matrix from the k space to the mode space to obtain a cross-section characteristic equation in the coupled mode space considering the thermal stress; 2) in the coupled mode space, solving a three-dimensional quantum transport equation and a Poisson equation containing a phonon scattering process by using a non-equilibrium Green's function method to obtain a current density energy spectrum; and calculating a heat source distribution from the current density energy spectrum; 3) solving a heat conduction equation and a solid mechanics equilibrium equation based on a numerical method and the heat source distribution to obtain a real space temperature distribution and a thermal stress distribution; 4) converting the thermal stress distribution into the coupled mode space, updating the temperature and the thermal stress in the three-dimensional quantum transport equation, and repeating steps 2), 3), and 4) to iteratively solve until convergence.

2. The method for fast simulation of quantum transport-thermal transport-thermal stress coupling in three-dimensional nano devices according to claim 1, wherein, The cross-section characteristic equation in the coupled mode space considering the thermal stress is: ， Where E represents energy. H is the carrier wavefunction. k ( ( ) represents the cross-section of the device. The k-space Hamiltonian, W k ( V represents the coupling Hamiltonian between different cross-sections of the device in k-space. k ( H represents the k-space potential distribution inside the device. k strain ( ) represents the strain Hamiltonian in the k-space of the device, U0( Let be the rotation matrix from k-space to modulus space corresponding to the cross-section of the device. It is an Hermitian operator.

3. The method for fast simulation of quantum transport-thermal transport-thermal stress coupling in three-dimensional nano devices according to claim 1, wherein, The rotation matrix U0from k-space to mode space corresponding to the device cross-section is In particular: ， wherein is the wave function, , N m is the number of selected modes, denotes the wave vector of the wave function.

4. The method for fast simulation of quantum transport-thermal transport-thermal stress coupling in three-dimensional nano devices according to claim 1, wherein, The non-equilibrium Green's function method in step 2) specifically comprises: simulating the interaction between carriers and phonons by using a self-consistent Born approximation and a phonon deformation potential method in the coupled mode space.

5. The method for fast simulation of quantum transport-thermal transport-thermal stress coupling in three-dimensional nano devices according to claim 1, wherein, The calculation of the heat source distribution from the current density energy spectrum in step 2) specifically comprises: ， where Q (x, y, z) is the heat source distribution, E is the energy, q is the point charge constant, ) is the thermal source distribution across the device cross section E is the energy, q is the point charge constant, is the current density spectrum in the coupled mode space from cross section to cross section .

6. The method for fast simulation of quantum transport-thermal transport-thermal stress coupling in three-dimensional nano devices according to claim 1, wherein, The requirement for the convergence in step 4) is that the current, the hole density, the electric potential, the thermal stress, and the temperature change between two iterations are all less than a preset tolerance.

Images