Redundant Control Signal Detection Method, Computing Device, and Computer-Readable Storage Medium

Abstract

The present application discloses a redundant control signal detection method, a computing device, and a computer-readable storage medium, including: obtaining simulation data generated after performing functional simulation on the logic function code of a target chip; the logic function code includes at least one input control signal and an output signal of a target register, and the simulation data includes simulation waveform signals corresponding to each input control signal and the output signal respectively within a plurality of clock cycles; based on the simulation data, performing redundant detection on each input control signal; the redundant detection includes detecting the change relationship between the input control signal and the output signal; outputting the obtained redundant detection result. In this way, by performing redundant detection on each input control signal of the target register through the simulation data generated after performing functional simulation on the logic function code of the target chip, redundant points in the target chip can be conveniently and quickly located, the chip timing can be optimized, the chip area and power consumption can be reduced, and at the same time, the reliability of the chip design is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and particularly to a method for detecting redundant control signals, a computing device, and a computer-readable storage medium. Background Art

[0002] In the process of digital chip design, after the designer completes the design of the logic function code including the register transfer level (RTL), simulation is performed to verify whether the design achieves the expected function, so as to discover logical errors, functional errors, or design defects in the design. Among them, the RTL code is converted into an equivalent logic gate circuit through synthesis, and the RTL code is optimized, such as deleting unused registers, constant registers, etc., and merging multiple registers with completely equivalent inputs.

[0003] However, after simulation verification and debugging, the code whose function meets the design expectations will still have some redundant points after synthesis optimization. For example, some input control signals of a register become redundant because they have no effect on the control of the register, or there are logical relationships between multiple input control signals of a register or between the signals and the register itself, resulting in some of these signals becoming redundant signals when controlling the register. However, these redundant signals (also called redundant points) will increase the complexity of the register control circuit, thereby leading to an increase in chip area and power consumption. Summary of the Invention

[0004] The purpose of the present application is to provide a method for detecting redundant control signals, a computing device, and a computer-readable storage medium to at least solve the problems in the related art.

[0005] To achieve the above object:

[0006] In a first aspect, an embodiment of the present application provides a method for detecting redundant control signals, the method including:

[0007] Obtaining simulation data generated after performing functional simulation on the logic function code of a target chip; the logic function code includes at least one input control signal and an output signal of a target register, and the simulation data includes simulation waveform signals corresponding to each of the input control signals and the output signal in a plurality of clock cycles;

[0008] Based on the simulation data, performing redundant detection on each of the input control signals; the redundant detection includes detecting the change relationship between the input control signal and the output signal;

[0009] Outputting the obtained redundant detection result.

[0010] In one embodiment, the redundancy detection of each of the input control signals based on the simulation data includes:

[0011] Determine a target input control signal of the target register;

[0012] Segment according to the inversion time of the simulation waveform signal corresponding to the target input control signal to obtain a plurality of segmented waveform signals corresponding to the target input control signal; the plurality of segmented waveforms include the segmented waveform signals of each of the input control signals and the segmented waveform signal of the output signal;

[0013] Based on the simulation waveform signals respectively corresponding to the plurality of segmented waveform signals, detect whether the control of the target input control signal corresponding to each segmented waveform signal over the target register is meaningful;

[0014] Generate a redundancy detection result for the target input control signal according to the obtained detection results for each of the segmented waveform signals.

[0015] In one embodiment, the detecting whether the control of the target input control signal corresponding to each segmented waveform signal over the target register is meaningful includes:

[0016] Judge whether the redundancy detection of each segmented waveform signal of the target input control signal is meaningful;

[0017] If it is meaningful, determine the segmented waveform signal as a target segmented waveform signal, and detect whether the control of the input control signal corresponding to the target segmented waveform signal over the target register is meaningful.

[0018] In one embodiment, the judging whether the redundancy detection of each segmented waveform signal of the target input control signal is meaningful includes:

[0019] If it is detected that the number of inversions of the simulation waveform signal of the target input control signal within one clock cycle is even, determine that the redundancy detection corresponding to the plurality of segmented waveform signals corresponding to the even number of inversions is meaningless;

[0020] If it is detected that the number of inversions of the simulation waveform signal corresponding to the target input control signal within one clock cycle is odd, determine that the redundancy detection of the last segmented waveform signal within one clock cycle is meaningful.

[0021] In one embodiment, the detecting whether the control of the input control signal corresponding to the target segmented waveform signal over the target register is meaningful includes:

[0022] Based on the simulation waveform signal corresponding to the target segmented waveform signal, determine whether the flip action of the input control signal corresponding to the target segmented waveform signal is meaningful for the control of the target register, and / or determine whether the value after the flip of the input control signal corresponding to the target segmented waveform signal is meaningful for the control of the target register.

[0023] In one embodiment, determining whether the flip action of the input control signal corresponding to the target segmented waveform signal is meaningful for the control of the target register includes:

[0024] Determine whether the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies a first preset condition for the control of the target register;

[0025] If it is satisfied, it is determined that the flip action of the input control signal corresponding to the target segmented waveform signal is meaningful for the control of the target register; the first preset condition is used to determine whether the target input control signal directly controls the target register or shields or opens the control channel of other control signals for the target register.

[0026] In one embodiment, it further includes:

[0027] When the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment does not satisfy the first preset condition for the control of the target register, determine whether the value after the flip of the input control signal corresponding to the target segmented waveform signal satisfies a second preset condition for the control of the target register; the second preset condition is used to determine whether the target input control signal directly controls the target register or shields or opens the control channel of other control signals for the target register;

[0028] When the value after the flip of the input control signal corresponding to the target segmented waveform signal satisfies the second preset condition for the control of the target register, determine that the value after the flip of the input control signal corresponding to the target segmented waveform signal is meaningless for the control of the target register.

[0029] In one embodiment, the first preset condition includes a first preset sub-condition; determining whether the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition includes:

[0030] Determine the target moment when the input control signal corresponding to the target segmented waveform signal flips;

[0031] Determine whether the simulation waveform signal corresponding to the output signal flips within the next clock cycle after the target moment;

[0032] If it is determined that when the simulation waveform signal corresponding to the output signal flips, the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the target moment satisfies the first preset sub-condition, it is determined that the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition;

[0033] The satisfaction of the first preset sub-condition includes at least one of the following:

[0034] The value of the output signal changes following the change of the value of the input control signal corresponding to the target segmented waveform signal;

[0035] When the value of the input control signal corresponding to the target segmented waveform signal is a preset value and the values of other input control signals change, the value of the output signal changes; the other input control signal is any input control signal other than the target input control signal among the at least one input control signal.

[0036] In one embodiment, the first preset condition includes a second preset sub-condition; determining whether the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition includes:

[0037] If it is determined that when the value of the simulation waveform signal corresponding to the output signal does not flip, the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the target moment satisfies the second preset sub-condition, it is determined that the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition;

[0038] The satisfaction of the second preset sub-condition includes at least one of the following:

[0039] When the values of the other input control signals flip, the value of the output signal remains unchanged;

[0040] When the value of the input control signal corresponding to the target segmented waveform signal flips, the value of the output signal changes in the next clock cycle.

[0041] In one embodiment, the satisfaction of the second preset condition includes any one of the following:

[0042] During the time period corresponding to the target segmented waveform signal, the values of the simulation waveform signals corresponding to no other input control signals flip; the other input control signal is any input control signal other than the target input control signal among the at least one input control signal;

[0043] During the time period corresponding to the target segmented waveform signal, the value of the simulation waveform signal corresponding to another input control signal flips, and when the value of the other input control signal that flips changes, the value of the output signal changes.

[0044] In one embodiment, determining whether the flip of the input control signal corresponding to the target segmented waveform signal is meaningful for controlling the target register further includes:

[0045] In response to there being no next flip moment for the simulation waveform signal corresponding to the target segmented waveform signal, it is determined that the flip action of the input control signal corresponding to the target segmented waveform signal is meaningful for controlling the target register.

[0046] In one embodiment, generating a redundant detection result for the target input control signal according to the obtained detection results of each of the segmented waveform signals includes:

[0047] According to the obtained detection results of each of the segmented waveform signals, determine the number of segmented waveform signals in the target input control signal that are meaningless for controlling the target register;

[0048] According to the number and the total number of segmented waveform signals in the target input control signal, determine the proportion of the segmented waveforms in the target input control signal that are meaningless for controlling the target register;

[0049] Generate a redundant detection result for the target input control signal based on the proportion.

[0050] In a second aspect, an embodiment of the present application provides a computing device, including: a processor and a memory storing a computer program. When the processor runs the computer program, the redundant control signal detection method described in the first aspect above is implemented.

[0051] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the redundant control signal detection method described in the first aspect above is implemented.

[0052] The redundant control signal detection method, computing device, and computer-readable storage medium provided by the embodiments of the present application perform redundant detection on each input control signal of the target register through the simulation data generated after functional simulation of the logic function code of the target chip, can conveniently and quickly locate the redundant points in the target chip, optimize the chip timing, reduce the chip area and power consumption, and at the same time improve the reliability of the chip design. Description of the Drawings

[0053] Figure 1 Schematic flowchart of the redundant control signal detection method provided in the first embodiment of the present application.

[0054] Figure 2 Schematic diagram of the process for analyzing whether the segmented signal is meaningful in the second embodiment of the present application Figure 1 。

[0055] Figure 3 Schematic diagram of the process for analyzing whether the segmented signal is meaningful in the second embodiment of the present application Figure 2 。

[0056] Figure 4 Schematic diagram of the simulation waveform in the second embodiment of the present application.

[0057] Figure 5 Schematic diagram of the structure of the computing device provided in the third embodiment of the present application. Detailed implementation manners

[0058] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0059] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0060] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this document, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining". Furthermore, as used in this document, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprising", "including" indicate the presence of the stated features, steps, operations, elements, components, items, kinds, and / or groups, but do not preclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are interpreted inclusively, or meaning either one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C". An exception to this definition occurs only when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0061] It should be understood that although the steps in the flowcharts in the embodiments of this application are shown sequentially in the direction of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear indication in this document, the execution of these steps has no strict order limitation and can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0062] It should be noted that in this document, step codes such as S101, S102, etc. are used. The purpose is to more clearly and briefly express the corresponding content and do not constitute a substantial limitation in terms of order. Those skilled in the art may execute S102 first and then S101, etc. during specific implementation, but these should all be within the protection scope of this application.

[0063] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0064] In the following description, suffixes such as "module", "component", or "unit" used to represent elements are only for the convenience of explaining the present application, and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0065] Refer to Figure 1 , which is a redundant control signal detection method provided by an embodiment of the present application. This redundant control signal detection method can be executed by a redundant control signal detection device provided by an embodiment of the present application. The redundant control signal detection device can be implemented in software and / or hardware. For example, it can be specifically a computing device such as a computer or a server. The redundant control signal detection method provided in this embodiment includes:

[0066] Step S101: Obtain simulation data generated after functional simulation of the logic function code of the target chip; the logic function code includes at least one input control signal and an output signal of the target register, and the simulation data includes simulation waveform signals corresponding to each input control signal and output signal in multiple clock cycles respectively.

[0067] Among them, the target chip can be any chip design to be detected. The logic function code of the target chip is used to describe the functions to be achieved by the target chip, and may include register transfer level (RTL, Register-Transfer Level) code. For example, it describes the input control signal and output signal of the register, as well as the actions of the register or the conditions for triggering the actions. There can be multiple registers designed in the logic function code corresponding to the target chip, and the logic function code of the target chip can correspondingly include the defined registers and at least one input control signal and output signal of the register. The target register is the register to be detected for redundant control signals, and all registers designed in the logic function code of the target chip can be tested. Here, by performing functional simulation on the logic function code of the target chip, simulation data including simulation waveforms corresponding to each input control signal and output signal of the target register in multiple clock cycles can be obtained. The size of the clock cycle can be set according to actual needs, such as 0.1s, etc., and no specific limitation is made here.

[0068] Step S102: Based on the simulation data, perform redundant detection on each input control signal; the redundant detection includes detecting the change relationship between the input control signal and the output signal to determine whether the input control signal is a redundant design.

[0069] In some embodiments, in the logic function code of the designed target chip, some input control signals of the designed register may be completely ineffective in the control of the register and become redundant control signals, or there are logical relationship constraints among multiple input control signals of the register, such that a certain input control signal may cause one or several other input control signals to become redundant control signals when controlling the register. Since the simulation data can represent the correlation between each input control signal and the output signal, therefore, based on the simulation data, redundancy detection can be performed on each input control signal of the target register.

[0070] Here, when performing redundancy detection on each input control signal based on the simulation data, the redundancy detection of each input control signal can be performed in combination with the simulation data based on the logical relationship between the input control signals determined by the logic function code of the target chip. Among them, since whether an input control signal is redundant can be characterized by the changes in the input control signal and the output signal, the change relationship between the input control signal and the output signal can be detected for redundancy detection.

[0071] In one implementation manner, performing redundancy detection on each input control signal based on the simulation data includes:

[0072] Determine the target input control signal of the target register;

[0073] Segment according to the flip moments of the simulation waveform signals corresponding to the target input control signal to obtain multiple segmented waveform signals corresponding to the target input control signal; the multiple segments of waveforms include the segmented waveform signals of each input control signal and the segmented waveform signal of the output signal;

[0074] Based on the simulation waveform signals corresponding to the multiple segmented waveforms, detect whether the control of the target register by the target input control signal corresponding to each segmented waveform signal is meaningful;

[0075] Generate a redundancy detection result for the target input control signal according to the obtained detection results for each segmented waveform signal.

[0076] Among them, the target input control signal can be any input control signal of the target register, generally the input control signal for which it is currently to be detected whether it is a redundant control signal. The simulation waveform signal is segmented according to the flip moment of the input control signal to obtain the segmented waveform signal corresponding to the time period from the current flip moment to the next flip moment. Segmenting the simulation waveform signal includes segmenting the clock signal, the input control signal, and the output signal. That is to say, the multiple segmented waveforms corresponding to the target input control signal can include the segmented waveform signal of the clock signal, the segmented waveform signals of each input control signal, and the segmented waveform signal of the output signal. Whether the control of the target register by the input control signal is meaningful means whether the input control signal can affect the output of the target register. That the control of the target register by the input control signal is meaningful means that the input control signal has an impact on the change of the output signal of the register. Generally, for the control of the target register by the input control signal to be meaningful, at least one of the following detection rules needs to be satisfied: The target input control signal shields the control of the target register by other input control signals of the target register, so that within the time period corresponding to the target input control signal, no matter how the other input control signals change, the output value of the target register does not change, that is, there is no flip; Open the control path of the target register by other input control signals of the target register, so that within the time period corresponding to the target input control signal, the change of the other input control signals affects the output value of the target register; This input control signal directly controls the output value of the target register, so that the output value of the target register will change following the change of this input control signal. Among them, for the control of the target register by the input control signal to be meaningless, the following detection rule needs to be satisfied: The target input control signal is shielded by other input control signals of the target register, so that within the time period corresponding to the target input control signal, no matter how the target input control signal changes, it does not affect the output value of the target register.

[0077] It can be understood that whether a certain input control signal is a redundant design can be judged by analyzing whether the input control signal plays a role in the control of the target register, and whether the input control signal plays a role in the control of the target register can be detected by specifically analyzing the change relationship between different input control signals and the output signal. Specifically, first, for any input control signal to be detected for redundant control signals, that is, the target input control signal, it is segmented according to the flip moment of the simulation waveform signal corresponding to the target input control signal to obtain a plurality of segmented waveform signals corresponding to the target input control signal; then, based on the logic function code, the simulation waveform signal corresponding to the output signal, and the simulation waveform signals of other input control signals, it is detected whether the input control signal corresponding to the segmented waveform signal has a meaningful control over the target register to obtain the detection results corresponding to each segmented waveform signal; finally, according to the obtained detection results of each segmented waveform signal, a redundant detection result for the target input control signal is generated. Among them, the redundant detection result can be used to represent the percentage of meaningful flips in the total number of flips of the target input control signal. The lower this percentage, the greater the probability that the target input control signal can be optimized.

[0078] In one embodiment, detecting whether the input control signal corresponding to each segmented waveform signal has a meaningful control over the target register includes:

[0079] Judging whether the redundant detection of each segmented waveform signal of the target input control signal is meaningful;

[0080] If it is meaningful, the segmented waveform signal is determined as the target segmented waveform signal, and it is detected whether the input control signal corresponding to the target segmented waveform signal has a meaningful control over the target register.

[0081] Among them, the detection of the target segmented waveform signal is used to detect whether the corresponding input control signal has a meaningful control over the target register. It can be understood that since the number of segmented waveform signals obtained after segmenting the target input control signal may be large, in order to improve the efficiency of redundant detection, it can be first judged whether the redundant detection of the segmented waveform signal is meaningful. If the redundant detection of the segmented waveform signal is meaningful, the segmented waveform signal is determined as the target segmented waveform signal, and it is detected whether the input control signal corresponding to the target segmented waveform signal has a meaningful control over the target register; if the redundant detection of the segmented waveform signal is meaningless, it can be considered that the input control signal corresponding to the segmented waveform signal has no meaningful control over the target register.

[0082] In one embodiment, judging whether the redundant detection of each segmented waveform signal of the target input control signal is meaningful includes:

[0083] If it is detected that the number of flips of the simulation waveform signal of the target input control signal within one clock cycle is even, it is determined that the redundant detection of the multiple segmented waveform signals corresponding to the even-numbered flips is meaningless;

[0084] If it is detected that the number of flips of the simulation waveform signal corresponding to the target input control signal within one clock cycle is odd, it is determined that the redundant detection of the last segmented waveform signal within one clock cycle is meaningful.

[0085] Specifically, when it is detected that the simulation waveform signal corresponding to the target input control signal has multiple flips within one clock cycle, it is judged whether the number of flips is even. If the number of flips is even, it is equivalent to no flip for the next register within one clock cycle. After segmenting the target input control signal according to the flip moments of the waveform signal, it is determined that the redundant detection of the multiple segmented waveform signals corresponding to the even-numbered flips is meaningless; if the number of flips is odd, after segmenting the target input control signal according to the flip moments of the waveform signal, it is determined that the redundant detection of the last segmented waveform signal within one clock cycle is meaningful, and at the same time, it can be determined that the redundant detection of the segmented waveform signals other than the last segmented waveform signal within this clock cycle is meaningless.

[0086] In this way, according to the different numbers of flips, the segmentation result of the target input control signal can be correspondingly determined, which is convenient and fast, and improves the efficiency and accuracy of the redundant control signal detection.

[0087] In an embodiment, detecting whether the input control signal corresponding to the target segmented waveform signal is meaningful for controlling the target register includes:

[0088] Based on the simulation waveform signal corresponding to the target segmented waveform signal, judging whether the flip action of the input control signal corresponding to the target segmented waveform signal is meaningful for controlling the target register, and / or judging whether the value after the flip of the input control signal corresponding to the target segmented waveform signal is meaningful for controlling the target register.

[0089] Among them, whether the control of the target register is meaningful is used to determine whether the target input control signal directly controls the target register or shields or opens the control channel of other control signals for the target register. Here, the target input control signal directly controlling the target register means that the target input control signal directly controls the value of the output signal of the target register, so that the value of the output signal of the target register will change following the change of the target input control signal. The target input control signal shielding other control signals means that the target input control signal shields the control of other input control signals of the target register over the target register, so that within the time period corresponding to the target input control signal, no matter how other input control signals change, the value of the output signal of the target register will not change, that is, there will be no flip. The target input control signal opening the control path of other control signals for the target register means that within the time period corresponding to the target input control signal, the change of other input control signals affects the value of the output signal of the target register.

[0090] Here, whether the control of the target register by the input control signal corresponding to the target segmented waveform signal is meaningful can include whether the flip action of the input control signal corresponding to the target segmented waveform signal on the target register is meaningful, and whether the value after the flip of the input control signal corresponding to the target segmented waveform signal on the target register is meaningful. When the flip action of the input control signal corresponding to the target segmented waveform signal on the target register is meaningful, it can be defaulted that the control of the target register by the input control signal corresponding to the target segmented waveform signal is meaningful. Among them, determining whether the flip action of the input control signal corresponding to the target segmented waveform signal on the target register is meaningful and determining whether the value after the flip of the input control signal corresponding to the target segmented waveform signal on the target register is meaningful can be determined based on the detection rules for whether the input control signal is meaningful or not for the target register mentioned above.

[0091] In one embodiment, determining whether the flip action of the input control signal corresponding to the target segmented waveform signal on the target register is meaningful includes: determining whether the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies a first preset condition for the control of the target register;

[0092] If it is satisfied, it is determined that the flip action of the input control signal corresponding to the target segmented waveform signal on the target register is meaningful; the first preset condition is used to determine whether the target input control signal directly controls the target register or shields or opens the control channel of other control signals for the target register.

[0093] Specifically, for any target segmented waveform signal to be analyzed, based on the simulation waveform signal corresponding to the output signal and the simulation waveform signals corresponding to the respective input control signals, first determine whether the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies a first preset condition. If the first preset condition is satisfied, it is determined that the flip action of the input control signal corresponding to the target segmented waveform signal has a meaning for the control of the target register. Among them, the first preset condition can be specifically set according to actual needs.

[0094] In one embodiment, it further includes:

[0095] When the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment does not satisfy the first preset condition, determine whether the value after the flip of the input control signal corresponding to the target segmented waveform signal satisfies a second preset condition for the control of the target register; the second preset condition is used to determine whether the target input control signal cannot directly control the target register or shields or opens the control channel of other control signals for the target register.

[0096] When the value after the flip of the input control signal corresponding to the target segmented waveform signal satisfies the second preset condition for the control of the target register, determine that the flip action of the input control signal corresponding to the target segmented waveform signal has no meaning for the control of the target register.

[0097] Among them, when the value after the flip of the input control signal corresponding to the target segmented waveform signal satisfies the second preset condition for the control of the target register, determine that the flip action of the input control signal corresponding to the target segmented waveform signal has no meaning for the control of the target register, and when the value after the flip of the input control signal corresponding to the target segmented waveform signal does not satisfy the second preset condition for the control of the target register, it can be determined that the flip action of the input control signal corresponding to the target segmented waveform signal has a meaning for the control of the target register. Among them, the first preset condition is used to evaluate whether the flip of the target segmented waveform signal at the flip moment has a meaning for the control of the target register, and the second preset condition is used to evaluate whether the value after the flip in the target segmented waveform signal has no meaning for the control of the target register, which can be specifically set according to actual needs.

[0098] In one embodiment, the first preset condition includes a first preset sub - condition; determining whether the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition includes:

[0099] Determine the target moment when the input control signal corresponding to the target segmented waveform signal flips;

[0100] Determine whether the value of the simulation waveform signal corresponding to the output signal flips within the next clock cycle after the target moment;

[0101] When it is determined that the value of the simulation waveform signal corresponding to the output signal flips, if the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the target moment satisfies the first preset sub-condition, it is determined that the control of the target register by the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition;

[0102] Satisfying the first preset sub-condition includes at least one of the following:

[0103] The value of the output signal changes following the change of the value of the input control signal corresponding to the target segmented waveform signal;

[0104] When the value of the input control signal corresponding to the target segmented waveform signal is a preset value and the values of other input control signals change, the value of the output signal changes; the other input control signals are any of the input control signals other than the target input control signal in at least one input control signal.

[0105] It can be understood that when a segmented waveform signal of a certain input control signal flips and other input control signals do not flip, if the output signal also flips accordingly, it indicates that the change in this input control signal affects the output of the target register, that is, the flip of this segmented waveform signal at the flip moment is meaningful for the control of the target register. If the output signal does not flip accordingly, it indicates that the change in this input control signal does not affect the output of the target register, that is, the flip of this segmented waveform signal at the flip moment is meaningless for the control of the target register. Based on this, it can be determined whether the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition for the control of the target register. Specifically, for any target segmented waveform signal to be analyzed, first determine the target moment when the input control signal corresponding to the target segmented waveform signal flips. Then, judge whether the value of the simulation waveform signal corresponding to the output signal flips within the next clock cycle after the target moment, that is, judge whether the value of the simulation waveform signal corresponding to the output signal flips within the time range of adding one clock cycle to the target moment. Then, when it is determined that the value of the simulation waveform signal corresponding to the output signal flips, it indicates that the value of the simulation waveform signal corresponding to the output signal flips accordingly following the flip of the input control signal corresponding to the target segmented waveform signal. At this time, continue to judge whether the flip of the input control signal corresponding to the target segmented waveform signal at the target moment satisfies the first preset sub-condition. If the first preset sub-condition is satisfied, it indicates that the flip of the input control signal corresponding to the target segmented waveform signal at the target moment is meaningful for the output signal, and it is determined that the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition; if the first preset sub-condition is not satisfied, it indicates that the flip of the input control signal corresponding to the target segmented waveform signal at the target moment is meaningless for the output signal, and it is determined that the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment does not satisfy the first preset condition.

[0106] Here, when the value of the output signal changes following the value of the input control signal corresponding to the target segmented waveform signal, it indicates that the input control signal corresponding to the target segmented waveform signal directly controls the output value of the target register, such that the output value of the target register changes following the change of the input control signal corresponding to the target segmented waveform signal. When the value of the input control signal corresponding to the target segmented waveform signal is a preset value and the values of other input control signals change, and the value of the output signal changes, it indicates that the input control signal corresponding to the target segmented waveform signal opens the control path of other input control signals of the target register to the target register. Among them, the preset value can be specifically determined in combination with the association relationship between different input control signals and the output signal. For example, when the output signal is determined after performing a logical AND operation on the target input control signal and other input control signals, the preset value can be the binary number 1, etc.

[0107] In one embodiment, the first preset condition includes a second preset sub-condition; determining whether the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition includes:

[0108] If it is determined that the value of the simulation waveform signal corresponding to the output signal does not flip, and the flip of the input control signal corresponding to the target segmented waveform signal at the target moment satisfies the second preset sub-condition, then it is determined that the flip of the input control signal corresponding to the target segmented waveform signal at the flip moment satisfies the first preset condition;

[0109] Satisfying the second preset sub-condition includes at least one of the following:

[0110] When the values of other input control signals flip, the value of the output signal remains unchanged;

[0111] When the value of the input control signal corresponding to the target segmented waveform signal flips, the value of the output signal changes in the next clock cycle.

[0112] Specifically, when it is determined that the value of the simulation waveform signal corresponding to the output signal has not flipped, it indicates that the value of the simulation waveform signal corresponding to the output signal has not flipped correspondingly following the flip of the input control signal corresponding to the target segmented waveform signal. At this time, continue to determine whether the flip of the input control signal corresponding to the target segmented waveform signal at the target time satisfies the second preset sub-condition. If the second preset sub-condition is satisfied, it indicates that the flip of the input control signal corresponding to the target segmented waveform signal at the target time is meaningful to the output signal, and it is determined that the flip of the input control signal corresponding to the target segmented waveform signal at the flip time satisfies the first preset condition; if the second preset sub-condition is not satisfied, it indicates that the flip of the input control signal corresponding to the target segmented waveform signal at the target time is meaningless to the output signal, and it is determined that the flip of the input control signal corresponding to the target segmented waveform signal at the flip time does not satisfy the first preset condition. Among them, when the values of other input control signals flip, the value of the output signal remains unchanged, that is, the value of the output signal does not change in the next clock cycle, indicating that the input control signal corresponding to the target segmented waveform signal shields the control of other input control signals of the target register on the target register. When the value of the input control signal corresponding to the target segmented waveform signal flips, the value of the output signal changes in the next clock cycle, indicating that the input control signal corresponding to the target segmented waveform signal is not shielded by other input control signals of the target register.

[0113] In one embodiment, satisfying the second preset condition includes any one of the following:

[0114] During the time period corresponding to the target segmented waveform signal, the values of the simulation waveform signals corresponding to no other input control signals flip; the other input control signal is any one of the at least one input control signal other than the target input control signal;

[0115] During the time period corresponding to the target segmented waveform signal, the values of the simulation waveform signals corresponding to other input control signals flip, and when the values of the other input control signals that flip change, the value of the output signal changes.

[0116] Among them, within the time period corresponding to the target segmented waveform signal, the values of the simulation waveform signals corresponding to other input control signals do not flip, and the functions of other signals are not turned on or shielded. It can be directly determined that the control of the input control signal corresponding to the target segmented waveform signal over the target register is meaningless. Within the time period corresponding to the target segmented waveform signal, the values of the simulation waveform signals corresponding to other input control signals flip, and when the values of the other input control signals that flip change, the value of the output signal changes, indicating that within the time period corresponding to the target segmented waveform signal, the flips of the other input control signals that flip are not shielded by the input control signal corresponding to the target segmented waveform signal, so that within the time period corresponding to the target segmented waveform signal, the changes in the other input control signals affect the output value of the target register.

[0117] In one embodiment, determining whether the flip action of the input control signal corresponding to the target segmented waveform signal is meaningful for controlling the target register further includes:

[0118] In response to the simulation waveform signal corresponding to the target segmented waveform signal having no next flip moment, it is determined that the flip action of the input signal corresponding to the target segmented waveform signal is meaningful for controlling the target register.

[0119] Among them, when the simulation waveform signal corresponding to the target segmented waveform signal has no next flip moment, it indicates that the analysis end moment of the target segmented waveform signal is reached, and the input control signal corresponding to this signal has not undergone the next flip yet, so it is defaulted that the control of the input control signal corresponding to the target segmented waveform signal over the target register is meaningful.

[0120] In one embodiment, generating a redundant detection result for the target input control signal according to the obtained detection results of each segmented waveform signal includes:

[0121] According to the obtained detection results of each segmented waveform signal, determine the number of segmented waveform signals in the target input control signal that are meaningless for controlling the target register;

[0122] According to the number and the total number of segmented waveform signals in the target input control signal, determine the proportion of the segmented waveform signals in the target input control signal that are meaningless for controlling the target register;

[0123] Generate a redundant detection result for the target input control signal based on the proportion.

[0124] Specifically, after obtaining the detection results of each segmented waveform signal in the target input control signal, according to the results of whether the control of the target register by the corresponding segmented waveform signal included in each detection result is meaningful, count the number of segmented waveform signals in the target input control signal that are meaningless for the control of the target register, and then combine the total number of segmented waveform signals in the target input control signal to determine the proportion of the segmented waveform signals in the target input control signal that are meaningless for the control of the target register. Furthermore, generate a redundancy detection result for the target input control signal based on this proportion.

[0125] Among them, the proportion can specifically be a percentage, etc., and no specific limitation is made here. In addition, it is also possible to count the number of segmented waveform signals in the target input control signal that are meaningful for the control of the target register according to the obtained detection results of each segmented waveform signal, and then combine the total number of segmented waveform signals in the target input control signal to determine the proportion of the segmented waveform signals in the target input control signal that are meaningful for the control of the target register, and further generate a redundancy detection result for the target input control signal based on this proportion. It should be noted that the redundancy detection result can be used to evaluate the possibility that the target input control signal is a redundant control signal, and specifically can include information such as this proportion. Here, the redundancy detection result can include the number of segmented waveform signals in the target input control signal that are meaningful for the control of the target register, and / or the number of segmented waveform signals in the target input control signal that are meaningless for the control of the target register, and / or the proportion between the number of segmented waveform signals in the target input control signal that are meaningful for the control of the target register and the total number of segmented waveform signals of the target input control signal, etc.

[0126] In this way, through the number of segmented waveform signals in the target input control signal that are meaningful or meaningless for the control of the target register, a redundancy detection result for the target input control signal is obtained, with convenient operation and high accuracy, improving the efficiency and accuracy of redundant control signal detection.

[0127] Step S103: Output the obtained redundancy detection result.

[0128] Specifically, after performing redundancy detection on each input control signal to obtain the corresponding redundancy detection result, the redundancy detection result can be output, so that based on this redundancy detection result, it can be used to assist in finding redundant points or existing conflict information in the logic function code of the target chip, etc. It should be noted that the redundancy detection result can be used to assist in judging whether there are redundant control signals in each input control signal of the target register. Among them, when the redundancy detection result includes the proportion of the segmented waveform signals in the target input control signal that are meaningless for the control of the target register, the larger this proportion, the higher the probability that the target input control signal is a redundant control signal for the target register.

[0129] In summary, in the redundant control signal detection method provided by the above embodiments, the simulation data generated after functional simulation of the logic function code of the target chip is used to perform redundant detection on each input control signal of the target register, which can conveniently and quickly locate the redundant points in the target chip, optimize the chip timing, reduce the chip area and power consumption, and improve the reliability of the chip design at the same time.

[0130] Based on the same inventive concept as the foregoing embodiments, the foregoing embodiments will be described in detail below through a specific example. In this example, the register to be analyzed is C (it can also be said that C is the output signal of the register to be analyzed), and its input control signals are divided into two categories. One category is the input control signal A to be analyzed, and the other category is the remaining input control signal B. The redundant control signal detection method provided in this example mainly includes the following parts:

[0131] I. Definition of detection rules

[0132] 1) According to the simulation waveform, each input control signal of the register is analyzed in segments according to the flip time. The meaning of each segment of the signal (each segment of the signal refers to the signal corresponding to the time from the flip time of the signal until the next flip) for the register it controls can be divided into: a. Mask the control of the remaining input control signals of the register on the register, so that no matter how the remaining input control signals change during the analysis period, the output of the register does not change. For example, C <= A & B, when A is 0, the meaning of A for C is to mask the effect of signal B on C; for example, C <= A | B, when A is 1, the meaning of A for C is to mask the effect of signal B on C. b. Open the control path of the remaining input control signals of the register to the register, so that the changes of the remaining input control signals of the register can affect the output of the register in a timely manner. For example, C <= A & B, when A is 1, the meaning of A for C is to open the control path from B to C; for example, C <= A | B, when A is 0, the meaning of A for C is to open the control path from B to C. c. As an input signal, directly control the output value of the register, and the output of the register will change with the change of the analysis signal. For example, C <= A & B, when the value of B is 1, C changes with the change of A. At this time, the meaning of A for C is to directly control the output of C as an input signal; for example, C <= A | B, when B is 0, C changes with the change of A. d. Masked by the remaining input control signals of the register (no matter how the analysis signal changes during the analysis period, it will not affect the output of the register. For example, C <= A & B, when the value of B is 0, at this time A is masked by B; for example, C <= A | B, when B is 1, at this time A is masked by B) and has no meaning for the register. When performing logical analysis, the input control signals to be analyzed in the logic function code can be assigned values to observe the change of the output signal of the register to determine whether the flip or value of the input control signal is meaningful to the register.

[0133] 2) Except when it is determined through logical analysis that this flip and the value after the flip are meaningless to the register being controlled, by default, all flips that cannot be confirmed have significance for the register. For example, when performing segmented analysis on the input control signal of the register, if the segmentation is incomplete (such as the signal has not flipped again by the end of the waveform analysis), it is defaulted that this segment has significance for the register, or after logical analysis, it cannot be confirmed whether it has significance for the register.

[0134] 3) Between two clock active edges of the register, if an input control signal has flipped greater than or equal to two times, if the input control signal flips an even number of times, then all flips and their values are meaningless; if the input control signal flips an odd number of times, then all flips and their values except the last flip are meaningless, and whether the last flip and the value after the last flip are meaningful needs to be analyzed in combination with the above rules.

[0135] 4) When a certain segment of the input control signal of the register is analyzed as being meaningless to the register, this segment of meaningless signal includes the flip at the segmentation start point, the value after the flip, and the flip in the opposite direction to the start point flip at the end of this segment value (as shown in the analysis of the first flip of the state[0] signal in the following example).

[0136] 5) Analyzing whether a certain segment of the input control signal is meaningful to the register includes analyzing whether the starting flip of this segment is meaningful to the register and whether the value after the flip is meaningful to the register.

[0137] II. Analysis Principle

[0138] Analyzing whether a segmented signal is meaningful mainly includes the following two parts:

[0139] 1) Analyze whether the flip at the start time of each segment has significance for the register. The start time of each segment refers to the time F when the input control signal A flips. Refer to Figure 2 , and mainly includes the following steps:

[0140] Step S201: Determine the time F of the flip in the segmented signal of the current analysis of A.

[0141] Among them, the segmented signal of the current analysis of A refers to the segmented signal currently being analyzed after segmenting A.

[0142] Step S202: Determine whether C flips within one clock cycle after time F. If so, execute Step S203; otherwise, execute Step S206.

[0143] Step S203: Determine whether A directly controls the output value of the register as an input control signal. If so, execute Step S205; otherwise, execute Step S204.

[0144] Step S204: Determine whether A opens the control path of B to the register. If so, execute Step S205; otherwise, execute Step S208.

[0145] Step S205: Determine that the flip in the segmented signal of the current analysis of A is meaningful to the register.

[0146] Step S206: Determine whether A masks the driving of the signal in B to the register. If so, execute Step S205; otherwise, execute Step S207.

[0147] Step S207: Determine whether A is masked by the signal in B. If so, execute Step S208; otherwise, execute Step S205.

[0148] Step S208: Determine that the flip in the segmented signal of the current analysis of A is meaningless to the register.

[0149] Among them, the methods for determining whether A directly controls the output value of the register as an input control signal, whether A opens the control path of B to the register, whether A masks the driving of the signal in B to the register, and whether A is masked by the signal in B can be specifically referred to the above detection rules and will not be elaborated here.

[0150] 2) If the result of the above judgment is that the flip in the segmented signal of the current analysis of A is meaningless to the register, then continue to analyze whether the value after the flip of A within this time period is meaningful to the register. Refer to Figure 3 , which mainly includes the following steps:

[0151] Step S301: Determine the time period where the segmented signal of the current analysis of A is located.

[0152] Among them, the segmented signal of the current analysis refers to the segmented signal currently being analyzed after segmenting A. The time period where the segmented signal is located refers to the time range corresponding to this segmented signal, which can be specifically characterized by the position and quantity of the clock cycles experienced by this segmented signal. For example, the time range from the 3rd clock cycle to the 6th clock cycle.

[0153] Step S302: Determine whether there is a signal flip in B within this time period. If so, execute Step S303; otherwise, execute Step S306.

[0154] Step S303: Determine whether A opens the control path of the flipped signal in B to the register. If so, execute Step S305; otherwise, execute Step S304.

[0155] Step S304: Determine whether each flip of each signal in B within this time period is masked by A. If so, execute Step S305; otherwise, execute Step S306.

[0156] Step S305: Determine that the value after A is flipped is meaningful to the register.

[0157] Step S306: Determine that the value after A is flipped is meaningless to the register.

[0158] Among them, the method for determining whether the value after A is flipped is meaningful to the register can be specifically referred to the above detection rules, which will not be elaborated here.

[0159] After the above two processes, if the conclusion is that A is meaningless to the register in both cases, it can be concluded that the current segmented signal of A is meaningless to the register. Finally, the probability that the A signal is a redundant signal to the register is calculated by analyzing whether each segmented signal of A in the simulation waveform file is meaningless to the register.

[0160] The following is illustrated through a specific scenario. Refer to Figure 4 , which is the simulation waveform of the input control signal and output signal of the register to be analyzed. From top to bottom, each signal is the clock signal: clk, input signals: rst_n, fpga2dsp_data_shift[7], state[3:0], cnt[3:0], rd_flag[1:0], and the output signal sda_out. Among them, A is the input control signal to be analyzed (for example, rst_n is A when analyzing the rst_n signal), B is the remaining input driving signals of the register (for example, B is fpga2dsp_data_shift[7], state[3:0], cnt[3:0], and rd_flag[1:0] when analyzing rst_n), and C is the output signal of the register to be analyzed (in this example, sda_out is C). The specific analysis is as follows:

[0161] (1) rst_n signal

[0162] During the entire simulation time, this signal does not flip. According to the input control analysis of sda_out, its value 1 has a significant meaning for sda_out (that is, it opens the control path of the remaining input driving signals to this register).

[0163] (2) fpga2dsp_data_fhift[7] signal

[0164] The signal did not flip throughout the simulation time. According to the analysis of the input control of sda_out, its value of 0 has a significance for the existence of sda_out (at the first analysis time of state[3] and the second analysis time of cnt[0], the control path from fpga2dsp_data_shift[7] to sdsa_out was opened, and during this time period, the value of fpga2dsp_data_shift[7] directly controlled the value of sda_out).

[0165] (3) state[3] signal

[0166] For the first segment of the analysis waveform, at the next valid edge of clk after the flip moment of F, sda_out did not flip. After logical analysis, this flip of the state[3] signal was masked by the cnt and rd_flag signals respectively. Therefore, this flip of the state[3] signal has no significance for the existence of sda_out. During the period when the value of state[3] was 1 after the flip, first, the flips of cnt[3] and cnt[0] were encountered. After logical analysis, state[3] neither opened the control paths of these two signals to sda_out nor masked these two signals. Then, the flip of cnt[0] was encountered. After logical analysis, when the value of state[3] was 1, it opened the control path of cnt to sda_out. Therefore, this value has a significance for the existence of sda_out. So, the first segment of the waveform of A is significant for C.

[0167] Since the second segment of the analysis waveform is incomplete (without the next flip, the end point cannot be determined, and it cannot be determined that its value has no significance for the existence of sda_out at all times before the end of this segment of the waveform), it is defaulted to be significant.

[0168] (4) state[2] signal

[0169] Since the first segment of the analysis waveform is incomplete (without the next flip, the end point cannot be determined, and thus it cannot be determined whether it has a significance for the existence of sda_out), it is defaulted to be significant.

[0170] (5) state[1] signal

[0171] The first paragraph analyzes the waveform. At the next valid edge of clk when F flips, sda_out does not flip. Through logical analysis, this flip is masked by cnt. Therefore, the flip of the state[1] signal has no significance for sda_out this time. During the period when the value of state[1] is 0 after flipping, cnt[3] and cnt[0] flip first. Through the logical expression analysis of sda_out, state[1] neither opens the control path of these two signals to sda_out nor masks these two signals. Then cnt[0] flips. Through the logical expression analysis of sda_out, the value 0 of state[1] opens the control path of cnt to sda_out. Therefore, this value has significance for sda_out.

[0172] The second paragraph analyzes the waveform. At the next valid edge of clk when F flips, sda_out does not flip. Through the logical expression analysis of sda_out, this flip is masked by cnt. Therefore, the flip of the state[1] signal has no significance for sda_out this time. During the period when the value of state[1] is 1 after flipping, cnt[3:0] and rd_flag[1:0] flip successively. Through the logical expression analysis of sda_out, state[1] opens the control path from cnt to sda_out, resulting in the flip of sda_out. Therefore, this value has significance for sda_out.

[0173] The third paragraph analyzes the waveform. Since it is incomplete (the end point cannot be determined without the next flip), it is defaulted to be significant.

[0174] (6)state[0] signal

[0175] The first paragraph analyzes the waveform. At the next valid edge of clk when it flips, sda_out does not flip. Through the logical expression analysis of sda_out, this flip is masked. Therefore, the flip of the state[0] signal has no significance for sda_out this time. During the period when the value of state[0] is 1 after flipping, the other input control signals of sda_out do not flip. Therefore, the first paragraph analysis waveform of state[0] has no significance for sda_out, including the upward flip of state[0] at the analysis start point, the value 1 after the upward flip, and the subsequent downward flip.

[0176] (7)cnt[3] signal

[0177] The first paragraph analyzes the waveform. Through logical analysis, its upward flip is masked and has no significance for sda_out. However, the value after flipping masks the flips of cnt[0] and state[3] in the logical expression of sda_out. Therefore, it has significance.

[0178] The waveform of the second paragraph is analyzed. After logical analysis, its flip is masked, but the value after the flip opens the control path of cnt[2:0] to sda_out. Therefore, its value has a meaningful existence.

[0179] Similarly, the waveforms of the second to ninth paragraphs also have a meaningful existence.

[0180] The waveform of the tenth paragraph is default to be meaningful because there is no next flip.

[0181] (8)cnt[2] signal

[0182] For the waveform of the first paragraph, after logical analysis, both its flip and the value after the flip are masked. Therefore, this section of the waveform has no meaningful existence for sda_out, including the flip at the starting point of this section, the value after the flip, and the ending flip.

[0183] For the waveform of the second paragraph, since the flip at its starting point is confirmed to be meaningless in the first paragraph and does not need to be analyzed.

[0184] For the waveform of the third paragraph, its starting flip is masked, but the value after the flip participates in opening the control path of cnt[0] or cnt[3] to sda_out. Therefore, it has a meaningful existence for sda_out.

[0185] Similarly, the waveforms of the fourth to seventh paragraphs are also meaningful.

[0186] For the waveform of the eighth paragraph, after logical analysis, both its flip and the value after the flip are masked. Therefore, this section of the waveform has no meaningful existence for sda_out, including the flip at the starting point of this section, the value after the flip, and the ending flip.

[0187] (9)cnt[1] signal

[0188] For the waveform of the first paragraph, after logical analysis, both its flip and the value after the flip are masked. Therefore, this section of the waveform has no meaningful existence for sda_out, including the flip at the starting point of this section, the value after the flip, and the ending flip

[0189] For the waveform of the second paragraph, since the flip at its starting point is confirmed to be meaningless in the first paragraph and does not need to be analyzed.

[0190] For the waveform of the third paragraph, after logical analysis, both its flip and the value after the flip are masked. Therefore, this section of the waveform has no meaningful existence for sda_out, including the flip at the starting point of this section, the value after the flip, and the ending flip.

[0191] For the waveform of the fourth paragraph, since the flip at its starting point is confirmed to be meaningless in the third paragraph and does not need to be analyzed.

[0192] The waveform of the 5th paragraph is analyzed. After analysis, the control path from cnt[3] or cnt[1] to sda_out is opened, so it has a significance for existence.

[0193] The waveform of the 6th paragraph is analyzed. It has a significance for existence, similar to the waveform analysis of the 5th paragraph.

[0194] The waveform of the 7th paragraph is analyzed. It is meaningless, just like the waveform analysis of the 3rd paragraph.

[0195] The waveform of the 8th paragraph is analyzed. Since its starting point flip is confirmed to be meaningless in the 7th paragraph and thus does not need to be analyzed.

[0196] The waveforms of the 9th and 10th paragraphs are analyzed. They have a significance for existence, similar to the waveform analysis of the 5th and 6th paragraphs.

[0197] The waveforms of the 11th and 12th paragraphs are analyzed. The results are the same as those of the waveform analysis of the 7th and 8th paragraphs.

[0198] The waveform of the 13th paragraph is analyzed. After analysis, the control path from cnt[3] or cnt[1] to sda_out is opened, so it has a significance for existence.

[0199] The waveforms of the 14th to 17th paragraphs are analyzed. They are all masked and meaningless.

[0200] (10)cnt[0] signal

[0201] It can be known through analysis that the waveform analyses of the 1st, 2nd, 3rd, 4th, 11th, 12th, 13th, 14th, 21st, 22nd, 23rd, 24th, 31st, 32nd, 39th, and 40th paragraphs all have a significance for existence, while the 5th, 6th, 7th, 8th, 9th, 10th, 15th, 16th, 17th, 18th, 19th, 20th, 25th, 26th, 27th, 28th, 29th, 30th, 33rd, 34th, 35th, 36th, 37th, and 38th paragraphs have no significance for existence.

[0202] (11)rd_flag[1] signal

[0203] The waveform of the 1st paragraph is analyzed. Through logical analysis, its flip is masked. The value after the flip is neither used to mask the remaining input control signals nor to open the control path of the remaining input control signals to sda_out. Therefore, the waveform of this paragraph of rd_flag[1] has no significance for sda_out, including the upward flip at the beginning of this paragraph, the value 1 after the upward flip, and the subsequent downward flip.

[0204] (12)rd_flag[0] signal

[0205] The waveform of the 1st paragraph is analyzed. Since there is no end point, it is defaulted to have a significance for existence.

[0206] As can be seen from the above, all the flips and their values of rst_n / fpga2dsp_data_fhift[7] / state[3] / state[2] / state[1] / cnt[3] / rd_flag[0] in the entire analysis waveform are meaningful to sda_out, so they are 100% meaningful in the entire analysis; all the flips of state[0] / rd_flag[1] in the entire analysis waveform are meaningless, so they are 0% meaningful in the entire analysis; cnt[2] is meaningless in 4 out of 9 flips in the entire analysis waveform, so it is 55.56% meaningful; cnt[1] is meaningless in 12 out of 17 flips in the entire analysis waveform, so it is 29.4% meaningful; cnt[0] is meaningless in 24 out of 40 flips in the entire analysis waveform, so it is 40% meaningful. Here, the smaller the percentage of meaningful flips, the higher the probability that the signal is a redundant point or there is a conflict in the control of the register. Whether it is a redundant point specifically needs to be further confirmed by the designer.

[0207] Here, according to the confirmation of the register transfer level (RTL) code returned by the analysis result, the state state machine uses one-hot encoding, and state[0] is indeed a redundant signal. The situation where rd_flag[1] and rd_flag[0] are both 1 is also restricted in the code. Therefore, rd_flag[1] is indeed a redundant signal, and this redundant signal can be removed from the register transfer level (RTL) code, thereby reducing the chip area and leakage current power consumption.

[0208] In summary, by reading in the register transfer level (RTL) code of the digital chip and its simulation waveform, combining the signal simulation waveform and its logic code, automatically analyzing whether each flip and the value after the flip of each input control signal of each register are meaningful to the register, and statistically analyzing the percentage of meaningful flips of the input control signals of each register in the analysis waveform accounting for their total number of flips (if there is no flip, analyze whether its value is meaningful to the register. If it is meaningful, it is 100%, otherwise it is 0%). The lower this percentage, the greater the probability that the signal can be optimized. The possible redundant points in the digital chip design can be quickly locked according to the detection results (since it is default in this embodiment that it cannot be determined whether the uncertain meaningful flips are all meaningful to the register, so the signals with low percentages in the detection results are all suspicious points). By analyzing these suspicious points, the redundant points or existing conflicts in the logic function code can be quickly found, greatly reducing the time and effort required to search for these points in the entire design analysis, thereby making it feasible to optimize the redundant points in the register input control signals of increasingly complex digital chips.

[0209] Based on the same inventive concept as the foregoing embodiments, an embodiment of the present invention provides a computing device, such as Figure 5As shown, the computing device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 5 The processor 310 shown in Figure 5 does not refer to the number of processors 310 being one, but only refers to the positional relationship of the processor 310 relative to other components. In practical applications, the number of processors 310 can be one or more; similarly, Figure 5 The memory 311 shown in Figure 5 has the same meaning, that is, it only refers to the positional relationship of the memory 311 relative to other components. In practical applications, the number of memories 311 can be one or more. When the processor 310 runs the computer program, the redundant control signal detection method applied to the above computing device is implemented.

[0210] The computing device may further include: at least one network interface 312. Each component in the electronic device is coupled together through a bus system 313. It can be understood that the bus system 313 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 5 all kinds of buses are labeled as the bus system 313.

[0211] Among them, the memory 311 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), an erasable programmable read-only memory (EPROM, Erasable Programmable Read-Only Memory), an electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), a ferromagnetic random access memory (FRAM, ferromagnetic random access memory), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM, Compact Disc Read-Only Memory); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM, Random Access Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as a static random access memory (SRAM, Static Random Access Memory), a synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory), a dynamic random access memory (DRAM, Dynamic Random Access Memory), a synchronous dynamic random access memory (SDRAM, Synchronous Dynamic Random Access Memory), a double data rate synchronous dynamic random access memory (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory), an enhanced synchronous dynamic random access memory (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), a sync link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), a direct rambus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 311 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memories.

[0212] The memory 311 in the embodiments of the present invention is used to store various types of data to support the operation of the computing device. Examples of such data include: any computer programs for operating on the computing device, such as an operating system and application programs; contact data; phone book data; messages; pictures; videos, etc. Among them, the operating system contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application programs can include various application programs, such as a Media Player, a Browser, etc., for implementing various application services. Here, the program for implementing the method of the embodiments of the present invention can be included in the application programs.

[0213] Based on the same inventive concept as the foregoing embodiments, this embodiment also provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium. The computer-readable storage medium can be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it can also be various devices including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the computer-readable storage medium is run by a processor, the above redundant control signal detection method is implemented. For the specific step flow implemented when the computer program is executed by the processor, please refer to Figure 1 the description of the illustrated embodiments, which will not be repeated here.

[0214] The technical features of the above-described embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0215] In this text, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, which includes not only those elements listed, but also other elements not expressly listed.

[0216] As described above, it is only a specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described.

Claims

1. A redundant control signal detection method, characterized in that: The method comprises: Acquire simulation data generated after functional simulation of the logic function code of the target chip; the logic function code includes at least one input control signal and an output signal of the target register, and the simulation data includes simulation waveform signals corresponding to each of the input control signal and the output signal in multiple clock cycles; Based on the simulation data, redundancy detection is performed on each of the input control signals; the redundancy detection includes detecting a change relationship between the input control signal and the output signal; Output the obtained redundant detection results; The redundant detection of each input control signal based on the simulation data includes: determining whether the flipping action of the input control signal corresponding to the simulation waveform signal is meaningful to the control of the target register, and / or determining whether the flipped value of the input control signal corresponding to the simulation waveform signal is meaningful to the control of the target register.

2. The method according to claim 1, characterized in that The performing redundancy detection on each of the input control signals based on the simulation data includes: determining a target input control signal of the target register; Segmenting the simulation waveform signal corresponding to the target input control signal according to the flipping moment to obtain a plurality of segmented waveform signals corresponding to the target input control signal; the plurality of segmented waveforms include the segmented waveform signals of the input control signals and the segmented waveform signals of the output signal; Based on the simulation waveform signals respectively corresponding to the plurality of segmented waveform signals, detecting whether the target input control signal corresponding to each segmented waveform signal has a meaningful effect on the control of the target register; Based on the obtained detection results of each of the segmented waveform signals, a redundant detection result of the target input control signal is generated.

3. The method according to claim 2, characterized in that The detecting whether the target input control signal corresponding to each segmented waveform signal has a meaningful effect on the control of the target register includes: Determining whether redundant detection of each segmented waveform signal of the target input control signal is meaningful; If it is meaningful, the segmented waveform signal is determined as a target segmented waveform signal, and it is detected whether the input control signal corresponding to the target segmented waveform signal is meaningful in controlling the target register.

4. The method according to claim 3, characterized in that The determining whether the redundant detection of each segmented waveform signal of the target input control signal is meaningful includes: If it is detected that the number of flips of the simulation waveform signal of the target input control signal within one clock cycle is an even number, it is determined that redundant detection of the plurality of segmented waveform signals corresponding to the even number of flips is meaningless; If it is detected that the number of flips of the simulation waveform signal corresponding to the target input control signal within one clock cycle is an odd number, it is determined that the redundant detection of the last segmented waveform signal within one clock cycle is meaningful.

5. The method according to claim 3, characterized in that: The detecting whether the input control signal corresponding to the target segmented waveform signal has a meaningful effect on the control of the target register includes: Based on the simulation waveform signal corresponding to the target segmented waveform signal, determine whether the flipping action of the input control signal corresponding to the target segmented waveform signal is meaningful to the control of the target register, and / or determine whether the flipped value of the input control signal corresponding to the target segmented waveform signal is meaningful to the control of the target register.

6. The method according to claim 5, characterized in that The determining whether the flipping action of the input control signal corresponding to the target segmented waveform signal is meaningful to the control of the target register includes: Determine whether the control of the target register by the flipping of the input control signal corresponding to the target segmented waveform signal at the flipping moment satisfies a first preset condition; If it is satisfied, it is determined that the flipping action of the input control signal corresponding to the target segmented waveform signal is meaningful to the control of the target register; the first preset condition is used to determine whether the target input control signal directly controls the target register or shields or opens the control channel of other control signals to the target register.

7. The method according to claim 6, characterized in that Also includes: When the control of the target register by the flipping of the input control signal corresponding to the target segmented waveform signal at the flipping moment does not satisfy the first preset condition, determining whether the control of the target register by the flipped value of the input control signal corresponding to the target segmented waveform signal satisfies the second preset condition; the second preset condition is used to determine whether the target input control signal directly controls the target register or shields or opens the control channel of other control signals to the target register; When the inverted value of the input control signal corresponding to the target segmented waveform signal satisfies a second preset condition for controlling the target register, it is determined that the inverted value of the input control signal corresponding to the target segmented waveform signal is meaningless for controlling the target register.

8. The method according to claim 6, characterized in that The first preset condition includes a first preset sub-condition; the determining whether the control of the target register by the flipping of the input control signal corresponding to the target segmented waveform signal at the flipping moment satisfies the first preset condition includes: Determine a target time for flipping an input control signal corresponding to the target segmented waveform signal; Determine whether the value of the simulation waveform signal corresponding to the output signal is reversed in the next clock cycle after the target time; If it is determined that when the value of the simulation waveform signal corresponding to the output signal is flipped, the flipping of the input control signal corresponding to the target segmented waveform signal at the target moment satisfies the first preset sub-condition for controlling the target register, then it is determined that the flipping of the input control signal corresponding to the target segmented waveform signal at the flipping moment satisfies the first preset condition for controlling the target register; The first preset sub-condition being met includes at least one of the following: The value of the output signal changes as the value of the input control signal corresponding to the target segmented waveform signal changes; When the value of the input control signal corresponding to the target segmented waveform signal is a preset value and the values ​​of other input control signals change, the value of the output signal changes; the other input control signal is any input control signal among the at least one input control signal except the target input control signal.

9. The method according to claim 8, characterized in that The first preset condition also includes a second preset sub-condition; the determination of whether the control of the target register by the flipping of the input control signal corresponding to the target segmented waveform signal at the flipping moment satisfies the first preset condition also includes: If it is determined that the value of the simulation waveform signal corresponding to the output signal has not flipped, and the flipping of the input control signal corresponding to the target segmented waveform signal at the target moment satisfies the second preset sub-condition for controlling the target register, then it is determined that the flipping of the input control signal corresponding to the target segmented waveform signal at the flipping moment satisfies the first preset condition for controlling the target register; The second preset sub-condition is satisfied, including at least one of the following: When the value of the other input control signal is flipped, the value of the output signal remains unchanged; When the value of the input control signal corresponding to the target segmented waveform signal is reversed, the value of the output signal changes in the next clock cycle.

10. The method according to claim 7, characterized in that The second preset condition is met, including any one of the following: In the time period corresponding to the target segmented waveform signal, the value of the simulation waveform signal corresponding to no other input control signal is reversed; the other input control signal is any input control signal of the at least one input control signal except the target input control signal; In the time period corresponding to the target segmented waveform signal, the value of the simulation waveform signal corresponding to other input control signals is reversed, and when the value of the reversed other input control signal changes, the value of the output signal changes.

11. The method according to claim 6, characterized in that The determining whether the flipping action of the input control signal corresponding to the target segmented waveform signal is meaningful to the control of the target register also includes: In response to the fact that the simulation waveform signal corresponding to the target segmented waveform signal has no next flipping moment, it is determined that the flipping action of the input control signal corresponding to the target segmented waveform signal is meaningful to the control of the target register.

12. The method according to any one of claims 2 to 11, characterized in that The generating of a redundant detection result of the target input control signal according to the obtained detection result of each segmented waveform signal comprises: Determine the number of segmented waveform signals in the target input control signal that are meaningless to the control of the target register according to the obtained detection results of each segmented waveform signal; Determine the proportion of segmented waveforms in the target input control signal that are meaningless to the control of the target register according to the number and the total number of segmented waveform signals in the target input control signal; A redundancy detection result of the target input control signal is generated based on the proportion.

13. A computing device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the redundant control signal detection method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the redundant control signal detection method according to any one of claims 1 to 12 is implemented.

Images