Chip layout information generation method, device, computer equipment and storage medium

Abstract

The present application relates to a chip layout information generation method, device, computer equipment and storage medium. The method includes: obtaining initial layout information of a target area; sending the initial layout information to each distributed node, and obtaining parameter information returned by each distributed node; adjusting the candidate chip layout model according to the parameter information returned by each distributed node in a synchronous manner and an asynchronous manner to obtain a target chip layout model. This method can analyze the initial layout information in different distributed nodes respectively, gradually adjust the model parameters of the chip layout model corresponding to each distributed node, and comprehensively adjust the model parameters returned by each distributed node to accurately adjust the model parameters of the candidate chip layout model to obtain the target chip layout model, so as to use the target chip layout model to obtain chip layout information for the target area, thereby improving the accuracy of the chip layout information.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a chip layout information generation method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] In the field of electronic design automation (EDA), placement is a crucial task that directly affects the performance, power consumption and manufacturing cost of the chip. The layout process involves placing thousands to millions of circuit units on the chip. Accurate and reasonable chip layout is conducive to optimizing chip performance, controlling chip power consumption, reducing manufacturing costs and extending chip life.

[0003] Traditional technology mainly searches for the optimal layout through iterative chip layout design. However, traditional technology does not fully capture layout features during the iterative design process, resulting in omissions of layout information in iterative analysis and incomplete analysis of layout effects, which causes chip performance degradation and is not conducive to improving the accuracy of chip layout information. Summary of the invention

[0004] Based on this, it is necessary to provide a chip layout information generation method, apparatus, computer equipment, computer-readable storage medium and computer program product that can improve the accuracy of chip layout information in order to solve the above technical problems.

[0005] In a first aspect, the present application provides a chip layout information generation method, comprising:

[0006] Acquire initial layout information corresponding to the target area; the initial layout information represents the occupancy of each position in the target area and the initial layout position of each circuit unit;

[0007] The initial layout information is sent to each distributed node, and parameter information returned by each distributed node is obtained; each distributed node is provided with a chip layout model to be trained; the chip layout model to be trained is used to process the initial layout information; the parameter information represents model parameters of the chip layout model to be trained;

[0008] The candidate chip layout model is adjusted according to the parameter information returned by each distributed node in a synchronous manner and an asynchronous manner to obtain a target chip layout model; the target chip layout model is used to determine the chip layout information corresponding to the target area according to the initial layout information corresponding to the target area.

[0009] In one embodiment, the method further comprises:

[0010] Determining updated layout positions of each circuit unit according to the initial layout information by using the target chip layout model;

[0011] Obtaining reward information corresponding to the updated layout position of each circuit unit through the target chip layout model; the reward information is used to characterize the rationality of the layout mode corresponding to the updated layout position;

[0012] In the case where the reward information meets the preset layout requirements, the chip layout information corresponding to the target area is determined according to the updated layout positions of the circuit units through the target chip layout model.

[0013] In one embodiment, the method further comprises:

[0014] When the reward information does not meet the preset layout requirement, adjusting the layout position of each circuit unit according to the reward information through the target chip layout model to obtain a new updated layout position;

[0015] In the case where the reward information corresponding to the new updated layout position meets the preset layout requirement, the chip layout information corresponding to the target area is determined according to the new updated layout position by using the target chip layout model.

[0016] In one embodiment, determining the updated layout position of each circuit unit according to the initial layout information by using the target chip layout model includes:

[0017] Generate an initial layout diagram according to the initial layout information by using the target chip layout model, and divide the initial layout diagram into at least two sub-layout diagrams;

[0018] The sub-layout diagram is encoded by the target chip layout model to obtain layout diagram encoding information; the layout diagram encoding information is used to characterize the coordinates and occupancy status of each position in the target area;

[0019] Acquire the to-be-placed position information of each circuit unit through the target chip layout model, and determine the updated layout diagram corresponding to the sub-layout diagram according to the layout diagram encoding information and the to-be-placed position information of each circuit unit;

[0020] The updated layout positions of the circuit units are determined by using the target chip layout model according to the updated layout diagram corresponding to the sub-layout diagram.

[0021] In one embodiment, the obtaining of reward information corresponding to the updated layout position of each circuit unit includes:

[0022] According to the updated layout positions of the circuit units, determining the signal transmission path length information, wiring congestion information and signal transmission time information corresponding to the updated layout positions;

[0023] Reward information corresponding to the updated layout position of each circuit unit is generated according to the signal transmission path length information, the wiring congestion information and the signal transmission time information.

[0024] In one embodiment, the step of adjusting the candidate chip layout model according to the parameter information returned by each distributed node in a synchronous manner and an asynchronous manner includes:

[0025] Generate a first node set and a second node set according to the distributed nodes; the first node set includes at least one distributed node; the second node set includes at least one distributed node;

[0026] In the case where all parameter information returned by each distributed node in the first node set is obtained, generating synchronization update information according to the parameter information returned by each distributed node in the first node set;

[0027] In case of acquiring parameter information returned by any distributed node in the second node set, generating asynchronous update information according to the parameter information returned by any distributed node;

[0028] The candidate chip layout model is adjusted according to the synchronous update information and the asynchronous update information.

[0029] In a second aspect, the present application further provides a chip layout information generating device, comprising:

[0030] An information acquisition module, used to acquire initial layout information corresponding to the target area; the initial layout information represents the occupancy of each position in the target area and the initial layout position of each circuit unit;

[0031] A parameter generation module, used to send the initial layout information to each distributed node and obtain parameter information returned by each distributed node; each distributed node is provided with a chip layout model to be trained; the chip layout model to be trained is used to process the initial layout information; the parameter information represents the model parameters of the chip layout model to be trained;

[0032] The model adjustment module is used to adjust the candidate chip layout model according to the parameter information returned by each distributed node in a synchronous manner and an asynchronous manner to obtain a target chip layout model; the target chip layout model is used to determine the chip layout information corresponding to the target area according to the initial layout information corresponding to the target area.

[0033] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the above method are implemented.

[0034] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0035] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0036] The chip layout information generation method, device, computer equipment, computer-readable storage medium and computer program product obtain the initial layout information corresponding to the target area, thereby accurately analyzing the occupancy of each position in the target area and the initial layout position of each circuit unit, and providing a data basis for the subsequent generation of layout information; sending the initial layout information to each distributed node, and obtaining the parameter information returned by each distributed node, so as to train the chip layout model to be trained set by each distributed node based on the initial layout information, accurately obtain the model parameters of the chip layout model to be trained, and thus determine the model parameters of the chip layout model in different distributed nodes based on the initial layout information, and provide a data basis for the subsequent generation of the target chip layout model; using synchronous and asynchronous methods to adjust the candidate chip layout model according to the parameter information returned by each distributed node, and obtain the target chip layout model, so as to adopt The model parameters are adjusted in a synchronous and asynchronous manner to obtain a target chip layout model, so that the target chip layout model can be used to accurately generate chip layout information corresponding to the target area based on the initial layout information corresponding to the target area, thereby combining the parameter information returned by each distributed node to reasonably adjust the candidate chip layout model to obtain a chip layout model for determining the chip layout information. The chip layout models corresponding to different distributed nodes can be used to comprehensively and fully analyze the initial layout information corresponding to the target area, and the initial layout information can be carefully analyzed in different distributed nodes respectively, and the model parameters of the chip layout models corresponding to each distributed node can be gradually adjusted, thereby comprehensively combining the model parameters returned by each distributed node to accurately adjust the model parameters of the candidate chip layout model to obtain the target chip layout model, so as to use the target chip layout model to obtain the chip layout information for the target area, thereby improving the accuracy of the chip layout information. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 A diagram of an application environment of a chip layout information generating method in one embodiment;

[0039] Figure 2 A schematic diagram of a process of generating chip layout information in an embodiment;

[0040] Figure 3 is a schematic flow chart of a chip layout information generating method in another embodiment;

[0041] Figure 4 A schematic diagram of determining a layout position of a circuit unit in an embodiment;

[0042] Figure 5 is a schematic diagram of a chip layout method in an embodiment;

[0043] Figure 6 A schematic diagram of determining chip layout information in an embodiment;

[0044] Figure 7 is a structural block diagram of a chip layout information generating device in one embodiment;

[0045] Figure 8 The figure is a diagram of the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] The chip layout information generation method provided in the embodiment of the present application can be applied to Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network, and the terminal 102 can receive and display the chip layout information sent by the server 104. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The server 104 obtains the initial layout information corresponding to the target area; the initial layout information represents the occupancy of each position in the target area and the initial layout position of each circuit unit; the server 104 sends the initial layout information to each distributed node, and obtains the parameter information returned by each distributed node; each distributed node is provided with a chip layout model to be trained; the chip layout model to be trained is used to process the initial layout information; the parameter information represents the model parameters of the chip layout model to be trained; the server 104 uses synchronous and asynchronous methods to adjust the candidate chip layout model according to the parameter information returned by each distributed node to obtain the target chip layout model; the target chip layout model is used to determine the chip layout information corresponding to the target area according to the initial layout information corresponding to the target area. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptops, etc. The server 104 may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services.

[0048] In an exemplary embodiment, Figure 2 As shown, a chip layout information generation method is provided, and the method is applied to a server as an example for description, including the following steps S202 to S206. Among them:

[0049] Step S202, obtaining initial layout information corresponding to the target area; the initial layout information represents the occupancy status of each position in the target area and the initial layout position of each circuit unit.

[0050] The target area may refer to a two-dimensional or three-dimensional area for placing circuit units and / or wiring.

[0051] The circuit unit may refer to various components and structures that need to be placed and wired in the target area. In practical applications, the circuit unit may include but is not limited to a macro unit.

[0052] Among them, the initial layout information may refer to information used to characterize the occupancy status of each position in the target area and the initial layout position of each circuit unit. In actual applications, the initial layout information may include the specific positions of the placed circuit units, the coordinates of the occupied positions in the target area, and the coordinates of the unoccupied positions in the target area.

[0053] As an example, in order to reasonably design the layout of the chip, the server can use the two-dimensional area or three-dimensional area in the chip that needs to be laid out as the target area, and obtain the layout state corresponding to the target area in the initial state as the initial layout information. In actual applications, the layout state corresponding to the target area in the initial state may include but is not limited to each circuit unit being randomly placed in the target area.

[0054] Step S204, sending the initial layout information to each distributed node, and obtaining parameter information returned by each distributed node; each distributed node is provided with a chip layout model to be trained; the chip layout model to be trained is used to process the initial layout information; the parameter information represents the model parameters of the chip layout model to be trained.

[0055] Among them, the distributed node may refer to an independent computing unit that participates in the calculation during the layout design process using a distributed training method.

[0056] Among them, the chip layout model to be trained may refer to a model set in a distributed node for determining the layout of circuit units in a target area. In practical applications, the chip layout model may include a Transformer model and a graph convolution model.

[0057] The parameter information returned by the distributed nodes may refer to information representing model parameters of the chip layout model to be trained. In practical applications, the parameter information returned by each distributed node may be different from each other.

[0058] As an example, the server can send the initial layout information of the target area to each distributed node. Each distributed node is provided with a corresponding chip layout model to be trained. The chip layout model to be trained can analyze the initial layout information of the target area, gradually generate corresponding layout mode information and adjust the model parameters of the chip layout model to be trained. In actual applications, since the computing environment corresponding to each distributed node may be different, the gradient corresponding to each distributed node may be different, and thus the model parameters of the chip layout model to be trained returned by the distributed node may be different.

[0059] Step S206, adjusting the candidate chip layout model in a synchronous manner and an asynchronous manner according to the parameter information returned by each distributed node to obtain a target chip layout model; the target chip layout model is used to determine the chip layout information corresponding to the target area according to the initial layout information corresponding to the target area.

[0060] The candidate chip layout model may refer to a chip layout model that requires parameter adjustment.

[0061] The target chip layout model may refer to a model obtained by adjusting the model parameters of the candidate chip layout model based on the parameter information returned by each distributed node.

[0062] As an example, after each distributed node adjusts the model parameters of the chip layout model to be trained corresponding to each distributed node based on the initial layout information, each distributed node can send the model parameters of the chip layout model to be trained corresponding to each distributed node to the server, the server can summarize the model parameter information sent by each distributed node, and by analyzing the model parameter information, adjust the model parameters of the candidate chip layout model set in the server in a synchronous and asynchronous manner to obtain a target chip layout model, the server can input the initial layout information corresponding to the target area into the target chip layout model, the target chip layout model can output chip layout information for the target area, and the chip layout information can be used to directly control or guide the layout method of each single-way unit in the target area.

[0063] In the above chip layout information generation method, by obtaining the initial layout information corresponding to the target area, the occupancy of each position in the target area and the initial layout position of each circuit unit are accurately analyzed, so as to provide a data basis for the subsequent generation of layout information; the initial layout information is sent to each distributed node, and the parameter information returned by each distributed node is obtained, so as to train the chip layout model to be trained set by each distributed node based on the initial layout information, and accurately obtain the model parameters of the chip layout model to be trained, so as to determine the model parameters of the chip layout model in different distributed nodes based on the initial layout information, so as to provide a data basis for the subsequent generation of the target chip layout model; the candidate chip layout model is adjusted according to the parameter information returned by each distributed node in a synchronous manner and an asynchronous manner to obtain the target chip layout model, so as to adjust the model in a synchronous and asynchronous manner. The target chip layout model is obtained by using the target chip layout model based on the initial layout information corresponding to the target area, so as to accurately generate the chip layout information corresponding to the target area by using the target chip layout model, thereby combining the parameter information returned by each distributed node to reasonably adjust the candidate chip layout model to obtain the chip layout model for determining the chip layout information, and can comprehensively and fully analyze the initial layout information corresponding to the target area by using the chip layout models corresponding to different distributed nodes, carefully analyze the initial layout information in different distributed nodes respectively, and gradually adjust the model parameters of the chip layout model corresponding to each distributed node, thereby comprehensively combining the model parameters returned by each distributed node, accurately adjusting the model parameters of the candidate chip layout model, and obtaining the target chip layout model, so as to obtain the chip layout information for the target area by using the target chip layout model, thereby improving the accuracy of the chip layout information.

[0064] In one exemplary embodiment, Figure 3As shown, a flow chart of a chip layout information generation method is provided, each distributed node (such as a local node) can obtain the original chip layout state sent by the server, and perform reinforcement learning based on the original chip layout state through the chip layout model to be trained corresponding to each distributed node, wherein the process of performing reinforcement learning based on the original chip layout state by the chip layout model to be trained corresponding to each distributed node may include: defining a layout state, defining an action for each circuit unit (such as a position where the circuit unit can be placed), defining reward information, executing an action for a certain circuit unit under the layout state, calculating reward information after the action is executed, when the reward information meets the corresponding layout requirements, executing an action for the next circuit unit, calculating reward information after the action is executed, and so on, until the reward information does not meet the corresponding layout requirements, adjusting the action for the corresponding circuit unit and executing it, recalculating the reward information, and judging whether the new reward information meets the corresponding layout requirements, until the layout positions of all circuit units are obtained (layout design is completed), and the reward information in this process can be used to adjust the model parameters of the chip layout model to be trained to obtain the trained chip layout model. Each distributed node may send the model parameters of the corresponding trained chip layout model to the server, and the server receives the model parameters sent by each distributed node. The server may use a synchronous and asynchronous method to adjust the model parameters of the candidate chip layout model based on the model parameters sent by each distributed node to obtain a target chip layout model, wherein the process of the server using a synchronous and asynchronous method to adjust the model parameters of the candidate chip layout model based on the model parameters sent by each distributed node may include: when receiving the model parameters sent by a certain distributed node, detecting whether the model parameters sent by all distributed nodes are received, if not, the server waits to receive the model parameters sent by the remaining distributed nodes until the server receives the model parameters sent by all distributed nodes, the server may adjust the model parameters of the candidate chip layout model based on the model parameters sent by all distributed nodes to obtain the target chip layout model, and / or, when receiving the model parameters sent by any distributed node, adjusting the model parameters of the candidate chip layout model based on the model parameters sent by the distributed node to obtain the target chip layout model.

[0065] In an exemplary embodiment, the method further includes: determining the updated layout position of each circuit unit according to the initial layout information through the target chip layout model; obtaining reward information corresponding to the updated layout position of each circuit unit through the target chip layout model; the reward information is used to characterize the rationality of the layout method corresponding to the updated layout position; when the reward information meets the preset layout requirements, determining the chip layout information corresponding to the target area according to the updated layout position of each circuit unit through the target chip layout model.

[0066] The updated layout position of each circuit unit may refer to the position coordinates of each circuit unit in the target area after the chip layout model to be trained corresponding to each distributed node redesigns or plans the initial layout corresponding to the target area.

[0067] The reward information may refer to information used to characterize the rationality of the layout method corresponding to the updated layout position.

[0068] The preset layout requirement may refer to pre-set information used to determine whether the layout of each circuit unit in the target area is reasonable.

[0069] As an example, the candidate chip layout model, the target chip layout model, and the chip layout model to be trained corresponding to each distributed node may have the same model structure, so the layout design logic of the candidate chip layout model, the target chip layout model, and the chip layout model to be trained corresponding to each distributed node may be the same. Take the layout design logic of the target chip layout model as an example for explanation: the target chip layout model can redesign the placement position of the circuit unit in the target area according to the initial layout information to obtain the updated layout position of each circuit unit, wherein the initial layout information and the updated layout position can be the same or different for the position coordinates of the same circuit unit. The server can analyze the rationality of the layout method corresponding to the updated layout position based on the updated layout position of each circuit unit through the target chip layout model, calculate the reward information corresponding to the updated layout position of each circuit unit, and when the reward information meets the preset layout requirements, the server can summarize the updated layout position of each circuit unit through the target chip layout model to determine the chip layout information corresponding to the target area.

[0070] In this embodiment, the updated layout position of each circuit unit is determined according to the initial layout information through the target chip layout model; the reward information corresponding to the updated layout position of each circuit unit is obtained through the target chip layout model; the reward information is used to characterize the rationality of the layout method corresponding to the updated layout position; when the reward information meets the preset layout requirements, the chip layout information corresponding to the target area is determined according to the updated layout position of each circuit unit through the target chip layout model, and based on the reward information corresponding to the updated layout position of each circuit unit, it can be accurately determined whether the chip layout information corresponding to the target area is generated based on the current updated layout position, thereby ensuring that the current layout design meets the preset layout requirements, thereby improving the accuracy of the chip layout information.

[0071] In some embodiments, the above method also includes: when the reward information does not meet the preset layout requirements, adjusting the layout position of each circuit unit according to the reward information through the target chip layout model to obtain a new updated layout position; when the reward information corresponding to the new updated layout position meets the preset layout requirements, determining the chip layout information corresponding to the target area according to the new updated layout position through the target chip layout model.

[0072] As an example, when the reward information corresponding to the updated layout position of each circuit unit does not meet the preset layout requirements, the server can determine through the target chip layout model that the updated layout position of each circuit unit needs to be redesigned and laid out. The server can determine the layout adjustment method information through the target chip layout model combined with the reward information, and adjust the layout position of each circuit unit according to the layout adjustment method information to obtain a new updated layout position, and recalculate the reward information. Then, the server determines whether the current layout design meets the preset layout requirements through the target chip layout model combined with the reward information. If it still does not meet the requirements, the server adjusts the layout position again according to the reward information through the target chip layout model until the reward information meets the preset layout requirements. At this time, the server can summarize the latest updated layout positions of each circuit unit through the target chip layout model to determine the chip layout information corresponding to the target area.

[0073] In this embodiment, when the reward information does not meet the preset layout requirements, the layout position of each circuit unit is adjusted according to the reward information through the target chip layout model to obtain a new updated layout position; when the reward information corresponding to the new updated layout position meets the preset layout requirements, the chip layout information corresponding to the target area is determined according to the new updated layout position through the target chip layout model. When the reward information does not meet the preset layout requirements, the layout position of each circuit unit can be redesigned and planned until the reward information meets the preset layout requirements, thereby ensuring that the current layout design meets the preset layout requirements and improving the accuracy of the chip layout information.

[0074] In some embodiments, the updated layout position of each circuit unit is determined according to the initial layout information through the target chip layout model, including: generating an initial layout diagram according to the initial layout information through the target chip layout model, and dividing the initial layout diagram into at least two sub-layout diagrams; encoding the sub-layout diagram through the target chip layout model to obtain layout diagram encoding information; the layout diagram encoding information is used to characterize the coordinates and occupancy status of each position in the target area; obtaining the to-be-layout position information of each circuit unit through the target chip layout model, and determining the updated layout diagram corresponding to the sub-layout diagram according to the layout diagram encoding information and the to-be-layout position information of each circuit unit; determining the updated layout position of each circuit unit according to the updated layout diagram corresponding to the sub-layout diagram through the target chip layout model.

[0075] The initial layout diagram may refer to information representing the initial layout positions of each circuit unit in the target area in an image form.

[0076] The sub-layout image may refer to an image obtained by segmenting the initial layout image.

[0077] The layout image encoding information may refer to information obtained by encoding the sub-layout image using an encoder. In practical applications, the encoder may include but is not limited to a Transformer encoder.

[0078] Among them, the position information to be laid out of each circuit unit may refer to information characterizing the position where each circuit unit can be laid out in the target area. In actual applications, each circuit unit can be placed one by one in the target area, and the position information to be laid out of each circuit unit may include the position where each circuit unit needs to be placed.

[0079] The updated layout diagram corresponding to the sub-layout diagram may refer to an image obtained after the target chip layout model adjusts the layout design of the sub-layout diagram based on the layout diagram encoding information and the to-be-layout position information of each circuit unit.

[0080] As an example, Figure 4 As shown, a schematic diagram for determining the layout position of a circuit unit is provided. The server can generate an initial layout diagram (such as a layout planning diagram) according to the initial layout information through the target chip layout model. The initial layout diagram is first divided into at least two sub-layout diagrams, and the sub-layout diagrams are linearly mapped. The linear mapping result can include the position representation of each circuit unit. Then, the server encodes the linear mapping result corresponding to the sub-layout diagram through the Transformer encoder in the target chip layout model to obtain the layout diagram encoding information (such as Transformer encoding). The server can obtain the layout position information of each circuit unit one by one through the target chip layout model, for example: Figure 5As shown, a schematic diagram of a chip layout method is provided. The target chip layout model can first select a circuit unit D1 from each circuit unit, and then select a circuit unit D2 from each circuit unit according to the current layout state. and layout design constraints to determine the layout location information of the circuit unit D1 , and then use agent A to perform actions (For example, the circuit unit D1 is placed in the position information to be laid out The new layout state is obtained at the position represented by , the layout state With corresponding reward information , then the chip layout model corresponding to the distributed node can select another circuit unit , and based on the current layout state and layout design constraints to determine the circuit unit The location information to be laid out , and then use agent A to perform actions (If the circuit unit Placed in the location information to be laid out The position represented by , layout state With corresponding reward information , and so on, the target chip layout model can determine the location information of each circuit unit to be laid out one by one.

[0081] In one embodiment, if Figure 4 As shown, the server can use the action network (Actor network) in the target chip layout model to adjust the layout diagram encoding information using the to-be-layout position information of each circuit unit when the input data is embedded in the layout diagram encoding information. The reward network (Critic network) in the target chip layout model can calculate the reward information under various layout states. The server can decode the adjusted layout diagram encoding information through the target chip layout model to obtain an updated layout diagram corresponding to the sub-layout diagram. The server can determine the updated layout position of each circuit unit according to the updated layout diagram corresponding to the sub-layout diagram through the target chip layout model.

[0082] In this embodiment, the updated layout position of each circuit unit is determined according to the initial layout information through the target chip layout model, including: generating an initial layout diagram according to the initial layout information through the target chip layout model, dividing the initial layout diagram into at least two sub-layout diagrams; encoding the sub-layout diagram through the target chip layout model to obtain layout diagram encoding information; the layout diagram encoding information is used to characterize the coordinates and occupancy status of each position in the target area; obtaining the to-be-layout position information of each circuit unit through the target chip layout model, and determining the updated layout diagram corresponding to the sub-layout diagram according to the layout diagram encoding information and the to-be-layout position information of each circuit unit; and obtaining the to-be-layout position information of each circuit unit through the target chip layout model. According to the updated layout diagram corresponding to the sub-layout diagram, the updated layout position of each circuit unit is determined, and the initial layout diagram can be generated based on the initial layout information, and the initial layout diagram is segmented and encoded to fully obtain the layout features in the initial layout to avoid omission of diagram information. In combination with the position information of each circuit unit to be laid out, an updated layout diagram corresponding to the sub-layout diagram is generated, and the correlation of the layout designs in each sub-layout diagram is integrated to obtain an accurate updated layout position, which provides a data basis for subsequently determining the layout mode information of the distributed nodes based on the updated layout position and determining the chip layout information in combination with the layout mode information of each distributed node, thereby improving the accuracy of the chip layout information.

[0083] In some embodiments, reward information corresponding to the updated layout position of each circuit unit is obtained, including: determining, based on the updated layout position of each circuit unit, signal transmission path length information, wiring congestion information, and signal transmission time information corresponding to the updated layout position; and generating reward information corresponding to the updated layout position of each circuit unit based on the signal transmission path length information, wiring congestion information, and signal transmission time information.

[0084] The signal transmission path length information may refer to information characterizing the length of the signal transmission path in the circuit composed of each circuit unit in the target area.

[0085] The wiring congestion information may refer to information characterizing the usage of wiring resources in the target area. In practical applications, the wiring congestion information may include the degree of congestion of wiring in the target area.

[0086] The signal transmission time information may refer to information characterizing the time required for a signal in a circuit composed of circuit units in the target area to be transmitted from one specific point to another specific point.

[0087] As an example, for each distributed node, the server can determine the signal transmission path length information, wiring congestion information and signal transmission time information corresponding to the updated layout position of each circuit unit corresponding to the distributed node through the distributed node, and then the server can perform weighted summation of the signal transmission path length information, wiring congestion information and signal transmission time information according to the weights corresponding to the signal transmission path length information, wiring congestion information and signal transmission time information through the distributed node to calculate the reward information corresponding to the updated layout position of each circuit unit.

[0088] In this embodiment, by determining the signal transmission path length information, wiring congestion information and signal transmission time information corresponding to the updated layout position according to the updated layout position of each circuit unit; generating reward information corresponding to the updated layout position of each circuit unit according to the signal transmission path length information, wiring congestion information and signal transmission time information, the rationality of the chip layout design can be accurately analyzed from multiple dimensions of signal transmission path length, wiring congestion and signal transmission time, and accurate reward information can be obtained, which is convenient for subsequent judgment of the accuracy of the updated layout position based on the reward information, thereby improving the accuracy of the layout mode information of the distributed nodes, and further improving the accuracy of the chip layout information.

[0089] In some embodiments, a candidate chip layout model is adjusted according to parameter information returned by each distributed node in a synchronous manner and an asynchronous manner, including: generating a first node set and a second node set according to each distributed node; the first node set includes at least one distributed node; the second node set includes at least one distributed node; when all parameter information returned by each distributed node in the first node set is obtained, synchronous update information is generated according to the parameter information returned by each distributed node in the first node set; when parameter information returned by any distributed node in the second node set is obtained, asynchronous update information is generated according to the parameter information returned by any distributed node; and the candidate chip layout model is adjusted according to the synchronous update information and the asynchronous update information.

[0090] The synchronous update information may refer to information generated according to the parameter information returned by each distributed node in the first node set when all the parameter information returned by each distributed node in the first node set is obtained.

[0091] The asynchronous update information may refer to information generated according to parameter information returned by any distributed node in the second node set when parameter information returned by any distributed node in the second node set is obtained.

[0092] As an example, the server can update and adjust the parameters of the candidate chip layout model in a synchronous and asynchronous manner. Specifically, the server can divide each distributed node into two groups, each group can be used as a node set, and the first node set is used to implement the parameter update in a synchronous manner, and the second node set is used to implement the parameter update in an asynchronous manner. The server can generate synchronous update information according to the parameter information returned by each distributed node in the first node set when all the parameter information returned by each distributed node in the first node set is obtained. The server can generate asynchronous update information according to the parameter information returned by any distributed node in the second node set when the parameter information returned by any distributed node is obtained. Then, the server can adjust the model parameters of the candidate chip layout model according to the synchronous update information and the asynchronous update information to generate the target chip layout model. In actual applications, the server can filter out candidate parameters from the synchronous update information and the asynchronous update information, and use the candidate parameters to adjust the model parameters of the candidate chip layout model to obtain the target chip layout model.

[0093] In this embodiment, a first node set and a second node set are generated according to each distributed node; the first node set includes at least one distributed node; the second node set includes at least one distributed node; when all parameter information returned by each distributed node in the first node set is obtained, synchronous update information is generated according to the parameter information returned by each distributed node in the first node set; when parameter information returned by any distributed node in the second node set is obtained, asynchronous update information is generated according to the parameter information returned by any distributed node; and the candidate chip layout model is adjusted according to the synchronous update information and the asynchronous update information, so that the parameter update of the candidate chip layout model can be realized in a synchronous and asynchronous manner, the response speed of the parameter update is improved, the model parameter adjustment time or training time of the chip layout model is avoided to be too long, the generation efficiency of the chip layout model is improved, and the generation efficiency of the chip layout information is further improved.

[0094] In some embodiments, the server may define the initial layout information corresponding to the target area as state s. State s may include a global layout image I and side information S. The global layout image I and side information S may be generated by a Transformer encoder, wherein I may represent the visual embedding of the current overall layout in the target area, including the specific locations of the placed macro units and the occupied and unoccupied areas of the layout, and S represents the non-visual representation of the current overall layout in the target area, including a netlist, node features, edge features, and the next macro unit to be placed. The server may define action a, which may indicate the location where the macro unit can be placed; the server may also define the reward information as the weighted sum of line length (signal transmission path length information), congestion (wiring congestion information), and timing (signal transmission time information). The target area may be used as a layout environment, and the initial layout information corresponding to the target area may be used as a simulated layout of the layout environment. In state Next action You can change the layout state and generate a new state ,state With corresponding reward information , the new state With corresponding reward information , the server can use the reward information and real-time layout status for reinforcement learning to realize chip layout design. In practical applications, the server can use the reinforcement learning layout model (such as the chip layout model) to design the chip layout. The input of the reinforcement learning layout model can include the initial layout netlist and coordinate data. The reinforcement learning layout model can use the Transformer encoder network and the graph convolutional neural network (Graph Convolutional Networks, GCN for short) to generate a new layout state and output the corresponding action and reward.

[0095] like Figure 6As shown, a schematic diagram of determining chip layout information is provided, and the server can generate multiple local layout networks (such as the chip layout model to be trained corresponding to the distributed nodes) at multiple distributed nodes (such as distributed node 1, distributed node 2, ..., distributed node n), and the server can also define a global layout network (such as a candidate chip layout model). The server can update the gradient of the global layout network in a synchronous and asynchronous manner based on the multiple local layout networks. Specifically, each distributed node can take the initial layout information of the target area as input, and the local layout network (network 1, network 2, ..., network n) corresponding to each distributed node can generate corresponding layout mode information based on the initial layout information of the target area and adjust the model parameters of each local layout network itself. Each distributed node can input the model parameters of each local layout network itself (adjusted model parameters) into the conversion layer. The conversion layer can use the synchronous layer and the asynchronous layer to determine the model parameter adjustment method for the global layout network in a synchronous and asynchronous manner based on the model parameter information sent by each distributed node, and adjust the model parameters of the global layout network according to the model parameter adjustment method to obtain the adjusted global layout network (such as the target chip layout model). In a specific implementation, the input of the global layout network may include the layout state s. The global layout network can perform reinforcement learning by predicting the probability of performing action a (i.e., placing or moving a specific macro unit) under the layout state s and the policy parameter θ. At this time, the policy function can be expressed as The global layout network can perform reinforcement learning by predicting the average long-term performance or reward that can be achieved under a given layout state s, based on the current strategy π and parameter w, starting from the current layout state s until the end of the layout process. At this time, the state function can be expressed as v(s,w). The candidate layout information with the best layout effect among several candidate layout information output by the distributedly trained global layout network can be used as the chip layout information for the target area.

[0096] In this embodiment, by using the Transformer encoder for encoding, more layout information can be included, which is beneficial to subsequent layout design and decision-making. When making reinforcement learning decisions, the reward information is taken into account in terms of timing, so that reinforcement learning can design a layout result that meets the timing. At the same time, multiple local network distributed training gradients are used. Multiple local networks are trained in different processes and the results are contributed to the global network to accelerate the training process. This can achieve efficient and accurate chip layout design and optimization and improve the accuracy of chip layout information.

[0097] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0098] Based on the same inventive concept, the embodiment of the present application also provides a chip layout information generating device for implementing the chip layout information generating method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more chip layout information generating device embodiments provided below can refer to the limitations of the chip layout information generating method above, and will not be repeated here.

[0099] In an exemplary embodiment, Figure 7 As shown, a chip layout information generating device is provided, including: an information acquisition module 702, a parameter generation module 704 and a model adjustment module 706, wherein:

[0100] The information acquisition module 702 is used to acquire initial layout information corresponding to the target area; the initial layout information represents the occupancy status of each position in the target area and the initial layout position of each circuit unit.

[0101] The parameter generation module 704 is used to send the initial layout information to each distributed node and obtain parameter information returned by each distributed node; each distributed node is provided with a chip layout model to be trained; the chip layout model to be trained is used to process the initial layout information; the parameter information represents the model parameters of the chip layout model to be trained.

[0102] The model adjustment module 706 is used to adjust the candidate chip layout model according to the parameter information returned by each distributed node in a synchronous manner and an asynchronous manner to obtain a target chip layout model; the target chip layout model is used to determine the chip layout information corresponding to the target area according to the initial layout information corresponding to the target area.

[0103] In one of the exemplary embodiments, the above-mentioned device also includes an information generation module, which is specifically used to determine the updated layout position of each circuit unit according to the initial layout information through the target chip layout model; obtain reward information corresponding to the updated layout position of each circuit unit through the target chip layout model; the reward information is used to characterize the rationality of the layout method corresponding to the updated layout position; when the reward information meets the preset layout requirements, determine the chip layout information corresponding to the target area according to the updated layout position of each circuit unit through the target chip layout model.

[0104] In one of the exemplary embodiments, the information generation module is further specifically used to adjust the layout positions of the circuit units according to the reward information through the target chip layout model to obtain a new updated layout position when the reward information does not meet the preset layout requirements; and to determine the chip layout information corresponding to the target area according to the new updated layout position through the target chip layout model when the reward information corresponding to the new updated layout position meets the preset layout requirements.

[0105] In one of the exemplary embodiments, the above-mentioned information generation module is specifically used to generate an initial layout diagram according to the initial layout information through the target chip layout model, and divide the initial layout diagram into at least two sub-layout diagrams; encode the sub-layout diagram through the target chip layout model to obtain layout diagram encoding information; the layout diagram encoding information is used to characterize the coordinates and occupancy status of each position in the target area; obtain the to-be-layout position information of each circuit unit through the target chip layout model, and determine the updated layout diagram corresponding to the sub-layout diagram according to the layout diagram encoding information and the to-be-layout position information of each circuit unit; determine the updated layout position of each circuit unit according to the updated layout diagram corresponding to the sub-layout diagram through the target chip layout model.

[0106] In one of the exemplary embodiments, the above-mentioned information generation module is specifically used to determine the signal transmission path length information, wiring congestion information and signal transmission time information corresponding to the updated layout position of each circuit unit according to the updated layout position of each circuit unit; and generate reward information corresponding to the updated layout position of each circuit unit according to the signal transmission path length information, the wiring congestion information and the signal transmission time information.

[0107] In one of the exemplary embodiments, the above-mentioned model adjustment module 706 is specifically used to generate a first node set and a second node set according to the distributed nodes; the first node set includes at least one distributed node; the second node set includes at least one distributed node; when all the parameter information returned by the distributed nodes in the first node set is obtained, synchronous update information is generated according to the parameter information returned by the distributed nodes in the first node set; when the parameter information returned by any distributed node in the second node set is obtained, asynchronous update information is generated according to the parameter information returned by any distributed node; and the candidate chip layout model is adjusted according to the synchronous update information and the asynchronous update information.

[0108] Each module in the above-mentioned chip layout information generating device can be implemented in whole or in part by software, hardware or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0109] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 8 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC) or other technologies. When the computer program is executed by the processor, a chip layout information generation method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0110] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0111] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0112] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0113] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0114] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0115] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0116] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0117] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip layout information generation method, characterized in that: The method comprises: Acquire initial layout information corresponding to the target area; the initial layout information represents the occupancy of each position in the target area and the initial layout position of each circuit unit; The initial layout information is sent to each distributed node, and parameter information returned by each distributed node is obtained; each distributed node is provided with a chip layout model to be trained; the chip layout model to be trained is used to process the initial layout information; the parameter information represents model parameters of the chip layout model to be trained; Generate a first node set and a second node set according to the distributed nodes; the first node set includes at least one distributed node; the second node set includes at least one distributed node; in the case where all parameter information returned by the distributed nodes in the first node set is obtained, generate synchronous update information according to the parameter information returned by the distributed nodes in the first node set; in the case where the parameter information returned by any distributed node in the second node set is obtained, generate asynchronous update information according to the parameter information returned by any distributed node; adjust the candidate chip layout model according to the synchronous update information and the asynchronous update information to obtain a target chip layout model; the target chip layout model is used to determine the chip layout information corresponding to the target area according to the initial layout information corresponding to the target area; The target chip layout model generates an initial layout diagram according to the initial layout information, and divides the initial layout diagram into at least two sub-layout diagrams; the sub-layout diagrams are linearly mapped by the target chip layout model, and the linear mapping results are encoded by the Transformer encoder in the target chip layout model to obtain layout diagram encoding information; the linear mapping results represent the positions of each circuit unit; the layout diagram encoding information is used to represent the coordinates and occupancy status of each position in the target area; the target chip layout model is used to obtain the position information of each circuit unit to be laid out, and the updated layout diagram corresponding to the sub-layout diagram is determined according to the layout diagram encoding information and the position information of each circuit unit to be laid out; the target chip layout model determines the updated layout position of each circuit unit according to the updated layout diagram corresponding to the sub-layout diagram; the target chip layout model obtains the reward information corresponding to the updated layout position of each circuit unit; the reward information is used to represent the rationality of the layout method corresponding to the updated layout position; when the reward information meets the preset layout requirements, the target chip layout model determines the chip layout information corresponding to the target area according to the updated layout position of each circuit unit.

2. The method according to claim 1, characterized in that The method further comprises: When the reward information does not meet the preset layout requirement, adjusting the layout position of each circuit unit according to the reward information through the target chip layout model to obtain a new updated layout position; In the case where the reward information corresponding to the new updated layout position meets the preset layout requirement, the chip layout information corresponding to the target area is determined according to the new updated layout position by using the target chip layout model.

3. The method according to claim 1, characterized in that The obtaining of reward information corresponding to the updated layout position of each circuit unit includes: According to the updated layout positions of the circuit units, determining the signal transmission path length information, wiring congestion information and signal transmission time information corresponding to the updated layout positions; Reward information corresponding to the updated layout position of each circuit unit is generated according to the signal transmission path length information, the wiring congestion information and the signal transmission time information.

4. A chip layout information generating device, characterized in that: The device comprises: An information acquisition module, used to acquire initial layout information corresponding to the target area; the initial layout information represents the occupancy of each position in the target area and the initial layout position of each circuit unit; A parameter generation module, used to send the initial layout information to each distributed node and obtain parameter information returned by each distributed node; each distributed node is provided with a chip layout model to be trained; the chip layout model to be trained is used to process the initial layout information; the parameter information represents the model parameters of the chip layout model to be trained; A model adjustment module, configured to generate a first node set and a second node set according to the distributed nodes; the first node set includes at least one distributed node; the second node set includes at least one distributed node; in the case where all parameter information returned by the distributed nodes in the first node set is obtained, synchronous update information is generated according to the parameter information returned by the distributed nodes in the first node set; in the case where the parameter information returned by any distributed node in the second node set is obtained, asynchronous update information is generated according to the parameter information returned by any distributed node; according to the synchronous update information and the asynchronous update information, a candidate chip layout model is adjusted to obtain a target chip layout model; the target chip layout model is used to determine the chip layout information corresponding to the target area according to the initial layout information corresponding to the target area; The information generation module is used to generate an initial layout diagram according to the initial layout information through the target chip layout model, and divide the initial layout diagram into at least two sub-layout diagrams; linearly map the sub-layout diagrams through the target chip layout model, and encode the linear mapping results through the Transformer encoder in the target chip layout model to obtain layout diagram encoding information; the linear mapping results represent the positions of each circuit unit; the layout diagram encoding information is used to represent the coordinates and occupancy status of each position in the target area; obtain the to-be-layout position information of each circuit unit through the target chip layout model, and according to the layout The invention relates to a method for determining an updated layout diagram corresponding to the sub-layout diagram based on the diagram coding information and the information of the positions to be laid out of each circuit unit; determining the updated layout positions of each circuit unit according to the updated layout diagram corresponding to the sub-layout diagram through the target chip layout model; obtaining reward information corresponding to the updated layout positions of each circuit unit through the target chip layout model; the reward information is used to characterize the rationality of the layout method corresponding to the updated layout position; and determining the chip layout information corresponding to the target area according to the updated layout positions of each circuit unit through the target chip layout model when the reward information meets the preset layout requirements.

5. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 3 are implemented.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

7. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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