Liquid crystal display device

Abstract

Each pixel of a liquid crystal display device has a 3TFT structure including a first liquid crystal capacitor including a first pixel electrode, a second liquid crystal capacitor including a second pixel electrode, a first TFT having a drain connected to the first pixel electrode, a second TFT having a drain connected to the second pixel electrode, and a buffer capacitor including a buffer capacitor electrode connected to the second pixel electrode via a third TFT, the liquid crystal display device being configured to supply a gate scan signal to a plurality of gate bus lines independently in a row by row manner and to apply a sub-gate-on pulse to the third TFTs belonging to at least two pixel rows substantially simultaneously.

Description

Technical Field

[0001] This invention relates to liquid crystal display devices, and more particularly to liquid crystal display devices having a structure suitable for use as large and / or high-resolution liquid crystal display devices. Background Technology

[0002] Liquid crystal display (LCD) devices are continuously evolving towards larger sizes and higher resolutions. To improve grayscale display characteristics (gamma characteristics) at tilted viewing angles, LCD devices have become widespread, where each pixel consists of a first pixel (bright pixel) displaying a grayscale level higher than the required grayscale and a second pixel (dark pixel) displaying a grayscale level lower than the required grayscale. This pixel structure is sometimes referred to as a multi-pixel structure or a pixel-segmentation structure. Furthermore, the first pixel and second pixel of each pixel are sometimes referred to as a first sub-pixel (bright sub-pixel) and a second sub-pixel (dark sub-pixel), respectively.

[0003] Patent Document 1 discloses a liquid crystal display device having three thin-film transistors (TFTs) in each pixel of a liquid crystal display device with a multi-pixel structure. Hereinafter, the structure with three TFTs per pixel described in Patent Document 1 will sometimes be referred to as a "3TFT structure". The entire disclosure of Patent Document 1 is incorporated herein by reference.

[0004] Two of the three TFTs respectively turn the pixel electrodes of the first pixel (bright pixel) and the second pixel (dark pixel) on / off to the source bus. For example, the drain of the first TFT is connected to the first pixel electrode of the first pixel, and the drain of the second TFT is connected to the second pixel electrode of the second pixel. The gates of the first TFT and the second TFT are connected to a common gate bus, and the sources of the first TFT and the second TFT are connected to a common source bus. The third TFT turns the buffer capacitor electrode on / off to the second pixel electrode. The gate of the third TFT is connected to the gate bus of the next level (e.g., the nth) that connects the gates of the first TFT and the second TFT.

[0005] The first TFT and the second TFT are simultaneously turned on by a gate conduction pulse included in the gate scan signal provided to the shared gate bus, and a display signal voltage provided to the shared source bus is applied to the first pixel electrode and the second pixel electrode. After the first TFT and the second TFT are turned off, the third TFT is turned on, and the second pixel electrode and the buffer capacitor electrode are electrically connected. Since the second liquid crystal capacitor containing the second pixel electrode and the buffer capacitor containing the buffer capacitor electrode are electrically connected, the charge accumulated in the second liquid crystal capacitor moves to the buffer capacitor. As a result, the voltage held by the second liquid crystal capacitor decreases, and the second pixel becomes a dark pixel.

[0006] Patent Document 2 discloses a structure in which a common gate scan signal is supplied to two discharge signal lines (sometimes referred to as "sub-gate buses" in this specification) that are connected to the gates of the third TFTs corresponding to the two pixel rows in a structure that scans two pixel rows using a common gate scan signal. (Patent Document 2) Figure 21 (Example 5).

[0007] Furthermore, Patent Document 3 discloses a liquid crystal display device capable of adjusting the timing of the sub-gate turn-on pulses included in the sub-gate scan signal supplied to the sub-gate bus connected to the gate of the third TFT. By adjusting the timing of the sub-gate turn-on pulses, the degree of effect brought about by the multi-pixel structure can be adjusted.

[0008] Existing technical documents

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 2006-276411

[0011] Patent Document 2: International Publication No. 2017 / 033341

[0012] Patent Document 3: International Publication No. 2017 / 104006 Summary of the Invention

[0013] The problem that the invention aims to solve

[0014] In a variation 5 of Patent Document 2, similar to the discharge signal line (sub-gate bus), the gate bus is also configured such that two lines converge to supply a common scan signal. Therefore, the number of source buses supplying the display signal voltage is doubled, resulting in problems such as low wiring layout efficiency (i.e., pixel aperture ratio) in the display area and increased cost due to the increased number of drivers supplying the display signal voltage.

[0015] If a 3TFT structure as described in Patent Document 3 is adopted, a sub-gate scan signal is required, which includes a sub-gate turn-on pulse for turning on at a timing different from that of the first and second TFTs. This requires space for configuring the sub-gate bus for the sub-gate scan signal and the circuitry supplying the sub-gate scan signal to the sub-gate bus, thus hindering the high resolution and / or narrow bezel of the liquid crystal display device. This is known as low layout efficiency.

[0016] Therefore, the object of the present invention is to provide a liquid crystal display device capable of suppressing the reduction in layout efficiency caused by the use of a 3TFT structure.

[0017] Solution for solving the problem

[0018] According to an embodiment of the present invention, a solution described in the following items is provided.

[0019] [Project 1] A liquid crystal display device, comprising:

[0020] Multiple pixels arranged in a matrix, having multiple pixel rows and multiple pixel columns;

[0021] Multiple gate buses, each associated with any one of the multiple pixel rows;

[0022] Multiple source buses, each associated with any one of the multiple pixel columns;

[0023] Multiple sub-gate buses are each associated with any one of the multiple pixel rows.

[0024] Each of the plurality of pixels possesses:

[0025] A first liquid crystal capacitor, which includes a first pixel electrode;

[0026] The second liquid crystal capacitor includes a second pixel electrode;

[0027] The first TFT has a drain connected to the first pixel electrode;

[0028] The second TFT has a drain connected to the second pixel electrode;

[0029] A buffer capacitor, comprising a buffer capacitor electrode connected to the second pixel electrode via a third TFT.

[0030] The gates of the first TFT and the second TFT of each pixel are connected to a gate bus associated with the pixel row containing that pixel.

[0031] The sources of the first TFT and the second TFT of each pixel are connected to a source bus associated with the pixel column containing that pixel.

[0032] The gate of the third TFT of each pixel is connected to a sub-gate bus associated with the pixel row containing that pixel.

[0033] The liquid crystal display device also has:

[0034] Source drive circuitry that provides source signals to the plurality of source buses; and

[0035] A gate driving circuit supplies gate scan signals, including gate turn-on pulses that turn on the first TFT and the second TFT, to the plurality of gate buses, and sub-gate scan signals, including sub-gate turn-on pulses that turn on the third TFT, to the plurality of sub-gate buses.

[0036] The multiple gate buses are supplied with gate scan signals independently one by one, and sub-gate conduction pulses are applied substantially simultaneously to the third TFTs belonging to at least two pixel rows.

[0037] [Item 2] The liquid crystal display device as described in Item 1 is configured to: independently supply gate scan signals to the plurality of gate buses one by one, and provide the plurality of sub-gate buses with a sub-gate scan signal shared by at least two sub-gate buses associated with the at least two pixel rows.

[0038] [Item 3] The liquid crystal display device as described in Item 2, wherein the at least two sub-gate buses are electrically connected to each other.

[0039] [Item 4] In the liquid crystal display device of Item 1, the at least two pixel rows include two adjacent pixel rows, and the third TFT belonging to the two pixel rows is connected to a common sub-gate bus.

[0040] [Item 5] In the liquid crystal display device of Item 4, the second pixel electrode of a pixel belonging to one pixel in one pixel row of the two pixel rows and the second pixel electrode of a pixel belonging to the same column as the pixel in the other pixel row are configured to be adjacent to each other when viewed from above, separated by the shared sub-gate bus.

[0041] [Item 6] In the liquid crystal display device as described in Item 4 or Item 5, in the pixels of one pixel row within the two pixel rows, the second pixel electrode is located closer to the other pixel row than the first pixel electrode, and in the pixels of the other pixel row, the second pixel electrode is located closer to the one pixel row than the first pixel electrode.

[0042] [Item 7] The liquid crystal display device as described in any one of Items 1 to 6, wherein the gate driving circuit is formed on the same substrate as the plurality of gate buses and the plurality of sub-gate buses.

[0043] [Item 8] The liquid crystal display device as described in Item 7, wherein the gate driving circuit has a shift register circuit.

[0044] In the shift register circuit, the number of stages that output the sub-gate scan signal is smaller than the number of stages that output the gate scan signal.

[0045] [Item 9] The liquid crystal display device as described in Item 7, wherein the gate driving circuit has a shift register circuit.

[0046] The shift register circuit has a stage for outputting the gate scan signal and the sub-gate scan signal.

[0047] [Item 10] The liquid crystal display device as described in Item 9, wherein the shift register circuit has a stage that outputs only the sub-gate scan signal.

[0048] [Item 11] The liquid crystal display device as described in Item 10 is configured such that: the sub-gate scan signal output from a stage that outputs the gate scan signal and the sub-gate scan signal is supplied to a sub-gate bus, and the sub-gate scan signal output from a stage that outputs only the sub-gate scan signal is supplied to at least two sub-gate buses associated with the at least two pixel rows.

[0049] [Item 12] In any one of Items 9 to 11, the multiple gate buses and the multiple sub-gate buses are not directly connected.

[0050] [Item 13] The liquid crystal display device as described in Item 7, wherein the gate driving circuit has a shift register circuit.

[0051] The circuit is configured to sequentially input p-phase (p being an integer greater than or equal to 2) clock signals to each stage of the shift register circuit, thereby substantially simultaneously applying sub-gate conduction pulses to the third TFT belonging to q consecutive pixel rows, where q is an integer greater than or equal to 2 that has no common divisor other than 1 relative to the number of phases p of the aforementioned clock signals.

[0052] [Item 14] The liquid crystal display device as described in Item 7 is configured as follows:

[0053] The gate drive circuit includes a shift register circuit.

[0054] A p-phase clock signal (p being an integer greater than 2) is sequentially input to each stage of the shift register circuit, and sub-gate conduction pulses are substantially applied simultaneously to the third TFT, which belongs to multiple pixel rows that are separated by r pixel rows (r being a multiple of p).

[0055] [Item 15] A driving method for a liquid crystal display device as described in any one of Items 1 to 14.

[0056] Beneficial effects

[0057] According to an embodiment of the present invention, a liquid crystal display device having a 3TFT structure and a driving method thereof are provided, which suppresses the reduction of layout efficiency. Attached Figure Description

[0058] Figure 1 This is a schematic plan view of a liquid crystal display device 100A according to an embodiment of the present invention.

[0059] Figure 2This is a schematic equivalent circuit diagram of two adjacent pixels in the column direction of the liquid crystal display device 100A.

[0060] Figure 3 This is a schematic representation of what is used for driving. Figure 2 The diagram shows the waveforms of the gate scan signal GS, the sub-gate scan signal SGS, the voltage of the first pixel electrode (bright pixel electrode) PE1, and the voltage of the second pixel electrode (dark pixel electrode) PE2 for the two pixels.

[0061] Figure 4 This is a schematic plan view of a liquid crystal display device 100B according to an embodiment of the present invention.

[0062] Figure 5 This is a schematic plan view of a liquid crystal display device 100C according to an embodiment of the present invention.

[0063] Figure 6 This is a schematic plan view of an existing liquid crystal display device 900 with a 3TFT structure.

[0064] Figure 7 It is a schematic voltage waveform diagram used to drive the gate scan signal GS, sub-gate scan signal SGS, voltage of first pixel electrode PE1, and second pixel electrode PE2 of two adjacent pixels in the column direction of the liquid crystal display device 900.

[0065] Figure 8 This is a schematic plan view of a liquid crystal display device 100D according to an embodiment of the present invention.

[0066] Figure 9 This is a schematic equivalent circuit diagram of two adjacent pixels in the column direction of a liquid crystal display device 100D.

[0067] Figure 10 This is a schematic circuit diagram of the first stage of the shift register circuit SR.

[0068] Figure 11 It means Figure 10 The diagram shows the schematic waveforms of the signals and the potential of the internal node netA.

[0069] Figure 12 This is a schematic diagram showing the circuit structure of the output gate scan signal GS.

[0070] Figure 13 This is a schematic diagram showing the circuit structure of the gate drive circuit 140, which is composed of a shift register circuit SR.

[0071] Figure 14 This is a schematic circuit diagram of the first stage of the shift register circuit SR, which outputs the gate scan signal GS and the sub-gate scan signal SGS.

[0072] Figure 15 This is a schematic diagram showing the circuit structure of the gate drive circuit 140A, which is composed of a shift register circuit SR.

[0073] Figure 16 This is a schematic diagram illustrating the structure of the gate driving circuit 140A that a liquid crystal display device according to an embodiment of the present invention can have.

[0074] Figure 17 This is a schematic diagram illustrating the structure of the gate driving circuit 140B that a liquid crystal display device according to an embodiment of the present invention can have.

[0075] Figure 18 This is a schematic diagram illustrating the structure of the gate driving circuit 140C that a liquid crystal display device according to an embodiment of the present invention can have.

[0076] Figure 19 This is a schematic diagram illustrating the structure of the gate driving circuit 140D that a liquid crystal display device according to an embodiment of the present invention can have.

[0077] Figure 20 This is a schematic circuit diagram of a first stage of another shift register circuit SR used in the gate drive circuit of a liquid crystal display device according to an embodiment of the present invention.

[0078] Figure 21 This is a schematic circuit diagram of a stage of another shift register circuit SR used in the gate drive circuit of a liquid crystal display device according to an embodiment of the present invention.

[0079] Figure 22 This is a schematic circuit diagram of a stage of another shift register circuit SR used in the gate drive circuit of a liquid crystal display device according to an embodiment of the present invention.

[0080] Figure 23 This is a schematic circuit diagram of a stage of another shift register circuit SR used in the gate drive circuit of a liquid crystal display device according to an embodiment of the present invention.

[0081] Figure 24 This is a schematic circuit diagram of a stage of another shift register circuit SR used in the gate drive circuit of a liquid crystal display device according to an embodiment of the present invention. Detailed Implementation

[0082] Hereinafter, a liquid crystal display device based on an embodiment of the present invention will be described with reference to the accompanying drawings. The liquid crystal display device according to the embodiments of the present invention is not limited to the liquid crystal display device illustrated below.

[0083] Figure 1 A schematic plan view illustrating a liquid crystal display device 100A according to an embodiment of the present invention. Figure 2 A schematic equivalent circuit diagram showing two adjacent pixels in the column direction of the liquid crystal display device 100A. Figure 3 Schematic representation of what is used for driving Figure 2 The waveforms of the gate scan signal GS, sub-gate scan signal SGS, voltage of the first pixel electrode (bright pixel electrode) PE1, and voltage of the second pixel electrode (dark pixel electrode) PE2 for the two pixels are shown.

[0084] like Figure 1 As shown, the liquid crystal display device 100A has multiple pixels P arranged in a matrix with multiple pixel rows (m rows) and multiple pixel columns (n ​​columns). The area where multiple pixels P are formed is called the active area AA or the display area. Sometimes, the pixel in row k and column 1 of the pixels arranged in m rows and n columns is represented as P(k, 1). k, 1, m, and n are positive integers that satisfy the relationship 1 ≤ k ≤ m and 1 ≤ 1 ≤ n. For example, in a liquid crystal display device for a so-called 4K television, when m = 2160 and n = 3840 × 3 (when color display pixels are composed of R pixels, G pixels, and B pixels, the "pixel" mentioned here is sometimes called a "dot", and the "color display pixel" composed of 3 "dots" is called a "pixel"). The active area AA is formed, for example, on a liquid crystal cell 110A having two substrates (e.g., glass substrates) arranged opposite each other with a liquid crystal layer between them.

[0085] The liquid crystal display device 100A also includes: multiple gate buses GB (m lines), each associated with any one of the multiple pixel columns; multiple source buses SB (n lines), each associated with any one of the multiple pixel columns; and multiple sub-gate buses SGB, each associated with any one of the multiple pixel columns. These are formed on a substrate of one side of the liquid crystal cell 110A.

[0086] like Figure 2 As shown, multiple pixels P each have a first pixel (bright pixel) P1 that displays a gray level higher than the gray level to be displayed, and a second pixel (dark pixel) P2 that displays a gray level lower than the gray level to be displayed. The first pixel P1 has: a first liquid crystal capacitor Clc1 containing a first pixel electrode PE1; a first auxiliary capacitor Ccs1 containing a first auxiliary capacitor electrode CE1; and a first TFTM1 connected to the drain of the first pixel electrode PE1 and the first auxiliary capacitor electrode CE1. The potentials of the first pixel electrode PE1 and the first auxiliary capacitor electrode CE1 are the same as the potential of node PE1n.

[0087] The second pixel P2 has: a second liquid crystal capacitor Clc2 including a second pixel electrode PE2, a second auxiliary capacitor Ccs2 including a second auxiliary capacitor electrode CE2, and a second TFTM2 with its drain connected to the second pixel electrode PE2 and the second auxiliary capacitor electrode CE2. The potentials of the second pixel electrode PE2 and the second auxiliary capacitor electrode CE2 are the same as the potential of the node PE2n. The second pixel P2 also has a buffer capacitor Cb, which includes a buffer capacitor electrode BE connected to the node PE2n via a third TFTM3.

[0088] The electrodes that are respectively opposite to the first pixel electrode PE1, the second pixel electrode PE2, the first auxiliary capacitor electrode CE1, the second auxiliary capacitor electrode CE2, and the buffer capacitor electrode BE are electrically connected to the common wiring CS and are subjected to a common voltage (also known as the opposing voltage). Figure 3 The waveforms of the voltages of the first pixel electrode PE1 and the second pixel electrode (dark pixel electrode) PE2 shown are based on a common voltage. For simplicity, they are both represented as positive polarity voltages, but the polarity can be reversed in rows k and k+1 (dot inversion or row inversion). In addition, voltages of opposite polarity are applied before and after the frame shown in the figure (during vertical scanning) (frame inversion drive).

[0089] Each pixel P has a first TFTM1 and a second TFTM2 whose gates are connected to a gate bus GB (e.g., GB(k)) associated with the pixel row (e.g., k rows) containing the pixel P, and the source of each pixel has a first TFTM1 and a second TFTM2 whose source is connected to a source bus (e.g., SB(1)) associated with the pixel column (e.g., 1 column) containing the pixel, and the gate of each pixel has a third TFTM3 whose gate is connected to a sub-gate bus (e.g., SGB(k)) associated with the pixel row (e.g., k rows) containing the pixel.

[0090] The liquid crystal display device 100A includes: a source driving circuit 120 that provides source signals to multiple source buses SB; and a gate driving circuit (140) that provides gate scan signals GS, including gate conduction pulses GOP that turn on the first TFTM1 and the second TFTM2, to multiple gate buses GB, and provides sub-gate scan signals SGS, including sub-gate conduction pulses SGOP that turn on the third TFTM3, to multiple sub-gate buses SGB. The gate driving circuit 140 is formed, for example, on the same substrate as the multiple gate buses GB and multiple sub-gate buses SGB in the two substrates of the liquid crystal cell. This configuration is sometimes referred to as a G0A (gate array) configuration. Alternatively, the source driving circuit 120 may be formed or mounted on the same substrate as the gate driving circuit 140.

[0091] like Figure 3As shown, gate scan signals GS are independently supplied to each of the multiple gate buses GB, and sub-gate turn-on pulses SGOP are substantially applied simultaneously to the third TFTM3 belonging to two pixel rows (e.g., row k and row k+1). For example, as Figure 1 As shown, even when configured to apply a common sub-gate scan signal SGS to the third TFTs belonging to two pixel rows, gate delay (SGOP delay) occurs due to the resistance and parasitic capacitance of the wiring in the liquid crystal display device 100A. Therefore, sometimes the sub-gate turn-on pulse SGOP is not strictly applied simultaneously to the third TFTs M3 belonging to two different pixel rows. "Substantially simultaneously" means ignoring the difference caused by gate delay.

[0092] An example of the driving method and operation of the liquid crystal display device 100A will be described. Here, an example is shown where a sub-gate conduction pulse SGOP is substantially applied simultaneously to the third TFTM3 belonging to two pixel rows (e.g., row k and row k+1), but it is also possible to configure it so that the sub-gate conduction pulse SGOP is substantially applied simultaneously to the third TFTM3 belonging to three or more pixel rows (e.g., row k, row k+1, and row k+2). The same applies to the liquid crystal display devices 100B, 100C, 140, 140A, 140B, 140C, and 140D illustrated later.

[0093] During each frame (vertical scan), the gate turn-on pulse (GOP) is sequentially applied to the gate bus (GB) corresponding to all rows (so-called line-sequence drive). For example, as Figure 3 As shown, after applying the gate turn-on pulse GOP to the gate bus GB(k), the gate turn-on pulse GOP is then applied to the gate bus GB(k+1).

[0094] When the gate conduction pulse GOP is applied to the gate bus GB(k), the first TFTM1 and the second TFTM2 of pixel P(k,1) are simultaneously turned on. The display signal voltage (bright pixel display signal voltage) supplied to the shared source bus SB (e.g., SB(1)) is applied to the first pixel electrode PE1 and the second pixel electrode PE2, as follows: Figure 3 As shown by PE1(k) and PE2(k), they rise.

[0095] Similarly, when the gate conduction pulse GOP is applied to the gate bus GB(k+1), the first TFTM1 and the second TFTM2 of pixel P(k+1, 1) are simultaneously turned on, and the display signal voltage (the display signal voltage for bright pixels) provided to the shared source bus SB (e.g., SB(1)) is applied to the first pixel electrode PE1 and the second pixel electrode PE2, as shown. Figure 3 As shown by PE1(k+1) and PE2(k+1), they rise.

[0096] When the first TFTM1 and second TFTM2 of pixels P(k,1) and P(k+1,1) are turned off, and within a certain period after the gate conduction pulse GOP applied to the gate bus GB(k+1) falls, when the sub-gate conduction pulse SGOP is applied to the sub-gate buses SGB(k) and SGB(k+1) substantially simultaneously, the third TFTM3 of pixels P(k,1) and P(k+1,1) belonging to the two pixel rows (row k, row k+1) are substantially turned on simultaneously. In this way, in each of pixels P(k,1) and P(k+1,1), since node PE2n is electrically connected to the buffer capacitor electrode BE, the charge accumulated in the second liquid crystal capacitor Clc2 and the second auxiliary capacitor Ccs2 moves to the buffer capacitor Cb. As a result, the voltage held by the second liquid crystal capacitor Clc2 and the second auxiliary capacitor Ccs2 decreases, and the second pixel P2 becomes a dark pixel. The first liquid crystal capacitor Clc1 and the first auxiliary capacitor Ccs1 of the first pixel P1 continuously maintain the display signal voltage (the display signal voltage used for bright pixels), thus becoming a bright pixel.

[0097] The structure involves independently supplying gate scan signals GS to multiple gate buses GB and supplying sub-gate scan signals SGS shared by two sub-gate buses SGB associated with two pixel rows, for example, as follows: Figure 1 As shown, this can be achieved by interconnecting the two sub-gate buses SGB in the sub-gate branch SGBb.

[0098] Alternatively, it can be like Figure 4 Like the liquid crystal unit 110B of the liquid crystal display device 100B shown, such as Figure 1 As shown, two sub-gate buses SGB are interconnected in the sub-gate branch SGBb, and the ends of the two sub-gate buses SGB are connected together using a terminating connection line SGBr to form a loop. Alternatively, the sub-gate branch SGBb can be omitted, and only the terminating connection line SGBr is used to connect the two sub-gate buses SGB. Another approach is as follows... Figure 5 Like the liquid crystal cell 110C in the liquid crystal display device 100C shown, the two sub-gate buses SGB are interconnected by multiple sub-gate branches SGBb. Of course, a termination connection line SGBr can also be further provided.

[0099] By interconnecting two sub-gate buses SGB at multiple points using sub-gate branches SGBb and / or termination lines SGBr, display unevenness caused by the difference in the delay time of the sub-gate conduction pulse SGOP between the two sub-gate buses SGB can be suppressed. Furthermore, even if one of the two sub-gate buses SGB breaks down, the sub-gate scan signal SGS is still provided from the other, thus improving the yield of the liquid crystal display device. Of course, these advantages can also be obtained when a shared sub-gate scan signal SGS is supplied to three or more sub-gate buses SGB.

[0100] For comparison, in Figure 6 The diagram shows a schematic plan view of a conventional liquid crystal display device 900 with a 3TFT structure. Figure 7 Schematic illustration of the drive Figure 6 The liquid crystal display device 900 shown displays the gate scan signal GS, sub-gate scan signal SGS, voltage of the first pixel electrode (bright pixel electrode) PE1, and voltage waveform of the second pixel electrode (dark pixel electrode) PE2 for two adjacent pixels in the column direction. The liquid crystal display device 900 includes a liquid crystal cell 910 having an active region AA containing multiple pixels, a source driving circuit 920, and a gate driving circuit 940.

[0101] In the liquid crystal cell 910 of the liquid crystal display device 900, gate scan signals GS are supplied independently to each of the multiple gate buses GB, and sub-gate scan signals SGS are also supplied independently to each of the multiple sub-gate buses SGB. Therefore, the voltage of the second pixel electrode PE2 of each pixel row decreases after a sub-gate conduction pulse SGOP is independently supplied from its corresponding sub-gate bus SGB.

[0102] The number of sub-gate scan signals SGS output by the gate drive circuit 140 in the liquid crystal display devices 100A to 100C based on the above embodiments is half the number of sub-gate scan signals SGS output by the gate drive circuit 940 in the liquid crystal display device 900. Therefore, the structure of the gate drive circuit 140 can be simpler than that of the gate drive circuit 940. When using a GOA structure, the advantages of improving layout efficiency and reducing costs by reducing the gate signal generation circuit and winding wiring are particularly significant.

[0103] Moreover, if adopted Figure 8 as well as Figure 9 The structure of the liquid crystal display device 100D shown can halve the number of sub-gate buses SGB within the active region AA. Figure 8 A schematic plan view of a liquid crystal display device 100D according to an embodiment of the present invention is shown. Figure 9A schematic equivalent circuit diagram of two adjacent pixels in the column direction of a liquid crystal display device 100D is shown.

[0104] In the liquid crystal display device 100D, the third TFTM3 belonging to two adjacent pixel rows (e.g., row k, row k+1) is connected to a shared sub-gate bus SGB (e.g., SGB(k, k+1)). The second pixel electrode PE2 of a pixel belonging to one pixel row within the two pixel rows and the second pixel electrode PE2 of a pixel in the same column as the first pixel belonging to the other pixel row are arranged adjacent to each other in a manner separated by the shared sub-gate bus SGB when viewed from above. The column-direction arrangement of the first pixel (bright pixel) P1 and the second pixel (dark pixel) P2 in the liquid crystal display device 100D is, for example, as shown in the example... Figure 9 As shown, in the sequence from pixel P(k, 1) to pixel P(k+1, 1), the sequence becomes: first pixel (bright pixel) P1 → second pixel (dark pixel) P2 → second pixel (dark pixel) P2 → first pixel (bright pixel) P1, and this is reversed along each pixel row. This is similar to... Figure 2 The liquid crystal display device 100A shown presents a contrasting arrangement where pixel P(k,1) → pixel P(k+1,1) becomes the first pixel (bright pixel) P1 → the second pixel (dark pixel) P2 → the first pixel (bright pixel) P1 → the second pixel (dark pixel) P2. In a liquid crystal display device 100D, in a pixel (e.g., pixel P(k, 1)) belonging to one pixel row of two pixel rows having a shared sub-gate bus SGB (e.g., SGB(k, k+1)), the second pixel (dark pixel) P2 (second pixel electrode PE2) is located further away from the first pixel (bright pixel) P1 (first pixel electrode PE1) than the first pixel (bright pixel) P1 (first pixel electrode PE1) on the other pixel row side (i.e., the shared sub-gate bus SGB side). In a pixel (e.g., pixel P(k+1, 1)) belonging to the other pixel row, the second pixel (dark pixel) P2 (second pixel electrode PE2) is located further away from the first pixel (bright pixel) P1 (first pixel electrode PE1) on the other pixel row side (i.e., the shared sub-gate bus SGB side).

[0105] Next, refer to Figures 10-12 An example of a gate drive circuit for a G0A structure is given.

[0106] Typical gate drive circuits with GOA structure, such as Figures 10-12 As shown, it is composed of a shift register circuit SR. Figure 10 This is a schematic circuit diagram of stage 1 of the shift register circuit SR. Figure 11 It means Figure 10 A schematic waveform diagram of each signal and the potential of the internal node netA. Figure 12 This is a schematic diagram showing the circuit structure of the output gate scan signal GS(GS(k)). Figure 13 This is a schematic diagram showing the circuit structure of the gate drive circuit 140, which is composed of a shift register circuit SR.

[0107] Reference Figure 10 The shift register circuit SR receives clock signal CLK, reference voltage signal Vss, Set signal, and Reset signal as inputs to each stage of the circuit. The Set and Reset signals utilize signals generated in other stages. Each stage of the shift register circuit SR is configured with: transistor MA, which outputs a gate scan signal GS(Gout(GS(k))) from the power node (CLK) based on the voltage level of the internal node netA; transistor MB, which boosts the internal node netA via a Set signal, Gout(GS(kx), where x = 2), which is x stages earlier (x is a positive integer); capacitor cap1, which maintains the voltage of the internal node netA boosted by transistor MB; and transistor Mc, which depresses the internal node netA via a Reset signal, Gout(GS(k+y), where y = 3), which is y stages later (y is a positive integer). Figure 11 In this context, 1H indicates the scanning period at level 1.

[0108] The circuit that generates the sub-gate scan signal SGS is also composed of a shift register circuit. The gate drive circuit 140 is in... Figure 13 In the example shown, there is a circuit 140G that outputs the gate scan signal GS(k) to the gate bus (GB(k)) and a circuit 140SG that outputs the sub-gate scan signal SGS(k) to the sub-gate bus (SGB(k)).

[0109] The number of sub-gate scan signals SGS output from the gate drive circuit 140 in the above embodiment can be less than the number of gate scan signals GS. Therefore, as Figure 13 As shown, the number of stages in circuit 140SG for output sub-gate scan signal SGS is smaller than the number of stages in circuit 140G for output gate scan signal GS.

[0110] Next, refer to Figures 14-19 This illustrates an example of a gate drive circuit 140 that includes both an output gate scan signal GS and a sub-gate scan signal SGS.

[0111] Figure 14 This is a schematic circuit diagram of stage 1 of the shift register circuit SR, which outputs the gate scan signal GS and the sub-gate scan signal SGS. Figure 15 This is a schematic diagram showing the circuit structure of the gate drive circuit 140A, which is composed of such a shift register circuit SR.

[0112] For example, one can think of, such as Figure 14 and Figure 15 As shown in the gate drive circuit, the structure of the gate drive circuit is simplified by using the gate scan signal GS of a certain stage as the sub-gate scan signal SGS of the previous stage. That is, the shift register circuit constituting the gate drive circuit has a stage that outputs both the gate scan signal GS and the sub-gate scan signal SGS.

[0113] Figure 16 The structure of another gate driving circuit 140A that can be included in the liquid crystal display device according to an embodiment of the present invention is schematically shown. In the gate driving circuit 140A, the gate scan signal GS of a certain stage is used as the sub-gate scan signal SGS of the two stages preceding it. Thus, as Figure 16 As shown, the number of lead-in wirings for the sub-gate scan signal (SGS) can be reduced, thereby increasing the yield and layout efficiency due to the increased space between wirings.

[0114] Figure 16 The gate drive circuit 140A shown contains a shift register circuit SR that outputs the sub-gate scan signal SGS and a shift register circuit SR that does not output the sub-gate scan signal SGS, which differs from the load of the gate wiring (gate bus GB and sub-gate bus SGB) connected to each stage. By adjusting the driving capability of the transistor MA according to this load, the output waveform of each stage can be made uniform, thereby improving the display quality.

[0115] The driving capability of a transistor is roughly proportional to the channel width W / channel length L (hereinafter W / L). Therefore, it is sufficient to adjust the W / L of the transistor MA to make it proportional to the total capacitance value of the gate bus GB and sub-gate bus SGB connected to the source of each stage of the transistor MA.

[0116] Furthermore, by making the number of sub-gate scan signals SGS driven by each clock signal CLK approximately the same, the load difference caused by the difference in clock signal CLK can be reduced. For example, it can be done as follows: Figure 17 As shown in the gate drive circuit 140B, it is configured such that four (p: p is an integer of 2 or more) phase clock signals CLK1 to 4 (CLK1 to p) are sequentially input into each stage of the shift register circuit SR. For the third TFT of consecutive pixel rows belonging to integers 3 (q: integers of 2 or more) that do not have a common divisor other than 1 relative to the phase number 4 (p) of the clock signal CLK, a sub-gate turn-on pulse SGOP (supplying a common sub-gate scan signal SGS to q consecutive pixel rows) is substantially applied simultaneously. At this time, the sub-gate scan signal SGS is output in q stages, but since p and q do not have a common divisor other than 1, it is possible to prevent the shift register circuit SR outputting the sub-gate scan signal SGS from being biased towards a specific clock signal CLK.

[0117] Or, such as Figure 18 As shown in the gate drive circuit 140C, four (p: p is an integer greater than or equal to 2) phase clock signals CLK1 to 4 (CLK1 to p) are sequentially input to each stage of the shift register circuit SR. This can be achieved by simultaneously applying a sub-gate turn-on pulse SGOP (supplying a common sub-gate scan signal SGS to the multiple pixel rows that are separated by r pixel rows (r is a multiple of p, here r = 4) to the third TFTs. Since the sub-gate scan signals SGS, which were originally driven by the same clock signal CLK, are combined (for example, the sub-gate scan signals output to SGB(k) and SGB(k+4)), the signal can be summarized without disrupting the balance between the clock signals CLK.

[0118] In essence, the structure that simultaneously applies a sub-gate conduction pulse to the third TFT belonging to at least two pixel rows can also be applied to only a part of the gate drive circuit.

[0119] For example, such as Figure 19 As shown in the gate drive circuit 140D, by applying a structure that substantially simultaneously applies sub-gate conduction pulses to the third TFTs belonging to at least two pixel rows to a scan terminal section that requires only the output of the sub-gate scan signal SGS instead of the gate scan signal GS, the number of circuits required for the output of the sub-gate scan signal SGS can be reduced. Figure 19 In the gate drive circuit 140D shown, the sub-gate scan signal SGS, which is configured to be output from both the output gate scan signal GS and the sub-gate scan signal SGS, is provided to a sub-gate bus SGB. The sub-gate scan signal SGS, which is output from only the stage that outputs the sub-gate scan signal SGS, is provided to at least two sub-gate buses SGB associated with at least two pixel rows. By employing this structure, the load on the gate wiring to the transistor MA can be uniformized.

[0120] In addition, such as Figure 20 as well as Figure 21 As shown, the structure of the output sub-gate scan signal SGS can also be set separately from the structure of the output gate scan signal GS in each stage of the shift register circuit SR. That is, in each stage of the shift register circuit SR, the output transistor MA for the output sub-gate scan signal SGS can also be set independently of the output transistor MA for the output gate scan signal GS. In this case, the output transistor MA and the output transistor MA' are as follows: Figure 20 As shown, it can be connected to a common clock signal input terminal, or as... Figure 21As shown, they are connected to different clock signal input terminals respectively. By using a shift register circuit with this structure, it is not necessary to directly connect the gate bus GB and the sub-gate bus SGB. In this way, for example, if a fault occurs in the gate bus GB or the sub-gate bus SGB (e.g., a broken wire), the scope of its impact is limited, thus facilitating the correction of the fault. Furthermore, as... Figure 22 , Figure 23 and Figure 24 As shown, in each stage of the shift register circuit SR, a structure with a terminal Qn for outputting drive signals to other stages can also be adopted.

Claims

1. A liquid crystal display device, characterized in that, have: Multiple pixels, arranged in a matrix with multiple pixel rows and multiple pixel columns; Multiple gate buses, each associated with any one of the multiple pixel rows; Multiple source buses, each associated with any one of the multiple pixel columns; and Multiple sub-gate buses are each associated with any one of the multiple pixel rows. Each of the plurality of pixels possesses: A first liquid crystal capacitor, which includes a first pixel electrode; The second liquid crystal capacitor includes a second pixel electrode; The first TFT has a drain connected to the first pixel electrode; The second TFT has a drain connected to the second pixel electrode; A buffer capacitor, comprising a buffer capacitor electrode connected to the second pixel electrode via a third TFT. The gates of the first TFT and the second TFT of each pixel are connected to a gate bus associated with the pixel row containing that pixel. The sources of the first TFT and the second TFT of each pixel are connected to a source bus associated with the pixel column containing that pixel. The gate of the third TFT of each pixel is connected to a sub-gate bus associated with the pixel row containing that pixel. The liquid crystal display device also has: A source drive circuit that provides source signals to the multiple source buses; and A gate driving circuit supplies gate scan signals, including gate turn-on pulses that turn on the first TFT and the second TFT, to the plurality of gate buses, and sub-gate scan signals, including sub-gate turn-on pulses that turn on the third TFT, to the plurality of sub-gate buses. The multiple gate buses are supplied with gate scan signals independently one by one, and sub-gate conduction pulses are applied substantially simultaneously to the third TFTs belonging to at least two pixel rows.

2. The liquid crystal display device according to claim 1, characterized in that, The configuration is as follows: gate scan signals are supplied independently to each of the plurality of gate buses, and a sub-gate scan signal shared by at least two sub-gate buses associated with the at least two pixel rows is provided to the plurality of sub-gate buses.

3. The liquid crystal display device according to claim 2, characterized in that, The at least two sub-gate buses are electrically connected to each other.

4. The liquid crystal display device according to claim 1, characterized in that, The at least two pixel rows include two pixel rows that are adjacent to each other. The third TFT belonging to the two pixel rows is connected to a shared sub-gate bus.

5. The liquid crystal display device according to claim 4, characterized in that, The second pixel electrode of a pixel belonging to one of the two pixel rows and the second pixel electrode of a pixel belonging to the other pixel row in the same column as the pixel are configured to be adjacent to each other when viewed from above, separated by the shared sub-gate bus.

6. The liquid crystal display device according to claim 4, characterized in that, In the pixels belonging to one of the two pixel rows, the second pixel electrode is located closer to the other pixel row than the first pixel electrode. In the pixels belonging to the other pixel row, the second pixel electrode is located closer to the first pixel row than the first pixel electrode.

7. The liquid crystal display device according to claim 1, characterized in that, The gate drive circuit is formed on the same substrate as the multiple gate buses and the multiple sub-gate buses.

8. The liquid crystal display device according to claim 7, characterized in that, The gate drive circuit has a shift register circuit in which the number of stages for outputting the sub-gate scan signal is smaller than the number of stages for outputting the gate scan signal.

9. The liquid crystal display device according to claim 7, characterized in that, The gate drive circuit includes a shift register circuit. The shift register circuit has a stage for outputting the gate scan signal and the sub-gate scan signal.

10. The liquid crystal display device according to claim 9, characterized in that, The shift register circuit has a stage that outputs only the sub-gate scan signal.

11. The liquid crystal display device according to claim 10, characterized in that, The configuration is as follows: the sub-gate scan signal output from the stage that outputs the gate scan signal and the sub-gate scan signal is supplied to a sub-gate bus, and the sub-gate scan signal output from the stage that outputs only the sub-gate scan signal is supplied to at least two sub-gate buses associated with the at least two pixel rows.

12. The liquid crystal display device according to any one of claims 9 to 11, characterized in that, The multiple gate buses and the multiple sub-gate buses are not directly connected.

13. The liquid crystal display device according to claim 7, characterized in that, The gate drive circuit includes a shift register circuit. The circuit is configured to sequentially input p-phase clock signals to each stage of the shift register circuit, and to substantially simultaneously apply sub-gate conduction pulses to the third TFT belonging to q consecutive pixel rows, where q is an integer greater than 2 that has no common divisor other than 1 relative to the number of phases p of the clock signals, and p is an integer greater than 2.

14. The liquid crystal display device according to claim 7, characterized in that, The gate drive circuit includes a shift register circuit. The circuit is configured to sequentially input p-phase clock signals to each stage of the shift register circuit, thereby substantially simultaneously applying sub-gate conduction pulses to the third TFT, which belongs to multiple pixel rows separated by r pixel rows, where p is an integer greater than or equal to 2 and r is a multiple of p.

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