Wafer processing detection method and system

Abstract

The present invention provides a wafer processing detection method and system, which relates to the field of processing detection technology, including: obtaining three-dimensional integrated design information of a first wafer and a second wafer, performing overlap detection, obtaining the edge overlap of the first wafer and the edge overlap of the second wafer, if both are greater than a preset edge overlap, obtaining a second detection instruction, generating a three-dimensional simulation data set, and controlling the wafer detection equipment to perform detection, outputting a three-dimensional detection image set, performing edge recognition, and obtaining bonding processing overlap with the edge recognition data, in order to identify the vertical overlap of the edges of the first wafer and the second wafer after bonding, generating a bonding offset reminder message. The present invention solves the technical problem that the prior art cannot accurately detect three-dimensional bonded wafers when connecting multi-layer wafers, and lacks offset analysis, resulting in an inability to accurately evaluate the bonding quality during wafer processing.

Description

Technical Field

[0001] The present invention relates to the field of processing detection technology, and in particular to a wafer processing detection method and system. Background Art

[0002] Wafer processing inspection is an important link aimed at ensuring the quality and reliability of the wafer processing process. When connecting multiple layers of wafers in traditional wafer processing, the assessment of edge overlap usually relies on manual visual inspection or simple measurement methods. However, this method is subjective and inaccurate, and it is difficult to meet the needs of efficient production. In addition, when there is a position deviation between the upper and lower integrated wafers, it may cause unstable or incomplete connections between adjacent wafers, thereby affecting the overall wafer processing quality.

[0003] Therefore, it is necessary to accurately evaluate edge overlap and provide reminder information of bonding offset during wafer processing, so as to achieve automation and improve accuracy in the wafer processing process, thereby improving production efficiency and quality reliability. Summary of the Invention

[0004] This application provides a wafer processing detection method and system to solve the technical problems in the existing technology that when connecting multi-layer wafers, it is impossible to accurately detect three-dimensional bonded wafers and lacks offset analysis, resulting in the inability to accurately evaluate the bonding quality during wafer processing.

[0005] In view of the above problems, the present application provides a wafer processing detection method and system.

[0006] The first aspect disclosed in the present application provides a wafer processing detection method, the method comprising: obtaining three-dimensional integrated design information of a first wafer and a second wafer; performing overlap detection based on the upper edge and lower edge of the thickness of the first wafer and the second wafer respectively, and obtaining the edge overlap of the first wafer and the edge overlap of the second wafer; if the edge overlap of the first wafer and the edge overlap of the second wafer are both greater than a preset edge overlap, obtaining a second detection instruction; generating a three-dimensional simulation data set using the three-dimensional integrated design information, and controlling a wafer detection device to detect a three-dimensional wafer body using the second detection instruction, and outputting a three-dimensional detection image set, wherein the three-dimensional wafer body is a wafer after three-dimensional through-hole bonding processing of the first wafer and the second wafer; performing edge recognition according to the three-dimensional detection image set, and obtaining bonding processing overlap using the edge recognition data, wherein the bonding processing overlap is the vertical overlap of the edges of the first wafer and the second wafer after bonding; generating bonding offset reminder information based on the bonding processing overlap.

[0007] Another aspect disclosed in the present application provides a wafer processing detection system, which is used for the above method, and the system includes: a design information acquisition unit, which is used to obtain three-dimensional integrated design information of a first wafer and a second wafer; an overlap detection unit, which is used to perform overlap detection based on the upper edge and the lower edge of the thickness of the first wafer and the second wafer, respectively, to obtain the edge overlap of the first wafer and the edge overlap of the second wafer; a detection instruction generation unit, which is used to obtain a second detection instruction if the edge overlap of the first wafer and the edge overlap of the second wafer are both greater than a preset edge overlap; a detection image acquisition unit, which The detection image acquisition unit is used to generate a three-dimensional simulation data set using the three-dimensional integrated design information, and control the wafer detection equipment to detect the three-dimensional wafer body with the second detection instruction, and output a three-dimensional detection image set, wherein the three-dimensional wafer body is the wafer after the first wafer and the second wafer are three-dimensionally bonded; the overlap acquisition unit, the overlap acquisition unit is used to perform edge recognition based on the three-dimensional detection image set, and obtain the bonding processing overlap using the edge recognition data, wherein the bonding processing overlap is the vertical overlap of the edges after the first wafer and the second wafer are bonded; the reminder information generation unit, the reminder information generation unit is used to generate bonding offset reminder information based on the bonding processing overlap.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0009] By performing overlap detection based on the thickness edges of the first wafer and the second wafer, the edge overlap can be accurately calculated, which can help judge the quality of the bonding process and provide quantitative measurement indicators; using three-dimensional integrated design information, a three-dimensional simulation data set is generated. These data sets contain the geometric information of the wafers after bonding and can be used for subsequent wafer detection; by performing edge recognition on the three-dimensional detection image set, the overlap of the bonding process can be calculated, which provides a reliable assessment of the bonding quality and can timely detect bonding offsets; based on the bonding process overlap, a bonding offset reminder message is generated, which helps the operator take timely measures to correct the offset problem and avoid further damage to the quality and reliability of the wafer processing. In summary, the wafer processing detection method solves the edge projection overlap detection and bonding offset reminder problems in the existing technology, realizes the accurate assessment and timely correction of the bonding process quality, and thus improves the reliability and efficiency of wafer processing.

[0010] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic flow chart of a wafer processing detection method is provided for an embodiment of the present application;

[0012] Figure 2 A schematic structural diagram of a wafer processing detection system is provided for an embodiment of the present application.

[0013] Explanation of the accompanying reference numerals: design information acquisition unit 10 , coincidence detection unit 20 , detection instruction generation unit 30 , detection image acquisition unit 40 , coincidence acquisition unit 50 , reminder information generation unit 60 . DETAILED DESCRIPTION

[0014] The embodiments of the present application provide a wafer processing detection method to solve the technical problems in the prior art that when multi-layer wafers are connected, the three-dimensional bonded wafers cannot be accurately detected, and the offset analysis is lacking, resulting in the inability to accurately evaluate the bonding quality during the wafer processing process.

[0015] After introducing the basic principles of the present application, various non-limiting implementation methods of the present application will be specifically introduced in conjunction with the drawings in the specification.

[0016] Example 1

[0017] like Figure 1 As shown, an embodiment of the present application provides a wafer processing detection method, the method comprising:

[0018] Acquiring three-dimensional integrated design information of the first wafer and the second wafer;

[0019] The design files of the first wafer and the second wafer are read through computer-aided design software, such as CAD software, to obtain three-dimensional integrated design information. The three-dimensional integrated design information refers to design data on the geometric shape, size, structure, and bonding of the wafer, including the wafer's geometric model, position coordinates, size parameters, etc.

[0020] Performing overlap detection based on the upper edge and the lower edge of the thickness of the first wafer and the second wafer respectively to obtain edge overlap of the first wafer and edge overlap of the second wafer;

[0021] Images of the first wafer and the second wafer, including the upper and lower edges of the two wafers, are acquired through optical inspection equipment, such as a CMOS collector in an image acquisition module. Edge detection operations are performed on the acquired images using edge detection algorithms, such as Canny edge detection, to identify the edge contours of the wafers. The edge contours of the first wafer and the second wafer are matched, for example, using a shape matching algorithm to calculate the overlap between the edges and obtain a metric value representing the edge coincidence. Based on the edge matching results, the edge coincidence of the first wafer and the edge coincidence of the second wafer are calculated by comparing the matched edge lengths, overlapping areas, etc. The acquisition of this edge coincidence provides a reference for subsequent wafer inspection and processing.

[0022] If the edge overlap of the first wafer and the edge overlap of the second wafer are both greater than a preset edge overlap, obtaining a second detection instruction;

[0023] Based on the edge overlap calculation result, the edge overlap of the first wafer and the edge overlap of the second wafer are compared with a preset edge overlap. If both the edge overlap of the first wafer and the edge overlap of the second wafer are greater than the preset edge overlap, a condition is satisfied. Based on the result that the condition is satisfied, a second inspection instruction is obtained, which is used to control relevant parameters of the wafer inspection equipment for inspecting the three-dimensional wafer body.

[0024] generating a three-dimensional simulation data set using the three-dimensional integrated design information, and controlling a wafer inspection device to inspect a three-dimensional wafer body using the second inspection instruction, and outputting a three-dimensional inspection image set, wherein the three-dimensional wafer body is a wafer obtained by three-dimensional through-hole bonding of the first wafer and the second wafer;

[0025] Based on the acquired design information, a three-dimensional simulation data set is generated by converting the design information into geometric elements such as points, lines, and surfaces in a three-dimensional coordinate system, and then three-dimensional modeling is performed to generate a three-dimensional model representing the first wafer and the second wafer.

[0026] Holes for through-hole bonding are prepared in advance on the joining surfaces of the first wafer and the second wafer. The first wafer and the second wafer are aligned and positioned by optical alignment equipment and mechanical clamping devices. The through holes of the two wafers are aligned and bonded under appropriate pressure and temperature to combine them into a whole, thereby generating the three-dimensional wafer body.

[0027] Using wafer inspection equipment, according to the second inspection instruction, the 3D wafer is inspected. This includes using the image acquisition module to capture top and side views of the wafer, and using the vertical inspection module to check the wafer's verticality. The data obtained from the 3D wafer inspection is integrated to generate a 3D inspection image set as output, demonstrating information such as wafer processing quality and through-hole bonding performance.

[0028] Furthermore, the wafer inspection equipment includes:

[0029] An image acquisition module, comprising a CMOS collector for acquiring images of the bonded three-dimensional wafer body;

[0030] A vertical detection module is connected to the image acquisition module and is used to detect the verticality of the CMOS collector and the measured plane of the three-dimensional wafer. When a preset vertical angle is met, the CMOS collector is triggered to capture top-view and side-view images and output the three-dimensional detection image set.

[0031] The image acquisition module, part of the wafer inspection equipment, includes a CMOS image sensor. This module's primary function is to capture images of the bonded 3D wafer for subsequent analysis and processing. The CMOS image sensor (comprised of a complementary metal oxide semiconductor) is an image sensor composed of numerous photodiodes that convert optical signals into electrical signals. The bonded 3D wafer is placed in the image acquisition module and illuminated by an appropriate light source. The CMOS image sensor scans the 3D wafer, converting the optical signals into electrical signals. The captured image data undergoes analog-to-digital conversion and is then transmitted to the subsequent processing unit for further analysis and processing.

[0032] The vertical detection module and the image acquisition module are connected through communication. The vertical detection module uses sensors to detect the vertical angle of the CMOS collector relative to the measured plane, and sets a preset vertical angle according to specific application requirements and process requirements. When it is detected that the verticality of the CMOS collector and the measured plane meets the preset conditions, that is, when the detected vertical angle is less than or equal to the preset vertical angle, the CMOS collector is triggered to collect overhead images and side images, and obtains overhead images and side images corresponding to the vertical angle. After processing and integration, these images form a three-dimensional detection image set as the output result.

[0033] Furthermore, the wafer inspection device further includes a light compensation control module, the light compensation control module includes an LED light group, and the method includes:

[0034] Collecting the real-time light environment of the image acquisition module to obtain ambient light information;

[0035] Performing illumination uniformity identification according to the ambient light information to obtain illumination uniformity;

[0036] A light compensation control parameter is generated according to the light uniformity, and the light compensation control parameter is input into the light compensation control module, so as to uniformly adjust the ambient light by adjusting the LED light group.

[0037] The light compensation control module is another component of the wafer inspection equipment. It includes an LED light group, which is used to control the brightness and color of the ambient light to achieve uniform lighting. The LED light group is a group of light-emitting diodes. By controlling the brightness and color of each LED, the characteristics of the light it emits can be changed.

[0038] Start the image acquisition module to capture an image of the wafer surface, which contains reflected and scattered light from the ambient light. Preprocess the acquired image, including removing noise and adjusting the image brightness and contrast. Perform light analysis on the preprocessed image, such as calculating the image's average brightness value, color distribution, and light gradient, to obtain ambient light information.

[0039] Based on the ambient light information, illumination uniformity is identified. For example, the image is divided into different regions and the brightness differences of the pixels within each region are calculated. Smaller differences indicate higher illumination uniformity. The distribution of different color channels in the image is analyzed. If the distribution of each channel is relatively uniform, the illumination uniformity is good. Based on the brightness difference calculation results and the distribution of the color channels, the illumination uniformity is obtained to indicate the uniformity of the ambient light.

[0040] Based on the illumination uniformity, light compensation control parameters are generated. For example, based on the illumination uniformity parameters, the LED light group is adjusted in different regions to make the light in each region more uniform; the color of the LED light group is adjusted, for example, by changing the brightness ratio of the red, green, and blue channels to achieve a more uniform illumination effect; based on the illumination uniformity parameters, the overall brightness of the LED light group is adjusted to illuminate the wafer surface more evenly. The generated light compensation control parameters are input into the light compensation control module, and the LED light group is adjusted through the light compensation control module. Based on the generated light compensation control parameters, the brightness, color, or illumination intensity of the LED light group in the local area is adjusted to achieve a more uniform ambient lighting effect. In this way, more consistent lighting conditions can be obtained in each area, thereby improving the accuracy and reliability of wafer detection.

[0041] Performing edge recognition based on the three-dimensional detection image set, and obtaining bonding process overlap using the edge recognition data, wherein the bonding process overlap is a vertical overlap of edges of the first wafer and the second wafer after bonding;

[0042] Furthermore, edge recognition is performed based on the three-dimensional detection image set, and bonding process overlap is obtained using edge recognition data, including:

[0043] Acquiring edge sample data of a top view image and edge sample data of a side view image of the first wafer;

[0044] Acquire the three-dimensional detection image set, wherein the three-dimensional detection image set includes a top view image set and a side view image set;

[0045] Acquire a first processing coincidence by extracting edge data of the overhead image and comparing the extracted edge data with edge sample data of the overhead image;

[0046] Acquire a second processing coincidence by extracting edge data from the side view image and comparing the extracted edge data with edge sample data of the side view image;

[0047] The bonding process overlap is obtained according to the first process overlap and the second process overlap.

[0048] A CMOS imager is used to capture top-view and side-view images of the first wafer, and the top-view and side-view images of the first wafer are output. An edge detection algorithm, such as Canny edge detection, is applied to the top-view image to extract edges and obtain edge information of the first wafer. Representative edge samples, such as key feature points and edge segments, are selected from the edge information. The edge samples represent the shape and position of the edge of the first wafer and constitute an edge sample dataset for the top-view image. The edge sample dataset for the side-view image is obtained in the same manner. The obtained edge sample data is used as a reference standard when evaluating the degree of edge matching in the actual detection image.

[0049] In the above steps, a CMOS collector in a wafer detection device is used to capture top view images and side view images of a three-dimensional wafer body, and output the three-dimensional detection image set, which includes a top view image set and a side view image set.

[0050] Similarly, an edge detection algorithm is used to extract edges from the top-view image to obtain edge data representing the edge position of the three-dimensional wafer body. The edge sample data of the top-view image of the first wafer is used as a reference sample data set. The extracted edge data is compared with the edge sample data. A matching algorithm, such as a correlation matching method, is used to calculate the difference between the edge data and the sample data. Based on the obtained difference, a first processing coincidence is obtained, which reflects the degree of edge matching.

[0051] The edge data extracted from the side view image is compared with the edge sample data, and the relative spacing between each two adjacent edge lines of the two wafer edge lines is identified to obtain the relative spacing uniformity, thereby determining the spacing offset. The spacing offset is used as the second processing overlap, which reflects the vertical overlap of the edges.

[0052] Different weights are assigned to the first processing overlap and the second processing overlap, and then a weighted comprehensive calculation is performed. The selection of weights can be determined according to specific circumstances and needs. For example, weights can be distributed according to edge importance, accuracy requirements, etc. Based on the results of the weighted calculation, a numerical representation of the bonding process overlap is generated. This value can represent the degree of vertical overlap of the edges of the first wafer and the second wafer after bonding, reflecting the accuracy and quality of the bonding process.

[0053] Furthermore, extracting edge data from the overhead image and comparing it with edge sample data of the overhead image to obtain a first processing coincidence includes:

[0054] Performing grayscale conversion on the top view image, and obtaining an edge grayscale pixel coordinate set in the top view image based on wafer edge detection;

[0055] Obtaining a sample edge grayscale pixel coordinate set according to the edge sample data of the overhead image;

[0056] The edge grayscale pixel coordinate set and the sample edge grayscale pixel coordinate set are used to compare the grayscale values of the coordinate points to obtain a coordinate coincidence rate, and the coordinate coincidence rate is output as the first processing coincidence rate.

[0057] The overhead image is converted into a grayscale image by converting the RGB channels of the color image into grayscale values. The grayscale image is processed using edge detection algorithms, such as Canny edge detection and Sobel operator, which can extract areas in the image with drastic grayscale changes and identify them as edges.

[0058] After edge detection, a binary image representing the edge is obtained, where edge portions are marked white and non-edge portions are black. By traversing the image pixels, the coordinates of white pixels (edge pixels) are found and stored in the edge grayscale pixel coordinate set. The edge grayscale pixel coordinate set represents the location of the wafer edge detected in the overhead image.

[0059] The same method is used to perform grayscale conversion on the edge sample data of the overhead image to obtain a sample edge grayscale pixel coordinate set.

[0060] For each coordinate point in the edge grayscale pixel coordinate set, its corresponding grayscale value is obtained. The coordinate point at the same location in the sample edge grayscale pixel coordinate set is found and its corresponding grayscale value is obtained. A grayscale value comparison of the coordinate points is performed, such as a correlation calculation, to obtain the similarity between the two grayscale values. Based on the results of the coordinate point grayscale value comparison, the number of coordinate points with a similarity above a preset threshold is counted. The number of these well-matched coordinate points is compared with the total number of coordinate points to obtain a coordinate coincidence rate, which is expressed as a percentage. The calculated coordinate coincidence rate is used as a metric for the first processing coincidence degree. The first processing coincidence degree can indicate the degree of match and overlap between the edge in the overhead image and the sample edge, reflecting the accuracy and quality of the first processing.

[0061] Furthermore, extracting edge data from the side view image and comparing it with edge sample data of the side view image to obtain a second processing coincidence includes:

[0062] Performing grayscale conversion on the side view image, and obtaining two wafer edge lines of the side view image based on wafer edge detection;

[0063] Identifying the relative spacing between every two adjacent edge lines of the two wafer edge lines to obtain relative spacing uniformity;

[0064] A spacing offset is determined according to the relative spacing uniformity, and the spacing offset is output as the second machining overlap.

[0065] The side view image is converted into grayscale using the same method as above, and the grayscale image is processed using an edge detection algorithm to obtain an edge image, and a curve fitting method is used to extract the edge line to obtain the edge lines of each of the first wafer and the second wafer after bonding.

[0066] For every two adjacent wafer edge lines, the relative spacing between them is calculated using the Euclidean distance between the lines. Based on this calculated relative spacing, the spacing between all adjacent wafer edge lines is calculated and summed. The total spacing is divided by the number of wafer edge lines to obtain the average spacing. For each spacing between adjacent wafer edge lines, the difference between each spacing and the average spacing is calculated by subtracting the average spacing from each spacing, i.e., the uniformity of the relative spacing. A smaller difference indicates a more uniform spacing. This uniformity information is used to determine whether the spacing distribution between wafer edge lines is uniform, thereby determining the shape and processing quality of the wafer.

[0067] The absolute values of the relative spacing uniformity are calculated to obtain their absolute values, which represent the spacing deviation. Larger deviation values indicate uneven spacing, while smaller values indicate more uniform spacing. The calculated spacing deviation is output as a metric for the second processing coincidence. The second processing coincidence reflects the spacing uniformity and processing quality of the wafer edge in the side view image. The spacing deviation can be used to quantitatively evaluate this uniformity difference.

[0068] Bonding offset reminder information is generated according to the bonding processing overlap.

[0069] Based on the numerical value of the bonding processing overlap, a threshold is set according to actual needs. When the bonding processing overlap is greater than or equal to the threshold, it indicates that the bonding meets the preset requirements; when the bonding processing overlap is less than the threshold, it indicates that there is an offset problem in the bonding. In this case, a bonding offset reminder message is generated, such as a warning message, an error prompt or guidance suggestion, to inform the operator of the existence of bonding offset, thereby prompting the operator to take corresponding corrective measures.

[0070] Furthermore, it also includes:

[0071] If the bonding process overlap is greater than or equal to a preset bonding process overlap, determining whether to integrate a third wafer; if the third wafer is integrated, performing bonding offset identification based on the first wafer, the second wafer, and the third wafer;

[0072] If the bonding process overlap is less than the preset bonding process overlap, a bonding offset reminder message is generated.

[0073] The calculated bonding process overlap is compared with the preset bonding process overlap. If it is greater than or equal to the preset bonding process overlap, it means that the bonding process overlap meets the conditions, and further judgment is made on whether the third wafer needs to be integrated. If the third wafer needs to be integrated, the next step of bonding offset identification is entered; otherwise, the processing flow is terminated.

[0074] When it is decided to integrate a third wafer, the edge lines or feature information of the first, second and third wafers are used to identify bonding offsets. The aforementioned image acquisition, image processing and edge detection operations are repeated. By comparing the positional relationship and alignment between the edge lines, the offset during the bonding process is determined and quantitatively evaluated.

[0075] When the bonding process overlap is less than the preset bonding process overlap, it indicates that there is a bonding offset problem. In this case, a bonding offset reminder message is generated, such as a warning message, an error prompt, or a guidance suggestion, to inform the operator of the bonding offset, thereby prompting the operator to take appropriate corrective measures.

[0076] In summary, the wafer processing detection method and system provided by the embodiments of the present application have the following technical effects:

[0077] 1. By performing edge overlap detection based on the thickness of the first and second wafers, the edge overlap can be accurately calculated, which can help determine the quality of the bonding process and provide quantitative metrics;

[0078] 2. Using the 3D integrated design information, a 3D simulation data set is generated. This data set contains the geometric information of the bonded wafer and can be used for subsequent wafer inspection.

[0079] 3. By performing edge recognition on the 3D inspection image set, the degree of overlap of the bonding process can be calculated, which provides a reliable assessment of the bonding quality and can detect bond deviation in a timely manner;

[0080] 4. Generate bond offset reminder information based on the bonding process overlap, which helps operators take timely measures to correct the offset problem and avoid further damage to the quality and reliability of wafer processing.

[0081] In summary, the wafer processing detection method solves the edge projection coincidence detection and bonding offset reminder problems in the existing technology, realizes accurate evaluation and timely correction of bonding processing quality, and thus improves the reliability and efficiency of wafer processing.

[0082] Example 2

[0083] Based on the same inventive concept as the wafer processing detection method in the above embodiment, Figure 2 As shown, the present application provides a wafer processing detection system, the system comprising:

[0084] A design information acquisition unit 10, wherein the design information acquisition unit 10 is used to acquire three-dimensional integrated design information of the first wafer and the second wafer;

[0085] An overlap detection unit 20 is configured to perform overlap detection based on the upper edge and the lower edge of the thickness of the first wafer and the second wafer, respectively, to obtain edge overlap of the first wafer and edge overlap of the second wafer;

[0086] A detection instruction generating unit 30, wherein the detection instruction generating unit 30 is configured to obtain a second detection instruction if both the edge overlap of the first wafer and the edge overlap of the second wafer are greater than a preset edge overlap;

[0087] a detection image acquisition unit 40, the detection image acquisition unit 40 being configured to generate a three-dimensional simulation data set using the three-dimensional integrated design information, and to control a wafer detection device to detect a three-dimensional wafer body using the second detection instruction, and output a three-dimensional detection image set, wherein the three-dimensional wafer body is a wafer obtained by three-dimensional through-hole bonding processing between the first wafer and the second wafer;

[0088] an overlap acquisition unit 50 for performing edge recognition based on the three-dimensional detection image set and acquiring bonding process overlap using edge recognition data, wherein the bonding process overlap is a vertical overlap of edges of the first wafer and the second wafer after bonding;

[0089] The reminder information generating unit 60 is used to generate bonding offset reminder information according to the bonding processing overlap.

[0090] Furthermore, the wafer inspection equipment includes:

[0091] An image acquisition module, comprising a CMOS collector for acquiring images of the bonded three-dimensional wafer body;

[0092] A vertical detection module is connected to the image acquisition module and is used to detect the verticality of the CMOS collector and the measured plane of the three-dimensional wafer. When a preset vertical angle is met, the CMOS collector is triggered to capture top-view and side-view images and output the three-dimensional detection image set.

[0093] Furthermore, the wafer inspection device further includes a light compensation control module, the light compensation control module includes an LED light group, and the inspection image acquisition unit 40 includes the following operating steps:

[0094] Collecting the real-time light environment of the image acquisition module to obtain ambient light information;

[0095] Performing illumination uniformity identification according to the ambient light information to obtain illumination uniformity;

[0096] A light compensation control parameter is generated according to the light uniformity, and the light compensation control parameter is input into the light compensation control module, so as to uniformly adjust the ambient light by adjusting the LED light group.

[0097] Furthermore, the system further includes a processing coincidence acquisition module to perform the following operation steps:

[0098] Acquiring edge sample data of a top view image and edge sample data of a side view image of the first wafer;

[0099] Acquire the three-dimensional detection image set, wherein the three-dimensional detection image set includes a top view image set and a side view image set;

[0100] Acquire a first processing coincidence by extracting edge data of the overhead image and comparing the extracted edge data with edge sample data of the overhead image;

[0101] Acquire a second processing coincidence by extracting edge data from the side view image and comparing the extracted edge data with edge sample data of the side view image;

[0102] The bonding process overlap is obtained according to the first process overlap and the second process overlap.

[0103] Furthermore, the system further includes a first processing coincidence output module to perform the following operation steps:

[0104] Performing grayscale conversion on the top view image, and obtaining an edge grayscale pixel coordinate set in the top view image based on wafer edge detection;

[0105] Obtaining a sample edge grayscale pixel coordinate set according to the edge sample data of the overhead image;

[0106] The edge grayscale pixel coordinate set and the sample edge grayscale pixel coordinate set are used to compare the grayscale values of the coordinate points to obtain a coordinate coincidence rate, and the coordinate coincidence rate is output as the first processing coincidence rate.

[0107] Furthermore, the system further includes a second processing coincidence output module to perform the following operation steps:

[0108] Performing grayscale conversion on the side view image, and obtaining two wafer edge lines of the side view image based on wafer edge detection;

[0109] Identifying the relative spacing between every two adjacent edge lines of the two wafer edge lines to obtain relative spacing uniformity;

[0110] A spacing offset is determined according to the relative spacing uniformity, and the spacing offset is output as the second machining overlap.

[0111] Furthermore, the system further includes an offset reminder information generation module to perform the following operation steps:

[0112] If the bonding process overlap is greater than or equal to a preset bonding process overlap, determining whether to integrate a third wafer; if the third wafer is integrated, performing bonding offset identification based on the first wafer, the second wafer, and the third wafer;

[0113] If the bonding process overlap is less than the preset bonding process overlap, a bonding offset reminder message is generated.

[0114] Through the above detailed description of a wafer processing detection method in this specification, those skilled in the art can clearly understand a wafer processing detection method and system in this embodiment. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0115] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer processing detection method, characterized in that: The method comprises: Acquiring three-dimensional integrated design information of the first wafer and the second wafer; Performing overlap detection based on the upper edge and the lower edge of the thickness of the first wafer and the second wafer respectively to obtain edge overlap of the first wafer and edge overlap of the second wafer; If the edge overlap of the first wafer and the edge overlap of the second wafer are both greater than a preset edge overlap, obtaining a second detection instruction; generating a three-dimensional simulation data set using the three-dimensional integrated design information, and controlling a wafer inspection device to inspect a three-dimensional wafer body using the second inspection instruction, and outputting a three-dimensional inspection image set, wherein the three-dimensional wafer body is a wafer obtained by three-dimensional through-hole bonding of the first wafer and the second wafer; Performing edge recognition based on the three-dimensional detection image set, and obtaining bonding process overlap using the edge recognition data, wherein the bonding process overlap is a vertical overlap of edges of the first wafer and the second wafer after bonding; generating bonding offset reminder information according to the bonding processing overlap; The step of performing edge recognition based on the three-dimensional detection image set and obtaining bonding process overlap using edge recognition data includes: Acquiring edge sample data of a top view image and edge sample data of a side view image of the first wafer; Acquire the three-dimensional detection image set, wherein the three-dimensional detection image set includes a top view image set and a side view image set; Acquire a first processing coincidence by extracting edge data of the overhead image and comparing the extracted edge data with edge sample data of the overhead image; Acquire a second processing coincidence by extracting edge data from the side view image and comparing the extracted edge data with edge sample data of the side view image; Obtaining bonding process overlap according to the first process overlap and the second process overlap; The first processing coincidence degree is obtained by extracting edge data of the overhead image and comparing the edge data with the edge sample data of the overhead image, including: Performing grayscale conversion on the top view image, and obtaining an edge grayscale pixel coordinate set in the top view image based on wafer edge detection; Obtaining a sample edge grayscale pixel coordinate set according to the edge sample data of the overhead image; Comparing the grayscale values of the coordinate points with the edge grayscale pixel coordinate set and the sample edge grayscale pixel coordinate set to obtain a coordinate coincidence rate, and outputting the coordinate coincidence rate as the first processing coincidence rate; The step of extracting edge data from the side view image and comparing the data with sample edge data of the side view image to obtain a second processing coincidence degree includes: Performing grayscale conversion on the side view image, and obtaining two wafer edge lines of the side view image based on wafer edge detection; Identifying the relative spacing between every two adjacent edge lines of the two wafer edge lines to obtain relative spacing uniformity; A spacing offset is determined according to the relative spacing uniformity, and the spacing offset is output as the second machining overlap.

2. The method according to claim 1, wherein The wafer inspection equipment includes: An image acquisition module, comprising a CMOS collector for acquiring images of the bonded three-dimensional wafer body; A vertical detection module is connected to the image acquisition module and is used to detect the verticality of the CMOS collector and the measured plane of the three-dimensional wafer. When a preset vertical angle is met, the CMOS collector is triggered to capture top-view and side-view images and output the three-dimensional detection image set.

3. The method according to claim 2, wherein The wafer inspection device further includes a light compensation control module, the light compensation control module includes an LED light group, and the method includes: Collecting the real-time light environment of the image acquisition module to obtain ambient light information; Performing illumination uniformity identification according to the ambient light information to obtain illumination uniformity; A light compensation control parameter is generated according to the light uniformity, and the light compensation control parameter is input into the light compensation control module, so as to uniformly adjust the ambient light by adjusting the LED light group.

4. The method according to claim 1, wherein The method further comprises: If the bonding process overlap is greater than or equal to a preset bonding process overlap, determining whether to integrate a third wafer; if the third wafer is integrated, performing bonding offset identification based on the first wafer, the second wafer, and the third wafer; If the bonding process overlap is less than the preset bonding process overlap, a bonding offset reminder message is generated.

5. A wafer processing detection system, characterized in that: A wafer processing detection method for implementing any one of claims 1 to 4, comprising: a design information acquisition unit, configured to acquire three-dimensional integrated design information of the first wafer and the second wafer; an overlap detection unit, configured to perform overlap detection based on the upper edge and the lower edge of the thickness of the first wafer and the second wafer, respectively, to obtain edge overlap of the first wafer and edge overlap of the second wafer; a detection instruction generating unit, configured to obtain a second detection instruction if both the edge overlap of the first wafer and the edge overlap of the second wafer are greater than a preset edge overlap; a detection image acquisition unit, the detection image acquisition unit being configured to generate a three-dimensional simulation data set using the three-dimensional integrated design information, and to control a wafer detection device to detect a three-dimensional wafer body using the second detection instruction, and output a three-dimensional detection image set, wherein the three-dimensional wafer body is a wafer obtained by three-dimensional through-hole bonding processing between the first wafer and the second wafer; an overlap acquisition unit, configured to perform edge recognition based on the three-dimensional detection image set and acquire bonding process overlap using edge recognition data, wherein the bonding process overlap is a vertical overlap of edges of the first wafer and the second wafer after bonding; A reminder information generating unit is used to generate bonding offset reminder information according to the bonding processing overlap.

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