Semiconductor packaging structure, substrate, device and manufacturing method

Abstract

A semiconductor packaging structure, substrate, device and manufacturing method, relating to the technical field of semiconductor devices, the semiconductor packaging structure comprising: a redistribution layer and a prefabricated bump; the redistribution layer is formed with a passivation layer on the surface close to the prefabricated bump; the prefabricated bump is formed on the passivation layer, the prefabricated bump has a bump base close to the passivation layer and a bump tip away from the passivation layer; the aspect ratio of the prefabricated bump is 1:1 to 5:1; the metal layer of the redistribution layer is connected to the prefabricated bump; wherein the bump tip is formed by filling a conductive material on a blind hole on a glass substrate, and the blind hole has a preset aspect ratio. By forming a packaging structure with a prefabricated bump under the redistribution layer, support strength can be provided for the redistribution layer, and the bump tip with a preset aspect ratio can be suitable for packaging with different spacing requirements to meet the future needs of high-bandwidth and high-density I / O device packaging interconnection.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor packaging structure, a substrate, a device and a manufacturing method. Background Art

[0002] Through Silicon Via (TSV) adapters are widely used in high-end 2.5D advanced packaging to achieve high-density electrical interconnection between integrated circuit (IC) chips and printed circuit boards (PCBs). However, TSV adapters are expensive. The advanced packaging field requires a low-cost improved technology that can achieve the same effect but without TSV adapters. The 2.5D redistribution layer RDL adapter is a good choice, but because the redistribution layer structure is only composed of polymers and metals, it is thin and soft. After the glass carrier is removed, it loses support and is prone to warping problems, resulting in poor subsequent lithography and ball implantation processes. Prefabricated bumps / solder balls (bumps) on the carrier may be an effective solution. Although prefabricated bumps can also be prepared on silicon substrate carriers, the silicon carrier is difficult to remove and the cost is high.

[0003] In addition, as the I / O density of the chip increases, the demand for narrow-pitch bumps increases significantly. Compared with the common columnar bumps, conical bumps are easier to achieve narrow pitches, and the tip structure is easier to bond to the packaging substrate. However, it is difficult to prefabricate conical bumps on silicon wafers. Although an inverted pyramid-shaped bump can be prepared based on the anisotropic wet etching rate caused by different crystal planes of silicon, the depth-to-width ratio of the bump is completely determined by the crystal structure characteristics of silicon and cannot be changed.

[0004] For the existing RDL-first fan-out packaging technology route (RDL is the redistribution layer), the RDL adapter board is prone to obvious warping after the carrier is removed and loses support. This will seriously affect the subsequent processes, resulting in a decrease in product yield. Summary of the invention

[0005] The main technical problem solved by the present invention is that with the development of packaging technology, the existing packaging structure cannot meet the future demand for high-bandwidth and high-density I / O device packaging interconnection.

[0006] According to a first aspect, an embodiment provides a semiconductor package structure, comprising: a redistribution layer and a prefabricated bump;

[0007] The redistribution layer is formed with a passivation layer on a surface close to the prefabricated bump;

[0008] The prefabricated bump is formed on the passivation layer, and the prefabricated bump has a bump base close to the passivation layer and a bump tip far away from the passivation layer; the depth-to-width ratio of the prefabricated bump is 1:1 to 5:1;

[0009] The metal layer of the redistribution layer is connected to the prefabricated bump;

[0010] The bump tip is formed by filling a conductive material on a blind hole on a glass substrate, and the blind hole has a preset depth-to-width ratio.

[0011] According to a second aspect, an embodiment provides a semiconductor substrate, comprising: a glass substrate and one or more semiconductor package structures;

[0012] One or more semiconductor package structures are formed on a glass substrate in a predetermined regular shape; wherein:

[0013] A semiconductor packaging structure, comprising: a redistribution layer and a prefabricated bump;

[0014] The redistribution layer is formed with a passivation layer on a surface close to the prefabricated bump;

[0015] The prefabricated bump is formed on the passivation layer, and the prefabricated bump has a bump base close to the passivation layer and a bump tip far away from the passivation layer; the aspect ratio of the prefabricated bump is 1:1 to 5:1, and the width of the bump tip is smaller than the width of the bump base;

[0016] The metal layer of the redistribution layer is connected to the prefabricated bump, wherein the metal pad of the redistribution layer penetrates the passivation layer and is connected to the bump base;

[0017] The bump tip is formed by filling a conductive material on a blind hole on a glass substrate, and the blind hole has a preset depth-to-width ratio.

[0018] According to a third aspect, an embodiment provides a semiconductor device, characterized by comprising the semiconductor packaging structure described in the first aspect.

[0019] According to a fourth aspect, an embodiment provides a method for manufacturing a semiconductor package structure, comprising:

[0020] Laser modification is performed on the glass substrate, and blind holes with a preset depth-to-width ratio are formed on the glass substrate by wet etching;

[0021] Filling the blind hole with conductive material to form a bump tip;

[0022] Forming an interlayer dielectric layer covering the tip of the bump, and patterning the interlayer dielectric layer corresponding to the tip of the bump to expose at least a portion of the tip of the bump;

[0023] Filling the first opening with a conductive material to form a bump base;

[0024] Forming a passivation layer covering the bump base, forming at least one metal layer on the passivation layer, the redistribution layer including the passivation layer and the metal layer, and the metal layer is connected to the bump base;

[0025] The semiconductor packaging structure includes a redistribution layer and a prefabricated bump, and the prefabricated bump includes a bump base and a bump tip.

[0026] According to the fifth aspect, an embodiment provides a semiconductor packaging structure, which is manufactured using the manufacturing method described in the fourth aspect.

[0027] According to the semiconductor packaging structure, substrate, device and manufacturing method of the above-mentioned embodiments, by forming a packaging structure with prefabricated bumps under the redistribution layer, support strength can be provided for the redistribution layer. The bump tip has a preset aspect ratio and can be suitable for packaging with different spacing requirements to meet the future needs of high-bandwidth, high-density I / O device packaging interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a semiconductor packaging structure provided by an embodiment of the present application;

[0029] Figure 2 A schematic structural diagram of a semiconductor substrate provided in another embodiment of the present application;

[0030] Figure 3 A flowchart of a manufacturing method provided for one embodiment of the present application;

[0031] Figure 4 A process schematic diagram of a manufacturing method provided in another embodiment of the present application (I);

[0032] Figure 5 A schematic diagram of a manufacturing method according to another embodiment of the present application (II);

[0033] Figure 6 A process schematic diagram of a manufacturing method provided in another embodiment of the present application (III);

[0034] Figure 7 A process schematic diagram of a manufacturing method provided in another embodiment of the present application (IV);

[0035] Figure 8 A process schematic diagram of a manufacturing method provided in another embodiment of the present application (V);

[0036] Fig. 9 A schematic diagram of a manufacturing method according to another embodiment of the present application (VI);

[0037] Fig.10 A process schematic diagram of a manufacturing method provided in another embodiment of the present application (VII);

[0038] Fig.11 A process schematic diagram of a manufacturing method provided in another embodiment of the present application (VIII);

[0039] Fig.12 A process schematic diagram (IX) of a manufacturing method provided in another embodiment of the present application.

[0040] Figure numerals: 1-low adhesion layer; 2-interlayer dielectric layer; 10-prefabricated bump; 11-bump tip; 12-bump base; 20-rewiring layer; 21-passivation layer; 22-metal pad; 23-metal layer; 24-pad; 100-semiconductor packaging structure; 101-blind hole; 200-glass substrate; 201-first opening; 211-second opening. DETAILED DESCRIPTION

[0041] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0042] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0043] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0044] For the existing RDL-first fan-out packaging technology route, the RDL adapter plate is prone to obvious warping after the carrier (or substrate) is removed and loses support. This will seriously affect the subsequent process, resulting in a decrease in product yield. Prefabricated bumps on the carrier may be an effective solution. Although prefabricated bumps can be prepared on silicon carriers, such bumps are either columnar with large spacing or inverted pyramids with non-adjustable aspect ratios. It cannot meet a variety of product requirements. In addition, silicon carriers are difficult to remove and are costly. Compared with common columnar bumps, conical bumps are easier to achieve narrow spacing and are easier to bond to the packaging substrate. However, it is difficult to prefabricate conical bumps on silicon wafers. Therefore, a new technical route is needed to prepare conical prefabricated bumps with adjustable aspect ratios and narrow spacing in other types of carriers, and the carrier is also easy to remove.

[0045] The existing blind hole production on the silicon substrate is not easy to form a narrow-pitch cone-shaped bump, the cost is high, and the silicon substrate is difficult to remove. The depth ratio of the inverted pyramid-shaped bump cannot be adjusted, and the silicon substrate is difficult to remove. The inverted pyramid-shaped bump is caused by etching on the silicon wafer. Due to the lattice structure of silicon, the silicon hole obtained is an inverted pyramid shape, and its aspect ratio is fixed (the aspect ratio range fluctuates within a very small range, so it is approximately considered to be a fixed aspect ratio).

[0046] The above shortcomings of the existing technologies are limited to meet the future semiconductor device demand for high-bandwidth, high-density I / O device packaging interconnection.

[0047] In the present application, a semiconductor packaging structure with a conical bump prefabricated on a glass substrate rather than a silicon substrate is proposed, specifically an RDL adapter board packaging structure, which can not only effectively solve the problem of poor bump planting caused by the warping problem of the RDL adapter board, but also has the advantages of small prefabricated conical bump spacing, highly adjustable aspect ratio, and easy bonding; in addition, the prefabricated bump and RDL are firmly combined and the glass substrate is easy to remove. This packaging structure can improve the I / O density and meet the future needs of high-bandwidth, high-density I / O device packaging and interconnection.

[0048] like Figure 1 As shown, some embodiments of the present application provide a semiconductor package structure 100, which may include: a redistribution layer 20 and a prefabricated bump 10. Figure 1 As shown, the redistribution layer 20 may generally include at least one metal layer 23 and multiple dielectric layers. The outermost dielectric layer may serve as a passivation layer 21, and the middle dielectric layer may serve as an insulating layer. The insulating layer may isolate the metal layer 23 and provide insulation and support.

[0049] The redistribution layer 20 is located near the surface of the prefabricated bump 10 ( Figure 1A passivation layer 21 is formed on the lower surface of the substrate.

[0050] The pre-bump 10 is formed on the passivation layer 21 (eg Figure 1 ), the prefabricated bump 10 has a bump base 12 close to the passivation layer 21 and a bump tip 11 away from the passivation layer 21; the aspect ratio of the prefabricated bump 10 can be 1:1 to 5:1, specifically, the aspect ratio of the bump tip 11 can be 1:1 to 5:1. The bump tip 11 is formed by filling a conductive material on a blind hole 101 of a glass substrate 200, the blind hole 101 has a preset aspect ratio, the redistribution layer 20 is formed on the prefabricated bump 10, and the glass substrate 200 can be modified by laser and wet etching to control the aspect ratio of the blind hole 101.

[0051] The aspect ratio of the prefabricated bump 10 may be 1:1 to 5:1. Taking 5:1 as an example, 5 represents the depth and 1 represents the width. The prefabricated bump 10 provided in the present application may be formed into a bump-type bump, which may be convenient for bonding with a semi-finished semiconductor device.

[0052] The metal layer 23 of the redistribution layer 20 is connected to the prefabricated bump 10; for example, the outermost metal layer can be used as a metal pad 22, a pad 24 or a bump, such as Figure 1 As shown, the top metal layer is used as a pad 24 or a bump, and the bottom metal layer is used as a metal pad 22. In some embodiments, the metal pad 22 of the redistribution layer 20 penetrates the passivation layer 21 and is fixedly connected to the bump base 12.

[0053] The semiconductor packaging structure 100 provided in the embodiment of the present application performs laser modification on a glass substrate 200. The femtosecond laser can modify the microstructure of the glass so that the chemical corrosion characteristics of the glass change, so that a blind hole 101 with an adjustable aspect ratio can be formed on the glass by wet etching, thereby forming a bump tip 11 with an adjustable aspect ratio.

[0054] In addition, the embodiment of the present application forms a bump base 12, and the bump base 12 is fixedly connected to the metal pad 22 of the redistribution layer 20, so as to provide support strength for the redistribution layer 20 and solve the warping problem of the RDL adapter board.

[0055] like Figure 1 As shown, in some embodiments, the first surface ( Figure 1 The area of ​​the upper surface of the metal pad 22 is larger than the second surface of the metal pad 22 near the prefabricated bump 10 ( Figure 1 The area of ​​the lower surface in the.

[0056] The bump base 12 and the metal pad 22 may form a double trapezoidal or convex structure, and the area of ​​the metal pad 22 of the redistribution layer 20 is reduced, so that more metal pads 22 can be added, thereby improving the I / O density.

[0057] For example, Fig.10 As shown, the interlayer dielectric layer 2 and the passivation layer 21 may be patterned by wet etching, and the cross-sections of the first opening 201 and the second opening 211 formed are trapezoidal, so that the bump base 12 and the metal pad 22 can form a double trapezoidal shape. Alternatively, the interlayer dielectric layer 2 and the passivation layer 21 may be patterned by dry etching or laser etching, and the cross-sections of the first opening 201 and the second opening 211 formed are rectangular, so that the bump base 12 and the metal pad 22 can form a convex shape.

[0058] like Fig.10 As shown, the bump base 12 penetrates the interlayer dielectric layer 2 and forms a double-trapezoidal stable structural feature together with the metal pad 22 penetrating the passivation layer 21. One side of it is connected to the cone-shaped bump tip 11, and the other side is connected to the metal pad 22 of the RDL, thus providing not only reliable electrical interconnection for the RDL adapter board, but also stable mechanical support.

[0059] The bump base 12 provides a good electrical connection between the bump tip 11 and the RDL and provides a solid mechanical support for the entire structure.

[0060] like Figure 1 As shown, in some embodiments, the width of the bump tip 11 is smaller than the width of the bump base 12. The conical bump tip 11 can achieve a narrow pitch, and the aspect ratio and height are adjustable, which can be applied to the packaging of a variety of products with different requirements and has a wide range of applications.

[0061] like Figure 1 As shown, in some embodiments, the width of the bump tip 11 at one end close to the bump base 12 is greater than the width of the other end away from the bump base 12. The bump tip 11 can be a conical tip or a flat top, and its depth-to-width ratio is highly adjustable and relatively sharp, so as to facilitate bonding with the connection structure of the bump or pad on the PCB package substrate, the silicon substrate or the micro bump.

[0062] To summarize, the semiconductor packaging structure 100 provided in the embodiment of the present application includes a redistribution layer 20 and a prefabricated bump 10, and the spacing between the prefabricated bump 10 structures can be as small as 0.5um, and the aspect ratio of the bump tip 11 of the prefabricated bump 10 is adjustable (1 to 5 or even higher, such as 1 to 50), which can effectively avoid the adverse effects of the warping problem in the RDL-first fan-out package, and the product yield is high. At the same time, the conical prefabricated bump 10 can achieve a narrow spacing, and the aspect ratio and height are adjustable, which can be applied to the packaging of a variety of products with different requirements, and has a wide range of applications.

[0063] like Figure 2 As shown, another embodiment of the present application further provides a semiconductor substrate, which may include: a glass substrate 200 and at least one semiconductor package structure 100 described in the above embodiment. One or more semiconductor package structures 100 are formed on the glass substrate 200 according to a predetermined shape rule. The predetermined shape rule may be as follows: Figure 2 The square grid arrangement shown can also be set according to specific product requirements.

[0064] In other embodiments, the semiconductor substrate may be a semiconductor wafer or substrate. The shape of the glass substrate 200 may be circular or square, depending on actual product requirements.

[0065] The substrate is removed from the glass substrate 200 and sliced ​​to obtain a chip (ie, the semiconductor packaging structure 100 ), which is then packaged with a semi-finished semiconductor device to form a finished semiconductor device.

[0066] In addition, a semiconductor device is provided in some other embodiments of the present application, which may include the semiconductor packaging structure 100 described in the above embodiment. The semiconductor device may include a semi-finished semiconductor device and the above semiconductor packaging structure 100. The semi-finished semiconductor device may include unpackaged semi-finished devices such as low-voltage high electron mobility transistors or various radio frequency passive devices, or other devices. The semi-finished semiconductor device is connected to the prefabricated bump 10 of the semiconductor packaging structure 100, and then the whole package is formed into a finished semiconductor device.

[0067] like Figure 3 As shown, some other embodiments of the present application further provide a method for manufacturing a semiconductor package structure 100 , wherein the semiconductor package structure 100 may include a redistribution layer 20 and a prefabricated bump 10 , and the prefabricated bump 10 may include a bump base 12 and a bump tip 11 .

[0068] Manufacturing methods may include:

[0069] Step 1: Figure 4As shown, the glass substrate 200 is laser modified, and a blind hole 101 with a preset aspect ratio is formed on the glass substrate 200 by wet etching. The width of the blind hole 101 can also be controlled by photoresist or hard mask. The height (depth) of the blind hole 101 can be controlled by controlling the aspect ratio, and finally the height of the bump tip 11 can be controlled. Before performing femtosecond laser modification, the glass substrate 200 can be cleaned.

[0070] Step 101: Figure 5 As shown, a low adhesion layer 1 covering the blind hole 101 is formed.

[0071] The low adhesion layer 1 can be formed by spin coating, spray coating, immersion, lamination, printing, sputtering, evaporation, etc. The low adhesion layer 1 can reduce the bonding force with materials such as glass by heating, laser dissociation, chemical etching, etc., so that the bump tip 11 can be peeled off from the glass substrate 200.

[0072] Step 2: Figure 6 As shown, a conductive material is filled on the blind hole 101 to form a bump tip 11 .

[0073] For example, the conductive material may be copper, and a Ti / Cu seed layer is firstly sputtered on the blind hole 101, and then copper is electroplated. The conductive material may also be a conductive material commonly used in semiconductor devices, such as gold, silver or aluminum. The embodiment of the present application uses copper as the conductive material and adopts the formation method of electroplating as an example for explanation, and does not limit the specific conductive material and formation method, and may use other conductive materials and other formation methods.

[0074] Step 3: Figure 7 As shown, an interlayer dielectric layer 2 covering the bump tip 11 is formed, and the interlayer dielectric layer 2 is patterned corresponding to the bump tip 11 to obtain a first opening 201 corresponding to the bump tip 11 , through which at least a portion of the bump tip 11 is exposed.

[0075] Step 4: Figure 8 As shown, a conductive material is filled on the first opening 201 to form a bump base 12 on the upper surface of the bump tip 11. For example, a Ti / Cu seed layer is sputtered on the first opening 201, followed by copper electroplating.

[0076] Step 5: Figures 9 and 10 As shown, a passivation layer 21 is formed to cover the bump base 12 , and at least one metal layer 23 is formed on the passivation layer 21 . The redistribution layer 20 may include the passivation layer 21 and the metal layer 23 , and the metal layer 23 is connected to the bump base 12 .

[0077] The above step 5 may include:

[0078] Step 501: Fig. 9As described above, a passivation layer 21 covering the bump base 12 is formed, and the passivation layer 21 is patterned to obtain a second opening 211 corresponding to the bump base 12 , and the second opening 211 at least includes a portion of the bump base 12 .

[0079] The passivation layer 21 may be a polymer or an inorganic material, such as photosensitive polyimide, silicon dioxide, silicon nitride or other flexible materials. The present application may use photosensitive polyimide, which may be patterned by photolithography, and the second opening 211 may be obtained by exposure and development. Of course, patterning may also be performed by laser etching, dry etching or wet etching.

[0080] Step 502 : forming a metal layer 23 on the passivation layer 21 . The metal layer 23 fills the second opening 211 and forms a corresponding metal pad 22 on the top surface of the bump base 12 .

[0081] The metal layer 23 may also be made of copper, and the metal layer 23 is formed by sputtering a seed layer and then electroplating.

[0082] The semiconductor packaging structure 100 is manufactured by prefabricating the bump 10 on a glass carrier and then forming a redistribution layer 20 on the prefabricated bump 10. This can overcome the warping problem of the RDL adapter board. The bump tip 11 with adjustable aspect ratio and size can be suitable for the packaging of a variety of products with different requirements, and has a wide range of applications.

[0083] In some embodiments, the interlayer dielectric layer 2 may be a laser debonding adhesive layer, and the manufacturing method may further include:

[0084] Step 6: Fig.11 and Fig.12 As shown, laser debonding treatment and wet etching are used to remove the laser debonding adhesive layer and the glass substrate 200 to obtain a semiconductor packaging structure 100 .

[0085] For example, the glass substrate 200 and the laser debonding adhesive layer may be removed by various techniques such as grinding, wet etching, laser stripping, thermal expansion, etc. For example, the glass substrate 200 may be removed by wet etching, and the laser debonding adhesive layer may be removed by laser stripping. For another example, the low adhesion layer 1 may also be a laser debonding adhesive layer, and the interlayer dielectric layer 2 and the low adhesion layer 1 may be removed together by laser debonding. Of course, the low adhesion layer 1 may also be formed by photoresist or other dielectric materials, so as to facilitate the separation of the glass substrate 200 from the prefabricated bump 10.

[0086] The embodiment of the present application can conveniently peel the bump tip 11 from the glass substrate 200 by laser debonding and wet etching, and by using the low adhesion layer 1. In order to protect the redistribution layer 20 when the glass substrate 200 is wet-etched, the dielectric layer of the redistribution layer 20 can be an organic dielectric layer instead of the commonly used silicon dioxide.

[0087] The semiconductor package structure 100 provided in the present application can be manufactured by the above-mentioned manufacturing method. If step 6 is not performed and the glass substrate 200 is not removed, the semiconductor substrate (corresponding to the semiconductor substrate 200) provided in the present application can be obtained after step 5. Fig.10 structure shown).

[0088] To summarize, the semiconductor packaging structure 100, substrate, device and manufacturing method provided in the embodiments of the present application can, on the one hand, form a redistribution layer 20 on the prefabricated bump 10. The redistribution layer 20 can overcome the warping problem after removing the carrier by utilizing the supporting effect of the prefabricated bump 10. At the same time, by utilizing the laser modification of the glass substrate 200, the problem of difficulty in peeling the prefabricated bump 10 from the silicon substrate can be solved. The aspect ratio and height of the bump tip 11 can also be adjusted, which can adapt to the packaging of products with different size requirements.

[0089] At the same time, by utilizing the laser debonding technology, it is possible to facilitate the stripping of the prefabricated bump 10 from the stripping substrate.

[0090] By controlling the size of the metal pad 22 and the bump base 12 , the I / O density can be increased to meet the future demand for high-bandwidth, high-density I / O device packaging interconnection.

[0091] This document is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, various operating steps and components for performing the operating steps may be implemented in different ways (e.g., one or more steps may be deleted, modified, or incorporated into other steps) depending on the specific application or considering any number of cost functions associated with the operation of the system.

[0092] Although the principles of this invention have been shown in various embodiments, many modifications of structures, arrangements, proportions, elements, materials and components particularly suitable for specific environments and operational requirements can be used without departing from the principles and scope of this invention. The above modifications and other changes or amendments will be included in the scope of this invention.

[0093] The foregoing specific description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Therefore, the consideration of the present disclosure will be illustrative rather than restrictive, and all these modifications will be included in its scope. Similarly, the advantages, other advantages and solutions to the problems of various embodiments have been described above. However, the benefits, advantages, solutions to the problems and any elements that can produce these, or make them more clear, should not be interpreted as critical, necessary or necessary. The term "include" and any other variants used in this article are all non-exclusive inclusions, so that the process, method, article or device including the list of elements not only includes these elements, but also includes other elements that are not explicitly listed or do not belong to the process, method, system, article or device. In addition, the term "coupled" and any other variants used in this article refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections and / or any other connections.

[0094] Those skilled in the art will appreciate that many changes may be made to the details of the above-described embodiments without departing from the basic principles of the invention. Therefore, the scope of the present invention should be determined solely by the claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A redistribution layer (20) and a prefabricated bump (10); The redistribution layer (20) is provided with a passivation layer (21) on a surface close to the prefabricated bump (10); The prefabricated bump (10) is formed on the passivation layer (21), and the prefabricated bump (10) has a bump base (12) close to the passivation layer (21) and a bump tip (11) far from the passivation layer (21); the aspect ratio of the prefabricated bump (10) is 1:1-5:1; the width of the bump tip (11) is smaller than the width of the bump base (12); The metal layer (23) of the redistribution layer (20) is connected to the prefabricated bump (10); wherein the metal pad (22) of the redistribution layer (20) penetrates the passivation layer (21) and is fixedly connected to the bump base (12); The bump tip (11) is formed by filling a conductive material on a blind hole (101) on a glass substrate (200), and the blind hole (101) has a preset aspect ratio.

2. The semiconductor package structure according to claim 1, wherein: The area of ​​a first surface of the bump base (12) close to the metal pad (22) is greater than the area of ​​a second surface of the metal pad (22) close to the prefabricated bump (10).

3. The semiconductor package structure according to claim 1, wherein: The width of the bump tip (11) at one end close to the bump base (12) is greater than the width of the other end away from the bump base (12).

4. A semiconductor substrate, characterized in that: include: A glass substrate (200) and one or more semiconductor package structures (100); The one or more semiconductor package structures (100) are formed on the glass substrate (200) in a regular manner according to a predetermined shape; wherein: The semiconductor packaging structure (100) comprises: a redistribution layer (20) and a prefabricated bump (10); The redistribution layer (20) is provided with a passivation layer (21) on a surface close to the prefabricated bump (10); The prefabricated bump (10) is formed on the passivation layer (21), and the prefabricated bump (10) has a bump base (12) close to the passivation layer (21) and a bump tip (11) far from the passivation layer (21); the aspect ratio of the prefabricated bump (10) is 1:1-5:1, and the width of the bump tip (11) is smaller than the width of the bump base (12); The metal layer (23) of the redistribution layer (20) is connected to the prefabricated bump (10), wherein the metal pad (22) of the redistribution layer (20) penetrates the passivation layer (21) and is connected to the bump base (12); The bump tip (11) is formed by filling a conductive material on a blind hole (101) on a glass substrate (200), and the blind hole (101) has a preset aspect ratio.

5. A semiconductor device, characterized in that: A semiconductor packaging structure (100) comprising any one of claims 1 to 3.

6. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Laser modification is performed on a glass substrate (200), and wet etching is used to form a blind hole (101) with a preset depth-to-width ratio on the glass substrate (200); Filling the blind hole (101) with a conductive material to form a bump tip (11); forming an interlayer dielectric layer (2) covering the bump tip (11), and patterning the interlayer dielectric layer (2) corresponding to the bump tip (11) to obtain a first opening (201) corresponding to the bump tip (11), and exposing at least a portion of the bump tip (11) through the first opening (201); Filling the first opening (201) with a conductive material to form a bump base (12); forming a passivation layer (21) covering the bump base (12), forming at least one metal layer (23) on the passivation layer (21), the redistribution layer (20) comprising the passivation layer (21) and the metal layer (23), and the metal layer (23) being connected to the bump base (12); The semiconductor packaging structure (100) comprises the redistribution layer (20) and a prefabricated bump (10), and the prefabricated bump (10) comprises the bump base (12) and the bump tip (11).

7. The manufacturing method according to claim 6, characterized in that: The interlayer dielectric layer (2) is a laser debonding adhesive layer, and the manufacturing method further comprises: Using laser debonding processing and wet etching to remove the laser debonding adhesive layer and the glass substrate (200) to obtain a semiconductor packaging structure (100); and / or, Before filling the blind hole (101) with a conductive material, the manufacturing method further comprises: A low adhesion layer (1) is formed to cover the blind hole (101).

8. A semiconductor packaging structure, characterized in that: The invention is manufactured by the manufacturing method according to claim 6 or 7.

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