Stacked capacitor structure and forming method thereof

Abstract

The present invention provides a stacked capacitor structure and a method for forming the same, which belongs to the technical field of semiconductor device manufacturing. The stacked capacitor structure includes a substrate, a bottom electrode layer, a first insulating layer, an intermediate electrode layer, a second insulating layer and a top electrode layer, wherein the bottom electrode layer is arranged on the substrate; the first insulating layer is arranged on the bottom electrode layer; the intermediate electrode layer is arranged on the first insulating layer; the second insulating layer is arranged on the intermediate electrode layer; and the top electrode layer is arranged on the second insulating layer. The stacked capacitor structure of the present invention can form a capacitor structure by cooperating with any two of the bottom electrode layer, the intermediate electrode layer and the top electrode layer with the insulating layer in the middle, thereby effectively ensuring the working reliability of the stacked capacitor while increasing the capacitance density.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a stacked capacitor structure and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, integrated circuits have increased the density of semiconductor components in a given area by reducing the size of semiconductor components. Although this has effectively improved the operating speed of the entire integrated circuit, it has also made the noise interference between components in the integrated circuit increasingly serious.

[0003] Therefore, metal-insulator-metal capacitors (MIM) are introduced into integrated circuits as filters to filter and shield external noise interference to meet the design requirements of integrated circuits. With the advancement of technology nodes, the requirements for the capacitance density and structural reliability of MIM capacitors in the same layer are also increasing.

[0004] Therefore, it is necessary to design a stacked capacitor structure and a method for forming the same, which can take into account both the capacitance density and the working reliability of the capacitor to solve the above problems. Summary of the invention

[0005] In view of the above shortcomings of the prior art, the present invention provides a stacked capacitor structure and a method for forming the same, so as to improve the technical problem that it is difficult to balance the capacitance density and structural reliability of the MIM capacitor in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a stacked capacitor structure, which includes a substrate, a bottom electrode layer, a first insulating layer, a middle electrode layer, a second insulating layer and a top electrode layer.

[0007] In which, a bottom electrode layer is arranged on the substrate; a first insulating layer is arranged on the bottom electrode layer; an intermediate electrode layer is arranged on the first insulating layer; a second insulating layer is arranged on the intermediate electrode layer; and a top electrode layer is arranged on the second insulating layer; along a direction perpendicular to the surface of the substrate, a projection of the first insulating layer on the substrate is covered by a projection of the bottom electrode layer on the substrate, a projection of the intermediate electrode layer on the substrate is located within a projection of the first insulating layer on the substrate, a projection of the second insulating layer on the substrate is covered by a projection of the intermediate electrode layer on the substrate, and a projection of the top electrode layer on the substrate is located within a projection of the second insulating layer on the substrate.

[0008] The present invention also provides a method for forming a stacked capacitor structure, the method comprising:

[0009] providing a substrate;

[0010] forming a first conductive material layer and a first insulating material layer in sequence on the substrate;

[0011] Wet-etching a portion of the first insulating material layer and the first conductive material layer to form a bottom electrode layer and a first insulating layer on the substrate;

[0012] forming a second conductive material layer and a second insulating material layer on the substrate and the first insulating layer in sequence;

[0013] Wet-etching a portion of the second insulating material layer and the second conductive material layer to form an intermediate electrode layer and a second insulating layer on the first insulating layer;

[0014] forming a third conductive material layer on the substrate, the first insulating layer and the second insulating layer;

[0015] A portion of the third conductive material layer is wet-etched so that the remaining third conductive material layer forms a top electrode layer on the second insulating layer.

[0016] In summary, the stacked capacitor structure is provided with a bottom electrode layer, a first insulating layer, an intermediate electrode layer, a second insulating layer and a top electrode layer in sequence on the substrate. The stacked capacitor structure can form a capacitor structure by cooperating with any two of the bottom electrode layer, the intermediate electrode layer and the top electrode layer to support the insulating layer in the middle. This allows the stacked capacitor structure to rely on the cooperation of other electrode layers and insulating layer structures to maintain the capacitor function even when any electrode layer, insulating layer or conductive structure on the electrode layer is damaged, thereby effectively ensuring the working reliability of the stacked capacitor while increasing the capacitance density. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0018] Figure 1 Schematic diagram of a process for forming a stacked capacitor structure according to an embodiment of the present invention;

[0019] Figures 2 to 4 It is a schematic diagram of sequentially forming a first conductive material layer and a first insulating material layer on a substrate in one embodiment of the present invention;

[0020] Figure 5 This is a flow chart of step S3 in one embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of forming a first mask layer on an insulating material layer in one embodiment of the present invention;

[0022] Figure 7 It is a schematic diagram of wet etching a portion of the first insulating material layer and the first conductive material layer to form a bottom electrode layer and a first insulating layer in one embodiment of the present invention;

[0023] Figure 8 It is a schematic diagram of forming a second conductive material layer on a substrate and a first insulating layer in one embodiment of the present invention;

[0024] Fig. 9 It is a schematic diagram of forming a second insulating material layer on the second conductive material layer in one embodiment of the present invention;

[0025] Fig.10 This is a flow chart of step S5 in one embodiment of the present invention;

[0026] Fig.11 It is a schematic diagram of forming a second mask layer on a second insulating material layer in one embodiment of the present invention;

[0027] Fig.12 It is a schematic diagram of wet etching to remove a portion of the second insulating material layer and the second conductive material layer to form an intermediate electrode layer and a second insulating layer in one embodiment of the present invention;

[0028] Fig.13 It is a schematic diagram of forming a third conductive material layer on a substrate, a first insulating layer and a second insulating layer in one embodiment of the present invention;

[0029] Fig.14 It is a schematic diagram of forming a silicon oxide material layer on the third conductive material layer in one embodiment of the present invention;

[0030] Fig.15 This is a flow chart of step S7 in one embodiment of the present invention;

[0031] Fig.16 is a schematic diagram of forming a third mask layer on the third conductive material layer in one embodiment of the present invention;

[0032] Fig.17 It is a schematic diagram of removing a portion of the third conductive material layer by wet etching to form a top electrode layer in one embodiment of the present invention;

[0033] Fig.18 A schematic diagram of forming a covering layer on the surfaces of a substrate, a bottom electrode layer, a first insulating layer, an intermediate electrode layer, a second insulating layer and a top electrode layer in one embodiment of the present invention;

[0034] Fig.19A schematic diagram of forming a covering layer on the surfaces of the first insulating layer, the middle electrode layer, the second insulating layer and the top electrode layer in one embodiment of the present invention;

[0035] Figure 20 to Figure 21 It is a schematic diagram of forming a first conductive structure, a second conductive structure and a third conductive structure above a stacked capacitor structure in one embodiment of the present invention;

[0036] Fig. 22 It is a schematic diagram of cascading a stacked capacitor structure between a first conductive layer and a second conductive layer in one embodiment of the present invention;

[0037] Fig.23 A schematic diagram of a structure for etching an insulating layer and an electrode layer in a conventional process;

[0038] Fig.24 Another schematic diagram of a structure for etching an insulating layer and an electrode layer using an existing process;

[0039] Fig.25 This is a scanning electron microscope image of the side wall at the junction of each electrode layer and the insulating layer during the wet etching process of the present invention.

[0040] Component number description

[0041] 100, substrate; 110, first conductive layer; 200, first conductive material layer; 210, bottom electrode layer; 300, first insulating material layer; 310, first mask layer; 320, first insulating layer; 400, second conductive material layer; 410, middle electrode layer; 500, second insulating material layer; 510, second mask layer; 520, second insulating layer; 600, third conductive material layer; 610, third mask layer; 620, top Electrode layer; 700, silicon oxide material layer; 710, silicon oxide layer; 800, covering layer; 810, silicon material layer; 820, silicon nitride material layer; 900, interlayer dielectric layer; 910, first through hole; 911, first conductive structure; 920, second through hole; 921, second conductive structure; 930, third through hole; 931, third conductive structure; 940, fourth through hole; 941, fourth conductive structure; 950, second conductive layer. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0045] See also Figures 17 to 22 On the one hand, the present invention provides a stacked capacitor structure, which sequentially arranges a bottom electrode layer 210, a first insulating layer 320, an intermediate electrode layer 410, a second insulating layer 520 and a top electrode layer 620 on a substrate 100, and gradually reduces the size of the upper electrode layer, so that an area not covered by the upper electrode layer is left on the bottom electrode layer 210 and the intermediate electrode layer 410, so as to set the conductive structure of the bottom electrode layer 210 and the intermediate electrode layer 410 connected to the upper layer. In the integrated circuit, the stacked capacitor structure can use any two film layers of the bottom electrode layer 210, the intermediate electrode layer 410 and the top electrode layer 620 to cooperate with the insulating layer in the middle to form a capacitor structure. This allows the stacked capacitor structure to rely on the cooperation of other electrode layers and insulating layer structures to maintain the capacitor function even when any electrode layer, insulating layer or conductive structure on the electrode layer is damaged, thereby increasing the capacitance density while ensuring the working reliability of the stacked capacitor.

[0046] like Fig.17 As shown, the stacked capacitor structure includes a substrate 100 , a bottom electrode layer 210 , a first insulating layer 320 , an intermediate electrode layer 410 , a second insulating layer 520 and a top electrode layer 620 .

[0047] like Fig.17As shown, the substrate 100 can be any material that meets the requirements of the integrated circuit substrate. As an example, the substrate 100 can include any one or more combinations of semiconductor materials and insulating materials. When the substrate 100 is made of semiconductor materials, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III / V compound semiconductors can be selected. In addition to the semiconductor materials listed above, the substrate 100 can also be Si / SiGe, Si / SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI), etc. When the substrate 100 is made of insulating material, the insulating material can be an organic insulator, an inorganic insulator or a combination thereof. This application is described in detail by taking the substrate 100 as an insulating substrate as an example, for example, the material of the substrate 100 is SiO2.

[0048] like Fig.17 , Fig.21 and Fig. 22 As shown, the bottom electrode layer 210 is arranged on the substrate 100, the first insulating layer 320 is arranged on the bottom electrode layer 210, the middle electrode layer 410 is arranged on the first insulating layer 320, the second insulating layer 520 is arranged on the middle electrode layer 410, and the top electrode layer 620 is arranged on the second insulating layer 520. In the direction perpendicular to the surface of the substrate 100, the projection of the first insulating layer 320 on the substrate 100 is covered by the projection of the bottom electrode layer 210 on the substrate 100, that is, the projection of the first insulating layer 320 on the substrate 100 completely overlaps with the projection of the bottom electrode layer 210 on the substrate 100, or is located within the projection of the bottom electrode layer 210 on the substrate 100; the projection of the middle electrode layer 410 on the substrate 100 is located within the projection of the first insulating layer 320 on the substrate 100, which leaves an area above the bottom electrode layer 210 that is not covered by the middle electrode layer 410, so as to set the bottom electrode layer 210 to connect to the upper layer conductive structure; the projection of the second insulating layer 520 on the substrate 100 is covered by the projection of the intermediate electrode layer 410 on the substrate 100, that is, the projection of the second insulating layer 520 on the substrate 100 completely overlaps with the projection of the intermediate electrode layer 410 on the substrate 100, or is located within the projection of the intermediate electrode layer 410 on the substrate 100; the projection of the top electrode layer 620 on the substrate 100 is located within the projection of the second insulating layer 520 on the substrate 100, which leaves an area above the intermediate electrode layer 410 that is not covered by the top electrode layer 620 for setting a conductive structure in which the intermediate electrode layer 410 is connected to the upper layer.

[0049] like Fig.17As shown, in all directions parallel to the surface of the substrate 100, the outer diameter of the edge of the second insulating layer 520 is less than or equal to the outer diameter of the edge of the intermediate electrode layer 410, and the height of the outer edge of the intermediate electrode layer 410 is less than or equal to the height of the outer edge of the second insulating layer 520, and the outer edges of the second insulating layer 520 and the intermediate electrode layer 410 are smooth and continuous at the junction and present a slope shape with the outer diameter increasing downward; the outer diameter of the edge of the first insulating layer 320 is less than or equal to the outer diameter of the edge of the bottom electrode layer 210, and the height of the outer edge of the bottom electrode layer 210 is less than or equal to the height of the outer edge of the first insulating layer 320, and the outer edges of the first insulating layer 320 and the intermediate electrode layer 410 are smooth and continuous at the junction and present a slope shape with the outer diameter increasing downward. Since the outer edge of the intermediate electrode layer 410 will not spread to the outside of the outer edge of the second insulating layer 520, and the outer edge of the bottom electrode layer 210 will not spread to the outside of the outer edge of the first insulating layer 320, the sidewalls of the stacked capacitor structure will not introduce redeposition defects caused by insufficient etching or recess defects caused by excessive etching.

[0050] Among them, the bottom electrode layer 210, the middle electrode layer 410 and the top electrode layer 620 are made of conductive materials, for example, metals, alloys, metal silicides, metal nitrides or combinations thereof. The metal can be selected from one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti). The alloy can be selected from any two or more of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti). The metal silicide can be selected from one or more of titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi). The metal nitride can be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TiN), and zirconium nitride (ZrN). Optionally, in some embodiments, the bottom electrode layer 210 , the middle electrode layer 410 , and the top electrode layer 620 are made of metal nitrides. For example, in one example, the bottom electrode layer 210 , the middle electrode layer 410 , and the top electrode layer 620 are made of TiN.

[0051] The first insulating layer 320 and the second insulating layer 520 are made of insulating materials with high dielectric constants. In one example, the first insulating layer 320 and the second insulating layer 520 can be made of silicon nitride (SiN), silicon oxynitride (SiO x N y ) one or more of the following.

[0052] like Fig.18 and Fig.19As shown, in some embodiments, the stacked capacitor structure further includes a covering layer 800, which covers at least the exposed surfaces of the first insulating layer 320, the middle electrode layer 410, the second insulating layer 520 and the top electrode layer 620. The covering layer 800 can achieve better electrical isolation and thermal stability between different stacked capacitor structures, thereby improving the reliability of the capacitor. Fig.18 As shown, in one example, the cover layer 800 covers the exposed surfaces of the substrate 100, the bottom electrode layer 210, the first insulating layer 320, the middle electrode layer 410, the second insulating layer 520 and the top electrode layer 620 to further improve the electrical isolation and thermal stability between different stacked capacitor structures. Fig.19 As shown, in another example, the covering layer 800 only covers the exposed surfaces of the first insulating layer 320, the middle electrode layer 410, the second insulating layer 520 and the top electrode layer 620 but does not cover the bottom electrode layer 210 and the surface of the substrate 100, so as to facilitate the process technology to form through holes and conductive structures in the substrate 100 and the film layer above the substrate 100.

[0053] The cover layer 800 may be made of an insulating material or a combination of a semiconductor material and an insulating material, and the insulating material may be silicon oxide (SiO2), silicon nitride (SiN), hydrogen silsesquioxane polymer (HSQ), methane silsesquioxane polymer (MSQ), methyl silicate compound or carbon-doped oxide. Optionally, in one example, the cover layer 800 includes a silicon material layer 810 and a silicon nitride material layer 820, wherein the silicon material layer 810 at least covers the exposed surfaces of the first insulating layer 320, the intermediate electrode layer 410, the second insulating layer 520 and the top electrode layer 620, and the silicon nitride material layer 820 is located on the silicon material layer 810.

[0054] like Fig.18 and Fig.19 As shown, in some embodiments, a silicon oxide layer 710 is disposed on the top electrode layer 620, and the silicon oxide layer 710 is located between the top electrode layer 620 and the covering layer 800. The silicon oxide layer 710 located on the top electrode layer 620 can serve as a protective layer for the top electrode layer 620 to prevent the precursor material of the deposition process of the covering layer 800 from reacting with the top electrode layer 620.

[0055] like Fig.21As shown, in some embodiments, a first conductive structure 911 is disposed on the bottom electrode layer 210, a second conductive structure 921 is disposed on the middle electrode layer 410, and a third conductive structure 931 is disposed on the top electrode layer 620, and the first conductive structure 911, the second conductive structure 921 and the third conductive structure 931 are insulated and isolated from each other. Specifically, an interlayer dielectric layer 900 is disposed above the stacked capacitor structure, and the interlayer dielectric layer 900 is located above the substrate 100, the first insulating layer 320, the second insulating layer 520 and the top electrode layer 620. The interlayer dielectric layer 900 is provided with a first through hole 910, a second through hole 920 and a third through hole 930. The first through hole 910 is located above the bottom electrode layer 210. The first through hole 910 penetrates the interlayer dielectric layer 900, the cover layer 800 and the first insulating layer 320 to expose a portion of the surface of the bottom electrode layer 210. The first through hole 910 is filled with a first conductive structure 911. The first conductive structure 911 is in conductive contact with the bottom electrode layer 210 at the bottom. The second through hole 920 is located above the middle electrode layer 410. The second through hole 920 penetrates the interlayer dielectric layer 900. , the cover layer 800 and the second insulating layer 520 to expose part of the surface of the middle electrode layer 410, the second through hole 920 is filled with a second conductive structure 921, and the second conductive structure 921 is in conductive contact with the middle electrode layer 410 at the bottom; the third through hole 930 is located above the top electrode layer 620, and the third through hole 930 penetrates the interlayer dielectric layer 900 and the cover layer 800 to expose part of the surface of the top electrode layer 620, and the third conductive structure 931 is filled and formed in the third through hole 930, and the bottom of the third conductive structure 931 is conductively connected to the top electrode layer 620. The first conductive structure 911, the second conductive structure 921 and the third conductive structure 931 are insulated and isolated by the interlayer dielectric layer 900. Under the above capacitor structure, even if any one of the conductive structures or the electrode layer connected to the conductive structure is damaged, the stacked capacitor can still be connected to the external circuit through the other two conductive structures, thereby maintaining normal capacitor function.

[0056] The interlayer dielectric layer 900 may be made of insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), hydrogen silsesquioxane polymer (HSQ), methane silsesquioxane polymer (MSQ), methyl silicate compounds, and carbon-doped oxides.

[0057] like Fig. 22As shown, the stacked capacitor structure is connected between the conductive interconnect structures of different film layers to shield the interference of electrical noise signals, thereby playing the role of a filter. In some embodiments, a first conductive layer 110 is disposed in the substrate 100, an interlayer dielectric layer 900 is disposed above the stacked capacitor structure, and a second conductive layer 950 is disposed on the interlayer dielectric layer 900. The interlayer dielectric layer 900 is provided with a first through hole 910, a second through hole 920, a third through hole 930 and a fourth through hole 940. The first through hole 910 is located above the bottom electrode layer 210, and the first through hole 910 penetrates the interlayer dielectric layer 900, the cover layer 800 and the first insulating layer 320 to expose a portion of the surface of the bottom electrode layer 210. The first through hole 910 is filled with a first conductive structure 911, and the first conductive structure 911 is in conductive contact with the bottom electrode layer 210 at the bottom. The second through hole 920 is located above the middle electrode layer 410, and the second through hole 920 penetrates the interlayer dielectric layer 900, the cover layer 800 and the second insulating layer 520 to expose a portion of the surface of the middle electrode layer 410. The second through hole 920 is filled with a first conductive structure 911, and the first conductive structure 911 is in conductive contact with the bottom electrode layer 210 at the bottom. The second conductive structure 921 is filled, and the second conductive structure 921 is conductively contacted with the intermediate electrode layer 410 at the bottom; the third through hole 930 is located above the top electrode layer 620, and the third through hole 930 passes through the interlayer dielectric layer 900 and the covering layer 800 to expose a portion of the surface of the top electrode layer 620, and the third conductive structure 931 is filled and formed in the third through hole 930, and the bottom of the third conductive structure 931 is conductively connected to the top electrode layer 620; the fourth through hole 940 passes through the interlayer dielectric layer 900 and extends into the substrate 100 to expose a portion of the surface of the first conductive layer 110, and the fourth through hole 940 is filled with the fourth conductive structure 941, and the bottom of the fourth conductive structure 941 is conductively connected to the first conductive layer 110.

[0058] In addition, the inventors have found that when the prior art forms a stacked capacitor structure on the substrate 100 through a dry etching process, the etching rate of the dry etching process is difficult to accurately control when etching a small-sized structure, and it is easy to introduce structural defects on the sidewalls of the stacked capacitor, resulting in poor capacitance and reliability performance of the stacked capacitor structure. Fig.23 As shown, when dry etching etches the conductive material film layer covering the substrate 100 and the insulating layer to form the upper electrode layer, redeposition may occur on the sidewall of the capacitor due to insufficient etching. The above defects may change the thickness of the insulating layer covering the bottom electrode layer and the top electrode layer in the capacitor, causing the capacitance of the capacitor to decrease or introducing additional parasitic capacitance, thereby affecting the capacitance and reliability performance of the formed capacitor. Fig.24As shown, when dry etching is used to form capacitor structures of different area sizes on the substrate 100, a pattern load effect will be introduced on the formed capacitor due to the non-uniformity of the dry etching rate when etching different areas or different pattern densities (for example, the etching rate is low when etching a large area film layer, and the etching rate is high when etching a small area film layer), thereby affecting the capacity and reliability performance of the formed capacitor.

[0059] To improve the above problems, the present invention provides a method for forming a stacked capacitor in another aspect, wherein the method uses wet etching to sequentially form a bottom electrode layer 210 and a first insulating layer 320, an intermediate electrode layer 410 and a second insulating layer 520, and a top electrode layer 620 with gradually decreasing areas on a substrate 100. The above method utilizes the consistency of the wet etching rate in the height direction, and through mask matching and etching time control, can effectively avoid introducing structural defects on the outer edges of each film layer of the stacked capacitor, thereby ensuring the consistency of the outer diameters of the bottom electrode layer 210 and the first insulating layer 320 and the intermediate electrode layer 410 and the second insulating layer 520, thereby ensuring that the junction of the bottom electrode layer 210 and the first insulating layer 320 and the junction of the intermediate electrode layer 410 and the second insulating layer 520 will not introduce defects of insufficient etching or excessive etching; and when multiple stacked capacitor structures are formed at the same time, the pattern load effect will not be introduced on the stacked capacitor formed due to the different etching areas in different regions, thereby effectively ensuring the capacity and structural reliability of the stacked capacitor.

[0060] For details, please see Figures 1 to 22 , Figures 1 to 22 Schematic diagram of the process and structure corresponding to each step of the method for forming a stacked capacitor structure in some embodiments.

[0061] See also Figure 1 The method for forming the stacked capacitor structure comprises the following steps:

[0062] S1. Provide a substrate 100; (see Figure 2 )

[0063] S2, sequentially forming a first conductive material layer 200 and a first insulating material layer 300 on the substrate 100; (see Figure 3 to Figure 4 )

[0064] S3, wet-etching a portion of the first insulating material layer 300 and the first conductive material layer 200 to form a bottom electrode layer 210 and a first insulating layer 320 on the substrate 100; (see Figure 7 )

[0065] S4, sequentially forming a second conductive material layer 400 and a second insulating material layer 500 on the substrate 100 and the first insulating layer 320; (see Figures 8 to 9)

[0066] S5, wet-etching a portion of the second insulating material layer 500 and the second conductive material layer 400 to form an intermediate electrode layer 410 and a second insulating layer 520 on the first insulating layer 320; (see 12)

[0067] S6, forming a third conductive material layer 600 on the substrate 100, the first insulating layer 320 and the second insulating layer 520; (see Fig.13 )

[0068] S7, wet-etching a portion of the third conductive material layer 600, so that the remaining third conductive material layer 600 forms a top electrode layer 620 on the second insulating layer 520. (See Fig.17 )

[0069] Combine the following Figures 2 to 22 The steps of the method for preparing the conductive connection structure in the embodiment of the present invention are described in detail.

[0070] like Figure 2 As shown, in some embodiments, in step S1, the provided substrate 100 can be any material that meets the requirements of the integrated circuit substrate. As an example, the substrate 100 can include any one or more combinations of semiconductor materials and insulating materials. When the substrate 100 is made of semiconductor materials, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III / V compound semiconductors can be selected. In addition to the semiconductor materials listed above, the substrate 100 can also be Si / SiGe, Si / SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI), etc. When the substrate 100 is made of insulating material, the insulating material can be an organic insulator, an inorganic insulator or a combination thereof. This application is described in detail by taking the substrate 100 as an insulating substrate as an example.

[0071] like Figure 3As shown, in some embodiments, in step S2, a first conductive material layer 200 is first formed on the surface of the substrate 100 so that the first conductive material covers the surface of the substrate 100; specifically, the first conductive material layer 200 can be formed on the substrate 100 by conventional deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or conventional sputtering processes.

[0072] Among them, the material of the first conductive material layer 200 can be selected from metal, alloy, metal silicide, metal nitride or a combination thereof, the metal can be selected from one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the alloy can be selected from any two or more combinations of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the metal silicide can be selected from one or more of titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi), and the metal nitride can be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TiN), and zirconium nitride (ZrN). Optionally, in some embodiments, the material of the first conductive material layer 200 is selected from metal nitride, for example, in one example, the material of the first conductive material layer 200 is selected from TiN.

[0073] like Figure 4 As shown, in some embodiments, after forming the first conductive material layer 200 on the substrate 100 in step S2, the first insulating material layer 300 is further formed on the first conductive material layer 200, so that the first insulating material layer 300 covers the surface of the first conductive material layer 200. Specifically, the first insulating material layer 300 can be formed on the first conductive material layer 200 by a CVD process. The material of the first insulating material layer 300 is an insulating material with a high dielectric constant. In one example, the first insulating material layer 300 is made of silicon nitride (SiN), silicon oxynitride (SiO x N y ) one or more of the following.

[0074] like Figures 5 to 7As shown, in step S3, a portion of the first insulating material layer 300 and the first conductive material layer 200 on the substrate 100 is removed by a wet etching process to form a bottom electrode layer 210 and a first insulating layer 320 on the substrate 100. The bottom electrode layer 210 is formed on the surface of the substrate 100, and the first insulating layer 320 is formed on the surface of the bottom electrode layer 210. Since the wet etching rate is consistent in the height direction, the wet etching rate of removing the first insulating material layer 300 and the first conductive material layer 200 in different regions along the height direction can be kept consistent, so that the outer edges of the bottom electrode layer 210 and the first insulating layer 320 formed by etching have continuity. In the direction perpendicular to the surface of the substrate 100, the projection of the first insulating layer 320 formed in step S3 on the surface of the substrate 100 is covered by the projection of the bottom electrode layer 210 on the surface of the substrate 100, which is manifested as the projection of the first insulating layer 320 on the surface of the substrate 100 completely overlaps with the projection of the bottom electrode layer 210 on the surface of the substrate 100, or is located within the projection of the bottom electrode layer 210 on the surface of the substrate 100, that is, in all directions parallel to the surface of the substrate 100, the outer diameter of the edge of the first insulating layer 320 is less than or equal to the outer diameter of the edge of the bottom electrode layer 210. The wet etching in step S3 can effectively avoid introducing structural defects on the outer edges of the formed bottom electrode layer 210 and the first insulating layer 320.

[0075] Specifically, Figure 5 As shown, in some embodiments, step S3 includes the following steps:

[0076] S31, forming a first mask layer 310 on the first insulating material layer 300;

[0077] like Figure 6 As shown, in step S31, a photoresist is coated on the surface of the first insulating material layer 300 to form a photoresist layer, and the photoresist layer covers the surface of the first insulating material layer 300; the photoresist layer is exposed and developed to pattern the photoresist layer according to design requirements, a portion of the photoresist layer is removed, and the remaining photoresist layer forms a first mask layer 310 on the first insulating layer 320.

[0078] S32 , wet-etching the first insulating material layer 300 and the first conductive material layer 200 along the first mask layer 310 to form a bottom electrode layer 210 and an insulating layer on the substrate 100 .

[0079] like Figure 7As shown, in step S32, the first mask layer 310 is used as a mask, and a wet etching process is adopted to remove the first insulating material layer 300 and the first conductive material layer 200 on the periphery of the first mask layer 310. For example, the first insulating material layer 300 and the first conductive material layer 200 on the periphery of the first mask layer 310 are removed by selective wet etching without etching and damaging the substrate 100. After etching, the first mask layer 310 made of photoresist is removed by a conventional ashing or stripping process to retain the bottom electrode layer 210 and the first insulating layer 320 formed by etching on the substrate 100. Due to the non-directionality of wet etching, the outer edges of the bottom electrode layer 210 and the first insulating layer 320 formed by wet etching have continuity, and structural defects will not be introduced on the outer edges of the bottom electrode layer 210 and the first insulating layer 320 due to insufficient or excessive etching.

[0080] like Figure 8 and Fig. 9 As shown, in some embodiments, in step S4, a second conductive material layer 400 is first formed on the first insulating layer 320 and the substrate 100 not covered by the bottom electrode layer 210 and the first insulating layer 320, and the second conductive material layer 400 covers the exposed surface of the substrate 100, the sidewall surface of the bottom electrode layer 210, and the sidewall and top surface of the first insulating layer 320; then, a second insulating material layer 500 is formed on the second conductive material layer 400, and the second insulating material layer 500 covers the surface of the second conductive material layer 400. In step S5, the second conductive material layer 400 can be formed on the substrate 100 and the first insulating layer 320 by conventional deposition processes such as CVD, PVD, PECVD, ALD, or conventional sputtering processes, and the second insulating material layer 500 can be formed on the second conductive material layer 400 by conventional CVD deposition processes.

[0081] Among them, the material of the second conductive material layer 400 can be selected from metal, alloy, metal silicide, metal nitride or a combination thereof, the metal can be selected from one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the alloy can be selected from any two or more combinations of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the metal silicide can be selected from one or more of titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi), and the metal nitride can be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TiN), and zirconium nitride (ZrN). Optionally, in some embodiments, the material of the second conductive material layer 400 is selected from metal nitride, for example, in one example, the material of the second conductive material layer 400 is selected from TiN.

[0082] The material of the first insulating material layer 300 is an insulating material with a high dielectric constant. In one example, the first insulating material layer 300 is made of silicon nitride (SiN), silicon oxynitride (SiO x N y ) one or more of the following.

[0083] like Figures 10 to 12 As shown, in step S5, the second insulating material layer 500 and the second conductive material layer 400 located on the substrate 100 and the second insulating material layer 500 and the second conductive material layer 400 partially located on the first insulating layer 320 are removed by a wet etching process, thereby forming an intermediate electrode layer 410 and a second insulating layer 520 in sequence on the first insulating layer 320, the intermediate electrode layer 410 being located on the first insulating layer 320, and the second insulating layer 520 being located on the intermediate electrode layer 410.

[0084] The etching process removes the second conductive material layer 400 in the predetermined area on the surface of the substrate 100 and the first insulating layer 320 in the height direction without damaging the substrate 100. During the etching process, the etching process can completely remove the second conductive material layer 400 on the outer edge surface of the first insulating layer 320, so as to prevent the second conductive material layer 400 deposited on the outer edge of the bottom electrode layer 210 from spreading to the outer edge surface of the first insulating layer 320 due to insufficient etching, thereby causing redeposition defects at the capacitor sidewall.

[0085] Specifically, after wet etching, along the direction perpendicular to the surface of the substrate 100, the projection of the second insulating layer 520 on the surface of the substrate 100 is covered by the projection of the intermediate electrode layer 410 on the surface of the substrate 100, the projection of the intermediate electrode layer 410 on the substrate 100 is located within the projection of the first insulating layer 320 on the substrate 100, and the projection of the first insulating layer 320 on the surface of the substrate 100 is covered by the projection of the bottom electrode layer 210 on the surface of the substrate 100. In each direction parallel to the surface of the substrate 100, the outer diameter of the edge of the intermediate electrode layer 410 is smaller than the outer diameters of the edges of the first insulating layer 320 and the bottom electrode layer 210, and an area not covered by the intermediate electrode layer 410 is left above the bottom electrode layer 210, so as to be used to set a conductive structure connecting the bottom electrode layer 210 and the upper layer. And, as Fig.25As shown, the side walls of the first insulating layer 320 and the bottom electrode layer 210 are in a smooth and continuous slope shape, that is, in all directions parallel to the surface of the substrate 100, the outer diameters of the first insulating layer 320 and the bottom electrode layer 210 at the junction are equal, and at other height positions, the outer diameter of the edge of the first insulating layer 320 is less than the minimum outer diameter of the edge of the bottom electrode layer 210, and the outer edge height of the bottom electrode layer 210 is less than or equal to the outer edge height of the first insulating layer 320. It can be seen that the wet etching process in step S5 can avoid introducing excessive etching depressions or redeposition defects at the outer edge of the bottom electrode layer 210. At the same time, since the wet etching rate is consistent in the height direction, when the capacitor structure is formed at the same time, the pattern load effect will not be introduced on the formed capacitor due to different etching areas, thereby effectively ensuring the capacity and structural reliability of the formed capacitor.

[0086] Specifically, Fig.10 As shown, in some embodiments, step S5 includes the following steps:

[0087] S51, forming a second mask layer 510 on the second insulating material layer 500, wherein the second insulating material layer 500 is located above the first insulating layer 320;

[0088] like Fig.11 As shown, specifically, a photoresist is coated on the surface of the second insulating material layer 500 to form a photoresist layer, and the photoresist layer covers the surface of the second insulating material layer 500; the photoresist layer is exposed and developed to pattern the photoresist layer according to design requirements, and the photoresist layer located above the substrate 100 and partially located above the first insulating layer 320 is removed, and the remaining photoresist layer forms a second mask layer 510 above the first insulating layer 320. In the direction perpendicular to the substrate 100, the projection of the second mask layer on the substrate 100 is located within the projection of the first insulating layer 320 on the substrate 100.

[0089] S52. Wet-etch the second insulating material layer 500 and the second conductive material layer 400 along the second mask layer 510 so that the remaining second conductive material layer 400 forms a second conductive layer 950 on the first insulating layer 320, and the remaining second insulating material layer 500 forms a second insulating layer 520 on the second conductive layer 950.

[0090] like Fig.11 and Fig.12As shown, in step S52, the second mask layer 510 is used as a mask, and a wet etching process is adopted to remove the second insulating material layer 500 and the second conductive material layer 400 outside the second mask layer 510. For example, selective wet etching is adopted to remove the second insulating material layer 500 and the second conductive material layer 400 located outside the second mask layer 510 without etching and damaging the substrate 100. After etching, a conventional ashing or stripping process is adopted to remove the second mask layer 510 of photoresist material to retain the intermediate electrode layer 410 and the second insulating layer 520 formed by etching on the first insulating layer 320.

[0091] like Fig.13 As shown, in step S6, a third conductive material layer 600 is formed on the second insulating layer 520, the first insulating layer 320 not covered by the middle electrode layer 410 and the second insulating layer 520, and the surface of the substrate 100 not covered by the bottom electrode layer 210 and the first insulating layer 320. The third conductive material layer 600 covers the exposed surface of the substrate 100, the side wall surface of the bottom electrode layer 210, the side wall and top surface of the first insulating layer 320, the side wall surface of the middle electrode layer 410, and the side wall and top surface of the second insulating layer 520. In step S6, the third conductive material layer 600 can be formed on the substrate 100, the first insulating layer 320 and the second insulating layer 520 by conventional deposition processes such as CVD, PVD, PECVD, ALD, or conventional sputtering processes.

[0092] Among them, the material of the third conductive material layer 600 can be selected from metal, alloy, metal silicide, metal nitride or a combination thereof, the metal can be selected from one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the alloy can be selected from any two or more combinations of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), ruthenium (Ru), tantalum (Ta), and titanium (Ti), the metal silicide can be selected from one or more of titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi), and the metal nitride can be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (TiN), and zirconium nitride (ZrN). Optionally, in some embodiments, the material of the third conductive material layer 600 is selected from metal nitride, for example, in one example, the material of the third conductive material layer 600 is selected from TiN.

[0093] like Figures 15 to 17 As shown, in step S7 , the third conductive material layer 600 on the substrate 100 and the first insulating layer 320 and a portion of the third conductive material layer 600 on the second insulating layer 520 are removed by a wet etching process, thereby forming a top electrode layer 620 on the second insulating layer 520 .

[0094] The etching process selectively removes the second conductive material layer 400 in a preset area on the surface of the substrate 100, the first insulating layer 320, and the second insulating layer 520 along the height direction without damaging the substrate 100, the first insulating layer 320, and the second insulating layer 520. During the etching process, the etching process can completely remove the third conductive material layer 600 on the outer edge surface of the first insulating layer 320 and the second insulating layer 520, so as to prevent the third conductive material layer 600 deposited on the outer edge of the bottom electrode layer 210 and the middle electrode layer 410 from spreading to the outer edge surface of the first insulating layer 320 and the second insulating layer 520 due to insufficient etching, thereby effectively preventing the occurrence of redeposition defects at the side wall of the capacitor.

[0095] Specifically, after wet etching, along the direction perpendicular to the surface of the substrate 100, the projection of the top electrode layer 620 formed by etching on the substrate 100 is located within the projection of the second insulating layer 520 on the substrate 100, the projection of the second insulating layer 520 on the surface of the substrate 100 is covered by the projection of the intermediate electrode layer 410 on the surface of the substrate 100, the projection of the intermediate electrode layer 410 on the substrate 100 is located within the projection of the first insulating layer 320 on the substrate 100, and the projection of the first insulating layer 320 on the surface of the substrate 100 is covered by the projection of the bottom electrode layer 210 on the surface of the substrate 100. Among them, in various directions parallel to the surface of the substrate 100, the outer diameter of the edge of the top electrode layer 620 is smaller than the outer diameters of the edges of the second insulating layer 520 and the intermediate electrode layer 410, so that an area not covered by the top electrode layer 620 is left above the intermediate electrode layer 410, thereby being used to set a conductive structure connecting the intermediate electrode layer 410 and the upper layer; the outer diameter of the edge of the intermediate electrode layer 410 is smaller than the outer diameters of the edges of the first insulating layer 320 and the bottom electrode layer 210, and an area not covered by the intermediate electrode layer 410 is left above the bottom electrode layer 210, thereby being used to set a conductive structure connecting the bottom electrode layer 210 and the upper layer.

[0096] And, if Fig.25As shown, the side walls of the second insulating layer 520 and the intermediate electrode layer 410 are in a smooth and continuous slope shape, that is, in all directions parallel to the surface of the substrate 100, the outer diameter of the edge of the second insulating layer 520 is less than or equal to the outer diameter of the edge of the intermediate electrode layer 410, wherein the outer diameters of the second insulating layer 520 and the intermediate electrode layer 410 at the junction are equal, the outer diameter of the edge of the second insulating layer 520 at other height positions is less than the minimum outer diameter of the bottom electrode layer 210, and the outer edge height of the intermediate electrode layer 410 is less than or equal to the outer edge height of the second insulating layer 520. Similarly, the sidewalls of the first insulating layer 320 and the bottom electrode layer 210 are in a smooth and continuous slope shape, that is, in all directions parallel to the surface of the substrate 100, the outer diameter of the edge of the first insulating layer 320 is less than or equal to the outer diameter of the edge of the bottom electrode layer 210, wherein the outer diameters of the first insulating layer 320 and the bottom electrode layer 210 at the junction are equal, the outer diameter of the edge of the first insulating layer 320 at other height positions is less than the minimum outer diameter of the bottom electrode layer 210, and the height of the outer edge of the bottom electrode layer 210 is less than or equal to the height of the outer edge of the first insulating layer 320. It can be seen that the wet etching process in step S6 can avoid introducing excessive etching depressions or redeposition defects at the outer edges of the bottom electrode layer 210 and the intermediate electrode layer 410. At the same time, since the wet etching rate is consistent in the height direction, when the capacitor structure is formed at the same time, the pattern load effect will not be introduced on the formed capacitor due to different etching areas, thereby effectively ensuring the capacity and structural reliability of the formed capacitor.

[0097] Specifically, Fig.15 As shown, in some embodiments, step S7 includes the following steps:

[0098] S71, forming a third mask layer 610 on the third conductive material layer 600, wherein the third mask layer 610 is located above the second insulating layer 520;

[0099] like Fig.16 As shown, specifically, a photoresist is coated on the surface of the third conductive material layer 600 to form a photoresist layer, and the photoresist layer covers the surface of the third conductive material layer 600; the photoresist layer is exposed and developed to pattern the photoresist layer according to design requirements, and the photoresist layer located above the substrate 100, the first insulating layer 320, and part of the photoresist layer located above the second insulating layer 520 is removed, and the remaining photoresist layer forms a third mask layer 610 above the second insulating layer 520. In the direction perpendicular to the substrate 100, the projection of the third mask layer on the substrate 100 is located within the projection of the second insulating layer 520 on the substrate 100.

[0100] S72 , wet-etching the third conductive material layer 600 along the third mask layer 610 , so that the remaining third conductive material layer 600 forms a top electrode layer 620 on the second insulating layer 520 .

[0101] like Fig.16 and Fig.17 As shown, in step S72, the third mask layer 610 is used as a mask and a wet etching process is adopted to remove the third conductive material layer 600 located outside the third mask layer 610. For example, selective wet etching is adopted to remove the third conductive material layer 600 located outside the third mask layer 610 without etching and damaging the first insulating layer 320, the second insulating layer 520 and the substrate 100. After etching, the third mask layer 610 of the photoresist material is removed by a conventional ashing or stripping process to retain the top electrode layer 620 formed by etching on the second insulating layer 520.

[0102] like Fig.18 and Fig.19 As shown, in some embodiments, the method for forming a stacked capacitor structure further includes forming a covering layer 800 on at least the exposed surfaces of the first insulating layer 320, the middle electrode layer 410, the second insulating layer 520 and the top electrode layer 620. Fig.18 As shown, a covering layer 800 is formed on the exposed surfaces of the substrate 100, the bottom electrode layer 210, the first insulating layer 320, the middle electrode layer 410, the second insulating layer 520 and the top electrode layer 620. Specifically, a silicon material layer 810 is first formed on the exposed surfaces of the substrate 100, the bottom electrode layer 210, the first insulating layer 320, the middle electrode layer 410, the second insulating layer 520 and the top electrode layer 620 by any suitable deposition process such as CVD, PVD, PECVD, ALD, etc., and then chemical vapor deposition or nitrogen ion implantation is performed on the silicon material layer 810 to form a silicon nitride material layer 820 on the surface of the silicon material layer 810, so that the silicon material layer 810 is converted into a silicon nitride material, thereby completing the formation of the covering layer 800. In another example, as Fig.19 As shown, in Fig.18 Based on the example shown, the covering layer 800 located on the surface of the substrate 100 and the side walls of the bottom electrode layer 210 and the first insulating layer 320 is removed by a dry etching or wet etching process, so that the remaining covering layer 800 covers the exposed surfaces of the first insulating layer 320, the middle electrode layer 410, the second insulating layer 520 and the top electrode layer 620.

[0103] Furthermore, in some embodiments, Fig.14As shown, after step S6, a silicon oxide material layer 700 is formed on the third conductive material layer 600, wherein the silicon oxide material layer 700 can be formed by any suitable deposition process such as CVD, PVD, PECVD, ALD, etc. For example, the silicon oxide material layer 700 is deposited on the third conductive material layer 600 by CVD, specifically, tetraethoxysilane (TEOS) and ozone (O3) are filled, and tetraethoxysilane (TEOS) and ozone (O3) are used as precursor materials to form the silicon oxide material layer 700 by thermal reaction on the third conductive material layer 600. Figure 16 to Figure 17 As shown, in step S7, during the process of wet etching the third conductive material layer 600 to form the top electrode layer 620, the silicon oxide material layer 700 located at the periphery of the third mask layer 610 is etched away together with the third conductive material layer 600, while the silicon oxide material layer 700 located under the third mask layer 610 is retained, thereby forming a silicon oxide layer 710 on the top electrode layer 620. Fig.18 and Fig.19 As shown, the silicon oxide layer 710 remaining on the top electrode layer 620 can serve as a protective layer for the top electrode layer 620 to prevent the precursor material of the subsequent deposition process of the cover layer 800 from reacting with the top electrode layer 620. It can be understood by those skilled in the art that the silicon oxide material layer 700 may not be provided if the above-mentioned beneficial effects of the silicon oxide material layer 700 are not considered.

[0104] like Figure 20 to Figure 21 In some embodiments, the method for forming the stacked capacitor structure further includes forming a first conductive structure 911 on the bottom electrode layer 210, forming a second conductive structure 921 on the middle electrode layer 410, and forming a third conductive structure 931 on the top electrode layer 620, wherein the first conductive structure 911 is located above the bottom electrode layer 210, the second conductive structure 921 is located above the middle electrode layer 410, and the third conductive structure 931 is located above the top electrode layer 620, and the first conductive structure 911, the second conductive structure 921, and the third conductive structure 931 are insulated and isolated from each other. Specifically, as Fig. 20As shown, an interlayer dielectric layer 900 is formed on the substrate 100, the first insulating layer 320, the second insulating layer 520 and the top electrode layer 620 by conventional deposition or sputtering processes. For example, in one example, the interlayer dielectric layer 900 is formed on the cover layer 800, wherein the interlayer dielectric layer 900 can be made of insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), hydrogen silsesquioxane polymer (HSQ), methane silsesquioxane polymer (MSQ), methyl silicate compounds, carbon-doped oxides, etc.; a first through hole 910 and a second through hole 920 are formed on the interlayer dielectric layer 900 by conventional photolithography processes. and a third through hole 930, wherein the first through hole 910 is located above the bottom electrode layer 210, and the first through hole 910 penetrates the interlayer dielectric layer 900, the cover layer 800 and the first insulating layer 320 to expose a portion of the surface of the bottom electrode layer 210; the second through hole 920 is located above the middle electrode layer 410, and the second through hole 920 penetrates the interlayer dielectric layer 900, the cover layer 800 and the second insulating layer 520 to expose a portion of the surface of the middle electrode layer 410; the third through hole 930 is located above the top electrode layer 620, and the third through hole 930 penetrates the interlayer dielectric layer 900 and the cover layer 800 to expose a portion of the surface of the top electrode layer 620. Then as Fig.21 As shown, a conventional deposition process is used to sequentially form a diffusion barrier layer, a seed layer and a metal layer in the first through hole 910, the second through hole 920 and the third through hole 930, thereby filling the first through hole 910 to form a first conductive structure 911, filling the second through hole 920 to form a second conductive structure 921, and filling the third through hole 930 to form a third conductive structure 931.

[0105] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for forming a stacked capacitor structure, characterized in that: include: providing a substrate; forming a first conductive material layer and a first insulating material layer in sequence on the substrate; forming a first mask layer on the first insulating material layer, and wet-etching a portion of the first insulating material layer and the first conductive material layer along the first mask layer to form a bottom electrode layer and a first insulating layer on the substrate; forming a second conductive material layer and a second insulating material layer on the substrate and the first insulating layer in sequence; forming a second mask layer on the second insulating material layer, and wet-etching a portion of the second insulating material layer and the second conductive material layer along the second mask layer to form an intermediate electrode layer and a second insulating layer on the first insulating layer; forming a third conductive material layer on the substrate, the first insulating layer and the second insulating layer; A third mask layer is formed on the third conductive material layer, and a portion of the third conductive material layer is wet-etched along the third mask layer, so that the remaining third conductive material layer forms a top electrode layer on the second insulating layer.

2. The forming method according to claim 1, characterized in that: Wet etching a portion of the second insulating material layer and the second conductive material layer to form an intermediate electrode layer and a second insulating layer on the first insulating layer, comprising: forming a second mask layer on the second insulating material layer, wherein the second insulating material layer is located above the first insulating layer; wherein, along a direction perpendicular to the surface of the substrate, a projection of the second mask layer on the substrate is located within a projection of the first insulating layer on the substrate; The second insulating material layer and the second conductive material layer are wet-etched along the second mask layer, so that the remaining second conductive material layer forms a second conductive layer on the first insulating layer, and the remaining second insulating material layer forms a second insulating layer on the second conductive layer.

3. The forming method according to claim 1, characterized in that: Wet etching a portion of the third conductive material layer so that the remaining third conductive material layer forms a top electrode layer on the second insulating layer, comprising: forming a third mask layer on the third conductive material layer, wherein the third mask layer is located above the second insulating layer; wherein, along a direction perpendicular to the surface of the substrate, a projection of the third mask layer on the substrate is located within a projection of the second insulating layer on the substrate; The third conductive material layer is wet-etched along the third mask layer so that the remaining third conductive material layer forms a top electrode layer on the second insulating layer.

4. The forming method according to claim 1, characterized in that: The materials of the bottom electrode layer, the middle electrode layer and the top electrode layer are TiN.

5. The forming method according to claim 1, characterized in that: Also includes: forming a first conductive structure on the bottom electrode layer; forming a second conductive structure on the intermediate electrode layer; forming a third conductive structure on the top electrode layer; The first conductive structure, the second conductive structure and the third conductive structure are insulated and isolated from each other.

6. A stacked capacitor structure prepared by the forming method according to any one of claims 1 to 5, characterized in that: include: substrate; A bottom electrode layer, which is disposed on the substrate; A first insulating layer, which is disposed on the bottom electrode layer; an intermediate electrode layer, which is disposed on the first insulating layer; a second insulating layer, which is disposed on the intermediate electrode layer; a top electrode layer, disposed on the second insulating layer; a covering layer, wherein the covering layer covers surfaces of the first insulating layer, the middle electrode layer, the second insulating layer, and the top electrode layer; a silicon oxide layer disposed between the top electrode layer and the cover layer; Wherein, along a direction perpendicular to the surface of the substrate, a projection of the first insulating layer on the substrate is covered by a projection of the bottom electrode layer on the substrate, a projection of the middle electrode layer on the substrate is located within a projection of the first insulating layer on the substrate, a projection of the second insulating layer on the substrate is covered by a projection of the middle electrode layer on the substrate, and a projection of the top electrode layer on the substrate is located within a projection of the second insulating layer on the substrate; The height of the outer edge of the bottom electrode layer is less than or equal to the height of the outer edge of the first insulating layer, and the height of the outer edge of the middle electrode layer is less than or equal to the height of the outer edge of the second insulating layer; the outer edges of the first insulating layer and the bottom electrode layer are continuous at the junction and are in a slope shape increasing from the outer diameter to the bottom, and the outer edges of the second insulating layer and the middle electrode layer are continuous at the junction and are in a slope shape increasing from the outer diameter to the bottom.

7. The stacked capacitor structure according to claim 1, characterized in that: A first conductive structure is disposed on the bottom electrode layer, a second conductive structure is disposed on the middle electrode layer, and a third conductive structure is disposed on the top electrode layer. The first conductive structure, the second conductive structure and the third conductive structure are insulated and isolated from each other.

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