Semiconductor device and manufacturing method thereof, and electronic device

Abstract

The present application provides a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device of the present application includes one or more layers of memory cells stacked vertically along a third direction, a word line extending along the third direction, and a bit line extending along a second direction and at least partially surrounding the word line; multiple layers of vertically stacked memory cells share a word line and are connected to different bit lines; the semiconductor layer of the transistor of each memory cell extends along the third direction and fully surrounds the word line; the first electrode of the capacitor of each memory cell extends along the first direction and at least partially surrounds the semiconductor layer, the first direction intersects with the second direction and is both in a plane perpendicular to the third direction; each first electrode and bit line respectively surrounds different areas of the side wall of the semiconductor layer along the third direction; the channel direction of the transistor is consistent with the extension direction of the word line. The memory architecture provided by the present application can effectively improve storage density and has a simple manufacturing process.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and electronic equipment. Background Art

[0002] The integration level of a two-dimensional semiconductor memory device is primarily determined by the area occupied by the memory cells. Therefore, pattern refinement in manufacturing technology is a major factor affecting the integration level of the two-dimensional semiconductor memory device.

[0003] In recent years, 3D memory has attracted increasing attention due to its advantages in increasing memory density, especially in the field of DRAM. Currently, there is increasing attention on the ease of industrial manufacturing and storage density advantages of 3D device design structures.

[0004] Whether it is a two-dimensional or 3D structure, the layout of storage cells or between storage cells in the memory is a direction to improve storage density. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] In one aspect, an exemplary embodiment of the present application provides a semiconductor device comprising one or more layers of memory cells vertically stacked along a third direction, a word line extending along the third direction, and a bit line extending along a second direction and at least partially surrounding the word line;

[0007] Multiple memory cells stacked vertically in multiple layers share one word line and are connected to different bit lines;

[0008] The semiconductor layer of the transistor of each memory cell extends along the third direction and completely surrounds the word line;

[0009] The first electrode of the capacitor of each memory cell extends along a first direction and at least partially surrounds the semiconductor layer, wherein the first direction intersects the second direction and both are located in a plane perpendicular to the third direction;

[0010] Each first electrode and the bit line respectively surrounds different areas of the sidewall of the semiconductor layer along the third direction;

[0011] A channel direction of the transistor is consistent with an extending direction of the word line.

[0012] In an exemplary embodiment, each of the transistors further includes a gate, wherein the gate is a portion of the word line; and a length of the gate is equal to a thickness of an insulating layer separating the bit line from the first electrode.

[0013] In an exemplary embodiment, an extending direction of the bit line is perpendicular to an extending direction of the first electrode.

[0014] In an exemplary embodiment, the first source / drain of the transistor and the first electrode of the capacitor are an integral structure, and the second source / drain of the transistor and the bit line are an integral structure.

[0015] In an exemplary embodiment, the first source / drain of the transistor fully surrounds the semiconductor layer and is connected to the semiconductor layer, and the second source / drain of the transistor fully surrounds the semiconductor layer and is connected to the semiconductor layer.

[0016] In an exemplary embodiment, an intersection angle between the first direction and the second direction is in a range of 45 degrees to 90 degrees.

[0017] In an exemplary embodiment, the first electrode of the capacitor includes a first portion and a second portion, the second portion at least partially wrapping the semiconductor layer.

[0018] In an exemplary embodiment, the first electrode of the capacitor includes a first portion, a second portion wrapping the semiconductor layer, and a third portion extending beyond the semiconductor layer and symmetrical to the first portion in the second direction.

[0019] In an exemplary embodiment, in the extending direction of the word line, the semiconductor layers corresponding to different memory cells are disconnected from each other.

[0020] In an exemplary embodiment, first electrodes of capacitors of memory cells in the same layer are disconnected from each other.

[0021] In an exemplary embodiment, the first electrode of the capacitor includes a different conductive material than the bit line.

[0022] In an exemplary embodiment, the second electrodes of the capacitors of the memory cells in different layers and the second electrodes of the capacitors of the memory cells in the same layer are an integrated structure, which is filled between the first electrodes of different capacitors to become a common electrode.

[0023] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0024] forming a stacked structure including at least two stacked units separated by a sacrificial layer, each stacked unit including a first conductive layer disposed between insulating layers and a second conductive layer disposed between the insulating layers;

[0025] forming a word line through hole penetrating the stacked structure to form a word line extending along a third direction and a semiconductor layer surrounding the word line;

[0026] Etching the stacked structure to form a first conductive portion and a second conductive portion intersecting each other in the first conductive layer and the second conductive layer, wherein the first conductive portion is wider than the second conductive portion, the first conductive portion extends along a first direction, and the second conductive portion extends along a second direction, wherein the first direction intersects the second direction and both lie in a plane perpendicular to the third direction;

[0027] Etching the first conductive portion and the second conductive portion in the first conductive layer to form a first electrode of the capacitor extending along a first direction and at least partially surrounding the semiconductor layer;

[0028] removing the sacrificial layer to form a sacrificial groove and removing the semiconductor layer via the sacrificial groove;

[0029] Etching the first conductive portion and the second conductive portion in the second conductive layer to form a bit line extending along a second direction and at least partially surrounding the semiconductor layer;

[0030] Each first electrode and the bit line respectively surrounds different areas of the sidewall of the semiconductor layer along the third direction;

[0031] A channel direction of the transistor is consistent with an extending direction of the word line.

[0032] In an exemplary embodiment, forming a word line includes sequentially depositing a semiconductor film, an insulating layer film, and a conductive film around the inner wall of the word line through hole to form a word line extending along the third direction, a semiconductor layer surrounding the word line along the third direction, and a gate insulating layer arranged between the word line and the semiconductor layer.

[0033] In an exemplary embodiment, the manufacturing method further comprises the following steps:

[0034] A groove is formed that penetrates the stacked structure and extends along the second direction, so that the first conductive parts in the first conductive layer and the second conductive layer are disconnected, exposing the first electrode of the capacitor of each storage unit; from the outside of the stacked structure and with the help of the formed groove, a dielectric film is deposited along the third direction to cover the exposed surfaces of the first electrode to form a first dielectric layer, and covers the surfaces of the first conductive parts in each second conductive layer exposed in the first direction and covers the surfaces of each insulating layer exposed in the first direction to form a second dielectric layer; a conductive material film is deposited on the first dielectric layer to form the second electrode of each layer of capacitor; a conductive material film is deposited on the second dielectric layer to form an electrical connection area, and the second electrodes of the capacitors in each layer are connected to each other through the electrical connection area to form a common electrode.

[0035] In an exemplary embodiment, the first conductive layer includes a different conductive material than the second conductive layer.

[0036] In yet another aspect, exemplary embodiments of the present application provide an electronic device comprising any of the above-mentioned semiconductor devices.

[0037] In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0038] In the structure of the present application, the bit line, capacitor and word line are perpendicular to each other, wherein the bit line is horizontal and the word line is vertical, and the first electrode of the capacitor is arranged on both sides of the word line. In this stacked structure design, the vertical device has a channel and a source and drain distributed in different layers, so the parasitic MOS is easy to remove; in addition, the semiconductor layer is a self-aligned structure, and the gate length is determined by the thickness of the deposited film, avoiding the dependence of small-size devices on advanced lithography equipment.

[0039] The manufacturing method of this application completes a multi-layer stacking structure of vertical devices with different S / D shapes by re-etching vertical lines of different widths, integrating the advantages of vertical devices into the 3D DRAM structure. The process is feasible and the structural design is novel, providing a new direction for the multi-layer stacking of vertical devices in 3D DRAM.

[0040] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0042] Figure 1 A schematic diagram of a three-dimensional structure of a 3D stacked semiconductor device provided in an exemplary embodiment of the present application;

[0043] Figure 2A A schematic diagram of a three-dimensional structure of a method for manufacturing a 3D stacked semiconductor device after forming a stacked structure, provided in an exemplary embodiment of the present application;

[0044] Figure 2B A schematic cross-sectional view of a stacked structure obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along the C1 direction (through the first conductive layer);

[0045] Figure 2C A schematic cross-sectional view of a stacked structure obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2;

[0046] Figure 2D A schematic cross-sectional view of a stacked structure obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C3;

[0047] Figure 3A A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through a first conductive layer);

[0048] Figure 3B A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2;

[0049] Figure 4A A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through a first conductive layer);

[0050] Figure 4B A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2;

[0051] Figure 5A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through a first conductive layer);

[0052] Figure 6A A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through the first conductive layer);

[0053] Figure 6B and Figure 6C for Figure 6A Schematic diagrams of other exemplary variations of the structure shown;

[0054] Figure 6D A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C3;

[0055] Figure 7A A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through a sacrificial layer);

[0056] Figure 7B A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2;

[0057] Figure 7C A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C3;

[0058] Figure 8A A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C1 (through a sacrificial layer filled with an insulating material);

[0059] Figure 8B A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2;

[0060] Figure 8C A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C3;

[0061] Figure 9AA schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through a first conductive layer);

[0062] Figure 9B for Figure 9A Schematic diagrams of other exemplary structures of the illustrated structure;

[0063] Figure 9C A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2;

[0064] Figure 10A A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through a first conductive layer);

[0065] Figure 10B A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along the C2 direction (perpendicular to the substrate and longitudinally passing through the first conductive portion);

[0066] Figure 10C A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C3;

[0067] Figure 11A A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along the C1 direction (through the first conductive layer); and

[0068] Figure 11B A schematic cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2. DETAILED DESCRIPTION

[0069] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0070] The embodiments herein can be implemented in a variety of different forms. Those skilled in the art can easily understand that the implementation and content can be transformed into various forms without departing from the purpose and scope of this application. Therefore, this application should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other in any way.

[0071] The scales of the figures in this application are intended to serve as a reference for actual processes, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing between them can be adjusted according to actual needs. The figures described in this application are merely schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the figures.

[0072] In this specification, for the sake of convenience, words and phrases indicating orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", "one side", "the other side", "one end", "the other end", etc., are used to illustrate the positional relationship of constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0073] In this specification, unless otherwise specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0074] In the description of this application, ordinal numbers such as "first" and "second" are provided to avoid confusion of constituent elements, rather than to limit the quantity.

[0075] In the description of this application, "film" and "layer" can be interchanged. For example, "metal layer" can sometimes be replaced with "metal film".

[0076] In the description of this application, “A and B are arranged in the same layer” means that A and B are formed simultaneously through the same patterning process.

[0077] In the description of this application, a transistor refers to a component comprising at least three terminals: a gate, a drain, and a source. A transistor has a channel region (i.e., a semiconductor layer) between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel region, and the source. In this application, the channel region refers to the area through which current mainly flows. In this application, the terms "channel region," "channel layer," and "semiconductor layer" are interchangeable.

[0078] In recent years, 3D semiconductor devices such as 3D DRAM have been widely used because their vertical stacking greatly improves the storage density of memory cells.

[0079] The inventive concept proposed in the embodiments of this application is applicable to both two-dimensional memory cell arrays and three-dimensional memory cell arrays. This application mainly uses a three-dimensional memory cell array as an example for explanation.

[0080] An exemplary embodiment of the present application provides a semiconductor device, comprising one or more layers of memory cells vertically stacked along a third direction, word lines extending along the third direction, and bit lines extending along a second direction and at least partially surrounding the word lines; a plurality of memory cells vertically stacked in multiple layers share one word line and are connected to different bit lines; a semiconductor layer of a transistor of each memory cell extends along the third direction and completely surrounds the word line; a first electrode of a capacitor of each memory cell extends along a first direction and at least partially surrounds the semiconductor layer, the first direction intersecting the second direction and both being in a plane perpendicular to the third direction; each first electrode and the bit line respectively surrounds different regions of the sidewall of the semiconductor layer along the third direction; a channel direction of the transistor is consistent with the extension direction of the word line.

[0081] In an exemplary embodiment, each of the transistors further includes a gate, wherein the gate is a portion of the word line; and a length of the gate is equal to a thickness of an insulating layer separating the bit line from the first electrode.

[0082] In an exemplary embodiment, an extending direction of the bit line is perpendicular to an extending direction of the first electrode.

[0083] In an exemplary embodiment, the first source / drain of the transistor and the first electrode of the capacitor are an integral structure, and the second source / drain of the transistor and the bit line are an integral structure.

[0084] As used in this application, the term "first direction" X is defined as the direction in which the first electrode of the capacitor extends; the term "second direction" Y is defined as the direction that intersects the "first direction" X and is the direction in which the bit line extends; the term "third direction" Z is defined as the direction perpendicular to the plane where the substrate is located, that is, the direction in which the word line extends; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction Y" and the "third direction Z" can be as follows Figure 1 and Figure 2A As shown.

[0085] As used in this application, the term "C1 direction" refers to a cross-sectional view parallel to the substrate, perpendicular to the third direction Z, and passing through the region where the first conductive layer, the sacrificial layer, etc. are located; the term "C2 direction" refers to a direction intercepted along the C2 plane perpendicular to the substrate and parallel to the first direction X; the term "C3 direction" refers to a direction intercepted along the C3 plane perpendicular to the substrate and parallel to the second direction Y, and the C3 direction is perpendicular to the C2 direction. "C1 direction", "C2 direction", and "C3 direction" can be as follows Figures 2B-2D As shown.

[0086] As used in this application, the term "integrated structure" may refer to a microstructural separation between A and B, such as the absence of distinct interfaces such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integral. For example, A and B may be formed from the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0087] Figure 1 A schematic diagram of a three-dimensional structure of a 3D stacked semiconductor device provided in an exemplary embodiment of the present application. Figure 1 As shown, the 3D stacked semiconductor device provided by the exemplary embodiment of the present application may include one or more layers of memory cells vertically stacked along a third direction, a word line 90 extending along the third direction, and a bit line 100 extending along a second direction and at least partially surrounding the word line. The multiple layers of vertically stacked memory cells share one word line 90 and are connected to different bit lines 100. Figure 1 It is shown that two transistors adjacent to each other in the second direction Y share one bit line 100 .

[0088] Continue to refer Figure 1The semiconductor layer 70 of the transistor of each memory cell extends along the third direction Z and completely surrounds the word line 90. The first electrode 200 of the capacitor of each memory cell extends along the first direction X and at least partially surrounds the semiconductor layer 70. Each first electrode 200 and the bit line 100 respectively surrounds different areas of the sidewall of the semiconductor layer along the third direction. In other words, the main surface (which can also be understood as the side surface of the ring structure) of the semiconductor layer (channel layer) 70 of the transistor of each memory cell extends along the third direction Z and surrounds the word line 90, and the first electrode 200 of the capacitor of each memory cell extends along the first direction X and at least partially surrounds the semiconductor layer 70.

[0089] The first direction X and the second direction Y may intersect and both lie in a plane perpendicular to the third direction Z. The angle between the intersecting first direction X and the second direction Y may be in the range of 45 degrees to 90 degrees. In an exemplary embodiment, the angle between the intersecting first direction X and the second direction Y may be in the range of 45 degrees to 60 degrees. In an exemplary embodiment, the angle between the intersecting first direction X and the second direction Y may be 90 degrees, that is, the first direction X and the second direction Y are perpendicular to each other.

[0090] Here, surrounding can be understood as partially surrounding or fully surrounding the gate or word line 90. In some embodiments, surrounding can be completely surrounding as a whole, and the cross-section of the semiconductor layer 70 after surrounding can be a closed ring, and the ring shape is adapted to the outer contour of the cross section of the word line 90. Exemplarily, the cross section of the word line 90 is, for example, a square structure. The direction of interception of the cross section is along the direction perpendicular to the substrate 10. In an exemplary embodiment, surrounding can be partially surrounding, and the cross section after surrounding is not closed, but presents a ring shape. For example, the cross section of the semiconductor layer 70 is a ring with an opening.

[0091] Figure 1 It is also shown that the channel direction of the transistor is consistent with the extension direction of the word line. In this application, "channel direction" refers to the length direction of the channel, that is, the third direction perpendicular to the substrate.

[0092] Continue to refer Figure 1 The first source / drain of the transistor is integrally formed with the first electrode 200 of the capacitor, and the second source / drain of the transistor is integrally formed with the bit line 100. The first source / drain of the transistor completely surrounds and is connected to the semiconductor layer 70, and the second source / drain of the transistor completely surrounds and is connected to the semiconductor layer 70.

[0093] Figure 1The diagram shows that the bit line 100 is located above the first electrode 200 of the capacitor along the channel direction. The extending direction of the bit line 100 is perpendicular to the extending direction of the first electrode 200, and the bit line 100 and the corresponding first electrode 200 of the capacitor are separated by a distance in the third direction Z. The distance is equal to the thickness of the insulating layer separating the bit line 100 and the first electrode 200. However, in other exemplary embodiments, the bit line 100 may be located below the first electrode 200 of the capacitor, and the extending direction of the bit line 100 may not be perpendicular to the extending direction of the first electrode 200, but may be at an angle less than 90 degrees, such as 45-60 degrees, 60-85 degrees, etc.

[0094] In an exemplary embodiment, each transistor further includes a gate, which is part of the word line 90, and a length of the gate is equal to the thickness of the insulating layer isolating the bit line 100 from the first electrode 200. In other words, the effective length of the channel layer can be equal to the distance between the bit line 100 and the first electrode 200 of the capacitor in the third direction Z.

[0095] In an exemplary embodiment, the first electrode 200 of the capacitor may include a first portion and a second portion, wherein the second portion at least partially wraps the semiconductor layer. In other exemplary embodiments, the first electrode 200 of the capacitor may further include a first portion, a second portion wrapping the semiconductor layer, and a third portion extending beyond the semiconductor layer and symmetrical to the first portion in the second direction.

[0096] In an exemplary embodiment, the semiconductor layers 70 corresponding to different memory cells are disconnected in the extending direction of the word line 90 .

[0097] In an exemplary embodiment, first electrodes of capacitors of memory cells in the same layer are disconnected from each other.

[0098] As used in this application, the term "disconnection setting" or "spacer setting" can be a physical structural disconnection to achieve spacing, such as with the help of an isolation layer formed by an insulating material, or a disconnection in electrical properties, for example, the conductivity of the semiconductor region between two channel regions is approximately insulating.

[0099] In an exemplary embodiment, the bit line 100 and the first electrode 200 of the capacitor include different conductive materials, such as different metal materials. In an exemplary embodiment, to maximize ohmic contact between the metal and the semiconductor layer 70 and avoid the formation of a Schottky barrier, different material combinations may be used. Alternatively, ohmic contact may be achieved by doping the semiconductor layer 70 with different concentrations or introducing recombination centers in the region contacting the metal layer (e.g., the source / drain contact region) of the semiconductor layer 70.

[0100] In an exemplary embodiment, the transistor further includes a gate insulating layer 80 disposed between the gate and the channel layer.

[0101] In an exemplary embodiment, the second electrodes 220 of the capacitors of the memory cells of different layers and the second electrodes 220 of the capacitors of the memory cells of the same layer are an integrated structure, which is filled between the first electrodes 200 of different capacitors to become a common electrode.

[0102] In an exemplary embodiment, the first electrode 200 may be in various shapes, including but not limited to a plate shape, a line shape, a strip shape, a cylinder shape, and the like.

[0103] In an exemplary embodiment, the first electrode 200 may be an inner electrode of a capacitor, and the second electrode 220 may be an outer electrode of the capacitor.

[0104] Although the terms "first source / drain" and "second source / drain" are used herein to designate two separate and distinct sources / drains, it is not intended that the sources / drains referred to as "first" source / drain and / or "second" source / drain have a unique meaning. It is intended that only one of the sources / drains be connected to the bit line, and the other be connected to the first electrode of the capacitor.

[0105] In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other. In an exemplary embodiment, one of the first source / drain and the second source / drain is a source of a transistor, and the other is a drain of the transistor.

[0106] The technical solution of this embodiment is further illustrated below by taking the manufacturing process of a 3D stacked DRAM device as an example.

[0107] The "composition process" or "patterning process" mentioned in this embodiment may include processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping of the photoresist, and is a mature manufacturing process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a composition process or a photolithography process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" still requires a composition process or a photolithography process during the entire production process, it is called a "thin film" before the composition process and a "layer" after the composition process. The "layer" after the composition process or the photolithography process contains at least one "pattern".

[0108] In an exemplary embodiment, a manufacturing process of a 3D stacked DRAM device may include:

[0109] S100: forming a stacked structure, specifically the steps may include providing a substrate 10, depositing an insulating layer film, a first conductive film, an insulating layer film, a second conductive film, and an insulating layer film in sequence on the substrate 10 along a third direction Z to form a stacked unit including a first conductive layer 30 disposed between two adjacent insulating layers 20 and a second conductive layer 40 disposed between two adjacent insulating layers 20; depositing a sacrificial layer film on the stacked unit to form a sacrificial layer 50; depositing an insulating layer film, a first conductive film, an insulating layer film, a second conductive film, and an insulating layer film in sequence on the sacrificial layer 50 to form another stacked unit; repeating the aforementioned steps, thereby forming a stacked structure 1 including four identical stacked units separated by three sacrificial layers 50, as shown in FIG. Figure 2A 、 Figure 2B 、 Figure 2C as well as Figure 2D As shown. Among them, Figure 2A A schematic diagram of a three-dimensional structure of a method for manufacturing a 3D stacked semiconductor device after forming a stacked structure, provided in an exemplary embodiment of the present application; Figure 2B A schematic cross-sectional view of a stacked structure obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along the C1 direction (through the first conductive layer 30); Figure 2C A schematic cross-sectional view of a stacked structure obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2; Figure 2D A schematic cross-sectional view of a stacked structure obtained in an intermediate step of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C3.

[0110] In an exemplary embodiment, each thin film layer may be deposited by using a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or the like.

[0111] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition (ALD) method, which can more accurately control the thickness of each thin film layer, such as to about 1 nm.

[0112] In an exemplary embodiment, the substrate 10 can be made of glass, silicon, a flexible material, or the like. The flexible material can be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. In an exemplary embodiment, the substrate can be a single-layer structure or a multi-layer stacked structure. The stacked structure substrate can include: flexible material / inorganic material / flexible material. The inorganic material can be, for example, any one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). In an exemplary embodiment, the substrate 10 can be a semiconductor substrate, such as a silicon substrate.

[0113] In an exemplary embodiment, the insulating layer 20 can be made of any one or more non-conductive materials selected from silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the insulating layer 20 can be made of an oxide insulating material, such as silicon dioxide (e.g., SiO2). The thickness of the insulating layer 20 disposed between the first conductive layer 30 and the second conductive layer 40 can determine the gate length. Since the thickness of the insulating layer can be precisely controlled at the nanometer scale, the gate length can also be precisely controlled as required. This control process is easy to operate, thereby avoiding the dependence of small-sized devices on advanced lithography equipment.

[0114] In an exemplary embodiment, both the first conductive layer 30 and the second conductive layer 40 can be metal layers, but made of different metal materials. Such metal materials may include, but are not limited to, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta), or composite metal materials, such as a titanium nitride (TiN) / tungsten (W) composite structure. In an exemplary embodiment, the first conductive layer 30 can be used to form the first electrode of a capacitor, and thus the thickness of the first conductive layer 30 can be the height of the capacitor to be formed, for example, 50 nm. The second conductive layer 40 can be used to form a bit line. In other exemplary embodiments, the first conductive layer 30 can also be used to form a bit line, while the second conductive layer 40 can be used to form the first electrode of the capacitor. Because the first conductive layer 30 and the second conductive layer 40 are made of different metal materials, the same etching solution has different etching rates for the two film layers during subsequent etching processes, such as wet etching, thereby achieving different film layer structures.

[0115] In an exemplary embodiment, the sacrificial layer 50 may be made of a different material than the insulating layer 20, so that when the sacrificial layer 50 is subsequently etched and removed, the sacrificial layer 50 and the insulating layer 20 may have different etch rates, thereby removing the sacrificial layer 50 while retaining the insulating layer 20. For example, if the insulating layer 20 is made of SiO2, the sacrificial layer 50 may be made of silicon nitride (Si3N4).

[0116] Figure 2B and Figure 2C , a stacked structure formed by stacking four stacked units is shown. However, in other exemplary embodiments, the device structure of the present application may also adopt a stacked structure formed by stacking more or fewer stacked units separated by sacrificial layers.

[0117] Figure 2B and Figure 2C , the stacked structure is shown to have a larger dimension in the first direction X than in the second direction Y, and the first direction X is perpendicular to the second direction Y (the same applies hereinafter). However, in other exemplary embodiments, the stacked structure may have a smaller dimension in the first direction X than in the second direction Y, and the first direction X may not be perpendicular to the second direction Y. For example, the angle between the first direction X and the second direction Y may be less than 90 degrees, such as within the range of 45-60 degrees or 60-85 degrees.

[0118] S200: forming word line through holes. Specifically, the steps may include depositing an insulating film on the stacked structure to form a hard mask layer 60; forming four word line through holes K penetrating the hard mask layer 60 and the stacked structure 1 by photolithography and etching. Figure 3A and Figure 3B shown; among them, Figure 3A A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S200) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C1 (through the first conductive layer 30); Figure 3B A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S200 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C2 .

[0119] Figure 3A The cross section of the word line through hole K on a plane parallel to the substrate is shown to be square with a side length W3. In other exemplary embodiments, the orthographic projection of the word line through hole K on a plane parallel to the substrate 10 may also be rectangular, circular, elliptical, or the like.

[0120] In an exemplary embodiment, the hard mask layer 60 is generally used in a patterning process and is removed after patterning. In an exemplary embodiment, the hard mask layer 60 may have a thickness of 50 nm.

[0121] S300: forming a word line structure. Specifically, the steps may include sequentially depositing a semiconductor film, an insulating film, and a conductive film around the inner wall of each word line through hole K formed in the above step to form a semiconductor layer 70, a gate insulating layer 80, and a word line 90, and then performing a chemical mechanical polishing (CMP) process to make the upper surface of the stacked structure flush. Figure 4A and 4B As shown. Among them, Figure 4A A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S300 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through the first conductive layer 30 ); Figure 4B A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S300 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C2 .

[0122] In an exemplary embodiment, the semiconductor layer 70 may be made of a metal oxide semiconductor material. In an exemplary embodiment, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the metal oxide semiconductor material has a slow corrosion rate in a weakly acidic or weakly alkaline solution. In an exemplary embodiment, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, or an oxide of Sn. These metal oxide materials, such as indium gallium zinc oxide (IGZO), may be used as a channel material. The side length of the semiconductor layer 70 may also be W3.

[0123] In an exemplary embodiment, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a 、Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Alx Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, it can be adjusted according to actual conditions.

[0124] In an exemplary embodiment, the gate insulating layer 80 may be a high-k dielectric layer, i.e., a dielectric layer with a K value of ≥ 3.9. The high-k dielectric layer may serve as a gate oxide. The gate insulating layer 80 may be made of one or more of silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0125] In an exemplary embodiment, the material of the word line 90 may be P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0126] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition method.

[0127] S400: Patterning the stacked structure. Specifically, the steps may include first transferring the preset pattern to a photoresist layer or a hard mask layer through a photolithography process using a mask having a preset pattern; then etching (e.g., anisotropic etching) each layer of the stacked structure based on the photoresist layer or the hard mask layer having the preset pattern to obtain each first conductive layer 30 having a preset pattern, wherein the preset pattern includes forming two conductive portions perpendicular to each other and having different widths in each first conductive layer 30, such as Figure 5 As shown. Among them, Figure 5 A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S400 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through the first conductive layer 30 ).

[0128] In the present application, the width of the conductive portion refers to the dimension of the conductive portion in a direction perpendicular to its own extending direction.

[0129] refer to Figure 5 , Figure 5It shows that a conductive portion in an approximate "grid" shape is formed in the first conductive layer 30, including two first conductive portions 31 and two second conductive portions 32. Each first conductive portion 31 extends along the first direction X and is parallelly spaced apart in the second direction Y. The portion that extends along the second direction Y and does not intersect with the first conductive portion 31 is called the second conductive portion 32. That is, the second conductive portion 32 is divided by two parallelly arranged first conductive portions 31 into a first portion and a third portion on both sides and a second portion in between. The first conductive portion 31 and the second conductive portion 32 are perpendicular to each other. Each word line via hole is located at the intersection of each first conductive portion 31 and each second conductive portion 32. At least one of the two parallel second conductive portions 32 is electrically connected to the first conductive portion 31.

[0130] Continue to refer to Figure 5 , the first conductive portion 31 has a width W1 in the direction perpendicular to its extending direction (i.e., the second direction Y), the second conductive portion 32 has a width W2 in the direction perpendicular to its extending direction (i.e., the first direction X), and the width W1 is greater than the width W2, and both the width W1 and the width W2 are greater than the side length (width) W3 of the word line via hole. That is, the orthographic projection of the word line via hole K on the plane parallel to the substrate 10 is located within the orthographic projection of the first conductive portion 31 on the plane parallel to the substrate 10 and is also located within the orthographic projection of the second conductive portion 32 on the plane parallel to the substrate 10.

[0131] Continue to refer to Figure 5 , the dimension of the first conductive portion 31 in its extending direction (i.e., the first direction X) can be greater than the dimension of the second conductive portion 32 in its extending direction (i.e., the second direction Y). Thus, the first direction X can be the extending direction of the first electrode of the capacitor to be prepared subsequently.

[0132] Continue to refer to Figure 5 , the spacing distance between the two second conductive portions 32 in the first direction X is greater than the spacing distance between the two first conductive portions 31 in the second direction Y. That is, when forming the second electrode of the capacitor subsequently, each first conductive portion 31 will be divided into two parts in the first direction X.

[0133] In an exemplary embodiment, Figure 5 the preset pattern shown is only an example. However, the preset pattern can also be other shapes. For example, the preset pattern can include forming two conductive portions that are perpendicular to each other and have different widths in each first conductive layer. However, the dimension of the first conductive portion 31 in its extending direction (i.e., the first direction X) can be less than the dimension of the second conductive portion 32 in its extending direction (i.e., the second direction Y). That is, the second direction Y can be the extending direction of the first electrode of the capacitor to be prepared subsequently.

[0134] In addition, through this patterning step, the second conductive layer 40 will also form the same tic-tac-toe preset pattern as the first conductive layer 30, that is, two conductive parts perpendicular to each other are formed in each second conductive layer 40 and the width of the first conductive part is greater than the width of the second conductive part.

[0135] S500: isotropically etching (wet etching) the stacked structure. Specifically, the steps may include etching the first conductive portion 31 and the second conductive portion 32 in the first conductive layer 30 until the second conductive portion 32 is substantially removed, leaving only the first conductive portion 31 extending along the first direction X and having a smaller width. Figure 6A and 6B As shown. Among them, Figure 6A A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S500) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along the C1 direction (through the first conductive layer 30), Figure 6B and Figure 6C for Figure 6A Schematic diagrams of other exemplary structures of the structure shown, Figure 6D A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S500 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C3 .

[0136] refer to Figure 6A As mentioned above, since the width W1 of the first conductive portion is greater than the width W2 of the second conductive portion, when the conductive portions are subsequently isotropically etched, the second conductive portion 32 extending along the second direction Y will be completely etched before the first conductive portion 31; etching is continued until the width W1 of the first conductive portion 31 is reduced but is still greater than the width W3 of the semiconductor layer 70, that is, the orthographic projection of the semiconductor layer 70 on the plane parallel to the substrate 10 falls within the orthographic projection of the first conductive portion 31 on the plane parallel to the substrate 10; at the same time, in the second direction Y, there is a spacing between the outer side of the first conductive portion 31 and the semiconductor layer 70, that is, the width W, and the width W can be in the range of 5-10nm.

[0137] In other exemplary embodiments, according to the designed width difference between the first conductive portion and the second conductive portion and the etching solution, the structure formed after etching can also be as follows: Figure 6B and 6C As shown, it is sufficient as long as the first conductive portion maintains contact and electrical connection on at least one side when extending and wrapping around the word line structure.

[0138] S600: removing the parasitic MOS between the transistors stacked in the third direction Z, that is, it is necessary to cut off the semiconductor layer between two adjacent transistors. The specific steps may include isotropically etching to remove the sacrificial layer 50, forming a sacrificial groove at the position of the sacrificial layer 50, and then continuing to isotropically etch to remove the semiconductor layer 70 with the help of the sacrificial groove, so that the semiconductor layer 70 vertically extending along the third direction Z is disconnected at the position of each sacrificial layer 50, that is, the gate insulating layer 80 is exposed at the position of each sacrificial layer 50. Figure 7A 、 7B And 7C. Among them, Figure 7A A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S600 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through the sacrificial layer 50 ); Figure 7B A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S600) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2; Figure 7C A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S600 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C3 .

[0139] S700: Deposit an insulating film, fill each sacrificial groove, and make the four sides of the stacked structure flush by CMP process, such as Figure 8A 、 8B And 8C. Among them, Figure 8A A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S700) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C1 (through a sacrificial layer filled with an insulating material); Figure 8B A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S700) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C2; Figure 8C A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S700 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C3 .

[0140] S800: Continue photolithography and etching the stacked structure to form a trench T penetrating the stacked structure and extending along the second direction Y, disconnecting the first conductive portion 31 and exposing a portion of the first electrode 200 for forming a capacitor, such as Figure 9A 、 9B And 9C. Among them, Figure 9AA schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S800) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C1 (through the first conductive layer 30); Figure 9B for Figure 9A Schematic diagrams of other exemplary structures of the illustrated structure; Figure 9C A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S800 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C2 .

[0141] Figure 9A The first electrode 200 of the capacitor extending along the first direction is shown to include a first portion, a second portion wrapping the semiconductor layer 70 , and a third portion extending beyond the semiconductor layer 70 and symmetrical to the first portion in the first direction.

[0142] Figure 9B The first electrode 200 of the capacitor extending along the first direction is shown to include a first portion and a second portion, wherein the second portion partially wraps around the semiconductor layer 70 , that is, the first electrode 200 does not extend beyond the semiconductor layer in the first direction X. In other exemplary embodiments, the second portion may also completely wrap around the semiconductor layer 70 .

[0143] S900: Forming a bit line. The specific steps may include etching the first conductive portion and the second conductive portion in the second conductive layer 40 from the outside of the stacked structure and using the formed trench T, that is, leaving the second conductive portion with a smaller width W2 extending along the second direction Y, and removing the first conductive portion with a wider width W1 extending along the first direction X in the second conductive layer 40, until the width W2 of the second conductive portion is reduced but still greater than the width W3 of the semiconductor layer 70, that is, the orthographic projection of the semiconductor layer 70 on a plane parallel to the substrate 10 falls within the orthographic projection of the second conductive portion on a plane parallel to the substrate 10; at the same time, in the first direction X, there is a spacing between the outer side of the second conductive portion and the semiconductor layer 70, that is, a width W, which can be in the range of 5-10 nm. In other words, the second conductive portion maintains contact and electrical connection on at least one side as it extends along the second direction Y and wraps around the word line structure. Therefore, forming the second conductive portion is forming the bit line 100 extending along the second direction Y, which is perpendicular to the first electrode of the capacitor extending along the first direction X. Finally, the filling insulating material is deposited to make the stacked structure flush, as shown in FIG. Figure 10A 、 10B And 10C. Among them, Figure 10AA schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S900 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C1 (through the first conductive layer 30 );

[0144] Figure 10B A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S900) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along the C2 direction (perpendicular to the substrate and longitudinally passing through the first conductive portion 31); Figure 10C A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S900 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C3 .

[0145] In this step, a bit line perpendicular to the first electrode is formed by removing the conductive portion extending in a direction different from that of the first electrode forming the capacitor.

[0146] S1000: forming the second electrode of the capacitor, specifically the steps may include depositing and filling a dielectric film along the third direction Z, so that in the stacked structure, the dielectric film covers the exposed surfaces of each first electrode 200 (forming a first dielectric layer), and at the same time covers the exposed surfaces of the first conductive portion of the second conductive layer 40 (i.e., covering the bit line) in the first direction X and covers the exposed surfaces of the insulating layer 20 between the conductive layers in the first direction X (forming a second dielectric layer), forming a total dielectric layer 210; then, depositing a conductive material film to completely cover the total dielectric film to form a second electrode 220; then, using a chemical mechanical polishing (CMP) process to make the outer surface of the stacked structure flush, as shown in FIG. Figure 11A and 11B As shown. Among them, Figure 11A A schematic cross-sectional view of an intermediate product obtained in an intermediate step (i.e., step S1000) of a method for manufacturing a 3D stacked semiconductor device provided in an exemplary embodiment of the present application, taken along direction C1 (through the first conductive layer 30); Figure 11B A schematic cross-sectional view of an intermediate product obtained in an intermediate step (ie, step S1000 ) of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application, taken along direction C2 .

[0147] In an exemplary embodiment, forming the second electrode may also include depositing a thin film of conductive material on the first dielectric layer to form the second electrode of each layer of capacitor; depositing a thin film of conductive material on the second dielectric layer to form an electrical connection area, and connecting the second electrodes of each layer of capacitor to each other through the electrical connection area to form a common electrode.

[0148] In an exemplary embodiment, the dielectric film and the conductive film may be deposited by atomic layer deposition.

[0149] In an exemplary embodiment, the dielectric layer 210 may be a high-k dielectric layer, ie, a dielectric layer with a dielectric constant K≥3.9. The dielectric layer 210 may be made of one of the following materials: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0150] In an exemplary embodiment, the conductive film may be made of a material including, but not limited to, at least one of the following: polysilicon, tungsten, and titanium nitride.

[0151] Figure 11A and 11B It is shown that the second electrodes of the capacitors of the memory cells of different layers and the second electrodes of the capacitors of the memory cells of the same layer are an integrated structure, and the integrated structure is filled between the first electrodes of different capacitors to become a common electrode.

[0152] The exemplary embodiment of the present application further provides a method for manufacturing a semiconductor device, the method comprising the following steps:

[0153] S3000: forming a stacked structure including at least two stacked units separated by a sacrificial layer, each stacked unit including a first conductive layer disposed between insulating layers and a second conductive layer disposed between the insulating layers;

[0154] S3100: forming a word line through hole penetrating the stacked structure to form a word line extending along a third direction and a semiconductor layer surrounding the word line;

[0155] S3200: Etching the stacked structure to form a first conductive portion and a second conductive portion intersecting each other in the first conductive layer and the second conductive layer, wherein the first conductive portion is wider than the second conductive portion, the first conductive portion extends along a first direction, and the second conductive portion extends along a second direction, and the first direction intersects the second direction and is located in a plane perpendicular to the third direction.

[0156] S3300: Etching the first conductive portion and the second conductive portion in the first conductive layer to form a first electrode of the capacitor extending along a first direction and at least partially surrounding the semiconductor layer;

[0157] S3400: removing the sacrificial layer to form a sacrificial groove and removing the semiconductor layer through the sacrificial groove;

[0158] S3500: Etching the first conductive portion and the second conductive portion in the second conductive layer to form a bit line extending along the second direction and at least partially surrounding the semiconductor layer, each first electrode and the bit line respectively surrounding different areas of the side wall of the semiconductor layer along the third direction, and the channel direction of the transistor is consistent with the extension direction of the word line.

[0159] In an exemplary embodiment, the step S3100 of forming a word line includes: sequentially depositing a semiconductor film, an insulating layer film, and a conductive film around the inner wall of the word line through hole to form a word line extending along the third direction, a semiconductor layer surrounding the word line along the third direction, and a gate insulating layer arranged between the word line and the semiconductor layer.

[0160] In an exemplary embodiment, the manufacturing method further comprises the following steps:

[0161] A groove is formed that penetrates the stacked structure and extends along the second direction, so that the first conductive parts in the first conductive layer and the second conductive layer are disconnected, exposing the first electrode of the capacitor of each storage unit; from the outside of the stacked structure and with the help of the formed groove, a dielectric film is deposited along the third direction to cover the exposed surfaces of the first electrode to form a first dielectric layer, and covers the surfaces of the first conductive parts in each second conductive layer exposed in the first direction and covers the surfaces of each insulating layer exposed in the first direction to form a second dielectric layer; a conductive material film is deposited on the first dielectric layer to form the second electrode of each layer of capacitor; a conductive material film is deposited on the second dielectric layer to form an electrical connection area, and the second electrodes of the capacitors in each layer are connected to each other through the electrical connection area to form a common electrode.

[0162] In an exemplary embodiment, the first conductive layer includes a different conductive material than the second conductive layer.

[0163] The exemplary embodiments of the present application further provide an electronic device including the semiconductor device described above. The semiconductor device may be a memory, such as a DRAM.

[0164] In an exemplary embodiment of the present application, the electronic device may include a DRAM memory, or a terminal device containing DRAM, such as a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0165] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A semiconductor device, characterized in that: The memory cell comprises a plurality of layers vertically stacked along a third direction, a word line extending along the third direction, and a bit line extending along a second direction and at least partially surrounding the word line; Multiple memory cells stacked vertically in multiple layers share one word line and are connected to different bit lines; The memory cell includes a transistor and a capacitor, the transistor includes a semiconductor layer, and the capacitor includes a first electrode; The semiconductor layer extends along the third direction and completely surrounds the word line; The first electrode extends along a first direction and at least partially surrounds the semiconductor layer, the first direction intersecting the second direction and both being in a plane perpendicular to the third direction; Each first electrode and the bit line respectively surrounds different areas of the sidewall of the semiconductor layer along the third direction; A channel direction of the transistor is consistent with an extending direction of the word line.

2. The semiconductor device according to claim 1, wherein Each of the transistors further includes a gate, which is a portion of the word line; a length of the gate is equal to a thickness of an insulating layer isolating the bit line from the first electrode.

3. The semiconductor device according to claim 1, wherein An extending direction of the bit line is perpendicular to an extending direction of the first electrode.

4. The semiconductor device according to claim 1, wherein The first source / drain of the transistor and the first electrode of the capacitor are an integrated structure, and the second source / drain of the transistor and the bit line are an integrated structure.

5. The semiconductor device according to claim 4, wherein The first source / drain of the transistor fully surrounds the semiconductor layer and is connected to the semiconductor layer, and the second source / drain of the transistor fully surrounds the semiconductor layer and is connected to the semiconductor layer. The semiconductor device according to claim 1 , wherein: An intersection angle between the first direction and the second direction is in the range of 45 degrees to 90 degrees.

7. The semiconductor device according to claim 1, wherein The first electrode of the capacitor includes a first portion and a second portion, the second portion at least partially wrapping the semiconductor layer.

8. The semiconductor device according to claim 1, wherein The first electrode of the capacitor includes a first portion, a second portion wrapping the semiconductor layer, and a third portion extending beyond the semiconductor layer and symmetrical to the first portion in the second direction.

9. The semiconductor device according to claim 1, wherein In the extending direction of the word line, the semiconductor layers corresponding to different memory cells are disconnected.

10. The semiconductor device according to claim 1, wherein The first electrodes of the capacitors of the memory cells in the same layer are disconnected from each other.

11. The semiconductor device according to claim 1, wherein The first electrode of the capacitor includes a different conductive material than the bit line.

12. The semiconductor device according to claim 1, wherein The second electrodes of the capacitors of the memory cells of different layers and the second electrodes of the capacitors of the memory cells of the same layer are an integrated structure, and the integrated structure is filled between the first electrodes of different capacitors to become a common electrode.

13. A method for manufacturing a semiconductor device, characterized in that: The steps include: forming a stacked structure including at least two stacked units separated by a sacrificial layer, each stacked unit including a first conductive layer disposed between insulating layers and a second conductive layer disposed between the insulating layers; forming a word line through hole penetrating the stacked structure to form a word line extending along a third direction and a semiconductor layer surrounding the word line; Etching the stacked structure to form a first conductive portion and a second conductive portion intersecting each other in the first conductive layer and the second conductive layer, wherein the first conductive portion is wider than the second conductive portion, the first conductive portion extends along a first direction, and the second conductive portion extends along a second direction, wherein the first direction intersects the second direction and both lie in a plane perpendicular to the third direction; Etching the first conductive portion and the second conductive portion in the first conductive layer to form a first electrode of the capacitor extending along a first direction and at least partially surrounding the semiconductor layer; removing the sacrificial layer to form a sacrificial groove and removing the semiconductor layer via the sacrificial groove; Etching the first conductive portion and the second conductive portion in the second conductive layer to form a bit line extending along the second direction and at least partially surrounding the semiconductor layer; Each first electrode and the bit line respectively surrounds different areas of the sidewall of the semiconductor layer along the third direction; A channel direction of a transistor including the semiconductor layer is consistent with an extending direction of the word line.

14. The manufacturing method according to claim 13, characterized in that: Forming a word line includes sequentially depositing a semiconductor film, an insulating layer film, and a conductive film around the inner wall of the word line through hole to form a word line extending along the third direction, a semiconductor layer surrounding the word line along the third direction, and a gate insulating layer arranged between the word line and the semiconductor layer.

15. The manufacturing method according to claim 13, characterized in that: The following steps are also included: forming a trench penetrating the stacked structure and extending along the second direction, disconnecting each of the first conductive portions in the first conductive layer and the second conductive layer, and exposing the first electrode of the capacitor of each memory cell; From the outside of the stacked structure and with the help of the formed grooves, a dielectric film is deposited along the third direction to cover the exposed surfaces of the first electrode to form a first dielectric layer, and covers the surfaces of the first conductive parts in each second conductive layer exposed in the first direction and covers the surfaces of each insulating layer exposed in the first direction to form a second dielectric layer; a conductive material film is deposited on the first dielectric layer to form the second electrode of each layer of capacitor; a conductive material film is deposited on the second dielectric layer to form an electrical connection area, and the second electrodes of each layer of capacitor are interconnected through the electrical connection area to form a common electrode.

16. The manufacturing method according to claim 13, characterized in that: The first conductive layer includes a different conductive material than the second conductive layer.

17. An electronic device, characterized in that: The semiconductor device comprises the semiconductor device according to any one of claims 1 to 12.

18. The electronic device according to claim 17, wherein: The electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

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