An Inverter Program Online Upgrade Architecture and Method

Abstract

The present application discloses an online inverter program upgrade architecture and method; the architecture includes a host computer, a controller, and a latch unit; the host computer is communicatively connected to the controller, the controller is communicatively connected to the latch unit, and the latch unit is adapted to latch the high level of the controller at the previous moment during the upgrade of the controller, so that the relay group continues to perform the enabling control of the high level. The method uses the above architecture to control the online upgrade of the inverter program. The beneficial effects of the present application: The present application can achieve uninterrupted load power supply during the program upgrade through a single controller, with low cost and high power density. In addition, the present application can also be applied to the scenario of multi-controller models, and can achieve uninterrupted load power supply when multiple controllers are upgraded simultaneously, with high power supply reliability.

Description

Technical Field

[0001] The present application relates to the technical field of new energy power generation, and particularly to an online upgrade architecture and method for an inverter program. Background Art

[0002] The existing software upgrade scheme for a photovoltaic energy storage inverter is as Figure 1 shown. An MCU controller 420 (such as a DSP) controls each converter (including a DC / DC unit 120, a bidirectional DC / DC unit 140, a DC / AC unit 150, a relay group 160, etc.). During the upgrade process, generally, a host computer 410 sends an upgrade instruction to the MCU controller 420. However, during the program upgrade, due to the reset of the MCU controller 420, the relay control signal relay_ctrl will be pulled to a low level, and then the relay will disconnect, and the load 300 will experience a power outage.

[0003] In order to maintain uninterrupted power supply to the load during the program upgrade process, there are the following two existing schemes: One scheme is to add a bypass relay between the power grid and the load and add a control bit for the bypass relay in the bootloader, thereby greatly reducing the power supply interruption time; Another scheme is to perform redundant control of the relay through multiple MCUs. When one MCU is being upgraded, another MCU maintains the relay control.

[0004] However, the existing schemes have the following defects when in use: For the above-mentioned bypass relay scheme, since an additional relay needs to be added, it will increase the additional cost and reduce the power density. In addition, there may still be a power supply interruption to the load between the MCU reset and the execution of the program bootloader. For the scheme of performing redundant control of the relay through multiple MCUs, compared with the scheme with only one MCU, it will increase the additional cost; and for a machine with multiple MCUs, in scenarios where multiple MCUs need to be upgraded simultaneously, etc., the relay will still disconnect, and it is impossible to maintain continuous power supply to the load. Summary of the Invention

[0005] One object of the present application is to provide an architecture for implementing an online upgrade method for an inverter program, which can solve at least one of the defects in the above-mentioned background art.

[0006] To achieve the above object, the technical solution adopted in this application is as follows: An online upgrade architecture for an inverter program, including a host computer, a controller, and a latch unit; the host computer is adapted to issue an upgrade instruction, the input side of the controller is communicatively connected to the host computer, and the controller is adapted to control a relay group; the output side of the controller is communicatively connected to the latch unit; the controller is communicatively connected to the latch unit, and the latch unit is used to output the relay control signal of the controller; the latch unit is adapted to latch the relay control signal of high level at the previous moment when the controller is upgraded, and then continue to perform high-level enabling control on the relay group.

[0007] Preferably, the latch unit adopts a D latch; the controller is adapted to respectively output a relay control signal and a clock signal to the D port and the EN port of the latch unit; when the controller is working normally, both the relay control signal and the clock signal are at high level; when the controller is upgraded, the clock signal is at low level, and then the latch unit maintains a high-level output.

[0008] Preferably, the online upgrade architecture for the inverter program further includes a delay circuit, and the clock signal output by the controller is sent to the EN port of the latch unit after being delayed by a set time through the delay circuit.

[0009] Preferably, the delay circuit includes a second AND gate unit. One of the input terminals of the second AND gate unit is used to receive the clock signal issued by the controller, the remaining input terminals of the second AND gate unit are all set to high level, and the output terminal of the second AND gate unit is communicatively connected to the EN port of the latch unit.

[0010] Preferably, the online upgrade architecture for the inverter program further includes a software protection circuit with a software protection function. The software protection circuit includes a third AND gate unit. The input terminal of the third AND gate unit is communicatively connected to the controller, and the output terminal of the third AND gate unit is communicatively connected to the D port of the latch unit; the controller respectively sends the relay control signal and the software protection signal to the input terminal of the third AND gate unit.

[0011] Preferably, the online upgrade architecture for the inverter program further includes a first AND gate unit and a protection unit; both the protection unit and the latch unit are respectively connected to the input terminal of the first AND gate unit, and the output terminal of the first AND gate unit is connected to control the relay group; the first AND gate unit is adapted to send a relay drive signal to the relay group according to the relay control signal output by the latch unit and the high-level blocking signal output by the protection unit.

[0012] Preferably, there are multiple controllers, one of which participates in the control of the relay group, and the rest do not participate in the control of the relay group; the controller participating in the control of the relay group is connected to the latch unit, and the rest of the controllers are communicatively connected to the controller connected to the latch unit or the host computer.

[0013] Preferably, there are multiple controllers and multiple latch units. The controllers are connected to the corresponding latch units to form control branches; the controllers serving as the input ends of the respective control branches are communicatively connected to each other or are all communicatively connected to the host computer; the latch units serving as the output ends of the respective control branches are all connected to the input end of the first AND gate unit.

[0014] An inverter program online upgrade method using the above inverter program online upgrade architecture includes the following steps: the host computer sends a program upgrade preparation instruction to the controller; after receiving the instruction, the controller controls the current working mode of the inverter so that the inverter can work in the grid-connected mode and execute the relay maintenance control mode; after the inverter completes the switching of the relay maintenance mode, the controller feeds back to the host computer that the program upgrade preparation is completed; after receiving the preparation completed information, the host computer sends an upgrade package to the controller to enter the program upgrade mode; after the control upgrade is completed, a high level is sent to the latch unit to work normally.

[0015] Preferably, the control of the working mode of the inverter includes the following process: judging the current working mode of the inverter; if the inverter is in the grid-connected mode, the inverter directly executes the relay maintenance control mode; if the inverter is in the off-grid mode, further judge whether the inverter meets the grid-connected requirements; for the inverter that meets the grid-connected requirements, switch to the grid-connected mode and then execute the relay maintenance control mode, and for the inverter that does not meet the grid-connected requirements, keep the off-grid mode; wherein, the relay maintenance control mode is that the relay maintains the previous state, and the control instruction of the controller at the next moment no longer affects the opening and closing of the relay.

[0016] Compared with the prior art, the beneficial effects of the present application are as follows:

[0017] The present application can realize uninterrupted load power supply during the program upgrade process through a single controller, with low cost and high power density. In addition, the present application can also be applied to the scenario of multi-controller models, and can realize uninterrupted load power supply when multiple controllers are upgraded simultaneously, with high power supply reliability. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of an existing inverter program online upgrade architecture.

[0019] Figure 2 It is a schematic structural diagram of the online upgrade architecture of the inverter program of this application.

[0020] Figure 3 It is the truth table when the latch unit in this application uses a D latch.

[0021] Figure 4 It is the timing diagram when the inverter in this application is performing program upgrade.

[0022] Figure 5 It is the timing diagram when the controller in this application completes the program upgrade and performs power-on reset.

[0023] Figure 6 It is the relay on-off timing diagram during the normal operation of the inverter in this application.

[0024] Figure 7 It is a schematic structural diagram of the online upgrade architecture of the inverter program with software protection function in this application.

[0025] Figure 8 It is a schematic structural diagram of Example 1 of the online upgrade architecture of the inverter program for the multi-controller scenario in this application.

[0026] Figure 9 It is a schematic structural diagram of Example 2 of the online upgrade architecture of the inverter program for the multi-controller scenario in this application.

[0027] Figure 10 It is a schematic structural diagram of Example 3 of the online upgrade architecture of the inverter program for the multi-controller scenario in this application.

[0028] Figure 11 It is a schematic diagram of the overall working process of the online upgrade method of the inverter program in this application.

[0029] In the figure: PV unit 110, DC / DC unit 120, energy storage unit 130, bidirectional DC / DC unit 140, DC / AC unit 150, relay group 160, power grid 200, load 300, host computer 410, controller 420, reset pull-down device 430, protection unit 440, first AND gate unit 450, delay circuit 460, latch unit 470, third AND gate unit 480. Detailed implementation manners

[0030] Next, in combination with the detailed implementation manners, this application will be further described. It should be noted that on the premise of no conflict, the following described embodiments or technical features can be combined arbitrarily to form new embodiments.

[0031] In the description of the present application, it should be noted that for orientation terms, such as the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., which indicate the orientation and positional relationship are based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of the present application.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0033] The terms "comprising" and "having" in the description and claims of the present application, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0034] For the convenience of understanding the following solution, the structure of a traditional inverter system can be briefly described first. The inverter system may include a power generation system, an energy storage system, a UPS system, etc.; that is, the technical solution of the present application can be implemented in a pre-power generation system, an energy storage system, a UPS system, etc.

[0035] For the convenience of understanding, the present application will be described through a photovoltaic energy storage system. As Figure 1 shown, a traditional photovoltaic energy storage system mainly includes a PV unit 110, an energy storage unit 130, a DC / DC unit 120, a bidirectional DC / DC unit 140, and a DC / AC unit 150. The PV unit 110 and the energy storage unit 130 are respectively connected to the corresponding DC / DC unit 120 and the bidirectional DC / DC unit 140 and then connected in parallel to the input side bus of the DC / AC unit 150. The output end of the DC / AC unit 150 is connected to the power grid 200 through a control switch. At the same time, the load 300 is also connected in parallel to the output side of the DC / AC unit 150 through a control switch.

[0036] In this field, a relay is a commonly used control switch. Thus, the relays installed on the positive and negative busbars between the power grid 200 and the DC / AC unit 150, and the relays installed on the positive and negative busbars between the load 300 and the DC / AC unit 150 can respectively form corresponding relay groups 160. When the inverter system is connected to the grid, the inverter system can supply power to the load 300 by closing the relay group 160. When the inverter system is off-grid, if the load 300 wants to continue working, the power grid 200 can supply power to the load 300 by continuously closing the relay group 160.

[0037] One aspect of the present application provides an online upgrade architecture for an inverter program, as Figure 2 shown. A preferred embodiment thereof includes a host computer 410, a controller 420, and a latching unit 470. The input sides of the host computer 410 and the controller 420 are communicatively connected, and the host computer 410 can send an upgrade instruction to the controller 420. The output end of the controller 420 can output a relay control signal for controlling the relay group 160. The controller 420 can be communicatively connected to the input side of the latching unit 470 so that the relay control signal output by the controller 420 is output through the latching unit 470.

[0038] When the controller 420 is operating normally, the controller 420 can send a high-level relay control signal to the latching unit 470, and then the latching unit 470 also outputs a corresponding high-level signal to the relay group 160, thereby controlling the relay group 160 to enter a closed high-level enabled state to ensure the grid-connected operation of the inverter system.

[0039] When the controller 420 needs to be upgraded, at this time, the control signal output by the controller 420 is low level, but the latching unit 470 can latch the high-level signal of the controller 420 at the moment before the upgrade according to the low-level signal output by the controller 420. Then, the latching unit 470 can continue to send a high-level enable signal to the relay group 160 during the upgrade of the controller 420, so that the relay group 160 remains in a closed state to ensure that the load 300 can continue to work normally through the power supply of the power grid 200. Compared with the traditional method, the present application can achieve uninterrupted power supply to the load 300 during the program upgrade process through a single controller 420, with lower cost and higher power density.

[0040] It should be noted that the controller 420 is a commonly used MCU controller in the art. The specific structure and working principle are well-known technologies to those skilled in the art, so they will not be elaborated in detail here. Common MCU controllers include DSP, etc. The upgrade instruction of the controller 420 can be implemented through the host computer 410, that is, the host computer 410 is communicatively connected to the controller 420 through a signal line. Common signal lines include boot, reset, and communication buses such as SCI. When the controller 420 is working normally, the host computer 410 can send high-level signals to the controller 420 through the signal lines boot and reset, so that the controller 420 can output the corresponding relay control signal relay_ctrl to the latch unit 470. The specific structure and working principle of the host computer 410 are also well-known technologies to those skilled in the art. Common host computers 410 include ARM, etc.

[0041] In this embodiment, to ensure the safety of the online architecture for inverter program upgrade, as Figure 2 shown, the online architecture for inverter program upgrade further includes a first AND gate unit 450 and a protection unit 440. The output side of the latch unit 470 is communicatively connected to the input end of the first AND gate unit 450, and the protection unit 440 is connected to the other input end of the first AND gate unit 450. The output end of the first AND gate unit 450 is control-connected to the relay group 160. The protection unit 440 can continuously send a high-level blocking signal relay_block to the first AND gate unit 450. The latch unit 470 can send the relay control signal sent by the controller 420 to the first AND gate unit 450. Furthermore, the first AND gate unit 450 can perform corresponding enabling control on the relay group 160 according to the change of the output level of the latch unit 470.

[0042] It should be noted that the specific structure and working principle of the first AND gate unit 450 are well-known technologies to those skilled in the art, so they will not be elaborated in detail here. The working logic of the AND gate unit is to output a high level only when all input ends are high levels. The protection unit 440 can be hardware protection or software protection. In this embodiment, hardware protection is preferably adopted. The specific structure and working principle of the protection unit 440 are well-known technologies to those skilled in the art, so they will not be elaborated in detail here.

[0043] In this embodiment, there are various specific structures of the latch unit 470 that can latch the output signal of the controller 420. For the convenience of understanding, one of the structures will be described in detail below. As Figure 2As shown, the latch unit 470 uses a D latch. The output side of the controller 420 can be communicatively connected to the D port and the EN port of the latch unit 470 respectively; thus, the controller 420 can output the relay control signal relay_ctrl and the clock signal clk to the D port and the EN port of the latch unit 470 respectively. The latch unit 470 can be connected to the input end of the first AND gate unit 450 through the Q port, and thus the latch unit 470 can send the relay control signal relay_ctrl' to the input end of the first AND gate unit 450 through the Q port. It should be noted that the relay control signal here is a representation of a group of signals, and actually can be control signals for multiple different relays.

[0044] When the controller 420 is working normally, both the relay control signal relay_ctrl and the clock signal clk sent by the controller 420 are high levels. Then, according to the working logic of the D latch, the relay control signal relay_ctrl' output by the latch unit 470 is a high level. The high-level relay control signal relay_ctrl' and the high-level blocking signal relay_block sent by the protection unit 440 can output a high-level relay drive signal relay_drv through the first AND gate unit 450 to drive the relay group 160 to close. The circuit for specifically driving the relay group 160 is the same as the conventional scheme, so it will not be described in detail here.

[0045] After the host computer 410 sends an upgrade instruction to the controller 420, the controller 420 can enter the upgrade mode. At this time, both the relay control signal relay_ctrl and the clock signal clk sent by the controller 420 are low levels. Then, according to the working logic of the D latch, the latch unit 470 will latch and maintain the high-level relay control signal relay_ctrl output by the controller 420 at the previous moment. Thus, the latch unit 470 can continue to output a high-level relay control signal relay_ctrl'; then, the high-level relay control signal relay_ctrl' and the high-level blocking signal relay_block sent by the protection unit 440 can continue to output a high-level relay drive signal relay_drv through the first AND gate unit 450 to drive the relay group 160 to continue to remain closed to achieve the continuous power-on operation of the load 300.

[0046] It should be noted that after the controller 420 enters the upgrade state, the relay control signal relay_ctrl and the clock signal clk can be pulled down to a low level by the reset pull-down device 430. The specific structure and working principle of the reset pull-down device 430 are well-known technologies to those skilled in the art, so they will not be elaborated in detail here. After the controller 420 completes the upgrade, it can be reset. At this time, the relay control signal relay_ctrl and the clock signal clk can be powered up to a high level again, enabling the controller 420 to resume control of the relay group 160. At this time, the latch unit 470 can be released from the latched state.

[0047] Meanwhile, the specific structure and working principle of the D latch are well-known technologies to those skilled in the art, so they will not be elaborated in detail here; for the convenience of understanding, the truth table of the D latch is as Figure 3 shown. When the EN port is at a high level and the D port is at a low level, the Q port will output a low level; when both the EN port and the D port are at a high level, the Q port will output a high level; when the EN port is at a low level, the Q port will maintain the level state of the previous moment.

[0048] It can be understood that due to possible time errors in the communication of the ports, when the controller 420 is reset by pulling up the level after the upgrade is completed, it is necessary to ensure that the relay control signal relay_ctrl is set to a high level simultaneously or prior to the clock signal clk, so as to ensure that the relay control signal relay_ctrl' output by the D latch remains at a high level continuously. Therefore, in this embodiment, it is preferable to perform a delay process on the clock signal clk; one specific example is as Figure 2 shown. The online upgrade architecture of the inverter program further includes a delay circuit 460. The clock signal clk output by the controller 420 can be sent to the EN port of the latch unit 470 after being delayed by the delay circuit 460 for a set time. For the convenience of understanding, the specific structure of the delay circuit 460 will be described in detail below.

[0049] Specifically, as Figure 2 shown, the delay circuit 460 includes a second AND gate unit, a resistor, and a capacitor. One input terminal of the second AND gate unit is connected to the output side of the controller 420 through a resistor, and a capacitor grounded is connected between the resistor and the second AND gate unit. The remaining input terminals of the second AND gate unit are all set to a high level "1", and the output terminal of the second AND gate unit is communicatively connected to the EN port of the latch unit 470. Thus, the clock signal clk sent by the controller 420 can output a delayed clock signal clk' to the EN port of the latch unit 470 after passing through the delay circuit 460.

[0050] It can be understood that the entire upgrade process of the controller 420 can be divided into an upgrade preparation stage, an upgrade process stage, and an upgrade completion stage. For the convenience of understanding, the entire upgrade process of the controller 420 will be described in detail below.

[0051] I. Upgrade preparation stage.

[0052] As Figure 4 shown, the host computer 410 sends an upgrade preparation instruction to the controller 420 through communication. After receiving the program upgrade preparation instruction, the controller 420 immediately sets the clock signal clk to a low level. After passing through the delay circuit 460, the clock signal clk can be delayed by Δt time to output the clock signal clk'. Due to the falling level of the clock signal clk', the latch unit 470 triggers the latch mode, causing the latch unit 470 to latch the current high-level relay control signal relay_ctrl. After the controller 420 completes the preparation, the controller 420 can feedback the preparation completion information to the host computer 410 and start entering the upgrade process stage. It should be known that Figure 4 part a in it represents the upgrade preparation instruction sent by the host computer 410 to the controller 420, and part c represents the preparation completion information feedback by the controller 420 to the host computer 410.

[0053] II. Upgrade process stage.

[0054] As Figure 4 shown, after the host computer 410 receives the preparation completion information feedback by the controller 420, the host computer 410 can make the controller 420 enter the upgrade state by setting the outputs of the signal lines boot and reset to a low level. Specifically, the signal line boot outputs a low level about 10 ms earlier than the signal line reset. At this time, due to the pull-down of the output level of the controller 420 by the reset pull-down device 430, the relay control signal relay_ctrl and the clock signal clk are pulled down to a low level. Then, after the clock signal clk passes through the delay circuit 460, the output clock signal clk' is still at a low level. At this time, the latch unit 470 maintains the latch state in the upgrade preparation stage, that is, the relay control signal relay_ctrl' output by the latch unit 470 remains at a high level. After the controller 420 enters the upgrade state and the reset ends (at this time the signal line reset returns to a high level again), the host computer 410 can send the upgrade program package to the controller 420 through communication and perform the upgrade. It should be known that Figure 4 part b in it represents the process of the host computer 410 sending the upgrade program package to the controller 420.

[0055] III. Upgrade completion stage.

[0056] As Figure 4As shown, after the upgrade package is sent and completed, that is, after the controller 420 is upgraded, the controller 420 starts to execute the user program. At this time, both the relay control signal relay_ctrl and the clock signal clk output by the controller 420 can be reset to a high level. It should be noted that due to the existence of the delay circuit 460, the relay control signal relay_ctrl can be set to a high level prior to or simultaneously with the clock signal clk, but it is not allowed for the clock signal clk to be set to a high level first. After the clock signal clk is set to a high level, the clock signal clk' output by the delay circuit 460 turns to a high level. At this time, the latch unit 470 can release the latched state, and the relay control signal relay_ctrl' output by the latch unit 470 is the current high-level relay control signal relay_ctrl, thereby ensuring that the relay group 160 continues to maintain the closed working state to continue to maintain the power-on operation of the load 300.

[0057] It should be known that the above working process is the working process of the controller 420 in the upgrade state. When the program of the controller 420 is upgraded and reset, the control of the relay group 160 needs to be maintained. The controller 420 also includes working scenarios in the non-upgrade state, such as the power-on reset scenario of the controller 420 and the normal on / off control scenario of the relay group 160. For the convenience of understanding, the control of the relay group 160 in the non-upgrade state scenario of the controller 420 will be described in detail below.

[0058] For the power-on reset scenario of the controller 420, the controller 420 does not need to maintain the control of the relay group 160. The specific control process of the controller 420 for the relay group 160 is as follows Figure 5 As shown, when the controller 420 performs a power-on reset, the initial states of both the relay control signal relay_ctrl and the clock signal clk output by it are low levels. Then the clock signal clk' output by the delay circuit 460 is also at a low level, and the relay control signal relay_ctrl' output by the latch unit 470 is also at a low level. Until the power-on reset of the controller 420 ends, the relay control signal relay_ctrl and the clock signal clk will be set to high levels. Then, after passing through the delay circuit 460, the clock signal clk' turns to a high level, and the relay control signal relay_ctrl' output by the latch unit 470 is the level signal of the current relay control signal relay_ctrl, that is, a high level. Then the relay group 160 is closed from the off state under the drive of the high-level relay drive signal relay_drv output by the first AND gate unit 450.

[0059] For the normal on / off control scenario of the relay group 160, the specific control process of the controller 420 is as follows Figure 6As shown, during the entire control process, the clock signal clk output remains at a high level, so the clock signal clk' output by the delay circuit 460 will also remain at a high level. At this time, the latch unit 470 is in a transparent state, making the relay control signal relay_ctrl' output by the latch unit 470 always maintain the same level as the relay control signal relay_ctrl. At this time, the relay drive signal relay_drv output by the first AND gate unit 450 is completely determined by the relay control signal relay_ctrl and the blocking signal relay_block, achieving the same effect as the conventional relay control scheme.

[0060] In this embodiment, the working scenarios of the controller 420 include not only the working scenarios of a single controller 420 but also the working scenarios of multiple controllers 420; one specific example is as Figures 8 to 10 shown, the number of controllers 420 is two. One controller 420 is used to control the DC / DC unit 120 and the bidirectional DC / DC unit 140, and the other controller 420 controls the DC / AC unit 150, but it is not limited to such a layout. Moreover, in the working scenario of multiple controllers 420, there are also various situations for the control modes of multiple controllers 420 over the relay group 160; for example, only one of the multiple controllers 420 participates in the control of the relay group 160, and the remaining controllers 420 do not participate in the control of the relay group 160; also, for example, multiple controllers 420 participate in the control of the relay group 160 simultaneously. For the convenience of understanding, three specific examples will be used for detailed description below.

[0061] Example 1: As Figure 8 shown, there are multiple controllers 420, and one of the controllers 420 participates in the control of the relay group 160, while the remaining controllers 420 do not participate in the control of the relay group 160. The controller 420 participating in the control of the relay group 160 is connected to the latch unit 470, and the remaining controllers 420 are communicatively connected to the controller 420 connected to the latch unit 470 or the host computer 410.

[0062] For ease of understanding, the working process of Example 1 will be described in detail below taking two controllers 420 as an example. The two controllers 420 can be respectively defined as controller DSP#1 and controller DSP#2. Among them, controller DSP#1 is used to control the DC / DC unit 120, the bidirectional DC / DC unit 140, and the relay group 160, and controller DSP#2 only controls the DC / AC unit 150 and does not participate in the control of the relay group 160. The host computer 410 communicates with controller DSP#1, and controller DSP#1 communicates with controller DSP#2, such as I2C communication. Controller DSP#1 can control controller DSP#2 to be upgraded through signal lines boot2 and reset2. Of course, controller DSP#2 can also directly communicate with the host computer 410 through signal lines boot2 and reset2, enabling the host computer 410 to directly control controller DSP#2 to be upgraded. In this scenario, controller DSP#1 controls the relay group 160 through the hardware architecture described above, and controller DSP#2 does not participate in relay control.

[0063] Example 2: As Figure 9 shown, there are multiple controllers 420 and latch units 470. The controller 420 is connected to the corresponding latch unit 470 to form a control branch. The controllers 420 serving as the input ends of each control branch communicate with each other, and one of the controllers 420 communicates with the host computer 410. The latch units 470 serving as the output ends of each control branch are all connected to the input end of the first AND gate unit 450. Furthermore, the control of the relay group 160 will be jointly determined by multiple controllers 420.

[0064] For ease of understanding, the working process of Example 2 will be described in detail below taking two controllers 420 as an example. The two controllers 420 can be respectively defined as controller DSP#1 and controller DSP#2. Among them, controller DSP#1 controls the DC / DC unit 120 and the bidirectional DC / DC unit 140, and controller DSP#2 controls the DC / AC unit 150. The relay group 160 is jointly controlled by controller DSP#1 and controller DSP#2.

[0065] At the same time, the host computer 410 communicates with controller DSP#1, and controller DSP#1 communicates with controller DSP#2, such as I2C communication. And controller DSP#1 can perform upgrade control on controller DSP#2 through signal lines boot2 and reset2. It should be noted that in this scenario, the signal lines boot2 and reset2 need to be subjected to reset pull-up processing to prevent controller DSP#2 from being reset due to the upgrade of controller DSP#1.

[0066] Under this architecture, the controller DSP#1 outputs a relay control signal relay_ctrl_1 and a clock signal clk_1. After being processed by the corresponding latch unit 470 and delay circuit 460, the corresponding relay control signal relay_ctrl_1' can be obtained. At the same time, the controller DSP#2 outputs a relay control signal relay_ctrl_2 and a clock signal clk_2. After being processed by the corresponding latch unit 470 and delay circuit 460, the corresponding relay control signal relay_ctrl_2' can be obtained. The relay control signal relay_ctrl_1', the relay control signal relay_ctrl_2', and the blocking signal relay_block output by the protection unit 440 jointly pass through the first AND gate unit 450 to obtain the required relay drive signal relay_drv, thereby realizing the control of the relay group 160. It is worth mentioning that the relationship between the relay control signal relay_ctrl_1' and the relay control signal relay_ctrl_2' can be not only a logical AND relationship, but also other logical relationships, which can be selected according to actual application requirements.

[0067] It can be understood that under this architecture, if the controller DSP#1 is upgraded, its upgrade process is the same as that of the aforementioned single controller 420, so it will not be repeated here. If the controller DSP#2 is upgraded, the controller DSP#1 will be equivalent to the host computer 410, enabling the controller DSP#2 to execute the same upgrade process as the aforementioned single controller 420. It should be noted that simultaneous upgrade of multiple controllers 420 cannot be achieved under this architecture.

[0068] Example 3: As Figure 10 shown, there are multiple controllers 420 and latch units 470. The controller 420 is connected to the corresponding latch unit 470 to form a control branch. The controller 420 serving as the input end of each control branch is communicatively connected to the host computer 410; the latch unit 470 serving as the output end of each control branch is connected to the input end of the first AND gate unit 450; furthermore, the control of the relay group 160 will be jointly determined by multiple controllers 420.

[0069] For ease of understanding, the working process of Example 2 will be described in detail below using two controllers 420 as an example. The two controllers 420 can be respectively defined as controller DSP#1 and controller DSP#2; among them, controller DSP#1 controls the DC / DC unit 120 and the bidirectional DC / DC unit 140, and controller DSP#2 controls the DC / AC unit 150; the relay group 160 is jointly controlled by controller DSP#1 and DSP#2. At the same time, the host computer 410 communicates separately with controller DSP#1 and controller DSP#2, such as I2C communication; the host computer 410 can perform upgrade control on controller DSP#1 through signal lines boot1 and reset1, and the host computer 410 can perform upgrade control on controller DSP#2 through signal lines boot2 and reset2.

[0070] Under this architecture, controller DSP#1 outputs the relay control signal relay_ctrl_1 and the clock signal clk_1. After being processed by the corresponding latch unit 470 and delay circuit 460, the corresponding relay control signal relay_ctrl_1′ can be obtained. At the same time, controller DSP#2 outputs the relay control signal relay_ctrl_2 and the clock signal clk_2. After being processed by the corresponding latch unit 470 and delay circuit 460, the corresponding relay control signal relay_ctrl_2′ can be obtained. The relay control signal relay_ctrl_1′, the relay control signal relay_ctrl_2′ and the blocking signal relay_block output by the protection unit 440 jointly pass through the first AND gate unit 450 to obtain the required relay drive signal relay_drv, thereby realizing the control of the relay group 160. It is worth mentioning that the relationship between the relay control signal relay_ctrl_1′ and the relay control signal relay_ctrl_2′ can be not only a logical AND relationship, but also other logical relationships, which can be selected according to actual application requirements.

[0071] It can be understood that the program upgrades of controller DSP#1 and controller DSP#2 under this architecture are independent of each other, so they can be upgraded simultaneously; the specific upgrade processes of controller DSP#1 and controller DSP#2 are the same as those of the single controller 420 described above, so they will not be repeated here.

[0072] It should be known that many controllers 420 need to have the function of software protection. Therefore, a software protection circuit with software protection function needs to be set in the inverter program online upgrade architecture of this embodiment. For ease of understanding, the following will use Figure 2 the scenario of the single controller 420 shown for detailed description.

[0073] Specifically, as Figure 7 shown, the software protection circuit includes a third AND gate unit 480. The input end of the third AND gate unit 480 is communicatively connected to the controller 420, so that the controller 420 can send a software protection signal relay_block_s and a relay control signal relay_ctrl to the input end of the third AND gate unit 480. The output end of the third AND gate unit 480 is communicatively connected to the D port of the latch unit 470, so that the operating state of the latch unit 470 will be affected by the level signal of the software protection signal relay_block_s, thereby realizing the software protection function of the circuit. For the scenario of multiple controllers 420, only the corresponding software protection circuit needs to be added to the corresponding control branch.

[0074] Another aspect of the present application provides an inverter program online upgrade method using the above inverter program online upgrade architecture, as Figure 11 shown. One preferred embodiment includes a preparation stage, an upgrade stage, and an upgrade completion stage of the program upgrade; specifically, the following processes are included:

[0075] (1) Upgrade preparation stage: When online upgrade of the program is required, the host computer 410 can send a program upgrade preparation instruction to the controller 420; after receiving the instruction, the controller 420 controls the current working mode of the inverter.

[0076] If the inverter is in the grid-connected mode, the inverter will execute the relay maintenance control mode through the above inverter program online upgrade architecture. If the inverter is in the off-grid mode, it is further determined whether the inverter meets the grid connection requirements; for the inverter that meets the grid connection requirements, after switching to the grid-connected mode, the relay maintenance control mode is executed through the foregoing inverter program online upgrade architecture; for the inverter that does not meet the grid connection requirements, the off-grid mode is maintained.

[0077] It should be noted that the relay maintenance control mode is that the relay maintains the previous state, and the control instruction of the controller 420 at the next moment no longer affects the opening and closing of the relay; that is, when the controller 420 is preparing to upgrade and pulls down the relay control signal relay_ctrl to a low level, the relay group 160 maintains the high-level enabling state in the latched state of the latch unit 470 to keep it closed, and the level signal of the controller 420 at the next moment of the upgrade is latched by the latch unit 470 and no longer controls the relay group 160. Specifically, when executing the relay maintenance control mode, it is necessary to set the output clock signal clk to a low level when the relay control signal relay_ctrl maintains a high level at the previous moment to realize the latching of the relay control signal relay_ctrl by the latch unit 470.

[0078] (2) Upgrade stage: After the inverter switches to the relay maintenance control mode and completes it, the controller 420 can feedback to the host computer 410 that the preparation stage of the program upgrade has been completed. Subsequently, after receiving the information that the upgrade preparation is completed feedback by the controller 420, the host computer 410 starts the program upgrade. First, the host computer 410 pulls down the signals output by the signal lines boot and reset respectively to make the controller 420 enter the program upgrade mode; then the controller 420 can receive the upgrade program package transmitted by the host computer 410 through the signal line SCI to complete the upgrade.

[0079] (3) Upgrade completion stage: After the program upgrade of the controller 420 is completed, the relay control signal relay_ctrl output by the controller 420 needs to ensure that it is set to high level no later than the clock signal clk, and then the controller 420 starts normal control work.

[0080] The above describes the basic principle, main features and advantages of the present application. Those skilled in the art should understand that the present application is not limited by the above embodiments. What is described in the above embodiments and the specification is only the principle of the present application. Without departing from the spirit and scope of the present application, the present application will have various changes and improvements, and these changes and improvements all fall within the scope of the present application claimed. The scope of protection required by the present application is defined by the appended claims and their equivalents.

Claims

1. An inverter program online upgrade architecture, characterized in that: include: Host computer; the host computer is suitable for issuing upgrade instructions; Controller; The controller is communicatively connected with the host computer, and the controller is suitable for controlling the relay group; as well as Latch unit; The controller is in communication connection with the latch unit, and the latch unit is used to output the relay control signal of the controller; the latch unit is suitable for latching the relay control signal of the previous high level when the controller is upgraded, and then continuing to perform high-level enabling control on the relay group; The latch unit adopts a D latch; the controller is suitable for outputting a relay control signal and a clock signal to the D port and the EN port of the latch unit respectively; When the controller is working normally, the relay control signal and the clock signal are both at high level; when the controller is upgrading, the clock signal is at low level, and then the latch unit maintains the high level output; There are multiple controllers, one of which participates in the control of the relay group, and the other controllers do not participate in the control of the relay group; The controller participating in the control of the relay group is connected to the latch unit, and the other controllers are communicatively connected to the controller connected to the latch unit or the host computer.

2. The inverter program online upgrade architecture according to claim 1, characterized in that: The inverter program online upgrade architecture also includes a delay circuit, and the clock signal output by the controller is delayed by a set time through the delay circuit and then sent to the EN port of the latch unit.

3. The inverter program online upgrade architecture according to claim 2, characterized in that: The delay circuit includes a second AND gate unit, one of the input ends of the second AND gate unit is used to receive the clock signal sent by the controller, the other input ends of the second AND gate unit are all set high, and the output end of the second AND gate unit is communicatively connected to the EN port of the latch unit.

4. The inverter program online upgrade architecture according to claim 1, characterized in that: The inverter program online upgrade architecture also includes a software protection circuit with a software protection function; The software protection circuit comprises a third AND gate unit, an input end of the third AND gate unit is communicatively connected to the controller, and an output end of the third AND gate unit is communicatively connected to the D port of the latch unit; The controller sends the relay control signal and the software protection signal to the input end of the third AND gate unit respectively.

5. The inverter program online upgrade architecture according to any one of claims 1 to 4, characterized in that: The inverter program online upgrade architecture also includes a first AND gate unit and a protection unit; The protection unit and the latch unit are respectively connected to the input end of the first AND gate unit, and the output end of the first AND gate unit is control-connected to the relay group; The first AND gate unit is adapted to send a relay driving signal to the relay group according to the relay control signal output by the latch unit and the high-level blocking signal output by the protection unit.

6. The inverter program online upgrade architecture according to claim 5, characterized in that: There are a plurality of the controller and the latch unit, and the controller is connected with the corresponding latch unit to form a control branch; The controllers serving as input ends of the control branches are connected to each other in communication, or are connected to the host computer in communication; the latch units serving as output ends of the control branches are connected to the input ends of the first AND gate units.

7. An inverter program online upgrade method using the inverter program online upgrade architecture of claim 1, characterized in that: The steps include: The host computer sends a program upgrade preparation instruction to the controller; After receiving the instruction, the controller controls the current working mode of the inverter so that the inverter can work in the grid-connected mode and execute the relay maintenance control mode; After the inverter completes the switching of the relay maintenance mode, the controller feeds back to the host computer that the program upgrade is ready; After receiving the preparation completion information, the host computer sends an upgrade package to the controller to enter a program upgrade mode; After the controller is upgraded, a high level is sent to the latch unit to perform normal operation.

8. The inverter program online upgrade method according to claim 7, characterized in that: The working mode control of the inverter includes the following processes: Determine the current working mode of the inverter; If the inverter is in grid-connected mode, the inverter directly executes the relay maintenance control mode; If the inverter is in off-grid mode, further determine whether the inverter meets the grid-connected requirements; For the inverters that meet the grid connection requirements, they are switched to the grid connection mode and then the relay maintenance control mode is executed. For the inverters that do not meet the grid connection requirements, they are kept in the off-grid mode. The relay maintenance control mode is that the relay maintains the state at the previous moment, and the control instruction of the controller at the next moment no longer affects the opening and closing of the relay.

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