Data transmission method, device, electronic device and readable storage medium

Abstract

An embodiment of the present invention provides a data transmission method, device, electronic device, and readable storage medium. The method includes: a data receiving program receives first data from the hardware end, and writes the first data to a shared memory when a data processing program is idle; a data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data to the shared memory when the data sending program is idle; and a data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end. The embodiment of the present invention implements data interaction between the software end and the hardware end, improves data transmission efficiency, helps reduce transmission delay between the software end and the hardware end, and improves the overall performance of the software and hardware system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data transmission method, device, electronic device and readable storage medium. Background Art

[0002] Software and hardware collaboration is an important means to improve system performance. Using FPGAs and software for collaborative work is a common practice in the industry. When FPGAs and software work together, the software is much slower than the hardware. When the hardware needs to wait for the software to execute data, the software is blocked from communicating with the FPGA and cannot transmit and process data simultaneously. The system's performance bottleneck is often constrained by the software side. Summary of the Invention

[0003] Embodiments of the present invention provide a data transmission method, device, electronic device, and readable storage medium, which can reduce the transmission delay between the software end and the hardware end and improve the overall performance of the software and hardware system.

[0004] To solve the above problems, an embodiment of the present invention discloses a data transmission method, which is applied to a software side, wherein the software side is used to perform data processing tasks in collaboration with a hardware side; the software side includes a data receiving program, a data sending program, and a data processing program; the method includes:

[0005] The data receiving program receives first data from the hardware end, and writes the first data into a shared memory when the data processing program is idle;

[0006] The data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data into the shared memory when the data sending program is idle;

[0007] The data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end.

[0008] Optionally, the shared memory includes at least two memory partitions; the data receiving program receives the first data from the hardware end, and writes the first data into the shared memory when the data processing program is idle, comprising:

[0009] The data receiving program receives first data from the hardware end, and writes the first data into a first memory partition when the data processing program is idle; the first memory partition is any idle memory partition in the shared memory;

[0010] The data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data to the shared memory when the data sending program is idle, including:

[0011] The data processing program obtains the first data from the first memory partition, and performs a data processing task based on the first data to obtain first result data. When the data sending program is idle, the first result data is written into the second memory partition; the second memory partition is any idle memory partition in the shared memory.

[0012] Optionally, the method further includes:

[0013] When the data processing program executes the data processing task, the data processing program sets the value of the first semaphore to a first value; the first value is used to indicate that the data processing program is in a non-idle state;

[0014] After the data processing program writes the first result data into the shared memory, the value of the first semaphore is set to a second value; the second value is used to indicate that the data processing program is in an idle state;

[0015] The data receiving program monitors the first semaphore in real time, and determines that the data processing program is idle when the value of the first semaphore is the second value.

[0016] Optionally, the method further includes:

[0017] After the data sending program reads the first result data from the shared memory, the value of the second semaphore is set to a third value; the third value is used to indicate that the data sending program is in a non-idle state;

[0018] After the data sending program sends the first result data to the hardware end, the value of the second semaphore is set to a fourth value; the fourth value is used to indicate that the data sending program is in an idle state;

[0019] The data processing program monitors the second semaphore in real time, and determines that the data sending program is idle when the value of the second semaphore is the fourth value.

[0020] Optionally, the software end is mounted on an electronic device, and the electronic device further includes a communication driver;

[0021] The data receiving program receives the first data from the hardware end, including:

[0022] The data receiving program receives the first data from the hardware end through the communication driver;

[0023] The data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end, including:

[0024] The data sending program obtains the first result data from the shared memory, and sends the first result data to the hardware end through the communication driver.

[0025] Optionally, the first data includes simulator stimulus data; the data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data to the shared memory when the data sending program is idle, comprising:

[0026] The data processing program obtains the simulator stimulus data from the shared memory;

[0027] The data processing program analyzes the simulator excitation data to obtain simulation input information;

[0028] The data processing program drives the simulation software to perform simulation processing on the simulation input information to obtain a simulation result;

[0029] The data processing program writes the simulation result into the shared memory when the data sending program is idle.

[0030] On the other hand, an embodiment of the present invention discloses a data transmission device, which is applied to a software end, and the software end is used to cooperate with a hardware end to perform data processing tasks; the device includes:

[0031] a data receiving module, configured to receive first data from the hardware end, and write the first data into a shared memory when the data processing program is idle;

[0032] a data processing module, configured to obtain the first data from the shared memory, perform a data processing task based on the first data, obtain first result data, and write the first result data into the shared memory when the data sending program is idle;

[0033] A data sending module is used to obtain the first result data from the shared memory and send the first result data to the hardware end.

[0034] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned data transmission method.

[0035] An embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned data transmission method.

[0036] The embodiments of the present invention include the following advantages:

[0037] An embodiment of the present invention provides a data transmission method that divides the software end into three independent programs: a data receiving program, a data processing program, and a data sending program. The data receiving program receives first data from the hardware end and writes the first data to a shared memory when the data processing program is idle; the data processing program obtains the first data from the shared memory and performs a data processing task based on the first data to obtain first result data, and writes the first result data to the shared memory when the data sending program is idle; and the data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end. The embodiment of the present invention implements data interaction between the software end and the hardware end through the data receiving program and the data sending program, and implements data transmission between the data receiving program, the data processing program, and the data sending program through the shared memory. Furthermore, the data processing program and the data receiving and sending programs can work simultaneously, performing data processing and data transmission, respectively. While ensuring exclusive access to the shared memory by the programs, data transmission efficiency is improved, thereby facilitating reduced transmission delays between the software end and the hardware end, and improving the overall performance of the software and hardware system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 is a flowchart of steps of an embodiment of a data transmission method of the present invention;

[0040] Figure 2 It is a structural block diagram of a data transmission device of the present invention;

[0041] Figure 3This is a structural block diagram of an electronic device for accessing memory provided by an example of the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0043] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0044] Method Example

[0045] Reference Figure 1 , shows a flowchart of a data transmission method embodiment of the present invention, the method may specifically include the following steps:

[0046] Step 101: a data receiving program receives first data from the hardware end, and writes the first data into a shared memory when the data processing program is idle;

[0047] Step 102: The data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data into the shared memory when the data sending program is idle.

[0048] Step 103: The data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end.

[0049] The data transmission method provided in the embodiment of the present invention can be applied to the software side, which is used to cooperate with the hardware side to perform data processing tasks; the software side includes a data receiving program, a data sending program and a data processing program.

[0050] In one possible application scenario of the present invention, collaborative verification of a design under test (DUT) is performed through software and hardware. Specifically, a design under test (DUT) and a corresponding reference model of the DUT can be deployed on the hardware side. For example, the DUT can be deployed in the programmable logic (PL) area of ​​a field programmable gate array (FPGA), and the reference model of the DUT can be deployed in the FPGA's processing system. The DUT and the reference model are then run simultaneously on the FPGA to perform functional verification of the DUT. When the running state of the DUT is inconsistent with that of the reference model, it is determined that the DUT has failed. In this case, a snapshot of the entire FPGA state information can be saved using hardware snapshot technology. The saved snapshot information is then transmitted to the software side, which runs simulation software, which is used to perform fine-grained debugging and repair of the DUT. Collaborative verification of the DUT based on hardware and software can improve verification efficiency while achieving fine-grained debugging and repair of the DUT.

[0051] The operating speed of the hardware side is much faster than the computing speed of the software side. In another application scenario of the present invention, collaborative computing can be performed by the software side and the hardware side. For example, in the field of image processing, neural network models are usually used for image processing, such as image recognition, image classification, image beautification (such as removing obstructions, watermarks, background blur, image fusion, etc.), AI drawing, etc. The computing speed of the software side is also limited. The neural network model can be reconstructed on the FPGA hardware, and the FPGA can be used to implement on-chip image processing. For example, the software side interacts with the user to obtain user requirements and the image to be processed, parses the image to be processed, and transmits the parsed image data to the FPGA. The FPGA processes the image data based on the user's requirements and feeds back the processing results to the software side. The software side parses the received processing results, generates the processed target image, and displays it to the user.

[0052] It's important to note that FPGAs are reconfigurable integrated circuits (ICs) with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs, adapting them to different applications and functions. FPGAs consist of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, enabling them to perform various logic functions. Programmable interconnect resources connect the logic blocks to form the desired circuit structure. Using FPGAs, designers can describe the desired circuit functionality using a hardware description language (HDL) and, using programming tools, convert this into a bitstream compatible with the FPGA chip. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the key advantages of FPGAs is their programmability and flexibility. They allow designers to implement customized functions and algorithms at the hardware level without the traditional custom IC design and manufacturing process. This makes FPGAs crucial for prototyping and rapid design iteration.

[0053] The hardware end in the embodiment of the present invention may be an FPGA, or other hardware devices or hardware modules, such as a GPU, a DSA, an ASIC, and the like.

[0054] Software and hardware need to communicate through defined interaction structures, achieving decoupling of hardware and software through interfaces. For example, for a CPU, the interface between software and hardware is the instruction set architecture (ISA). The processor below the ISA is hardware, and the various programs, data sets, and files above the instruction set are software.

[0055] The software end in the embodiment of the present invention refers to a program on an instruction set, and the software end can be installed in a personal computer (PC) or other electronic devices with an operating system that can run software.

[0056] In this embodiment of the present invention, the software side can be divided into three independent programs according to their functions: a data receiving program, a data processing program, and a data sending program. The data receiving program is used to receive data from the hardware side; the data processing program is used to parse and process the received data; and the data sending program is used to send the processing results of the data processing program to the hardware side.

[0057] The data receiving program, data processing program, and data sending program implement data transfer via shared memory. Specifically, after receiving first data from the hardware end, the data receiving program writes the first data to the shared memory while the data processing program is idle. The data processing program retrieves the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and then writes the first result data to the shared memory while the data sending program is idle. The data sending program retrieves the first result data from the shared memory and then sends the first result data to the hardware end.

[0058] It is understandable that in an embodiment of the present invention, only one of the data receiving program and the data processing program can perform a write operation on the shared memory at the same time. In other words, the data receiving program and the data processing program cannot perform a write operation on the shared memory at the same time to avoid data errors caused by the data receiving program and the data processing program writing data to the shared memory at the same time (for example, if the data receiving program and the data processing program simultaneously change the same memory space in the shared memory, it will cause data errors). The data receiving program receives the first data from the hardware end and packages the first data. When the data processing program is idle, the accumulated first data is written to the shared memory and the first data is passed to the data processing program. It should be noted that while the data processing program reads the first data from the shared memory and performs the data processing task, the data receiving program can continue to receive data from the hardware end, but temporarily does not write to the shared memory. The data is accumulated locally and the accumulated data is written to the shared memory after the data processing program is idle.

[0059] Only one of the data processing program and the data sending program can read or write to the shared memory at the same time. In other words, when the data processing program is writing data to the shared memory, the data sending program cannot read the data from the shared memory. This prevents data errors caused by differences in data order between the data processing program and the data sending program (for example, one program writes data sequentially while the other reads data in reverse order) or differences in instantaneous data rates (for example, the data processing program writes data at 200 MHz while the data sending program reads data at 50 MHz). The data processing program executes the data processing task to obtain the first result data and then writes the first result data to the shared memory after the data sending program becomes idle. It should be noted that while the data sending program is reading the first result data from the shared memory, the data processing program can continue to execute the next data processing task, but temporarily suspends writing the result data to the shared memory. Instead, it accumulates the data locally and writes the accumulated result data to the shared memory after the data sending program becomes idle.

[0060] For example, assuming that data is first transmitted from the hardware end to the software end, that is, the data receiving program first receives the first data from the hardware end, at this time, the data processing program and the data sending program are both in the initial state, that is, the idle state, and the data receiving program can directly write the first data to the shared memory. The data processing program reads the first data from the shared memory and performs a data processing task based on the read first data until the first result data is obtained. At this time, the data sending program is in the idle state, and the data processing program can write the first result data to the shared memory. After the writing is completed, the data processing program is in the idle state. The data sending program reads the first result data from the shared memory and sends the first result data to the hardware end. When the data processing program is in the idle state, the data receiving program continues to write the new first data received from the hardware end to the shared memory.

[0061] Furthermore, the hardware end in the embodiments of the present invention can be an FPGA, and PCIE-XDMA can be used as the communication protocol between the software and hardware ends. PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard primarily used to expand computer system bus data throughput and improve device communication. XDMA is the official "advanced" PCIE IP included with Xilinx FPGAs. Its operation is primarily at the "application layer." Simply put, after the FPGA is instantiated and configured, the FPGA essentially does not need to perform any additional logic operations. The software end can exchange data with the FPGA via DMA by calling library functions. All DMA operations are fully implemented by the host computer corresponding to the software end through the PCIE configuration of the XDMA registers.

[0062] Optionally, the software end is mounted on an electronic device, and the electronic device further includes a communication driver; the data receiving program receives the first data from the hardware end, including:

[0063] Step S11: the data receiving program receives first data from the hardware end through the communication driver;

[0064] The data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end, including:

[0065] Step S12: The data sending program obtains the first result data from the shared memory, and sends the first result data to the hardware end through the communication driver.

[0066] The communication driver may include a software driver library (eg, an XDMA driver function library) and a hardware driver configuration, such as PCIE-XDMA.

[0067] For example, the hardware side (i.e., an FPGA board) is connected to the PCIe slot of an electronic device (i.e., a PC) equipped with a software side. The hardware side uses the AXI-STREAM protocol interface to send data to the software side. The data receiving program can interact with the hardware side through the XDMA driver function library to receive the first data from the hardware side. The first result data on the software side is returned to the hardware side by the data sending program via PCIe-XDMA. After data parsing by the hardware parsing module, it is written into a FIFO or passed to the hardware for processing. FIFO, short for "First In, First Out," is a common queue data structure management method. In a FIFO, the first element to enter the queue is the first to be removed, and the last element to enter the queue is the last to be removed, just like the person at the front of the queue leaves the queue first. This data structure can be used to simulate various real-world scenarios, such as queuing and request processing. FIFO queues are commonly used for managing shared resources, processing tasks, and cache management.

[0068] Optionally, the first data includes simulator stimulus data; the data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data to the shared memory when the data sending program is idle, comprising:

[0069] Step S21, the data processing program obtains the simulator stimulus data from the shared memory;

[0070] Step S22: the data processing program analyzes the simulator excitation data to obtain simulation input information;

[0071] Step S23: the data processing program drives the simulation software to perform simulation processing on the simulation input information to obtain a simulation result;

[0072] Step S24: When the data sending program is idle, the data processing program writes the simulation result into the shared memory.

[0073] In an optional embodiment of the present invention, a simulator can be verified through the collaboration of software and hardware. The simulator is used to simulate processor behavior. For example, during the processor design process, the simulator can be used to simulate processor behavior. By verifying the simulator, the processor design logic can be verified and tested.

[0074] Specifically, the hardware side triggers the simulator by inputting stimulus data into the simulator, which then generates the simulator's operational results. The hardware side transmits the simulator stimulus data to the software side. The software's data receiving program receives the data and, when the data processing program is idle, writes the simulator stimulus data to shared memory. The data processing program retrieves the simulator stimulus data from shared memory and parses it to obtain simulation input information. The data processing program then inputs the simulation input information into the simulation software for simulation processing, generating simulation results. When the data sending program is idle, the simulation results are written to shared memory. The data sending program then sends the simulation results to the hardware side, which compares the simulation results with the simulator's operational results to determine if the simulator has run into errors.

[0075] In another possible application scenario of the present invention, the hardware end can also send the running results of the simulator to the software end, and the software end compares the running results of the simulator with the simulation results of the simulation software, and sends the comparison results to the hardware end, and the hardware end directly determines whether the simulator has an error based on the comparison results.

[0076] In an optional embodiment of the present invention, the shared memory includes at least two memory partitions; the data receiving program receives the first data from the hardware end, and writes the first data into the shared memory when the data processing program is idle, comprising:

[0077] Step S31: The data receiving program receives first data from the hardware end, and writes the first data into a first memory partition when the data processing program is idle; the first memory partition is any idle memory partition in the shared memory;

[0078] The data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data to the shared memory when the data sending program is idle, including:

[0079] Step S32, the data processing program obtains the first data from the first memory partition, and performs a data processing task based on the first data to obtain first result data. When the data sending program is idle, the first result data is written to the second memory partition; the second memory partition is any idle memory partition in the shared memory.

[0080] In the embodiment of the present invention, the shared memory may be divided into a plurality of memory partitions, and the data receiving program, the data processing program, and the data sending program may use the shared memory in a ping-pong operation in turn.

[0081] Specifically, assume that data is first transmitted from the hardware end to the software end, that is, the data receiving program first receives the first data from the hardware end. At this time, the data receiving program, the data processing program, and the data sending program are all in the initial state, that is, the idle state. After the data receiving program receives the first data D1 from the hardware end, when the data processing program is idle, the first data D1 is written to the first memory partition R1; the data processing program obtains the first data D1 from the first memory partition R1, executes the data processing task corresponding to the first data D1, and obtains the first result data S1; at this time, the data sending program is in the idle state, and the data processing program writes the first result data S1 to the second memory partition R2. The data sending program obtains the first result data S1 from the second memory partition R2 and sends the first result data S1 to the hardware end.

[0082] It is understandable that when the data processing program writes the first result data S1 to the second memory partition R2, the data processing program is idle for the first memory partition R1, so the data receiving program can continue to write new first data D2 to the first memory partition R1.

[0083] Through this ping-pong operation, the data receiving program and the data processing program can write data to the shared memory at the same time (write to different memory partitions), saving program waiting time and improving data transmission efficiency.

[0084] It should be noted that after all the data in a memory partition has been read, the memory partition can be cleared to allow new data to be written into it.

[0085] Furthermore, in embodiments of the present invention, semaphores can be used to control access to shared memory by data receiving programs, data processing programs, and data sending programs. Semaphores are a synchronization mechanism in operating systems used to control access to shared resources by multiple processes. In embodiments of the present invention, semaphores can be used to determine shared memory usage and control the execution logic between multiple programs.

[0086] Optionally, the method further includes:

[0087] Step S41: When executing a data processing task, the data processing program sets the value of the first semaphore to a first value; the first value is used to indicate that the data processing program is in a non-idle state;

[0088] Step S42: After the data processing program writes the first result data into the shared memory, the value of the first semaphore is set to a second value; the second value is used to indicate that the data processing program is in an idle state;

[0089] Step S43: The data receiving program monitors the first semaphore in real time, and determines that the data processing program is idle when the value of the first semaphore is the second value;

[0090] Step S44: After the data sending program reads the first result data from the shared memory, the value of the second semaphore is set to a third value; the third value is used to indicate that the data sending program is in a non-idle state;

[0091] Step S45: After the data transmission program sends the first result data to the hardware end, the value of the second semaphore is set to a fourth value; the fourth value is used to indicate that the data transmission program is in an idle state;

[0092] Step S46: The data processing program monitors the second semaphore in real time, and when the value of the second semaphore is the fourth value, determines that the data sending program is idle.

[0093] In the embodiment of the present invention, the data receiving program, the data processing program and the data sending program may be initialized first, and the initial states of these three programs are all idle states.

[0094] In one possible application scenario of the present invention, a data receiving program waits for the hardware end to send first data. After receiving the first data, the data receiving program waits for a first semaphore indicating that the data processing program is idle to be set (valid). It is understood that if the first semaphore is set or valid, for example, the value of the first semaphore is the second value, such as "1," the data processing program is in an idle state; if the first semaphore is not set or invalid, for example, the value of the first semaphore is the first value, such as "0," the data processing program is in a non-idle state.

[0095] If new first data is sent while the data receiving program is waiting for the first semaphore to be set, the data receiving program will splice the new data after the data that has not yet been written into the shared memory.

[0096] After the first semaphore is valid, the data receiving program writes the received first data into the shared memory and continues to wait for data from the hardware end or the data processing program is idle.

[0097] When the data processing program is processing data, the value of the first semaphore is updated to the first value, indicating that the data processing program is in a non-idle state. After the execution is completed, the semaphore indicating that valid data processing has been completed waits for the data sending program to be idle, and then writes the first result data to the shared memory. After the first result data is written, the semaphore indicating that the data processing has been completed is invalidated, and the value of the first semaphore is updated to the second value, indicating that the data processing program is in an idle state.

[0098] After receiving the first result data to be sent, the data sending program sets the value of the second semaphore to a third value, such as "1", indicating that the data sending program is in a non-idle state. After sending the first result data to the hardware end, the value of the second semaphore is updated to a fourth value, such as "0", indicating that the data sending program is in an idle state.

[0099] In summary, an embodiment of the present invention provides a data transmission method that divides the software end into three independent programs: a data receiving program, a data processing program, and a data sending program. The data receiving program receives first data from the hardware end and writes the first data to a shared memory when the data processing program is idle. The data processing program retrieves the first data from the shared memory and performs a data processing task based on the first data to obtain first result data. When the data sending program is idle, the first result data is written to the shared memory. The data sending program retrieves the first result data from the shared memory and sends the first result data to the hardware end. In an embodiment of the present invention, only one of the data receiving program and the data processing program can write to the shared memory at the same time. However, while the data processing program is performing a data processing task, the data receiving program can continue to receive data from the hardware end, but temporarily suspends writing to the shared memory. The accumulated data will be written to the shared memory after the data processing program is idle. Similarly, while the data sending program is reading the first result data from the shared memory, the data processing program can continue to perform the next data processing task, but temporarily suspends writing the result data to the shared memory. The accumulated result data will be written to the shared memory after the data sending program is idle. The embodiment of the present invention realizes data interaction between the software end and the hardware end through a data receiving program and a data sending program, and realizes data transmission between the data receiving program, the data processing program and the data sending program through shared memory. Moreover, the data processing program and the data receiving and sending programs can work simultaneously to perform data processing and data transmission respectively. While ensuring the program's exclusive access to the shared memory, the data transmission efficiency is improved, which is conducive to reducing the transmission delay between the software end and the hardware end and improving the overall performance of the software and hardware system.

[0100] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required for the embodiments of the present invention.

[0101] Device embodiment

[0102] Reference Figure 2, shows a structural block diagram of a data transmission device of the present invention, wherein the device is applied to a software end, and the software end is used to cooperate with a hardware end to perform data processing tasks; the device may specifically include:

[0103] a data receiving module 201, configured to receive first data from the hardware end and write the first data into a shared memory when the data processing program is idle;

[0104] a data processing module 202 configured to obtain the first data from the shared memory, perform a data processing task based on the first data, obtain first result data, and write the first result data into the shared memory when the data sending program is idle;

[0105] The data sending module 203 is configured to obtain the first result data from the shared memory and send the first result data to the hardware end.

[0106] Optionally, the shared memory includes at least two memory partitions; and the data receiving module includes:

[0107] a first data receiving submodule, configured to receive first data from the hardware end, and write the first data into a first memory partition when the data processing program is idle; the first memory partition is any idle memory partition in the shared memory;

[0108] Data processing module, including:

[0109] The first processing sub-module is used to obtain the first data from the first memory partition, perform a data processing task based on the first data, obtain first result data, and write the first result data into the second memory partition when the data sending program is idle; the second memory partition is any idle memory partition in the shared memory.

[0110] Optionally, the device further comprises:

[0111] A first setting module is used to set the value of the first semaphore to a first value when executing a data processing task; the first value is used to indicate that the data processing program is in a non-idle state;

[0112] a second setting module, configured to set the value of the first semaphore to a second value after writing the first result data into the shared memory; the second value is used to indicate that the data processing program is in an idle state;

[0113] The first determining module is configured to monitor the first semaphore in real time, and determine that the data processing program is idle when the value of the first semaphore is the second value.

[0114] Optionally, the device further comprises:

[0115] A third setting module is configured to set the value of the second semaphore to a third value after reading the first result data from the shared memory; the third value is used to indicate that the data sending program is in a non-idle state;

[0116] a fourth setting module, configured to set the value of the second semaphore to a fourth value after sending the first result data to the hardware end; the fourth value is used to indicate that the data sending program is in an idle state;

[0117] The second determining module is configured to monitor the second semaphore in real time, and determine that the data sending program is idle when the value of the second semaphore is the fourth value.

[0118] Optionally, the software end is mounted on an electronic device, and the electronic device further includes a communication driver;

[0119] The data receiving module includes:

[0120] A first receiving submodule, configured to receive first data from the hardware end through the communication driver;

[0121] The data sending module includes:

[0122] The first sending submodule is configured to obtain the first result data from the shared memory, and send the first result data to the hardware end through the communication driver.

[0123] Optionally, the first data includes simulator stimulus data; and the data processing module includes:

[0124] An incentive acquisition submodule, configured to acquire the simulator incentive data from the shared memory;

[0125] A data analysis submodule is used to analyze the simulator stimulus data to obtain simulation input information;

[0126] The simulation driving submodule is used to drive the simulation software to perform simulation processing on the simulation input information to obtain simulation results;

[0127] The result writing submodule is used to write the simulation result into the shared memory when the data sending program is idle.

[0128] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0129] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0130] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0131] Reference Figure 3 , is a structural block diagram of an electronic device for data transmission provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data transmission method of the aforementioned embodiment.

[0132] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0133] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used does not mean that there is only one bus or one type of bus.

[0134] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0135] The embodiment of the present invention further provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figure 1 The data transmission method shown.

[0136] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0137] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatuses, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0138] The embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0139] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0140] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0141] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0142] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0143] The above is a detailed introduction to a data transmission method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A data transmission method, characterized in that: Applied to a software side, the software side is used to cooperate with the hardware side to perform data processing tasks; the software side includes a data receiving program, a data sending program, and a data processing program; the method includes: The data receiving program receives first data from the hardware end, and writes the first data into a shared memory when the data processing program is idle; The data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data into the shared memory when the data sending program is idle; The data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end; The software side refers to the program above the instruction set; the hardware side refers to the processor below the instruction set; the data receiving program is used to receive data from the hardware side; the data processing program is used to parse and process the received data; the data sending program is used to send the processing results of the data processing program to the hardware side; The shared memory includes at least two memory partitions; the data receiving program receives first data from the hardware end, and writes the first data into the shared memory when the data processing program is idle, including: The data receiving program receives first data from the hardware end, and writes the first data into a first memory partition when the data processing program is idle; the first memory partition is any idle memory partition in the shared memory; The data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data to the shared memory when the data sending program is idle, including: The data processing program obtains the first data from the first memory partition, performs a data processing task based on the first data, obtains first result data, and writes the first result data into a second memory partition when the data sending program is idle; the second memory partition is any idle memory partition in the shared memory; After all the data in any memory partition is read, the memory partition is cleared so that new data can be written.

2. The method according to claim 1, characterized in that The method further comprises: When the data processing program executes the data processing task, the data processing program sets the value of the first semaphore to a first value; the first value is used to indicate that the data processing program is in a non-idle state; After the data processing program writes the first result data into the shared memory, the value of the first semaphore is set to a second value; the second value is used to indicate that the data processing program is in an idle state; The data receiving program monitors the first semaphore in real time, and determines that the data processing program is idle when the value of the first semaphore is the second value.

3. The method according to claim 1, characterized in that The method further comprises: After the data sending program reads the first result data from the shared memory, the value of the second semaphore is set to a third value; the third value is used to indicate that the data sending program is in a non-idle state; After the data sending program sends the first result data to the hardware end, the value of the second semaphore is set to a fourth value; the fourth value is used to indicate that the data sending program is in an idle state; The data processing program monitors the second semaphore in real time, and determines that the data sending program is idle when the value of the second semaphore is the fourth value.

4. The method according to claim 1, wherein The software end is mounted on an electronic device, and the electronic device also includes a communication driver; The data receiving program receives the first data from the hardware end, including: The data receiving program receives the first data from the hardware end through the communication driver; The data sending program obtains the first result data from the shared memory and sends the first result data to the hardware end, including: The data sending program obtains the first result data from the shared memory, and sends the first result data to the hardware end through the communication driver.

5. The method according to claim 1, wherein The first data includes simulator stimulus data; the data processing program obtains the first data from the shared memory, performs a data processing task based on the first data, obtains first result data, and writes the first result data to the shared memory when the data processing program is idle, including: The data processing program obtains the simulator stimulus data from the shared memory; The data processing program analyzes the simulator excitation data to obtain simulation input information; The data processing program drives the simulation software to perform simulation processing on the simulation input information to obtain a simulation result; The data processing program writes the simulation result into the shared memory when the data sending program is idle.

6. A data transmission device, characterized in that: Applied to a software side, the software side is used to perform data processing tasks in collaboration with a hardware side; the device includes: a data receiving module, configured to receive first data from the hardware end, and write the first data into a shared memory when the data processing program is idle; a data processing module, configured to obtain the first data from the shared memory, perform a data processing task based on the first data, obtain first result data, and write the first result data into the shared memory when the data sending program is idle; a data sending module, configured to obtain the first result data from the shared memory and send the first result data to the hardware end; The software side refers to the program above the instruction set; the hardware side refers to the processor below the instruction set; the data receiving program is used to receive data from the hardware side; the data processing program is used to parse and process the received data; the data sending program is used to send the processing results of the data processing program to the hardware side; The shared memory includes at least two memory partitions; the data receiving module includes: a first data receiving submodule, configured to receive first data from the hardware end, and write the first data into a first memory partition when the data processing program is idle; the first memory partition is any idle memory partition in the shared memory; Data processing module, including: a first processing submodule, configured to obtain the first data from the first memory partition, perform a data processing task based on the first data to obtain first result data, and write the first result data to a second memory partition when the data sending program is idle; the second memory partition is any idle memory partition in the shared memory; The device is also used for: After all the data in any memory partition is read, the memory partition is cleared so that new data can be written.

7. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data transmission method according to any one of claims 1 to 5.

8. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to perform the data transmission method according to any one of claims 1 to 5.

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