Spearman simple correlation coefficient solution method and field programmable logic gate array operation circuit

Abstract

The application relates to a method for solving a Spearman simple correlation coefficient, which comprises the following steps: a field programmable logic gate array operation circuit is used to realize fast solving of the Spearman simple correlation coefficient; a fast version of the Spearman simple correlation coefficient is obtained by simplifying the Spearman simple correlation coefficient, so that field programmable logic gate array operation hardware circuit designed based on the Spearman simple correlation coefficient can be simplified, and the operation speed is accelerated; and the Spearman simple correlation coefficient is solved based on a parallel computing mode of the field programmable logic gate array, so that the calculation time can be further shortened, and the purpose of solving the Spearman simple correlation coefficient in real time and quickly is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data processing, in particular to a method for calculating Spearman's simple correlation coefficient and a field programmable gate array operation circuit. BACKGROUND

[0002] Statistical signal processing, which is extended and developed from signal processing, is an important research field at present, and the analysis of the correlation between two groups of data has gradually become a research hotspot among scholars. Correlation analysis has been widely used in various scientific and technological fields since its development with the establishment of the discipline of statistics a century ago. The correlation coefficient is a specific measure of the strength of the linear relationship between two random variables in quantitative correlation analysis. If one of the two random variables increases (decreases) as the other increases (decreases), the two random variables are positively correlated; otherwise, if one of the two random variables decreases (increases) as the other increases (decreases), the two random variables are negatively correlated, and the strength of the relationship changes in degree based on the value of the correlation coefficient. In many related fields such as signal processing and statistics, the correlation coefficient has become a common method for quantifying the strength of the statistical relationship between random variables. Pearson's Product Moment Correlation Coefficient (PPMCC) proposed by Karl Pearson, the founder of mathematical statistics, Spearman's rho (SR) proposed by statistician Spearman, and Kendall's tau (KT) proposed by psychologist Kendall are the three most commonly used correlation coefficients in theoretical research and practical application. Statistician Fisher proved that PPMCC is the optimal asymptotic unbiased estimate of the parent correlation coefficient when the sample follows a bivariate normal distribution, and its statistical properties are very complete. At the same time, the time complexity of the operation is low, the operation efficiency is high, and the real-time requirement can be met. Because PPMCC has the above advantages, it occupies a dominant position in both theoretical research and practical application. However, in practical application, the collected data is inevitably disturbed by noise, especially impulse noise, such as low-frequency atmospheric noise, electromagnetic interference caused by lightning storms in nature, human noise, and interference noise generated by electronic equipment. PPMCC is very sensitive to noise in the sample. When there is impulse noise in the sample, the performance of PPMCC will decrease sharply or even completely fail. SR and KT are less sensitive to non-normal distribution in the sample because they only use the ranking information, i.e. rank information, and have a certain robustness to impulse noise.

[0003] Compared with the three classical correlation coefficients described above, the research and application of Spearman's foot rule (SF) is relatively less. Spearman's foot rule is a natural attribute for measuring the Manhattan distance between two sets of rank variables, and depends on the rank information of the sample, so it has certain robustness to impulse noise as SR and KT. The relevant literature has proved that the performance of Spearman's foot rule is better than that of SR and KT under certain conditions, and at the same time, the calculation of SF is based on the absolute value of the difference of sample ordering information, which also makes the calculation of Spearman's foot rule more simple and efficient than SR and KT.

[0004] Due to the advantages of simplicity, robustness and natural attribute of SF itself, it has been rediscovered and applied in many research fields such as genetics and information retrieval, so it has certain practical significance to realize the fast solution of SF. In the prior art, CPU is often used to calculate and solve Spearman's foot rule, but due to the fact that CPU mainly adopts serial calculation method, it is limited by the limitations of serial operation, resulting in that CPU is time-consuming in calculating and solving Spearman's foot rule.

[0005] In summary, in order to adapt to the calculation and solution of Spearman's foot rule by CPU in the prior art, due to the fact that CPU mainly adopts serial calculation method, it is limited by the limitations of serial operation, resulting in that CPU is time-consuming in calculating and solving Spearman's foot rule and other problems, the applicant makes corresponding exploration to solve the problem. SUMMARY

[0006] The purpose of the present application is to solve the above problems and provide a method for solving Spearman's foot rule and a field programmable logic gate array operation circuit.

[0007] In order to achieve the various purposes of the present application, the present application adopts the following technical solutions:

[0008] The method for solving Spearman's foot rule proposed to adapt to one of the purposes of the present application comprises:

[0009] Step S10, inputting signal X i Input the row and column storage blocks in the field programmable logic gate array operation circuit to obtain X1...X i ...X n and X1...X j ...X n , complete the first level cache;

[0010] Step S20, inputting X1...Xi ...X n and X1...X j ...X n Input comparator array, complete n 2 Comparison operations, get a ij =sign(x i -x j ) and enter the pipeline to complete the second-level cache;

[0011] Step S30: Signal Y i Input row and column storage blocks and get Y1…Y i …Y n and Y1…Y j …Y n , complete the first level cache;

[0012] Step S40: Y1...Y i …Y n and Y1…Y j …Y n Input comparator array, complete n 2 Comparison operation, get b ij =sign(y i -y j ) and enter the pipeline to complete the second-level cache;

[0013] Step S50: Y1...Y i …Y n and Y1…Y obtained in step S3 j …Y n Input the comparator, complete n comparison operations, and get c i =sign(x i -y i ) and enter the pipeline to complete the second-level cache;

[0014] Step S60: the data obtained in steps S20, S40 and S50 are

[0015] a ij =sign(X i -X j ), b ij =sign(Y i -Y j ) and c i =sign(X i -Y i ) input array multiplication accumulator at the same time, under the control of the control unit, the time-sharing is completed and

[0016] Step S70, input the result of step S60 into a subtracter, and complete

[0017] input subtracter, and complete

[0018] Step S80, input the result of step S70 into a divider, and complete input divider, and complete

[0019] Step S90, input the result of step S80 into a subtracter, and complete

[0020] input subtracter, and complete

[0021]

[0022] Step S100, input the result of step S90 into a register, and complete the output, wherein i, j = 1...n.

[0023] Optionally, the step S60 comprises:

[0024] Step S601, input a ij = sign(X i -X j ), b ij = sign(Y i -Y j ) and c i = sign(X i -Y i ) into corresponding multiplier arrays simultaneously, and complete n 2 times parallel input multiplication under the control of a control unit, to obtain sign(X i -X j ) sign(X i -Y i ) and sign(Y i -Y j ) sign(X i -Y i );

[0025] Step S602, input sign(X i -X j ) sign(X i -Y i ) and sign(Y i -Y j ) sign(X i -Y i) input the corresponding adder at the same time, and complete n 2 parallel input addition operations, we get and

[0026] A field programmable logic gate array arithmetic circuit is proposed to meet another purpose of the present application, and is applied to any of the above-mentioned methods for solving the Spearman correlation coefficient, comprising:

[0027] The comparator array is used to generate a i and Y i Calculate a ij and b ij ;

[0028] The comparator is used to i and Y i Calculate c i ;

[0029] Array multiply accumulator, which is used to calculate

[0030] Subtractor, which is used to calculate T1-T2 and

[0031] Divider, which is used to calculate

[0032] Row and column storage blocks, which are used to serially register signal X i and Y i , which supports block addressing;

[0033] Pipeline, which is used to temporarily store intermediate calculation results;

[0034] A control unit, which is used for timing control of the array multiplier accumulator;

[0035] Register, which is used to store the final calculation result;

[0036] Signal X i and Y i The calculation steps performed after inputting into the field programmable logic gate array calculation circuit are:

[0037] Step S1: Signal X i Input row and column storage blocks to obtain X1…X i …X n and X1…X j …X n , complete the first level cache;

[0038] Step S2: X1…X obtained in step S1 i …X n and X1…Xj …X n Input comparator array, complete n 2 Comparison operations, get a ij =sign(x i -x j ) and enter the pipeline to complete the second-level cache;

[0039] Step S3: Signal Y i Input row and column storage blocks and get Y1…Y j …Y n and Y1…Y j …Y n , complete the first level cache;

[0040] Step S4: Y1...Y i …Y n and Y1…Y i …Y n Input comparator array, complete n 2 Comparison operation, get b ij =sign(y i -y j ) and enter the pipeline to complete the second-level cache;

[0041] Step S5: X1...X obtained in step S1 i …X n and Y1…Y obtained in step S3 j …Y n Input the comparator, complete n comparison operations, and get c i =sign(x i -y i ) and enter the pipeline to complete the second-level cache;

[0042] Step S6: the

[0043] a ij =sign(X i -X j ), b ij =sign(Y i -Y j ) and c i =sign(X i -Y i ) input array multiplication accumulator at the same time, under the control of the control unit, the time-sharing is completed and

[0044] Step S7: the

[0045] input subtracter, to complete

[0046] Step S8, input the sign(X

[0047] input divider, to complete

[0048] Step S9, input the sign(X

[0049] input subtracter, to determine the Spearman simple correlation coefficient as:

[0050]

[0051] Step S10, input the Spearman simple correlation coefficient obtained in step S9 into the register to obtain the output result, wherein i, j = 1…n.

[0052] Optionally, the array multiplication accumulator comprises:

[0053] a multiplication array, for calculating a ij c i , b ij c i , wherein i, j = 1…n;

[0054] an adder, for calculating

[0055] a signal X i and Y i The operation steps executed after inputting the array multiplication accumulator are:

[0056] Step S61, input a ij = sign(X i -X j ), b ij = sign(Y i -Y j ) and c i = sign(X i -Y i ) into the corresponding multiplication array at the same time, under the control of the control unit, complete n 2 times parallel input multiplication operation at different times to obtain sign(X i -X j ) sign(X i -Y i ) and sign(Y i -Y j ) sign(X i -Y i ).

[0057] Step S62, sign(X i -X j ) sign(X i -Y i ) and sign(Y i -Y j ) sign(X i -Y i ) are input into corresponding adders respectively, and n 2 times of parallel input addition operations are completed in time division to obtain wherein, i, j = 1…n.

[0058] Optionally, the field programmable logic gate array operation circuit adopts a pipeline processing mode.

[0059] An electronic device is provided for another purpose of the present application, and the above-mentioned simple Spearman correlation coefficient solving method is applied.

[0060] A computer device is provided for another purpose of the present application, which comprises a memory and a processor, the memory stores a computer program implemented according to any one of the above-mentioned methods, and the processor implements any one of the simple Spearman correlation coefficient solving methods when executing the computer program.

[0061] A computer readable storage medium is provided for another purpose of the present application, which stores a computer program implemented according to any one of the above-mentioned methods in the form of computer readable instructions, and when the computer program is invoked and run by a computer, the steps included in the corresponding method are executed.

[0062] Compared with the prior art, the present application is directed to the calculation and solving of the simple Spearman correlation coefficient by the CPU in the prior art. Since the CPU mainly adopts a serial calculation mode, it is limited by the limitations of serial operation, which leads to the problem that the calculation and solving of the simple Spearman correlation coefficient by the CPU is time-consuming. The present application includes but is not limited to the following beneficial effects:

[0063] Firstly, the simple Spearman correlation coefficient solving method of the present application fully utilizes the high-performance parallel processing capability of the field programmable logic gate array operation circuit (FPGA operation circuit), which can further shorten the calculation time of the simple Spearman correlation coefficient, and realize real-time and rapid signal correlation processing based on the simple Spearman correlation coefficient (SF);

[0064] Secondly, the Pearson product-moment correlation coefficient is basically invalid in the pulse noise environment, while the Spearman's rank correlation coefficient (SF) is robust to the pulse noise and is simpler and more efficient in calculation than the Spearman's rank correlation coefficient and the Kendall rank correlation coefficient;

[0065] Thirdly, since it takes time to solve SF by using CPU, the application adopts a field programmable logic gate array operation circuit (FPGA operation circuit) to realize fast solving of the Spearman's rank correlation coefficient, obtains a fast version of the Spearman's rank correlation coefficient by simplifying the Spearman's rank correlation coefficient, so as to simplify the field programmable logic gate array operation hardware circuit designed based on the Spearman's rank correlation coefficient and speed up the operation; and the Spearman's rank correlation coefficient is solved by using the parallel computing mode based on the field programmable logic gate array, so as to further shorten the calculation time and achieve the purpose of solving the Spearman's rank correlation coefficient in real time and fast. BRIEF DESCRIPTION OF DRAWINGS

[0066] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0067] Figure 1 An exemplary architecture of the method for solving the Spearman's rank correlation coefficient in the embodiments of the present application. DETAILED DESCRIPTION

[0068] The embodiments of the present application are described in detail below with reference to the accompanying drawings, in which examples of the embodiments are shown, wherein the same or similar notations are used to represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as a limitation on the present application.

[0069] Those skilled in the art can understand that, unless specifically stated, the singular forms "a", "an" and "the" used herein also include the plural forms. It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we say that an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any single unit and all combinations of the associated listed items.

[0070] Unless expressly stated to be mutually exclusive, the various embodiments disclosed in this application may be cross-combined with the relevant technical features of the various embodiments to flexibly construct new embodiments, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or resolve certain deficiencies in the prior art. Those skilled in the art should be aware of such flexibility.

[0071] See also Figure 1 In one embodiment of the present invention, the method for calculating the Spearman correlation coefficient employs a field programmable logic gate array (FPGA) operation circuit, comprising:

[0072] Step S10: Signal X i Input the row and column storage blocks in the field programmable logic gate array arithmetic circuit to obtain X1…X i …X n and X1…X j …X n , complete the first level cache;

[0073] Step S20: X1...X obtained in step S10 i …X n and X1…X j …X n Input comparator array, complete n 2 Comparison operations, get a ij =sign(x i -x j ) and enter the pipeline to complete the second-level cache;

[0074] Step S30: Signal Y i Input row and column storage blocks and get Y1…Y i …Y n and Y1…Y j …Y n , complete the first level cache;

[0075] Step S40: Y1...Y i …Y n and Y1…Y j …Y n Input comparator array, complete n 2 Comparison operation, get b ij =sign(y i -y j ) and enter the pipeline to complete the second-level cache;

[0076] Step S50: X1...X obtained in step S10 i …X n and Y1…Y obtained in step S3j …Y n Input comparator, complete n comparison operation, get c i = sign(x i -y i ), and input into the pipeline, complete two-level cache;

[0077] Step S60, the step S20, step S40 and step S50 obtained in

[0078] a ij = sign(X i -X j ), b ij = sign(Y i -Y j ) and c i = sign(X i -Y i ) are input into the array multiplication accumulator, and under the control of the control unit, the and

[0079] Step S70, the step S60 obtained in

[0080] Input subtractor, complete

[0081] Step S80, the step S70 obtained in

[0082] Input divider, complete

[0083] Step S90, the step S80 obtained in

[0084] Input subtractor to determine the Spearman simple correlation coefficient as:

[0085]

[0086] Step S100, the step S90 obtained in the Spearman simple correlation coefficient is input into the register, get the output result, wherein, i, j = 1…n.

[0087] Further, the step S60 includes:

[0088] Step S601, a ij = sign(X i -X j ), b ij = sign(Y i -Y j ) and ci = sign(X i -Y i ) while inputting corresponding multiplier array, under the control of control unit, complete n 2 times parallel input multiplication operation at different time, get sign(X i -X j ) sign(X i -Y i ) and sign(Y i -Y j ) sign(X i -Y i );

[0089] Step S602, input sign(X i -X j ) sign(X i -Y i ) and sign(Y i -Y j ) sign(X i -Y i ) obtained in step S601 into corresponding adder at the same time, complete n 2 times parallel input addition operation at different time, get and

[0090] In some embodiments, in practical applications, many signal processing tasks need to detect signals under noise interference. The signal detection problem under single-channel impulse noise is usually modeled as follows:

[0091] X[i] = θY[i] + Z[i],

[0092] where Y[i] is a known transmitted signal without noise interference, θ is an attenuation coefficient representing the presence (θ ≠ 0) or absence (θ = 0) of signal, Z[i] is impulse noise, and X[i] is a received signal affected by noise;

[0093] Let denote the received signal of length n in the system model X[i] = θY[i] + Z[i], denote the known transmitted signal without noise interference, denote the noise;

[0094] Arrange the sequence in order of magnitude from small to large to get a new sequence of order statistics X1< L < X n Assuming that X j is located at the kth position in the sequence , define the number k as X jThe rank of X j is denoted as P j The rank of Y j is denoted as Q i .

[0095] Spearman’s footrule (SF) is defined as follows:

[0096]

[0097] Definition P i is the rank of signal X i , i.e. Q i is the rank of signal Y i , i.e. The sign function sgn(·) can be expressed as sgn(·) = 2H(·) - 1, where H(t) is defined as Therefore, U can be expressed as:

[0098]

[0099] According to the relationship between the rank and the empirical cumulative distribution function, and we can get:

[0100]

[0101] Therefore, according to the law of large numbers, and converge to F X (t) = Φ(t) and F Y (t) = Φ(t), respectively, when n tends to infinity:

[0102]

[0103] Substituting equation (4) into equation (2), we can get the approximate expression of U:

[0104]

[0105] Spearman’s footrule (SF) can be approximated as:

[0106]

[0107] Substituting equation (4) into equation (2), by simplifying U through the relationship sgn(·) = 2H(·) - 1, we get equation (7):

[0108]

[0109] where i, j = 1...n.

[0110] Substituting equation (7) into equation (6), a fast version of Spearman's rho (SF) can be obtained:

[0111]

[0112] In some embodiments, in order to effectively illustrate the accuracy of the approximate version of Spearman's rho proposed by the present application, the approximate version of Spearman's rho proposed by the present application and the original version of Spearman's rho are compared through Monte Carlo experiments, and the specific experimental design is as follows:

[0113] Attenuation coefficient θ = 0.5, Y i The input signal is determined as known, which is subject to a standard normal model N(0, 1), and the impulse noise Z i Generated by a mixed Gaussian model: Z ~ (1-ε)N(0, σ1) + εN(0, σ2), where ε = 0.05 represents the probability of the occurrence of the impulse component in the entire impulse noise environment, and σ2 = 100 >> σ1 = 1 represents the standard deviation of the impulse component.

[0114] The number of Monte Carlo experiments is set to 1000 times, and the purpose of the experiment is to verify the unbiasedness of the approximate version of Spearman's rho proposed by the present application to the original version of Spearman's rho, and the relevant experimental data are shown in Table 1:

[0115] Table 1 Relevant experimental data

[0116] Signal length n [E(r ASF )-E(r SF )]]> 100 0.0155 150 0.0124 200 0.0107 250 0.0095 300 0.0089 350 0.0084 400 0.0082 450 0.0078 500 0.0076 550 0.0075 600 0.0073 650 0.0072 700 0.0071 750 0.0070 800 0.0069

[0117] The experimental results show that as the signal length increases, the bias of the two gradually decreases, indicating that the approximate version of Spearman's rho is asymptotically unbiased relative to the original version of Spearman's rho, and when the signal length is large enough, the original version of Spearman's rho (SF) can be well estimated.

[0118] In some embodiments, in order to effectively illustrate the reliability of the fast solving method of Spearman's rho proposed by the present application, the fast version of Spearman's rho proposed by the present application and the approximate version of Spearman's rho are compared through Monte Carlo experiments, and the specific experimental design is as follows:

[0119] Y i The input signal is determined as known, which is subject to a standard normal model N(0, 1), and the impulse noise Z iGenerated by a mixture of Gaussian models: Z ~ (1-ε)N(0,σ1)+εN(0,σ2), where ε=0.05 represents the probability of the impulse component occurring in the overall impulse noise environment, and σ2=100 >> σ1=1 represents the standard deviation of the impulse component.

[0120] The number of Monte Carlo experiments is set to 1000, and the purpose of the experiment is to verify the unbiasedness of the fast version of the Spearman's rho simple correlation coefficient proposed in the application to the simplified approximate version of the Spearman's rho simple correlation coefficient under different attenuation coefficients. The comparison experimental data are shown in Table 2:

[0121] Table 2 Comparison experimental data

[0122] Attenuation coefficient θ SF ASF SF of the invention 0 0.0005 ± 5.89e -4 ]] 0.0015 ± 5.94e -4 ]] 0.0015 ± 5.94e -4 <!-- 9 -->]]> 0.1 0.0559 ± 5.95e -4 ]] 0.0570 ± 6.00e -4 ]] 0.0570 ± 6.00e -4 ]] 0.2 0.1104 ± 6.04e -4 ]] 0.1116 ± 6.10e -4 ]] 0.1116 ± 6.10e -4 ]] 0.3 0.1649 ± 6.07e -4 ]] 0.1665 ± 6.17e -4 ]] 0.1665 ± 6.17e -4 ]] 0.4 0.2186 ± 5.86e -4 ]] 0.2209 ± 6.05e -4 ]] 0.2209 ± 6.05e -4 ]] 0.5 0.2701 ± 4.79e -4 ]] 0.2738 ± 5.01e -4 ]] 0.2738 ± 5.01e -4 ]] 0.6 0.3162 ± 4.98e -4 ]] 0.3220 ± 5.35e -4 ]] 0.3220 ± 5.35e -4 ]] 0.7 0.3604 ± 4.57e -4 ]] 0.3694 ± 5.10e -4 ]] 0.3694 ± 5.10e -4 ]] 0.8 0.4002 ± 3.55e -4 ]] 0.4135 ± 4.15e -4 ]] <![CDATA[0.4135±4.15e -4 ]]> 0.9 0.4377 ± 3.17e -4 ]] 0.4567 ± 3.95e -4 ]] 0.4567 ± 3.95e -4 ]]

[0123] The data in Table 2 is in the form of "mean ± standard deviation" of multiple Monte Carlo experiments. The experimental results show that when the environmental noise is single-channel impulse noise, the fast version of the Spearman's rho simple correlation coefficient has excellent robustness to the interference of impulse noise, just like the original version of the Spearman's rho simple correlation coefficient. At the same time, it can be seen that the method for quickly solving the Spearman's rho simple correlation coefficient proposed in the application has good unbiasedness compared with the approximate version of the Spearman's rho simple correlation coefficient, and can well estimate the original version of SF.

[0124] From the above embodiments, compared with the prior art, the CPU in the prior art calculates and solves the Spearman's rho simple correlation coefficient. Since the CPU mainly adopts a serial calculation mode, it is limited by the limitations of serial operation, and the calculation and solution of the CPU to the Spearman's rho simple correlation coefficient is time-consuming and the like. The application includes but is not limited to the following beneficial effects:

[0125] Firstly, the method for solving the Spearman's rho simple correlation coefficient fully utilizes the high-performance parallel processing capability of the field programmable logic gate array operation circuit (FPGA operation circuit), can further shorten the calculation time of the Spearman's rho simple correlation coefficient, and realizes real-time and fast signal correlation processing based on the Spearman's rho simple correlation coefficient (SF);

[0126] Secondly, the Pearson product-moment correlation coefficient is basically invalid in the impulse noise environment, while the Spearman's rho simple correlation coefficient (SF) is robust to impulse noise and is simple and efficient in calculation compared with the Spearman's rank correlation coefficient and the Kendall rank correlation coefficient;

[0127] Third, since it is time-consuming to solve SF using a CPU, this application uses a field programmable gate array computing circuit (FPGA computing circuit) to quickly solve the Spearman simple correlation coefficient. By simplifying the Spearman simple correlation relationship to obtain its fast version, the field programmable gate array computing hardware circuit designed based on the Spearman simple correlation coefficient can be simplified, thereby speeding up the calculation speed; and by solving the Spearman simple correlation coefficient through a parallel computing mode based on a field programmable gate array, the calculation time can be further shortened, thereby achieving the purpose of solving the Spearman simple correlation coefficient in real time and quickly.

[0128] Based on any of the above embodiments, a field programmable logic gate array arithmetic circuit for quickly solving the Spearman's simple correlation coefficient (SF) is proposed to meet another purpose of the present application. Its operation adopts a pipeline processing method. The circuit is applied to any of the above methods for solving the Spearman's simple correlation coefficient, including:

[0129] The comparator array is used to generate a i and Y i Calculate a ij and b ij ;

[0130] The comparator is used to i and Y i Calculate c i ;

[0131] Array multiply accumulator, which is used to calculate

[0132] Subtractor, which is used to calculate T1-T2 and

[0133] Divider, which is used to calculate

[0134] Row and column storage blocks, which are used to serially register signal X i and Y i , which supports block addressing;

[0135] Pipeline, which is used to temporarily store intermediate calculation results;

[0136] A control unit, which is used for timing control of the array multiplier accumulator;

[0137] Register, which is used to store the final calculation result;

[0138] Signal X i and Y i The calculation steps performed after inputting into the field programmable logic gate array calculation circuit are:

[0139] Step S1: Signal X i Input row and column storage blocks to obtain X1…X i …X n and X1…X j …X n , complete the first level cache;

[0140] Step S2: X1…X obtained in step S1 i …X n and X1…X j …X n Input comparator array, complete n 2 Comparison operations, get a ij =sign(x i -x j ) and enter the pipeline to complete the second-level cache;

[0141] Step S3: Signal Y i Input row and column storage blocks and get Y1…Y i …Y n and Y1…Y j …Y n , complete the first level cache;

[0142] Step S4: Y1...Y i …Y n and Y1…Y j …Y n Input comparator array, complete n 2 Comparison operation, get b ij =sign(y i -y j ) and enter the pipeline to complete the second-level cache;

[0143] Step S5: X1...X obtained in step S1 i …X n and Y1…Y obtained in step S3 j …Y n Input the comparator, complete n comparison operations, and get c i =sign(x i -y i ) and enter the pipeline to complete the second-level cache;

[0144] Step S6: the

[0145] a ij =sign(X i -X j ), b ij =sign(Y i-Y j ) and c i = sign(X i -Y i ) are input into the array multiplication accumulator, and under the control of the control unit, the operations of and

[0146] Step S7, the result obtained in step S6 is input into the subtractor, and the operation of

[0147] is completed.

[0148] Step S8, the result obtained in step S7 is input into the divider, and the operation of

[0149] is completed.

[0150] Step S9, the result obtained in step S8 is input into the subtractor, and the operation of

[0151] is completed to determine the Spearman simple correlation coefficient as:

[0152]

[0153] Step S10, the Spearman simple correlation coefficient obtained in step S9 is input into the register, and the output result is obtained, wherein i, j = 1…n.

[0154] Optionally, the array multiplication accumulator comprises:

[0155] a multiplier array for calculating a ij c i , b ij c i , wherein i, j = 1…n.

[0156] an adder for calculating

[0157] the signals X i and Y i after being input into the array multiplication accumulator, the operation steps performed are:

[0158] Step S61, a ij = sign(X i -X j ), b ij = sign(Y i -Y j ) and c i = sign(X i -Y i)sign(X 2 i -X j )sign(X i -Y i )and sign(Y i -Y j )sign(X i -Y i ) are input into corresponding adders at different times under the control of the control unit, n

[0159] Steps S62 and S61 obtain sign(X i -X j )sign(X i -Y i )and sign(Y i -Y j )sign(X i -Y i ) are input into corresponding adders at different times under the control of the control unit, n 2 times of parallel input addition operations are completed to obtain where i, j = 1...n.

[0160] Optionally, the field programmable logic gate array operation circuit adopts a pipeline processing mode.

[0161] In some embodiments, the field programmable logic gate array operation circuit is an FPGA operation circuit, and FPGA (Field-Programmable Gate Array) is a semi-custom integrated circuit with rich logic resources and high-performance mathematical operation modules such as multipliers and adders, which enables fast parallel operation. The programmability of the internal logic determines the flexibility of the designed circuit structure, so that real-time, high-dynamic centralized complex mathematical operation circuits can be designed and implemented using FPGA.

[0162] The application further provides an electronic device applying the method for solving the Spearman simple correlation coefficient.

[0163] The application further provides a computer device including a memory and a processor, wherein the memory stores a computer program implemented according to any one of the methods, and the processor implements any one of the methods for solving the Spearman simple correlation coefficient when executing the computer program.

[0164] ​The application further provides a computer readable storage medium storing a computer program realized according to the method in any of the above embodiments in the form of computer readable instructions, and when the computer program is invoked and run by a computer, the steps included in the corresponding method are executed.

[0165] The above only describes some embodiments of the application, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the principles of the application, and these improvements and refinements should also be considered as the protection scope of the application.

[0166] In summary, compared with the prior art, the application is directed to the calculation and solving of the Spearman simple correlation coefficient by the CPU in the prior art, and due to the fact that the CPU mainly adopts a serial calculation mode, which is limited by the limitations of serial operation, the calculation and solving of the Spearman simple correlation coefficient by the CPU is time-consuming, and the like, and the application includes but is not limited to the following beneficial effects:

[0167] Firstly, the solving method of the Spearman simple correlation coefficient fully utilizes the high-performance parallel processing capability of the field programmable logic gate array operation circuit (FPGA operation circuit), can further shorten the calculation time of the Spearman simple correlation coefficient, and realizes real-time and fast signal correlation processing based on the Spearman simple correlation coefficient (SF);

[0168] Secondly, the Pearson product-moment correlation coefficient is basically invalid in a pulse noise environment, while the Spearman simple correlation coefficient (SF) is robust to pulse noise and is simpler and more efficient in calculation than the Spearman rank correlation coefficient and the Kendall rank correlation coefficient;

[0169] Thirdly, since the calculation of the SF by the CPU is time-consuming, the application adopts the field programmable logic gate array operation circuit (FPGA operation circuit) to realize fast solving of the Spearman simple correlation coefficient, simplifies the Spearman simple correlation coefficient to obtain its fast version, thereby simplifying the field programmable logic gate array operation hardware circuit designed based on the Spearman simple correlation coefficient and accelerating the operation speed; and the Spearman simple correlation coefficient is solved by the parallel calculation mode based on the field programmable logic gate array, which can further shorten the calculation time and achieve the purpose of real-time and fast solving of the Spearman simple correlation coefficient.

Claims

1. A method for solving the Spearman correlation coefficient, characterized in that: include: Step S10: Signal X i Input the row and column storage blocks in the field programmable logic gate array arithmetic circuit to obtain X1…X i …X n and X1…X j …X n , complete the first level cache; Step S20: X1...X obtained in step S10 i …X n and X1…X j …X n Input comparator array, complete n 2 Comparison operations, get a ij =sign(x i -x j ) and enter the pipeline to complete the second-level cache; Step S30: Signal Y i Input row and column storage blocks and get Y1…Y i …Y n and Y1…Y j …Y n , complete the first level cache; Step S40: Y1...Y i …Y n and Y1…Y j …Y n Input comparator array, complete n 2 Comparison operation, get b ij =sign(y i -y j ) and enter the pipeline to complete the second-level cache; Step S50: X1...X obtained in step S10 i …X n and Y1…Y obtained in step S30 j …Y n Input the comparator, complete n comparison operations, and get c i =sign(x i -y i ) and enter the pipeline to complete the second-level cache; Step S60: the data obtained in steps S20, S40 and S50 are a ij =sign(X i -X j ), b ij =sign(Y i -Y j ) and c i =sign(X i -Y i ) input array multiplication accumulator at the same time, under the control of the control unit, the time-sharing is completed and Step S70: the Enter the subtractor, complete Step S80: the Enter the divider, complete Step S90: the Input to the subtractor to determine the Spearman shorthand correlation coefficient is: Step S100: Input the Spearman's shorthand correlation coefficient obtained in step S90 into a register to obtain an output result, wherein i, j = 1...n.

2. The method for calculating the Spearman correlation coefficient according to claim 1, wherein: The step S60 includes: Step S601: ij =sign(X i -X j ), b ij =sign(Y i -Y j ) and c i =sign(X i -Y i ) and simultaneously input the corresponding multiplier array, and under the control of the control unit, the n 2 Parallel input multiplication operation, get sign(X i -X j )sign(X i -Y i ) and sign(Y i -Y j )sign(X i -Y i ); Step S602: The sign (X i -X j )sign(X i -Y i ) and sign(Y i -Y j )sign(X i -Y i ) input the corresponding adder at the same time, and complete n 2 parallel input addition operations, we get and 3. A field programmable logic gate array arithmetic circuit, applied to the Spearman shortcut correlation coefficient solution method according to any one of claims 1 to 2, characterized in that: include: The comparator array is used to generate a i and Y i Calculate a ij and b ij ; The comparator is used to i and Y i Calculate c i ; Array multiply accumulator, which is used to calculate Subtractor, which is used to calculate T1-T2 and Divider, which is used to calculate Row and column storage blocks, which are used to serially register signal X i and Y i , which supports block addressing; Pipeline, which is used to temporarily store intermediate calculation results; A control unit, which is used for timing control of the array multiplier accumulator; Register, which is used to store the final calculation result; Signal X i and Y i The calculation steps performed after inputting into the field programmable logic gate array calculation circuit are: Step S1: Signal X i Input row and column storage blocks to obtain X1…X i …X n and X1…X j …X n , complete the first level cache; Step S2: X1…X obtained in step S1 i …X n and X1…X j …X n Input comparator array, complete n 2 Comparison operations, get a ij =sign(x i -x j ) and enter the pipeline to complete the second-level cache; Step S3: Signal Y i Input row and column storage blocks and get Y1…Y i …Y n and Y1…Y j …Y n , complete the first level cache; Step S4: Y1...Y i …Y n and Y1…Y j …Y n Input comparator array, complete n 2 Comparison operation, get b ij =sign(y i -y j ) and enter the pipeline to complete the second-level cache; Step S5: X1...X obtained in step S1 i …X n and Y1…Y obtained in step S3 j …Y n Input the comparator, complete n comparison operations, and get c i =sign(x i -y i ) and enter the pipeline to complete the second-level cache; Step S6: a obtained in step S2, step S4 and step S5 ij =sign(X i -X j ), b ij =sign(Y i -Y j ) and c i =sign(X i -Y i ) input array multiplication accumulator at the same time, under the control of the control unit, the time-sharing is completed and Step S7: the Enter the subtractor, complete Step S8: the Enter the divider, complete Step S9: the Input to the subtractor to determine the Spearman shorthand correlation coefficient is: Step S10: Input the Spearman's shorthand correlation coefficient obtained in step S9 into a register to obtain an output result, where i, j = 1...n.

4. The field programmable logic gate array operation circuit according to claim 3, characterized in that: The array multiplier accumulator comprises: An array of multipliers used to compute a ij c i 、b ij c i , where i, j = 1…n; Adder, used for calculation Signal X i and Y i The steps performed after inputting the array multiplication accumulator are: Step S61, a ij =sign(X i -X j ), b ij =sign(Y i -Y j ) and c i =sign(X i -Y i ) and simultaneously input the corresponding multiplier array, and under the control of the control unit, the n 2 Parallel input multiplication operation, get sign(X i -X j )sign(X i -Y i ) and sign(Y i -Y j )sign(X i -Y i ); Step S62, step S61 obtained sign (X i -X j )sign(X i -Y i ) and sign(Y i -Y j )sign(X i -Y i ) input the corresponding adder at the same time, and complete n 2 parallel input addition operations, we get and Among them, i, j = 1…n.

5. The field programmable logic gate array operation circuit according to claim 3, characterized in that: The field programmable logic gate array operation circuit adopts a pipeline processing method.

6. An electronic device, characterized in that: Apply the Spearman's shortcut correlation coefficient solution method as described in any one of claims 1 to 2.

7. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program implemented according to the method described in any one of claims 1 to 2, and the processor implements any one of the methods for solving the Spearman shortcut correlation coefficient when executing the computer program.

8. A computer-readable storage medium, characterized in that It stores a computer program implemented according to the method described in any one of claims 1 to 2 in the form of computer-readable instructions, and when the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

Images